Light emitting diode epitaxial wafer and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode epitaxial wafer and a preparation method thereof, wherein the epitaxial wafer comprises a substrate and an N-type layer, a multi-quantum well layer and a P-type layer sequentially stacked on the substrate, wherein the multi-quantum well layer comprises a plurality of well layers and barrier layers alternately grown in a period, and at least one of the well layers comprises a first sublayer, a second sublayer and a third sublayer sequentially stacked, wherein the first sublayer is a Si-doped InGaN layer, the second sublayer is a C-doped InGaN layer, and the third sublayer is an Mg- and Si-doped InGaN layer. The present disclosure can improve the light-emitting consistency and light-emitting efficiency of the light-emitting diode epitaxial wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] LED (Light Emitting Diode) is a semiconductor electronic component that can emit light. As a new type of efficient, environmentally friendly and green solid-state lighting source, it is rapidly and widely used, and the light-emitting diode epitaxial wafer plays a vital role in the realization of the functions of the light-emitting diode.

[0003] At present, the epitaxial wafer of a light-emitting diode includes a substrate, and an N-type layer, an active layer and a P-type layer sequentially stacked on the substrate. The active layer includes a plurality of quantum well layers and a plurality of quantum barrier layers grown alternately, each of the quantum well layers includes a first quantum well layer, a second quantum well layer and a third quantum well layer stacked sequentially, and the first quantum well layer and the third quantum well layer are both In x Ga 1-x N layer, and the second quantum well layer is a GaN layer. The quantum well layer adopts the In pulse growth method to reduce the probability of the formation of In enriched centers, improve the In-rich localized state effect in the quantum well InGaN material, and make the In component stably and concentratedly distributed in the quantum well layer.

[0004] However, the current light emitting diode epitaxial wafers are relatively poor in terms of light emission consistency (such as brightness consistency and wavelength consistency, etc.) and light emission efficiency. Summary of the invention

[0005] The embodiments of the present disclosure provide a light-emitting diode epitaxial wafer and a method for preparing the same, which can improve the light-emitting consistency and light-emitting efficiency of the light-emitting diode epitaxial wafer. The technical solution is as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a light-emitting diode epitaxial wafer, the epitaxial wafer comprising a substrate and an N-type layer, a multi-quantum well layer and a P-type layer sequentially stacked on the substrate, the multi-quantum well layer comprising a plurality of well layers and barrier layers alternately grown in a periodic manner, at least one of the well layers comprising a first sublayer, a second sublayer and a third sublayer sequentially stacked, the first sublayer being a Si-doped InGaN layer, the second sublayer being a C-doped InGaN layer, and the third sublayer being an Mg- and Si-doped InGaN layer.

[0007] Optionally, the doping concentration of C in the second sublayer is in the range of 5×10 16 cm -3 ~1×10 18 cm -3 .

[0008] Optionally, the second sublayer is generated using triethylgallium and trimethylgallium as gallium sources, and C in the second sublayer is provided by the trimethylgallium.

[0009] Optionally, the doping concentration of Si in the first sublayer is in the range of 1×10 16 cm -3 ~1×10 18 cm -3 .

[0010] Optionally, in the first sublayer, the In component content gradually increases from a side close to the N-type layer to a side close to the P-type layer, and a maximum value of the In component content ranges from 10% to 30%.

[0011] Optionally, the doping concentration of Mg is in the range of 1×10 17 cm -3 ~1×10 18 cm -3 .

[0012] Optionally, the thickness of the first sublayer is in the range of The thickness of the second sublayer is in the range of The thickness range of the third sublayer is

[0013] In a second aspect, an embodiment of the present disclosure provides a method for preparing a light-emitting diode epitaxial wafer, the method comprising:

[0014] providing a substrate;

[0015] An N-type layer, a multi-quantum well layer and a P-type layer are sequentially stacked and grown on the substrate, wherein the multi-quantum well layer includes a plurality of well layers and barrier layers that are alternately grown in a periodic manner, and at least one of the well layers includes a first sublayer, a second sublayer and a third sublayer that are sequentially stacked, wherein the first sublayer is a Si-doped InGaN layer, the second sublayer is a C-doped InGaN layer, and the third sublayer is an Mg- and Si-doped InGaN layer.

[0016] Optionally, the concentration range of C in the second sublayer is 5×10 16 cm -3 ~1×10 18 cm -3 .

[0017] Optionally, the second sublayer is formed in the following manner: the second sublayer is grown using triethylgallium and trimethylgallium as gallium sources, wherein the mass fraction of trimethylgallium in the mixture of triethylgallium and trimethylgallium is (0, 10%).

[0018] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0019] In the embodiment of the present disclosure, doping Mg in the third sublayer is beneficial to improving the luminescence efficiency. The main reasons include the following: (1) The holes generated by Mg ionization can neutralize part of the piezoelectric polarization negative charge at the interface between the well layer and the barrier layer, reducing the interface polarization charge density, thereby effectively weakening the piezoelectric polarization field and suppressing the quantum confined Stark effect, thereby increasing the radiative recombination rate of carriers in the multi-quantum well layer; (2) It can suppress the phase separation and stress relaxation phenomena in the InGaN layer and improve the crystal quality of the InGaN layer; (3) The high surface potential barrier formed by the well layer and the barrier layer limits the migration of carriers to the position of the dislocation center, thereby suppressing the non-radiative recombination at the dislocation center, thereby improving the luminescence efficiency.

[0020] In addition, doping the second sublayer with C can reduce the conductivity of the second sublayer, promote the lateral expansion of electrons and holes, realize the planar spreading of carriers in the well layer, and expand the current distribution of the well layer, thereby effectively improving the uniformity of luminescence and obtaining an epitaxial wafer with a consistent luminescence wavelength.

[0021] Furthermore, doping Si in the first sublayer and the third sublayer can reduce the polarization electric field between the well layer and the barrier layer, thereby improving the internal quantum efficiency of the InGaN layer and further improving the luminous efficiency of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a structural schematic diagram of a micro light emitting diode epitaxial wafer provided by an embodiment of the present disclosure;

[0024] Figure 2 It is a schematic structural diagram of a single period quantum well barrier in a micro light emitting diode epitaxial wafer provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a flow chart of a method for preparing a micro light emitting diode epitaxial wafer provided by an embodiment of the present disclosure;

[0026] Figure 4 This is a flow chart of another method for preparing a micro light emitting diode epitaxial wafer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0028] The light-emitting diode in the embodiment of the present disclosure is suitable for a display screen, wherein the display screen includes a display screen made of ordinary-size LEDs, a display screen made of miniLEDs or MicroLEDs. In the following, in conjunction with the accompanying drawings, the light-emitting diode in the embodiment of the present disclosure is described using MicroLED as an example. Figure 1 The structure diagram of a micro light emitting diode epitaxial wafer provided by the embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the micro diode epitaxial wafer includes a substrate 10 and an N-type layer 11, a multi-quantum well layer 12 and a P-type layer 13 sequentially stacked on the substrate 10, and the multi-quantum well layer 12 includes a plurality of well layers 121 and barrier layers 122 grown alternately in a periodic manner.

[0029] Figure 2 Schematic diagram of a single period quantum well barrier in a micro light emitting diode epitaxial wafer provided by the embodiment of the present disclosure. Figure 2 As shown, the well layer 121 includes a first sublayer 1211, a second sublayer 1212 and a third sublayer 1213 stacked in sequence, the first sublayer 1211 is a Si-doped InGaN layer, the second sublayer 1212 is a C-doped InGaN layer, and the third sublayer 1213 is an Mg- and Si-doped InGaN layer.

[0030] In the embodiment of the present disclosure, doping the third sublayer 1213 with Mg is beneficial to improving the luminous efficiency, and the reasons mainly include the following points: (1) Doping the third sublayer 1213 with Mg can achieve interface modification between the well layer 121 and the barrier layer 122. Interface modification means that the holes generated by Mg ionization can neutralize part of the piezoelectric polarization negative charge at the interface between the well layer 121 and the barrier layer 122, reduce the interface polarization charge density, and thus effectively weaken the piezoelectric polarization field and suppress the quantum confined Stark effect, thereby increasing the radiative recombination rate of carriers in the multi-quantum well layer 12. In addition, X-ray photoelectron spectroscopy and scanning transmission electron microscopy characterization found that the interface modification of Mg can promote the growth of InGaN material in the well layer 121 and make the In component distribution in the well layer 121 more uniform, thereby improving the luminous efficiency of the micro light-emitting diode. (2) Mg doping can inhibit phase separation, stress relaxation and related defects in the well layer 121, thereby improving the crystal quality of the InGaN layer (i.e., the third sublayer 1213); (3) Since Mg atoms tend to aggregate near dislocation pits, the growth of InGaN material in the region at the interface between the well layer 121 and the barrier layer 122 is inhibited, thereby forming a thinner well layer 121 in this region. The high surface potential barrier formed by the thin well can effectively prevent carriers from migrating to the center of the dislocation for non-radiative recombination, thereby improving the luminescence efficiency.

[0031] In addition, doping the second sublayer 1212 with C can increase the resistance of the second sublayer 1212 and reduce the conductivity of the second sublayer 1212. When the carriers pass through the second sublayer 1212 with larger impedance, the electrons and holes will expand laterally, which can make the carriers evenly distributed in the entire well layer, reduce the probability of uneven distribution of carriers, and make the current expand evenly when current is passed, thereby effectively improving the uniformity of light emission, and obtaining an epitaxial wafer with a consistent light emission wavelength.

[0032] Furthermore, when InGaN material is grown on the GaN polar plane, its built-in polarization field will greatly reduce the internal quantum efficiency of the InGaN layer. Doping Si in the first sublayer and the third sublayer can reduce the polarization electric field between the well layer 121 and the barrier layer 122, thereby improving the internal quantum efficiency of the InGaN layer and further improving the luminous efficiency of the micro light emitting diode.

[0033] Optionally, the doping concentration of C in the second sublayer 1212 is in the range of 5×10 16 cm -3 ~1×10 18 cm -3 .

[0034] A certain doping concentration of C can reduce the conductivity of the second sublayer 1212 of the quantum well, promote the lateral expansion of electrons and holes, thereby realizing the planar spreading of carriers in the light-emitting quantum well, and obtaining an epitaxial wafer with a consistent light-emitting wavelength. If the doping concentration of C is too high, it will cause a large impedance, greatly reduce the carrier mobility, cause a large energy loss when electrons and holes recombine, cause non-radiative recombination, reduce the internal quantum efficiency of the LED device, and cause the operating voltage of the LED device to increase. If the doping concentration of C is too low, it will not achieve the effect of promoting the consistency of light emission of the epitaxial wafer.

[0035] Optionally, the second sublayer 1212 is generated using triethylgallium and trimethylgallium as gallium sources, and C in the second sublayer 1212 is provided by the trimethylgallium.

[0036] By using a small amount of trimethylgallium as a gallium source, the second sublayer 1212 of the quantum well can reach a certain C concentration, thereby reducing the conductivity of the second sublayer 1212 of the quantum well, promoting the lateral expansion of electrons and holes, thereby achieving the planar spreading of carriers in the light-emitting quantum well, expanding the current distribution of the quantum well layer 121, thereby effectively improving the uniformity of light emission, and then obtaining an epitaxial wafer with a consistent light emission wavelength. In addition, C doping can be achieved without using additional processes, which is convenient to implement.

[0037] Optionally, the In component content in the second sub-layer is a constant value, and the value range of the constant value is (30%, 50%).

[0038] Since the second sub-layer 1212 is heavily doped with In components, the light emission of the epitaxial wafer can be more concentrated in the second sub-layer 1212, thereby improving the brightness consistency of the epitaxial wafer.

[0039] Optionally, the doping concentration of Si in the first sublayer 1211 is in the range of 1×10 16 cm -3 ~1×10 18 cm -3 .

[0040] Si doping can alleviate the polarization effect between the well layer 121 and the barrier layer 122. The Si doping range here is low doping. Since Si atoms are far less than Ga / In atoms, Si can fill the defect vacancies in the first sublayer 1211, reduce leakage channels, and improve the antistatic ability of the LED.

[0041] Optionally, in the first sublayer 1211, the In component content gradually increases from the side close to the N-type layer to the side close to the P-type layer, and the maximum value of the In component content ranges from 10% to 30%. For example, in the first sublayer 1211, the In component content on the side close to the P-type layer is 20%.

[0042] The gradual increase of the In component from 0 can provide a good transition from the barrier layer 122 material to the well layer 121 material, reduce the lattice mismatch, and thus improve the luminous efficiency of the micro light emitting diode.

[0043] The first sublayer 1211 has low Si doping and a gradually increasing In component, which provides a high-quality first sublayer 1211 , thereby making the first sublayer 1211 better transition to the second sublayer 1212 .

[0044] Optionally, in the third sublayer 1213, the doping concentration of Mg is in the range of 1×10 17 cm -3 ~1×10 18 cm -3 In the third sublayer 1213, the doping concentration of Si is in the range of 1×10 16 cm -3 ~1×10 18 cm -3 .

[0045] The third sublayer 1213 can achieve local isoelectronic doping of the light-emitting quantum well by slightly doping with Si and Mg, reduce the In-rich clustering phenomenon, and improve the consistency of light-emitting brightness.

[0046] The In component content in the third sublayer 1213 InGaN layer gradually decreases from the side close to the N-type layer 11 to the side close to the P-type layer 13, and the maximum value of the In component content ranges from (10%, 30%).

[0047] As the In component content in the third sublayer 1213 gradually decreases, the diffusion of In atoms into the barrier layer 122 is hindered, the polarization effect between the well layer 121 and the barrier layer 122 is reduced, and the energy band tilt of the light-emitting well layer 121 is reduced, thereby improving the consistency of the light-emitting wavelength.

[0048] Optionally, the thickness of the first sublayer 1211 is in the range of The thickness range of the second sublayer 1212 is The thickness range of the third sublayer 1213 is In some examples, the thickness of the first sublayer 1211 is The thickness of the second sub-layer 1212 is The thickness of the third sublayer 1213 is

[0049] Since the first sublayer 1211 and the third sublayer 1213 are both low indium components, the thickness is less than It does not serve as a transition layer and its thickness is greater than The overall thickness of the well layer 121 will be too thick, thereby aggravating the polarization effect between the well layer 121 and the barrier layer 122, resulting in poor luminescence consistency; the second sublayer 1212 is a high In component and has a thickness less than When the quantum well luminescence intensity is insufficient, the thickness is greater than This causes the crystal quality of the multi-quantum well region to seriously deteriorate, resulting in poor reliability of the LED device.

[0050] In summary, the thickness of the first sublayer 1211 can better play the role of transition layer within a suitable range; the thickness range setting of the second sublayer 1212 can make the luminescence of the heavily doped In component more concentrated in the second sublayer 1212, thereby achieving the purpose of improving the brightness consistency; since the third sublayer 1213 is close to the barrier layer 122, its thickness setting can reduce the diffusion of In atoms into the barrier layer 122. Therefore, the thickness setting of the three sublayers can effectively reduce the polarization effect between the well layer 121 and the barrier layer 122, reduce the energy band tilt of the well layer 121, and improve the consistency of the luminescent wavelength. Exemplarily, the substrate 10 can be a sapphire substrate, a silicon substrate or a silicon carbide substrate, wherein the sapphire substrate is a commonly used substrate with mature technology and low cost. Optionally, the substrate 10 can be a flat substrate or a patterned substrate.

[0051] Exemplarily, the N-type layer is an N-type GaN layer. The N-type GaN layer is doped with Si, and the doping concentration of Si is in the range of 1×10 18 ~1×10 19 cm -3Too high Si doping concentration will reduce the crystal quality and increase defects, while too low Si doping concentration will reduce the conductivity of the N-type GaN layer. 18 ~1×10 19 cm -3 Within this range, the N-type GaN layer can have good crystal quality and sufficient electrical conductivity, thereby helping to improve the luminous efficiency of the micro light-emitting diode.

[0052] Exemplarily, the thickness of the N-type GaN layer may be in the range of 0.5 μm to 3 μm.

[0053] Exemplarily, the multi-quantum well layer 12 includes well layers 121 and barrier layers 122 that are alternately grown in multiple periods, wherein the multiple periods may be 8 to 15 periods, for example, 8, 10, 13 or 15 periods.

[0054] Exemplarily, the thickness of each well layer is 2 nm to 5 nm.

[0055] Exemplarily, the barrier layer 122 is a GaN layer. Exemplarily, the thickness of each barrier layer 122 is 8-20 nm.

[0056] See again Figure 1 In some examples, the micro-LED epitaxial wafer further includes a buffer layer 14, a 3D nucleation layer 15, and a U-type GaN layer 16 (ie, an undoped GaN layer). The buffer layer 14, the 3D nucleation layer 15, and the U-type GaN layer 16 are sequentially stacked between the substrate 10 and the N-type layer 11.

[0057] The buffer layer 14 is used to reduce the lattice mismatch between the substrate 10 and subsequent structures, which is beneficial to reducing the lattice defects in the epitaxial layer.

[0058] For example, the buffer layer 14 may be an AlN buffer layer or the like.

[0059] Exemplarily, the thickness of the buffer layer ranges from 10nm to 50nm, for example, the thickness of the buffer layer is 10nm, 20nm, 37nm or 49nm, etc. The thickness of the buffer layer is different, and the quality of the epitaxial layer finally formed will also be different. If the thickness of the buffer layer is too thin, the surface of the buffer layer will be loose and rough, and it will not provide a good template for the growth of subsequent structures. As the thickness of the buffer layer increases, the surface of the buffer layer gradually becomes denser and smoother, which is conducive to the growth of subsequent structures. However, if the thickness of the buffer layer is too thick, the surface of the buffer layer will be too dense, which is also not conducive to the growth of subsequent structures and cannot reduce lattice defects in the epitaxial layer.

[0060] The 3D nucleation layer 15 is used to provide necessary nucleation centers for the growth of subsequent structures, which is beneficial to the adsorption and lateral growth of subsequent structures. Exemplarily, the 3D nucleation layer is a GaN layer.

[0061] Exemplarily, the thickness range of the 3D nucleation layer 15 is 0.3 μm to 0.5 μm.

[0062] The U-shaped GaN layer 16 is used to reduce defects and improve the lattice quality of the epitaxial wafer, so as to further improve the luminous efficiency of the micro light-emitting diode.

[0063] Exemplarily, the thickness of the U-shaped GaN layer is 0.5 μm to 3 μm. If the thickness of the U-shaped GaN layer 16 is set too thin, the effect of reducing dislocation defects is relatively small. If the thickness is set too thick, the resistance will increase.

[0064] In some examples, the P-type layer 13 may include a low-temperature P-type layer 131, an electron blocking layer 132, a high-temperature P-type layer 133, and a P-type contact layer 134 that are sequentially stacked on the multi-quantum well layer 12.

[0065] Among them, the low-temperature P-type layer 13 is used to provide holes and avoid damaging the activity of the multi-quantum well layer 12 due to too high temperature.

[0066] Exemplarily, the low-temperature P-type layer is an Al w Ga 1-w N layer, where 0.1 < w < 0.3, and the doping concentration of Mg is 5×10 19 ~1×10 21 cm -3 .

[0067] Exemplarily, the thickness range of the low-temperature P-type layer is 50 nm to 100 nm.

[0068] The electron blocking layer 132 is used to block electrons from escaping from the multi-quantum well layer 12, thereby avoiding a reduction in the internal quantum efficiency.

[0069] Exemplarily, the electron blocking layer 132 can be an Al k Ga 1-k N(0.2 < k < 0.5) layer.

[0070] Exemplarily, the thickness of the electron blocking layer 132 is 20 nm to 100 nm.

[0071] The high-temperature P-type layer 133 is used to provide holes for the epitaxial wafer. Moreover, the relatively high temperature during the growth of the high-temperature P-type layer 133 can repair the low-temperature defects of the low-temperature P-type layer 133, which helps to improve the luminous efficiency of the micro light-emitting diode.

[0072] For example, the high temperature P-type layer 133 is a Mg-doped GaN layer, and the Mg doping concentration is 5×10 19 cm -3 ~1×10 21 cm -3 Exemplarily, the thickness of the high temperature P-type layer 133 is in the range of 100 nm to 200 nm.

[0073] The P-type contact layer 134 is used to contact with subsequently fabricated structures such as electrodes to reduce contact resistance.

[0074] For example, the P-type contact layer is a Mg-doped GaN layer, and the Mg doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 .

[0075] Exemplarily, the thickness of the P-type contact layer 134 ranges from 10 nm to 50 nm.

[0076] It should be noted that Figure 1 The micro-LED epitaxial wafer structure in the figure is only an example, and the micro-LED epitaxial wafer structure may include more film layers or remove some film layers in the buffer layer 14, the 3D nucleation layer 15, and the U-type GaN layer 16. As long as it includes the N-type layer 11, the multi-quantum well layer 12, and the P-type layer 13, and the well layer includes the first sublayer 1211, the second sublayer 1212, and the third sublayer 1213.

[0077] Based on the structural schematic diagram of the above-mentioned micro-light emitting diode epitaxial wafer, the embodiment of the present disclosure also provides a method for preparing the micro-light emitting diode epitaxial wafer.

[0078] Figure 3 FIG. 1 is a flow chart of a method for preparing a micro light emitting diode epitaxial wafer provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:

[0079] S31: providing a substrate.

[0080] S32: An N-type layer, a multi-quantum well layer and a P-type layer are sequentially grown on the substrate. The multi-quantum well layer includes a well layer and a barrier layer that are alternately grown in multiple periods. The well layer includes a first sublayer, a second sublayer and a third sublayer that are sequentially stacked, wherein the first sublayer is an InGaN layer doped with Si, the second sublayer is an InGaN layer doped with C, and the third sublayer is an InGaN layer doped with Mg and Si.

[0081] Figure 4 This is a flow chart of another method for preparing a micro light emitting diode epitaxial wafer provided by an embodiment of the present disclosure. The preparation method comprises:

[0082] S41: growing a buffer layer on a substrate.

[0083] Exemplarily, the substrate is a sapphire substrate, and the buffer layer is an AlN layer.

[0084] In S41, an AlN layer is deposited on the sapphire substrate by PVD (Physical Vapour Deposition) magnetron sputtering. During the deposition process, the growth temperature in the PVD equipment is controlled to be 400-800°C (for example, 400°C, 570°C, 800°C, etc.), the sputtering power is 3000W-5000W (for example, 3000W, 4000W, 4500W, 4691W, etc.), and the pressure is 2mTorr-20mTorr (for example, 2mTorr, 3mTorr, 5mTorr, 18mTorr, 19.5mTorr), so as to grow an AlN layer on the substrate 10.

[0085] S42: growing a 3D nucleation layer on the buffer layer.

[0086] In S42, the substrate formed with the buffer layer is placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, the temperature of the MOCVD reaction chamber is controlled at 950°C ~ 1080°C, the pressure of the reaction chamber is controlled at 200Torr ~ 500Torr, and a 3D nucleation layer is grown on the buffer layer in a mixed atmosphere of nitrogen, hydrogen and ammonia.

[0087] S43: growing a U-type GaN layer on the 3D nucleation layer.

[0088] In S43 , the temperature in the MOCVD reaction chamber is set at 1000° C. to 1100° C., the pressure in the reaction chamber is set at 100 Torr to 300 Torr, and a U-type GaN layer is generated on the 3D nucleation layer.

[0089] S44: growing an N-type layer on the U-type GaN layer.

[0090] In S44 , the temperature in the MOCVD reaction chamber is set to 1000° C. to 1100° C., the pressure in the MOCVD reaction chamber is set to 100 Torr to 300 Torr, and an N-type GaN layer is grown on the U-type GaN layer.

[0091] S45: growing a multi-quantum well layer on the N-type layer.

[0092] The multi-quantum well layer comprises a well layer and a barrier layer grown alternately in a plurality of periods, wherein a plurality of InGaN layers / GaN layers are grown alternately in a period of 8 to 15 periods.

[0093] In S45 , the growth conditions of the barrier layer include: a growth temperature of 800° C. to 960° C. and a growth pressure of 100 Torr to 300 Torr. The growth conditions of the well layer include: a growth temperature of 700° C. to 850° C. and a growth pressure of 200 Torr to 500 Torr.

[0094] The well layer includes a first sublayer, a second sublayer and a third sublayer stacked in sequence, the first sublayer is a Si-doped InGaN layer, the second sublayer is a C-doped InGaN layer, and the third sublayer is an InGaN layer doped with C and Mg.

[0095] In the embodiment of the present disclosure, the formation process of each well layer includes the following steps.

[0096] The first step is to grow a first sublayer on the N-type GaN layer.

[0097] For example, the growth temperature of the first sublayer is 820° C., the growth pressure is 200 Torr, and a mixed gas of nitrogen and ammonia is introduced during the growth process to grow the first sublayer of the quantum well layer on the N-type GaN layer or barrier layer.

[0098] During the growth of the first sublayer, Si is doped into the first sublayer 1211 by ion implantation, and the doping concentration of Si is 1×10 16 cm -3 ~1×10 18 cm -3 In addition, it can also be done by a eutectic method, an injection method, and a vapor phase doping method.

[0099] In the first step, triethylgallium is used as the gallium source of the InGaN layer, and an In source is introduced into the reaction chamber. The content of the In component is controlled by controlling the rate of introducing In, so that the In component content gradually increases from zero along the growth direction of the first sublayer, and the maximum value range is (10%, 30%). For example, the In component content in the InGaN layer gradually increases from zero to 20%.

[0100] The second step is to grow a second sub-layer on the first sub-layer.

[0101] For example, the growth temperature of the second sub-layer is 800° C., the growth pressure is 200 Torr, and a mixed gas of nitrogen and ammonia is introduced into the reaction chamber to grow the second sub-layer on the first sub-layer.

[0102] In the second step, an In source is introduced into the reaction chamber at a uniform speed to grow the second sublayer, so that the In component content in the second sublayer is a constant value, and the constant value range is (30%, 50%). In the second step, a vapor deposition method can be used to introduce a mixture of triethylgallium and trimethylgallium into the reaction chamber, and trimethylgallium and triethylgallium are used as gallium sources to grow the second sublayer, wherein the mass fraction of trimethylgallium in the mixture of triethylgallium and trimethylgallium is (0, 10%).

[0103] Since triethylgallium (Ga(C2H5)3) is a group III organic source with a large ligand, the ethyl group has a weak surface bond and can be desorbed before the reaction grows carbon. Complex groups can also decompose on the surface. Triethylgallium produces carbon-carbon double bonds in the desorbed molecules and leaves H atoms on the surface without producing C-containing substances. However, trimethylgallium (Ga(CH3)3) has a smaller ligand, a stronger surface bond, and a weaker desorption ability of carbon, thus producing carbon-containing substances. A certain concentration of C doping is achieved by adjusting the content of trimethylgallium in the mixture of triethylgallium and trimethylgallium. Therefore, the C doping concentration in the second sublayer is controlled to be 5×10 16 cm -3 ~1×10 18 cm -3 .

[0104] Step 3: growing a third sub-layer on the second sub-layer.

[0105] For example, the growth temperature of the third sublayer is 850°C, the growth pressure is 200 Torr, and a mixed gas of nitrogen and ammonia is introduced to grow the third sublayer on the second sublayer. In the third step, an In source is introduced into the reaction chamber to grow the third sublayer InGaN layer, and the In component content gradually decreases from the side close to the N-type layer to the side close to the P-type layer, and the maximum value range of the In component content is (10%, 30%).

[0106] Optionally, the third sublayer is doped with Mg and Si by ion implantation, or by a eutectic method, a doping method, or a vapor phase doping method.

[0107] Doping Si in the third sub-layer has a similar effect to doping Si in the first sub-layer, which will not be described in detail here.

[0108] S46: growing a low-temperature P-type layer on the multi-quantum well layer.

[0109] For example, the low temperature P-type GaN layer is Al w Ga 1-w N, where 0.1 <w<0.3。

[0110] In S46, the temperature of the reaction chamber is controlled within the range of 700 °C to 800 °C, and the pressure is controlled within the range of 200 Torr to 500 Torr. A low-temperature P-type layer is grown on the multi-quantum well layer. Moreover, during the growth process, Mg doping is carried out, and the doping concentration of Mg is 5×10 19 ~1×10 21 cm -3 .

[0111] Optionally, the thickness range of the low-temperature P-type GaN layer is 50 nm to 100 nm.

[0112] S47: Grow an electron blocking layer on the low-temperature P-type layer.

[0113] Exemplarily, the electron blocking layer 132 can be an Al k Ga 1-k N(0.2 < k < 0.5) layer.

[0114] In S47, the temperature in the reaction chamber is adjusted to 800 °C to 1000 °C, and the pressure in the reaction chamber is controlled at 100 Torr to 300 Torr. An electron blocking layer is grown on the low-temperature P-type layer.

[0115] Exemplarily, the thickness of the electron blocking layer is 2 nm to 100 nm.

[0116] S48: Grow a high-temperature P-type layer on the electron blocking layer.

[0117] Exemplarily, the high-temperature P-type layer 133 is a GaN layer.

[0118] In S48, the temperature of the reaction chamber is controlled at 800 °C to 1000 °C, and the pressure of the reaction chamber is controlled in an environment of 200 Torr - 600 Torr. A high-temperature P-type layer with a thickness range of 100 nm to 200 nm is grown on the high-temperature P-type layer. During the growth process of the high-temperature P-type layer, Mg doping is carried out, and the doping concentration of Mg is 5×10 19 cm -3 ~1×10 21 cm -3 .

[0119] S49: Grow a P-type contact layer on the high-temperature P-type layer.

[0120] In S49, the temperature in the reaction chamber is controlled at 850 °C to 1000 °C, and the pressure of the reaction chamber is controlled at 100 Torr to 300 Torr. A P-type contact layer is grown on the electron blocking layer. During the growth process of the P-type contact layer, Mg doping is carried out, and the doping concentration range is 1×10 20 cm -3 ~1×10 21 cm-3 .

[0121] Optionally, the preparation method further includes: after the growth of the epitaxial layer of the micro light-emitting diode is completed, annealing the epitaxial wafer. For example, reducing the temperature of the reaction chamber and performing annealing treatment in a nitrogen atmosphere, the annealing temperature range is 650 °C to 850 °C, the annealing treatment is carried out for 5 to 15 minutes, and then the heating system and the gas supply system are turned off. Wait for the temperature of the reaction chamber to drop to room temperature, and the epitaxial growth ends when it reaches room temperature.

[0122] After annealing the epitaxial wafer, subsequent processes can also be performed on the epitaxial wafer to fabricate a micro-LED, such as fabricating electrodes and the like.

[0123] Adopt Figure 4 The micro light-emitting diode epitaxial wafer prepared by the method shown is compared with the micro light-emitting diode epitaxial wafer in the related art (hereinafter referred to as the control group).

[0124] The structure of the epitaxial wafer of the control group is basically the same as that Figure 1 shown, the difference is that the well layer containing three sub-layers is replaced with a well layer of a single-layer structure. And the well layer of the single-layer structure is an In g Ga 1-g N layer, where 0.2 < g < 0.5. And In g Ga 1-g The thickness range of the N layer is 2 nm to 5 nm.

[0125] Correspondingly, the preparation process of the epitaxial wafer of the control group is basically the same as that Figure 3 shown. Except that the growth process of the well layer in step S45 is replaced with: introducing pure nitrogen into the reaction chamber, and controlling the growth temperature of the reaction chamber in the range of 700 °C to 850 °C, the growth pressure is controlled in the range of 200 Torr to 500 Torr, and growing In g Ga 1-g N layer, where 0.2 < g < 0.5; introducing a mixed gas of nitrogen and hydrogen into the reaction chamber, and controlling the growth temperature of the reaction chamber in the range of 800 °C to 960 °C, the growth pressure is controlled in the range of 100 Torr to 300 Torr, and growing the GaN layer.

[0126] For Figure 4 the epitaxial wafer prepared by the method shown and the epitaxial wafer of the control group, the luminescence uniformity (such as brightness uniformity, wavelength uniformity) and luminescence efficiency are tested in the same way, Figure 4 The epitaxial wafer prepared by the method shown has good luminescence uniformity and high luminescence efficiency.

[0127] Exemplarily, using PL (photoluminescence) test means for testing to verify Figure 4 The comparison of the luminescence consistency of the epitaxial wafers prepared by the method shown in the figure and the epitaxial wafers of the control group. 100 epitaxial wafers prepared by the control group and the method disclosed in the present invention ( Figure 4 100 epitaxial wafers are prepared by the method shown in the figure, and the wavelength concentration of the peak wavelength is tested by photoluminescence testing means. For example, N points are selected on an epitaxial wafer as test samples, and the peak wavelength of these N points is tested. The number of points of the tested wavelength in the specified wavelength range is n, and the wavelength concentration is (n / N)*100%. In this test experiment, N is 500, and the experimental results can be seen in Table 1, which is a comparison of the wavelength concentration results of the epitaxial wafers prepared by the control group and the present disclosure.

[0128] Table 1. Comparison of wavelength concentration results of epitaxial wafers prepared by the control group and the present disclosure

[0129]

[0130]

[0131]

[0132] According to the comparison of the test results, the average wavelength concentration of the epitaxial wafer prepared by the disclosed solution is about 3.5% higher than that of the epitaxial wafer prepared by the control group. It can be seen that the emission wavelength of the epitaxial wafer prepared by the disclosed solution has good consistency.

[0133] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode epitaxial wafer, characterized in that: The epitaxial wafer comprises a substrate and an N-type layer, a multi-quantum well layer and a P-type layer sequentially stacked on the substrate. The multi-quantum well layer includes a plurality of well layers and barrier layers that are alternately grown in a periodic manner, and at least one of the well layers includes a first sublayer, a second sublayer and a third sublayer that are stacked in sequence, wherein the first sublayer is a Si-doped InGaN layer, the second sublayer is a C-doped InGaN layer, and the third sublayer is an Mg- and Si-doped InGaN layer.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The doping concentration of C in the second sublayer ranges from 5×10 16 cm -3 ~1×10 18 cm -3 .

3. The light emitting diode epitaxial wafer according to claim 2, characterized in that: The second sublayer is generated using triethylgallium and trimethylgallium as gallium sources, and C in the second sublayer is provided by the trimethylgallium.

4. The light emitting diode epitaxial wafer according to any one of claims 1 to 3, characterized in that: The doping concentration of Si in the first sublayer ranges from 1×10 16 cm -3 ~1×10 18 cm -3 .

5. The light emitting diode epitaxial wafer according to claim 4, characterized in that: In the first sublayer, the In component content gradually increases from a side close to the N-type layer to a side close to the P-type layer, and a maximum value of the In component content ranges from 10 wt % to 30 wt %.

6. The light emitting diode epitaxial wafer according to any one of claims 1 to 3, characterized in that: The Mg doping concentration range is 1×10 17 cm -3 ~1×10 18 cm -3 .

7. The light emitting diode epitaxial wafer according to any one of claims 1 to 3, characterized in that: The thickness of the first sublayer is in the range of The thickness of the second sublayer is in the range of The thickness range of the third sublayer is 8. A method for preparing a light emitting diode epitaxial wafer, characterized in that: The preparation method comprises: providing a substrate; An N-type layer, a multi-quantum well layer and a P-type layer are sequentially stacked and grown on the substrate, wherein the multi-quantum well layer includes a plurality of well layers and barrier layers that are alternately grown in a periodic manner, and at least one of the well layers includes a first sublayer, a second sublayer and a third sublayer that are sequentially stacked, wherein the first sublayer is a Si-doped InGaN layer, the second sublayer is a C-doped InGaN layer, and the third sublayer is an Mg- and Si-doped InGaN layer.

9. The preparation method according to claim 8, characterized in that: The concentration of C in the second sublayer ranges from 5×10 16 cm -3 ~1×10 18 cm -3 .

10. The preparation method according to claim 9, characterized in that: The second sub-layer is formed in the following manner: The second sublayer is grown using triethylgallium and trimethylgallium as gallium sources, wherein the mass fraction of trimethylgallium in the mixture of triethylgallium and trimethylgallium is (0, 10%).

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