Digital-to-analog converter sampling rate switching device, control system and method thereof, and chip

Abstract

The application discloses a digital-to-analog converter sampling rate switching device, a control system, a method and a chip, and the device comprises a clock generation module, a configuration module and a protocol establishment module. The clock generation module is used for generating a first clock signal, a second clock signal and a synchronization pulse signal, and providing the first clock signal to a digital-to-analog converter, providing the second clock signal to the configuration module, and providing the synchronization pulse signal to the protocol establishment module and the digital-to-analog converter respectively, wherein the first clock signal and the second clock signal are determined according to a target sampling rate of the digital-to-analog converter. The configuration module is used for outputting a target line rate corresponding to the target sampling rate according to the second clock signal. The protocol establishment module is used for establishing a JESD204B protocol according to the target line rate and the synchronization pulse signal, and realizing data transmission of the digital-to-analog converter switched from a current sampling rate to the target sampling rate. The device can realize flexible conversion of the sampling rate of the digital-to-analog converter by adjusting relevant parameter configurations, and does not occupy storage space.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a digital-to-analog converter sampling rate switching device, control system, method and chip based on JESD204B. Background Technology

[0002] Digital-to-analog converters (DACs) are crucial interface circuits in modern digital circuits, widely used in communication, audio, and video applications. The sampling rate, a key technical indicator of DAC operation, represents the number of samples that can be collected within a given time interval, determining the maximum frequency components of the DAC's output signal. Currently, only a small percentage of products on the market offer sampling rate switching, and most solutions rely on interpolation. This approach limits the variable sampling rate to even-numbered ratios, and due to interpolation, the actual storage space used doesn't decrease while reducing the sampling rate, effectively reducing the maximum playback time. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first objective of this application is to propose a digital-to-analog converter sampling rate switching device based on JESD204B. This device can flexibly switch the sampling rate of the digital-to-analog converter by adjusting the relevant clock frequency and parameter configuration of the JESD204B protocol, thus providing a longer storage and playback time under the condition of fixed storage space.

[0005] The second objective of this application is to propose a field-programmable gate array (FPGA) chip.

[0006] The third objective of this application is to propose a control system for a digital-to-analog converter sampling rate switching device based on JESD204B.

[0007] The fourth objective of this application is to propose a control method for a digital-to-analog converter sampling rate switching device based on JESD204B.

[0008] To achieve the above objectives, the first aspect of this application proposes a JESD204B-based digital-to-analog converter sampling rate switching device, comprising: a clock generation module, a configuration module, and a protocol establishment module. The clock generation module is connected to the configuration module and the protocol establishment module, respectively, and the configuration module is connected to the protocol establishment module. The clock generation module is used to generate a first clock signal, a second clock signal, and a synchronization pulse signal, and provides the first clock signal to the digital-to-analog converter, the second clock signal to the configuration module, and the synchronization pulse signal to the protocol establishment module and the digital-to-analog converter, respectively. The first clock signal and the second clock signal are determined according to the target sampling rate of the digital-to-analog converter. The configuration module is used to output a target line rate corresponding to the target sampling rate based on the second clock signal. The protocol establishment module is used to establish a JESD204B protocol based on the target line rate and the synchronization pulse signal, enabling the digital-to-analog converter to switch from the current sampling rate to the target sampling rate for data transmission.

[0009] According to the embodiments of this application, the digital-to-analog converter sampling rate switching device based on JESD204B can generate the clock signals required by each module through the clock generation module, generate the target line rate corresponding to the target sampling rate according to the configuration module, and re-establish the JESD204B protocol through the protocol establishment module, so as to realize the flexible switching of digital-to-analog converter sampling rate, and at the same time, under the condition of fixed storage space, it has a longer storage playback time.

[0010] To achieve the above objectives, the field-programmable gate array chip proposed in the second aspect of this application includes the digital-to-analog converter sampling rate switching device based on JESD204B described in the above embodiments of this application.

[0011] To achieve the above objectives, the control system for the JESD204B-based digital-to-analog converter sampling rate switching device proposed in the third aspect of this application includes: a digital-to-analog converter and the field-programmable gate array chip described in the above embodiments, wherein the digital-to-analog converter and the field-programmable gate array chip transmit data using the JESD204B protocol.

[0012] To achieve the above objectives, the fourth aspect of this application proposes a control method for a JESD204B-based digital-to-analog converter (DAC) sampling rate switching device. The method is characterized in that the FPGA-based DAC sampling rate switching device includes a clock generation module, a configuration module, and a protocol establishment module. The method includes: determining a target sampling rate; generating a first clock signal and a second clock signal according to the target sampling rate using the clock generation module, providing the first clock signal to the DAC, and providing the second clock signal to the configuration module; outputting a target line rate corresponding to the target sampling rate using the configuration module based on the second clock signal, and providing the target line rate to the protocol establishment module; generating a synchronization pulse signal using the clock generation module, and providing the synchronization pulse signal to both the DAC and the protocol establishment module; and establishing a JESD204B protocol using the protocol establishment module based on the target line rate and the synchronization pulse signal, thereby enabling the DAC to switch from the current sampling rate to the target sampling rate for data transmission.

[0013] According to the control method of the digital-to-analog converter sampling rate switching device based on JESD204B proposed in the embodiments of this application, a first clock signal for configuring the digital-to-analog converter and a second clock signal for configuring the field-programmable gate array chip are obtained by determining the target sampling rate. Based on the second clock signal and the target sampling rate, relevant configuration parameters can be obtained. Finally, by re-establishing the JESD204B protocol, the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission, realizing the flexible switching of the digital-to-analog converter with variable sampling. At the same time, under the condition of fixed storage space, it has a longer storage and playback time.

[0014] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0015] Figure 1 This is a structural diagram of a digital-to-analog converter sampling rate switching device based on JESD204B according to an embodiment of this application;

[0016] Figure 2 This is a structural diagram of a digital-to-analog converter sampling rate switching device based on JESD204B according to a specific embodiment of this application;

[0017] Figure 3 This is a structural diagram of a configuration module according to an embodiment of this application;

[0018] Figure 4 This is a structural diagram of the configuration module in the first specific embodiment of this application;

[0019] Figure 5 This is a structural diagram of the configuration module of the second specific embodiment of this application;

[0020] Figure 6 This is a structural diagram of the configuration module of the third specific embodiment of this application;

[0021] Figure 7 This is a control system structure diagram of a digital-to-analog converter sampling rate switching device based on JESD204B according to an embodiment of this application;

[0022] Figure 8 This is a flowchart of a control method for a digital-to-analog converter sampling rate switching device based on JESD204B according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0024] The following is a reference appendix. Figure 1-8 This application describes a digital-to-analog converter sampling rate switching device, its control system, method, and chip according to embodiments of the present application.

[0025] Figure 1 This is a structural diagram of a digital-to-analog converter sampling rate switching device based on JESD204B according to an embodiment of this application.

[0026] like Figure 1 As shown, the JESD204B-based digital-to-analog converter sampling rate switching device 1000 may include: a clock generation module 100, a configuration module 200, and a protocol establishment module 300. The clock generation module 100 is connected to the configuration module 200 and the protocol establishment module 300, respectively, and the configuration module 200 is connected to the protocol establishment module 300.

[0027] Among them, see Figure 2The clock generation module 100 generates a first clock signal DAC_DCLK, a second clock signal FPGA_DCLK, and a synchronization pulse signal SYSREF. It provides the first clock signal to the digital-to-analog converter (DAC), the second clock signal FPGA_DCLK to the configuration module 200, and the synchronization pulse signal SYSREF to both the protocol establishment module 300 and the DAC (the one provided to the protocol establishment module 300 is denoted as FPGA_SYSREF, and the one provided to the DAC is denoted as DAC_SYSREF). The first clock signal DAC_DCLK and the second clock signal FPGA_DCLK are determined based on the target sampling rate of the DAC. The configuration module 200 outputs the target line rate corresponding to the target sampling rate based on the second clock signal FPGA_DCLK. The protocol establishment module 300 establishes the JESD204B protocol based on the target line rate and the synchronization pulse signal FPGA_SYSREF, enabling the DAC to switch from the current sampling rate to the target sampling rate for data transmission.

[0028] Understandably, the JESD204B protocol is a high-speed serial interface connecting digital-to-analog converters (DACs) and field-programmable gate arrays (FPGAs), supporting serial data rates up to 12.5Gbps. It is the preferred interface protocol for data transmission between data converters and FPGAs. The JESD204B protocol uses the edge of the clock signal to identify the start of synchronization and uses certain handshake signals to enable both the sender and receiver to correctly identify the frame length and boundaries. Therefore, the clock signal and its timing relationship are extremely important for JESD204B.

[0029] In this embodiment, the clock generation module 100 generates the clock signals required by each module. Specifically, the first clock signal DAC_DCLK generated by the clock generation module 100 is provided to the digital-to-analog converter (DAC), and the second clock signal FPGA_DCLK is provided to the configuration module 200. The configuration module 200 is located in the field-programmable gate array (FPGA), meaning the clock generation module 100 provides the sampling clock to both the DAC and the FPGA. Secondly, the JESD204B protocol uses the edge of the clock signal to identify the start of synchronization. After all the internal clocks in the FPGA and the DAC are ready, the clock generation module 100 generates two synchronization pulse signals (FPGA_SYSREF and DAC_SYSREF) which are provided to the protocol establishment module 300 and the DAC, respectively, to establish the Frame clock and LFMC (Local Multi-Frame Clock) in the JESD204B protocol process. The JESD204B protocol is established after the Frame clock and LFMC are aligned.

[0030] For example, in this embodiment, a correspondence between the sampling rate and the first clock signal DAC_DCLK and the second clock signal FPGA_DCLK can be pre-established and stored. Then, based on this correspondence and the target sampling rate to be switched, the first clock signal DAC_DCLK required by the digital-to-analog converter and the second clock signal FPGA_DCLK required by the configuration module 200 in the programmable gate array chip can be obtained. The correspondence can be stored in tabular form.

[0031] Furthermore, after receiving the second clock signal FPGA_DCLK, the configuration module 200 outputs the target line rate according to the second clock signal FPGA_DCLK to provide the target line rate in the JESD204B protocol.

[0032] After the target sampling rate is output, and the sampling clocks of the digital-to-analog converter and the programmable gate array chip are ready, when the protocol establishment module 300 receives the synchronization pulse signal FPGA_SYSREF provided by the clock generation module 100, and the digital-to-analog converter receives the synchronization pulse signal DAC_SYSREF provided by the clock generation module 100, the JESD204B protocol is established to enable the digital-to-analog converter to switch from the current sampling rate to the target sampling rate for data transmission.

[0033] Figure 3 This is a structural diagram of a configuration module according to an embodiment of this application.

[0034] like Figure 3 As shown, the configuration module 200 includes a phase detector 201, a voltage-controlled oscillator 202, and a first frequency divider 203. The first input terminal of the phase detector 201 is connected to the clock generation module 100, the second input terminal of the phase detector 201 is connected to the output terminal of the first frequency divider 203, the output terminal of the phase detector 201 is connected to the input terminal of the voltage-controlled oscillator 202, and the output terminal of the voltage-controlled oscillator 202 is connected to the input terminal of the first frequency divider 203 and the protocol establishment module 300.

[0035] Among them, phase detector 201 is used to perform phase detection on the second clock signal FPGA_DCLK and the first frequency division signal output by the first frequency divider 203; voltage-controlled oscillator 202 is used to generate a third clock signal of corresponding frequency according to the phase detection result; the first frequency divider 203 is used to perform frequency division processing on the third clock signal using the first frequency division parameter to obtain the first frequency division signal.

[0036] Furthermore, the protocol establishment module 300 is used to establish the JESD204B protocol when the voltage-controlled oscillator 203 outputs a stable third clock signal.

[0037] It is understandable that the first frequency divider 203 is located between the input terminal of the phase detector 201 and the output terminal of the voltage-controlled oscillator 202, forming a feedback loop with the phase detector 201 and the voltage-controlled oscillator 202.

[0038] Specifically, the first input terminal of the phase detector 201 receives the second clock signal FPGA_DCLK generated by the clock generation module 100, and the second input terminal of the phase detector 201 receives the signal after frequency division by the first frequency divider 203. The phase detector 201 compares the frequencies of the input second clock signal FPGA_DCLK and the signal in the feedback loop formed by the first frequency divider 203, and outputs a signal representing the phase difference between the two, which serves as the input signal for the voltage-controlled oscillator 202. The phase detector 201 controls the frequency of the output signal of the voltage-controlled oscillator by performing phase detection on the signal with the phase difference between the two. The input terminal of the voltage-controlled oscillator 202 is connected to the output terminal of the phase detector 201, and outputs a periodic signal of the corresponding frequency according to the signal output by the phase detector 201. The input terminal of the first frequency divider 203 is connected to the output terminal of the voltage-controlled oscillator 202, reducing the frequency of the voltage-controlled oscillator to the same level as the second clock signal, and then inputting it to the phase detector 201 for comparison of the two signals.

[0039] Understandably, the output signal of the voltage-controlled oscillator 202, after being divided by the first frequency divider 203, is input to the phase detector 201 along with the second clock signal FPGA_DCLK. The phase detector 201 compares the frequency difference between these two signals and outputs a signal representing the two differences. This signal is then used by the voltage-controlled oscillator 202 to change the frequency of the output signal, thereby stabilizing the output of the voltage-controlled oscillator 202. The second clock signal FPGA_DCLK is generated by the clock generation module 100 and acts as a frequency-stabilized crystal oscillator. It is compared with the signal generated by the oscillation circuit inside the configuration module 200 after frequency division, ensuring the frequency of the signal output by the configuration module 200 is stable.

[0040] Figure 4 This is a structural diagram of the configuration module in the first specific embodiment of this application.

[0041] like Figure 4 As shown, the configuration module 200 may further include: a second frequency divider 204, connected between the clock generation module 100 and the first input terminal of the phase detector 201, for performing frequency division processing on the second clock signal FPGA_DCLK using the second frequency division parameter.

[0042] Specifically, the second frequency divider 204 is used to divide the second clock signal FPGA_DCLK generated by the clock generation module 100, and together with the signal after being divided by the first frequency divider 203, they are subjected to phase detection by the phase detector 201.

[0043] Figure 5 This is a structural diagram of the configuration module of the second specific embodiment of this application.

[0044] like Figure 5 As shown, the configuration module 200 also includes a third frequency divider 205, which is connected between the output of the voltage-controlled oscillator 203 and the protocol establishment module 300, and is used to perform frequency division processing on the third clock signal using the third frequency division parameter.

[0045] Specifically, the third frequency divider 205 is used to divide the signal after passing through the voltage-controlled oscillator 202. The signal after being processed by the third frequency divider 205 is the target linear rate.

[0046] For example, such as Figure 6 As shown, a low-pass filter 206 can also be connected between the phase detector 201 and the voltage-controlled oscillator 202. The low-pass filter 206 filters out high-frequency components in the configuration module 200, converting the signal into a DC pulse voltage input to the voltage-controlled oscillator 202. Wherein, f PLLClkin The second clock signal FPGA_DCLK generated by the clock generation module 100, f PLLClkin After being divided by the second frequency divider M Divider 204, the signal fed back from the first frequency divider N Divider 203 is phase-detected by the phase detector PFD 201. The low-pass filter Loop Filter 206 filters out the high-frequency components in the signal generated by the phase detector PFD 201, retaining the DC component. The voltage-controlled oscillator VCO 202 outputs a periodic signal of the corresponding frequency according to the input voltage. Subsequently, the signal is divided by the third frequency divider N Divider 205 to generate the target linear velocity f. LineRate .

[0047] As one possible implementation, the first, second, and third frequency division parameters can be obtained based on the target sampling rate.

[0048] For example, the first clock signal DAC_DCLK and the second clock signal FPGA_DCLK can be obtained first based on the target sampling rate, and then the first frequency division parameter, the second frequency division parameter and the third frequency division parameter can be obtained based on the target sampling rate and the second clock signal FPGA_DCLK.

[0049] Optionally, a correspondence table exists between the first clock signal DAC_DCLK, the second clock signal FPGA_DCLK, the first frequency division parameter, the second frequency division parameter, the third frequency division parameter, and the target sampling rate. When switching the target sampling rate, the JESD204B-based digital-to-analog converter sampling rate switching device can directly obtain the values ​​of the first clock signal DAC_DCLK (i.e., the target sampling rate), the second clock signal FPGA_DCLK, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter based on the target sampling rate to be switched. The correspondence table is shown below:

[0050]

[0051] For example, the clock generation module 100 initially generates a first clock signal DAC_DCLK and a second clock signal FPGA_DCLK of 1200MHz and 300MHz, respectively. The values ​​of the first, second, and third frequency division parameters are 40, 1, and 1, respectively. The JESD204B protocol is stably established, and the target sampling rate of the digital-to-analog converter is 1200MHz. When the target sampling rate needs to be switched to 600MHz, according to the corresponding relationship table, the clock generation module 100 generates a new first clock signal DAC_DCLK and a second clock signal FPGA_DCLK of 600MHz and 150MHz, respectively. Then, the values ​​of the first, second, and third frequency division parameters are adjusted to 80, 1, and 2, respectively, with a corresponding target line rate of 6000Mbps. The JESD204B protocol is stably established, thereby realizing the switching of the target sampling rate from 1200MHz to 600MHz.

[0052] As one possible implementation, the target linear rate, the second clock signal, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter are related by the following formula:

[0053]

[0054] Among them, f LineRate f represents the target linear velocity. PLLClkin The second clock signal is represented by N, the first frequency division parameter is represented by M, the second frequency division parameter is represented by D, and the third frequency division parameter is represented by D.

[0055] Specifically, the second clock signal FPGA_DCLK is divided by three frequency dividers with different frequency division parameters in the configuration module 200 to generate the target line rate. The conversion of the second clock signal to the target sampling rate can be achieved by adjusting the frequency division parameters of each frequency divider in the configuration module 200. The frequency division parameter of the frequency divider indicates how many times the frequency divider divides the signal. For example, when the first frequency division parameter is 40, it means that the first frequency divider 203 divides the third clock signal by 40.

[0056] It should be noted that the first clock signal DAC_DCLK, the second clock signal FPGA_DCLK, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter can be selected within a reasonable range according to actual needs, and this application does not impose any restrictions on them.

[0057] Furthermore, the clock generation module 100 is specifically used to generate a synchronization pulse signal SYSREF after generating the first clock signal DAC_DCLK and the second clock signal FPGA_DCLK.

[0058] Specifically, after the first clock signal DAC_DCLK and the second clock signal FPGA_DCLK are generated, the second clock signal FPGA_DCLK generates the target line rate through the configuration module 200, and the clock generation module 100 synchronously generates the synchronization pulse signal SYSREF, which is provided to the protocol establishment module 300 and DAC respectively. The SYNC signal is pulled low to re-establish the JESD204B protocol.

[0059] To implement the above embodiments, this application also proposes a field-programmable gate array chip, including a digital-to-analog converter sampling rate switching device based on JESD204B as described in any of the above embodiments of this application.

[0060] For example, the field-programmable gate array chip can be an FPGA with the model number XCKU040-FFVA1156.

[0061] To implement the above embodiments, this application also proposes a control system for a digital-to-analog converter sampling rate switching device based on JESD204B. Figure 7 This is a structural diagram of the control system of a digital-to-analog converter sampling rate switching device based on JESD204B according to an embodiment of this application.

[0062] like Figure 7 As shown, the control system 2000 of the JESD204B-based digital-to-analog converter sampling rate switching device includes: a digital-to-analog converter 2001 and the aforementioned field-programmable gate array chip 2002. Data transmission between the digital-to-analog converter 2001 and the field-programmable gate array chip 2002 is performed using the JESD204B protocol.

[0063] For example, the digital-to-analog converter can be a DAC37J84, which is a DAC chip that supports a maximum input data rate of 1.23 GSPS and has an ESD204B interface of 12.5 Gbps, which can be used for multiple sampling rate switching.

[0064] To achieve the above embodiments, this application also proposes a control method for a digital-to-analog converter sampling rate switching device based on JESD204B.

[0065] Figure 8 This is a flowchart of a control method for a JESD204B-based digital-to-analog converter sampling rate switching device according to an embodiment of this application. The FPGA-based digital-to-analog converter sampling rate switching device includes a clock generation module, a configuration module, and a protocol establishment module. The method may include the following steps:

[0066] S101, Determine the target sampling rate.

[0067] S102, the clock generation module generates a first clock signal and a second clock signal according to the target sampling rate, and provides the first clock signal to the digital-to-analog converter and the second clock signal to the configuration module.

[0068] S103, through the configuration module, outputs the target line rate corresponding to the target sampling rate according to the second clock signal, and provides the target line rate to the protocol establishment module.

[0069] S104 generates a synchronization pulse signal through the clock generation module and provides the synchronization pulse signal to the digital-to-analog converter and the protocol establishment module respectively.

[0070] S105 establishes the JESD204B protocol based on the target linear rate and synchronization pulse signal through the protocol establishment module, enabling the digital-to-analog converter to switch from the current sampling rate to the target sampling rate for data transmission.

[0071] It should be noted that other specific implementations of the control method of the digital-to-analog converter sampling rate switching device based on JESD204B in the embodiments of this application can be found in the specific implementations of the digital-to-analog converter sampling rate switching device based on JESD204B in the above embodiments of this application.

[0072] Furthermore, the other configurations and functions of the digital-to-analog converter and the field-programmable gate array chip in the embodiments of this application are known to those skilled in the art, and will not be described in detail here to reduce redundancy.

[0073] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0074] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0076] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0077] Furthermore, the terms "first," "second," etc., used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this application can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this application, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly and specifically defined in the embodiments.

[0078] In this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0079] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0080] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A sampling rate switching device for a digital-to-analog converter based on JESD204B, characterized in that, include: The system includes a clock generation module, a configuration module, and a protocol establishment module. The clock generation module is connected to the configuration module and the protocol establishment module, respectively. The configuration module is also connected to the protocol establishment module. The clock generation module is used to generate a first clock signal, a second clock signal, and a synchronization pulse signal, and to provide the first clock signal to the digital-to-analog converter, the second clock signal to the configuration module, and the synchronization pulse signal to the protocol establishment module and the digital-to-analog converter, respectively. The first clock signal and the second clock signal are determined according to the target sampling rate of the digital-to-analog converter. A correspondence between the sampling rate and the first clock signal and the second clock signal is pre-established, and then the first clock signal and the second clock signal required by the digital-to-analog converter are obtained according to the target sampling rate to be switched based on the correspondence. The configuration module is used to output the target line rate corresponding to the target sampling rate according to the second clock signal; The protocol establishment module is used to establish a JESD204B protocol based on the target line rate and the synchronization pulse signal, so as to enable the digital-to-analog converter to switch from the current sampling rate to the target sampling rate for data transmission.

2. The digital-to-analog converter sampling rate switching device based on JESD204B according to claim 1, characterized in that, The configuration module includes: a phase detector, a voltage-controlled oscillator (VCO), and a first frequency divider. The first input terminal of the phase detector is connected to the clock generation module, the second input terminal of the phase detector is connected to the output terminal of the first frequency divider, the output terminal of the phase detector is connected to the input terminal of the VCO, and the output terminal of the VCO is connected to the input terminal of the first frequency divider and the protocol establishment module. The phase detector is used to perform phase detection on the second clock signal and the first frequency division signal output by the first frequency divider; The voltage-controlled oscillator is used to generate a third clock signal of a corresponding frequency based on the phase detection result; The first frequency divider is used to divide the third clock signal using a first frequency division parameter to obtain the first frequency divided signal; The protocol establishment module is used to establish the JESD204B protocol when the voltage-controlled oscillator outputs a stable third clock signal.

3. The digital-to-analog converter sampling rate switching device based on JESD204B according to claim 2, characterized in that, The configuration module also includes: The second frequency divider is connected between the clock generation module and the first input terminal of the phase detector, and is used to perform frequency division processing on the second clock signal using the second frequency division parameter.

4. The digital-to-analog converter sampling rate switching device based on JESD204B according to claim 3, characterized in that, The configuration module also includes: The third frequency divider is connected between the output of the voltage-controlled oscillator and the protocol establishment module, and is used to perform frequency division processing on the third clock signal using the third frequency division parameter.

5. The digital-to-analog converter sampling rate switching device based on JESD204B according to claim 4, characterized in that, The first frequency division parameter, the second frequency division parameter, and the third frequency division parameter are obtained based on the target sampling rate.

6. The digital-to-analog converter sampling rate switching device based on JESD204B according to claim 5, characterized in that, The target linear rate, the second clock signal, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter have the following relationship: in, Indicates the target linear velocity. N represents the second clock signal, M represents the first frequency division parameter, and D represents the third frequency division parameter.

7. The digital-to-analog converter sampling rate switching device based on JESD204B according to any one of claims 1-6, wherein the clock generation module is specifically used to: generate the synchronization pulse signal after generating the first clock signal and the second clock signal.

8. A field-programmable gate array (FPGA) chip, characterized in that, Includes a digital-to-analog converter sampling rate switching device based on JESD204B as described in any one of claims 1-7.

9. A control system for a digital-to-analog converter sampling rate switching device based on JESD204B, characterized in that, include: The digital-to-analog converter and the field-programmable gate array chip as described in claim 8, wherein the digital-to-analog converter and the field-programmable gate array chip transmit data using the JESD204B protocol.

10. A control method for a digital-to-analog converter sampling rate switching device based on JESD204B, characterized in that, The FPGA-based digital-to-analog converter sampling rate switching device includes a clock generation module, a configuration module, and a protocol establishment module. The method includes: Determine the target sampling rate; The clock generation module generates a first clock signal and a second clock signal according to the target sampling rate, and provides the first clock signal to the digital-to-analog converter and the second clock signal to the configuration module; a correspondence between the sampling rate and the first clock signal and the second clock signal is established in advance, and then the first clock signal and the second clock signal required by the digital-to-analog converter are obtained according to the target sampling rate to be switched according to the correspondence; The configuration module outputs the target line rate corresponding to the target sampling rate according to the second clock signal, and provides the target line rate to the protocol establishment module; The clock generation module generates a synchronization pulse signal, which is then provided to the digital-to-analog converter and the protocol establishment module, respectively. The protocol establishment module establishes the JESD204B protocol based on the target line rate and the synchronization pulse signal, enabling the digital-to-analog converter to switch from the current sampling rate to the target sampling rate for data transmission.

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