Video Pixel Clock Recovery Method and Structure for DP Interface

Abstract

The video pixel clock recovery method and structure for DP interface provided by the present invention belong to the technical field of DP video signals, and include: obtaining, through DP decoding, the end flag signal generated by the transmission of each row of video data and the number of pixels of each row of video data; sampling the end flag signal by means of the high-speed link clock; calculating the reference clock count corresponding to the corresponding row based on two adjacent end flag signals; taking the number of pixels as the M value and the reference clock count as the N value, and recovering the target pixel clock of each pixel in the video data of the corresponding row. By obtaining the target signal through DP decoding and performing operations according to the target signal to generate another set of M and N values for recovering the target pixel clock, the present invention does not need to use the M and N values decoded by the transmitting end, overcomes the problem in the prior art that the transmitting end will turn on SSC, causing fluctuations in the high-speed link clock, resulting in the inability of the M and N values to accurately correspond to the high-speed link clock, having errors and making the clock recovery take a long time to stabilize.

Description

Technical Field

[0001] The present invention relates to the technical field of DP video signal, and in particular to a method and structure for video pixel clock recovery for a DP interface. Background Art

[0002] In the DP interface protocol, data transmission depends on one to four high-speed links. The minimum rate of each link is 1.62 Gbps. When applying for video transmission, the DP transmitter encodes the video data and then sends it. The DP receiver needs to perform clock recovery to obtain the pixel clock, that is, the video pixel transmission frequency, so as to process the received video data in units of pixels. According to the DP protocol, the transmitter needs to send a set of M values and N values in the data stream, and the ratio of these two values should be equal to the ratio of the rate of the DP high-speed link to the target pixel clock rate. The DP receiver can process these two values and use a digital PLL to perform clock recovery, so as to obtain the frequency of the pixel clock and generate a pixel clock signal for internal video data processing.

[0003] In the previously designed circuit that fully complies with the DP protocol, the digital circuit uses the M value and N value decoded from the transmitter to generate the pixel clock from the high-speed link clock. However, in actual applications, it is found that during the process of generating the pixel clock, since the transmitter may turn on the spread spectrum clock (SSC), the high-speed link clock frequency may have a certain fluctuation. Also, since the frequency of sending the M value and N value by the DP transmitter is low and the speed is slow, the real-time performance is relatively poor. Therefore, in the initial stage, the M value and N value may not accurately correspond to the high-speed link clock frequency, and the DP receiver needs a long time to adapt to the changing high-speed link clock, that is, it takes a long time for the clock recovery to stabilize. Summary of the Invention

[0004] The technical problem of the present invention is to provide a method and structure for video pixel clock recovery for a DP interface, which do not use the M value and N value sent by the DP transmitter, and generate a set of M values and N values by themselves to participate in the recovery of the target pixel clock, so as to improve the speed at which the target pixel clock enters the stable state.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] Video pixel clock recovery method for DP interface, comprising the following steps: obtaining a target signal through DP decoding; wherein the target signal includes: an end flag signal generated by sending each line of video data and the number of pixels of each line of video data; sampling the target signal by a high-speed link clock; calculating the reference clock count of the corresponding line based on two adjacent end flag signals; taking the number of pixels as the M value and the reference clock count as the N value, and recovering the target pixel clock of each pixel in the video data of the corresponding line. The present invention obtains the target signal through DP decoding, and generates another set of M and N values by itself according to the target signal to recover the target pixel clock, without using the M and N values decoded by the sending end, overcoming the technical problem in the prior art that the sending end will turn on SSC, causing fluctuations in the high-speed link clock, resulting in the M and N values not being able to accurately correspond to the high-speed link clock, and making the clock recovery take a long time to stabilize. It can perform clock recovery quickly and accurately, and avoid potential errors brought by SSC.

[0007] Further, calculating the reference clock count of the corresponding line based on two adjacent end flag signals includes: using a low-speed reference clock to record the time between the rising edges of two adjacent end flag signals to obtain the reference clock count.

[0008] Further, taking the number of pixels as the M value and the reference clock count as the N value to recover the target pixel clock includes: obtaining the ratio of the M value to the N value through division operation; modulating the fractional part of the ratio by a modulator to output a modulated integer value; and a digital PLL module calculating and recovering the target pixel clock of each pixel in the video data of the corresponding line according to the modulated integer value.

[0009] Video pixel clock recovery structure for DP interface, comprising a DP sending end and a DP receiving end. The DP sending end includes an encoding module; the DP receiving end includes a pre-stage circuit, an operation module, a divider, a modulator and a digital PLL module; the receiving end of the pre-stage circuit is connected to the sending end of the encoding module, the sending end of the pre-stage circuit is connected to the receiving end of the operation module, the sending end of the operation module is connected to the receiving end of the divider, the sending end of the divider is connected to the receiving end of the modulator, and the sending end of the modulator is connected to the receiving end of the digital PLL module; the pre-stage circuit is used to obtain a target signal, wherein the target signal includes: an end flag signal generated by sending each line of video data and the number of pixels of each line of video data; and obtaining the reference clock count based on the end flag signal; the operation module is used to assign the number of pixels of the video data to M and the reference clock count to N; the divider is used to obtain the integer and fractional parts of the ratio of M to N through division operation; the modulator is used to modulate the fractional part of the ratio of M to N to output a modulated integer value; the digital PLL module is used to calculate and recover the target pixel clock of each pixel in the video data of the corresponding line according to the modulated integer value.

[0010] Further, the pre-stage circuit includes: a decoding module and a digital module; the decoding module is configured to decode a target signal from the DP transmitting end; the digital module is configured to sample the target signal by a high-speed link clock, and record the time between the rising edges of two adjacent end flag signals by a low-speed reference clock to obtain a reference clock count. Brief Description of the Drawings

[0011] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, the present invention and its features, shapes, and advantages will become more apparent. The same reference numerals indicate the same parts in all the drawings. The drawings are not necessarily drawn to scale, and the emphasis is on showing the gist of the present invention.

[0012] Figure 1 is a flowchart of a video pixel clock recovery method for a DP interface provided by the present invention;

[0013] Figure 2 is a schematic diagram of a video pixel clock recovery structure for a DP interface provided by the present invention; Detailed Embodiments

[0014] The present invention will be further described below with reference to the drawings and specific embodiments, but it is not intended to limit the present invention.

[0015] In the prior art, digital circuits generally generate a target pixel clock from the M value and N value decoded by the DP transmitting end. The M and N values of the DP protocol respectively correspond to the target pixel clock rate and the high-speed link clock rate. However, in actual applications, it is found that during the process of generating the target pixel clock in this way, the transmitting end may turn on the spread spectrum clock SSC. Since the update frequency of the M and N values obtained from the DP transmitting end is relatively slow, and the spread spectrum clock SSC causes the high-speed link clock to have a certain fluctuation, the M and N values cannot accurately correspond to the frequency of the high-speed link clock, resulting in the clock recovery taking a long time to stabilize.

[0016] To solve the above technical problems, the present invention provides a video pixel clock recovery method for a DP interface, as Figure 1As shown, it includes the following steps: First, obtain the target signal through DP decoding; the target signal includes: the end flag signal generated by the transmission of each line of video data and the number of pixels of each line of video data; the end flag signal generated by the transmission of each line of video data specifically refers to the BS signal or the CPBS signal. Whether it is actually the BS signal or the CPBS signal is specified by the DP protocol and depends on whether the DP video transmission enables the HDCP mode. In the HDCP mode, the CPBS signal is used; otherwise, the BS signal is used. The functions they achieve in their respective modes are the same. The number of pixels of each line of video data specifically refers to the HTOTAL signal, which is specified by the DP protocol. The number of pixels per line in the video format, that is, HTOTAL, should be updated at the frequency of once per frame in the MSA data packet.

[0017] Then, the digital module samples the BS signal or the CPBS signal through the high-speed link clock, records the time between the rising edges of two adjacent BS signals or CPBS signals using the low-speed reference clock, and obtains the reference clock count REF_CNT for the corresponding line. During this time interval, the video signal completes the transmission of one line of pixels, and the number of its pixels is HTOTAL.

[0018] Then, take the number of pixels as the M value and the reference clock count as the N value. That is, in the present invention, the M and N values respectively correspond to the target pixel clock rate and the reference clock rate. Then, perform a division operation through a divider to obtain the integer part INT and the fractional part FRAC of the ratio of the M value to the N value. Then, use a modulator Delta-Sigma to modulate the fractional part of the ratio and output the modulation integer value MULT. The role of modulation is to convert the fractional part obtained from M / N into a single integer and output it to the digital PLL module. For example, if M / N = 9.7, the delta-sigma modulator will output 10 70% of the time and 9 30% of the time. In this way, on average, the digital PLL module obtains 9.7. Finally, the digital PLL module calculates and restores the target pixel clock PIXEL CLOCK for each pixel in the video data of the corresponding line according to the modulation integer value MULT. The specific formula refers to (M / N) * reference clock frequency = target clock frequency.

[0019] The present invention also provides a video pixel clock recovery structure for the DP interface, such as Figure 2As shown, it includes a DP transmitter and a DP receiver. The DP transmitter includes an encoding module; the DP receiver includes a pre-stage circuit, an arithmetic module, a divider, a modulator, and a digital PLL module; the receiving end of the pre-stage circuit is connected to the transmitting end of the encoding module, the transmitting end of the pre-stage circuit is connected to the receiving end of the arithmetic module, the transmitting end of the arithmetic module is connected to the receiving end of the divider, the transmitting end of the divider is connected to the receiving end of the modulator, and the transmitting end of the modulator is connected to the receiving end of the digital PLL module; the pre-stage circuit is used to obtain a target signal, where the target signal includes: an end flag signal generated by the transmission of each row of video data and the number of pixels of each row of video data; and obtain a reference clock count based on the end flag signal; the pre-stage circuit includes: a decoding module and a digital module; the decoding module is used to decode and obtain the target signal from the DP transmitter; the digital module is used to sample the target signal through a high-speed link clock and record the time between the rising edges of two adjacent end flag signals through a low-speed reference clock to obtain a reference clock count. The arithmetic module is used to assign the number of pixels of the video data to M and assign the reference clock count to N; the divider is used to obtain the integer and fractional parts of the ratio of M to N through division operations; the modulator is used to modulate the fractional part of the ratio of M to N and output a modulated integer value; the digital PLL module is used to calculate and recover the target pixel clock of each pixel in the corresponding row of video data according to the modulated integer value.

[0020] In summary, the present invention generates another set of M values and N values by itself to recover the target pixel clock, without the need to use the M and N values decoded by the transmitter, overcoming the technical problem in the prior art that the transmitter will turn on SSC, causing fluctuations in the high-speed link clock, resulting in the inability of the M and N values to accurately correspond to the high-speed link clock, and making the clock recovery take a long time to stabilize. It can perform clock recovery quickly and accurately, avoid potential errors brought by SSC, and at the same time reduce the waiting time from when the DP interface is accessed to the output of the video signal. In addition, by using the low-speed reference clock generated by the crystal oscillator and the integer PLL module to generate the target pixel clock, it can improve the stability while simplifying the circuit design difficulty, further ensuring that the pixel clock frequency can enter a stable state in a shorter time, accelerating the video output process, and enhancing the user experience.

[0021] The preferred embodiments of the present invention have been described above; it should be understood that the present invention is not limited to the above specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any person skilled in the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, which does not affect the essence of the present invention; therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A video pixel clock recovery method for a DP interface, characterized in that It includes the following steps: DP decoding to obtain the target signal; wherein the target signal includes: an end flag signal generated by the transmission of each line of video data and the number of pixels of each line of video data; sampling the target signal by a high-speed link clock; calculating the reference clock count of the corresponding line based on two adjacent end flag signals; taking the number of pixels as the M value, taking the reference clock count as the N value, and restoring the target pixel clock of each pixel in the video data of the corresponding line; The calculating the reference clock count of the corresponding line based on two adjacent end flag signals includes: using a low-speed reference clock to record the time between the rising edges of two adjacent end flag signals to obtain the reference clock count; The taking the number of pixels as the M value, taking the reference clock count as the N value, and restoring the target pixel clock includes: obtaining the ratio of the M value to the N value through division operation; modulating the decimal part of the ratio by a modulator to output a modulated integer value; The digital PLL module calculates and restores the target pixel clock of each pixel in the video data of the corresponding line according to the modulated integer value.

2. A video pixel clock recovery structure for a DP interface, based on the video pixel clock recovery method for a DP interface according to claim 1, comprising a DP transmitter and a DP receiver, wherein the DP transmitter includes an encoding module; characterized in that, The DP receiver includes a pre-stage circuit, an operation module, a divider, a modulator, and a digital PLL module; the receiving end of the pre-stage circuit is connected to the sending end of the encoding module, the sending end of the pre-stage circuit is connected to the receiving end of the operation module, the sending end of the operation module is connected to the receiving end of the divider, the sending end of the divider is connected to the receiving end of the modulator, and the sending end of the modulator is connected to the receiving end of the digital PLL module; The pre-stage circuit is used to obtain the target signal, wherein the target signal includes: an end flag signal generated by the transmission of each line of video data and the number of pixels of each line of video data; and obtaining the reference clock count based on the end flag signal; the operation module is used to assign the number of pixels of the video data to M and assign the reference clock count to N; the divider is used to obtain the integer and decimal parts of the ratio of M to N through division operation; the modulator is used to modulate the decimal part of the ratio of M to N and output a modulated integer value; the digital PLL module is used to calculate and restore the target pixel clock of each pixel in the video data of the corresponding line according to the modulated integer value.

3. The video pixel clock recovery structure for a DP interface according to claim 2, wherein The pre-stage circuit includes: a decoding module and a digital module; The decoding module is used to decode and obtain the target signal from the DP sending end; The digital module is used to sample the target signal by a high-speed link clock and record the time between the rising edges of two adjacent end flag signals by a low-speed reference clock to obtain the reference clock count.

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