Chip detection circuits and electronic equipment

Abstract

The present application provides a chip detection circuit and electronic device, the chip detection circuit includes: a phase-locked loop, a signal generation module, a clock recovery module and a signal detector; the signal generation module is used to convert a first clock into random code data, and convert the random code data into a differential analog signal; the clock recovery module is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain the locked first clock, and then recover the differential analog signal to obtain the recovered data; the signal detector is used to determine whether the recovered data is the same as the predetermined data, and obtain a judgment result. When the judgment result is used to characterize that the recovered data is not the same as the predetermined data, the chip is determined to be an abnormal chip. Thus, the problem of low efficiency in screening out bad chips in the existing solution is solved.

Description

Technical Field

[0001] The present application relates to the field of chip detection technology, and in particular to a chip detection circuit and electronic equipment. Background Art

[0002] As the integration of chips becomes higher and higher, there are more and more cases where two, three or even more chips are integrated in the same package. In order to ensure the yield of the chip, all functions of the final chip must be tested. If one of the sub-chips is a bad chip, then the other sub-chips in the package will also be screened out, resulting in waste and increased costs. If certain functions can be tested before each chip is packaged to screen out the bad chips, other good chips will not be wasted. High-speed receiving circuits usually use external loopback testing methods, which generally require specific peripheral components to achieve signal transmission and detection and are supplemented by certain software programs.

[0003] Therefore, a method for testing a chip on a chip without requiring external components is needed. Summary of the invention

[0004] The main purpose of the present application is to provide a chip detection circuit and electronic equipment to solve the problem of low efficiency in bad chip screening in existing solutions.

[0005] According to one aspect of an embodiment of the present invention, a chip detection circuit is provided, which includes a phase-locked loop, a signal generating module, a clock recovery module and a signal detector; the phase-locked loop has a first output end and a second output end, the first output end of the phase-locked loop is used to output a first clock, and the second output end of the phase-locked loop is used to output a second clock, wherein the first clock is the highest frequency clock of the phase-locked loop, and the frequency of the second clock is equal to the frequency of the first clock; the signal generating module has an input end and an output end, the input end of the signal generating module is electrically connected to the first output end of the phase-locked loop, and the signal generating module is used to convert the first clock into random code data, and convert the random code data into a differential analog signal; the clock recovery module has a first input end, a second input end and an output end, the first input end of the clock recovery module is electrically connected to the output end of the signal generating module, and the second input end of the clock recovery module is electrically connected to the output end of the signal generating module. The end is electrically connected to the second output end of the phase-locked loop, the clock recovery module is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain the locked first clock, and then recover the differential analog signal to obtain the recovered data, and the output end of the clock recovery module is used to output the recovered data and the locked first clock; the signal detector has an input end, the input end of the signal detector is electrically connected to the output end of the clock recovery module, the signal detector is used to determine whether the recovered data is the same as the predetermined data, and obtain a judgment result. When the judgment result is used to characterize that the recovered data is the same as the predetermined data, the chip is determined to be a normal chip; when the judgment result is used to characterize that the recovered data is not the same as the predetermined data, the chip is determined to be an abnormal chip, wherein the predetermined data is used to characterize that the chip is in a normal state.

[0006] Optionally, the clock recovery module includes a clock recovery circuit and a phase interleaver; the clock recovery circuit is electrically connected to the output end of the signal generating module and the input end of the signal detector, respectively, and the clock recovery circuit is used to recover the differential analog signal to obtain recovered data; the phase interleaver is electrically connected to the clock recovery circuit and the second output end of the phase-locked loop, respectively, and the phase interleaver is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain a locked first clock.

[0007] Optionally, the clock recovery module includes a frequency detector and a phase detector, which are electrically connected to the clock recovery circuit and are used to determine a method for adjusting the phase of the first clock, and the method for adjusting the phase of the first clock is to increase the phase of the first clock or to decrease the phase of the first clock.

[0008] Optionally, the signal generating module includes a signal generator and a transmitter; the signal generator is electrically connected to the first output end of the phase-locked loop, and the signal generator is used to convert the first clock into random code data; the transmitter is electrically connected to the signal generator and the clock recovery circuit respectively, and the transmitter is used to convert the random code data into a differential analog signal, and send the differential analog signal to the clock recovery circuit.

[0009] Optionally, the signal detector also has an output end, and the chip detection circuit also includes an error generator and a controller, the error generator is electrically connected to the clock recovery circuit, and the error generator is used to output the control code to the clock recovery circuit; the controller is electrically connected to the phase-locked loop, the output end of the signal detector and the error generator, respectively, and the controller is used to wake up the error generator after the signal detector outputs the judgment result.

[0010] Optionally, the phase-locked loop also has a third output terminal, and the third output terminal of the phase-locked loop is used to output a third clock. The chip detection circuit also includes a frequency comparator, which is electrically connected to the phase interleaver and the third output terminal of the phase-locked loop respectively. The frequency comparator is used to receive the deviation clock output by the phase interleaver, and compare the deviation clock with the third clock to obtain a comparison result, wherein the deviation clock is obtained after the phase interleaver locks the phase of the control coding clock with the phase of the second clock.

[0011] Optionally, the chip detection circuit further includes a first serial port, and the first serial port is electrically connected to the output end of the signal detector and the controller respectively.

[0012] Optionally, the chip detection circuit also includes a serial-to-parallel module; the serial-to-parallel module is electrically connected to the input ends of the clock recovery circuit and the signal detector, respectively, and is used to down-convert the recovered data to obtain down-converted data.

[0013] Optionally, the chip detection circuit further includes a second serial port, and the second serial port is electrically connected to the frequency comparator and the controller respectively.

[0014] According to another aspect of an embodiment of the present invention, there is further provided an electronic device, the electronic device comprising any one of the chip detection circuits described above.

[0015] In an embodiment of the present invention, the phase of the first clock of the differential analog signal is locked with the phase of the second clock through a clock recovery module to obtain a locked first clock, and then the differential analog signal is recovered to obtain recovered data. The output end of the clock recovery module is used to output the recovered data and the locked first clock, and the signal detector then determines whether the recovered data is the same as the predetermined data. When the recovered data is the same as the predetermined data, it is determined that the chip is normal, otherwise it is abnormal, thereby solving the problem of low efficiency in screening out bad chips in the existing solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic diagram of a chip detection circuit according to an embodiment of the present application is shown.

[0018] The above drawings include the following reference numerals:

[0019] 10. Phase-locked loop; 20. Signal generation module; 21. Signal generator; 22. Transmitter; 30. Clock recovery module; 31. Clock recovery circuit; 32. Phase interleaver; 33. Phase and frequency detector; 34. Analog front end; 40. Signal detector; 50. Error generator; 60. Controller; 70. Frequency comparator; 80. Serial-to-parallel module. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0024] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0025] Phase interleaver: The input is the 4 phases of a clock (0 degrees, 90 degrees, 180 degrees, 270 degrees), and the output is the clock after phase adjustment (same frequency but different phase), whose phase is any one of the 256 phases between 0 degrees and 360 degrees.

[0026] Signal generator: Pseudo-random code generator is not a truly random sequence, but a repeatable sequence with certain rules generated by a relatively complex algorithm. It has the statistical characteristics of random noise, as well as regularity and repeatability.

[0027] Signal detector: Pseudo-random code checker, the input is a string of digital sequence and a clock synchronized with the sequence, and the output is an indication signal. The sequence is detected, if it conforms to the known regularity, the indication signal is 1, if there is a data in the sequence that does not conform to the regularity, the indication signal is 0.

[0028] Serial-to-parallel module: The input is 1-bit data and a clock synchronized with the data. Usually, the clock frequency is high, and the output is multi-bit data and a clock synchronized with the data. Common output bit widths are 10-bit, 20-bit, 32-bit, etc. The serial-to-parallel module converts the input high-speed single-bit data and clock into low-speed multi-bit data that can be processed by subsequent digital circuits.

[0029] Error generator: A frequency error generator uses a certain algorithm to add a fixed frequency deviation to the original clock to obtain another clock.

[0030] As mentioned in the background technology, in the existing solution, when all functions of the final chip are tested, if one of the sub-chips is a bad chip, then other sub-chips in the package will also be screened out, causing waste and increasing costs. In order to solve the problem of low efficiency in screening out bad chips in the existing solution, a chip detection circuit and electronic equipment are provided in a typical embodiment of the present application.

[0031] According to an embodiment of the present application, a chip detection circuit is provided, such as Figure 1 As shown, the chip detection circuit includes a phase-locked loop 10, a signal generating module 20, a clock recovery module 30 and a signal detector 40; the phase-locked loop 10 has a first output end and a second output end, the first output end of the phase-locked loop 10 is used to output a first clock, and the second output end of the phase-locked loop 10 is used to output a second clock, wherein the first clock is the highest frequency clock of the phase-locked loop 10, and the frequency of the second clock is equal to the frequency of the first clock; the signal generating module 20 has an input end and an output end, the input end of the signal generating module 20 is electrically connected to the first output end of the phase-locked loop 10, and the signal generating module 20 is used to convert the first clock into random code data, and convert the random code data into a differential analog signal; the clock recovery module 30 has a first input end, a second input end and an output end, the first input end of the clock recovery module 30 is electrically connected to the output end of the signal generating module 20, and the second input end of the clock recovery module 30 is electrically connected to the output end of the signal generating module 20 The second output end of the phase-locked loop 10 is electrically connected, and the clock recovery module 30 is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain the locked first clock, and then recover the differential analog signal to obtain the recovered data. The output end of the clock recovery module 30 is used to output the recovered data and the locked first clock; the signal detector 40 has an input end, and the input end of the signal detector 40 is electrically connected to the output end of the clock recovery module 30. The signal detector 40 is used to determine whether the recovered data is the same as the predetermined data to obtain a judgment result. When the judgment result is used to characterize that the recovered data is the same as the predetermined data, the chip is determined to be a normal chip; when the judgment result is used to characterize that the recovered data is not the same as the predetermined data, the chip is determined to be an abnormal chip, wherein the predetermined data is used to characterize that the chip is in a normal state.

[0032] In the chip detection circuit, the phase of the first clock of the differential analog signal is locked with the phase of the second clock through the clock recovery module to obtain the locked first clock, and then the differential analog signal is recovered to obtain the recovered data. The output end of the clock recovery module is used to output the recovered data and the locked first clock. The signal detector then determines whether the recovered data is the same as the predetermined data. When the recovered data is the same as the predetermined data, it is determined that the chip is normal, otherwise it is abnormal, thereby solving the problem of low efficiency in screening out bad chips in the existing solution. Compared with the original circuit scale of less than 5%, the layout area increases by less than 3%. Through hardware automatic control, the test time cost is reduced.

[0033] In order to ensure the performance of the test chip, the chip operates at the highest speed during the test. If the chip can pass the test at the highest speed, there is basically no need to test other low speeds. This is because the chip's manufacturing defects, timing performance, etc. have been verified, and only a small part of the logic control at other rates has not been verified.

[0034] In one embodiment of the present application, Figure 1 As shown, the clock recovery module 30 includes a clock recovery circuit 31 and a phase interleaver 32; the clock recovery circuit 31 is electrically connected to the output end of the signal generating module 20 and the input end of the signal detector 40, respectively, and the clock recovery circuit 31 is used to perform recovery processing on the differential analog signal to obtain recovered data; the phase interleaver 32 is electrically connected to the clock recovery circuit 31 and the second output end of the phase-locked loop 10, respectively, and the phase interleaver 32 is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain the locked first clock.

[0035] Specifically, by locking the phase of the first clock of the differential analog signal with the phase of the second clock, the differential analog signal can be restored to obtain restored data.

[0036] In one embodiment of the present application, Figure 1 As shown, the clock recovery module 30 includes a frequency detector 33, which is electrically connected to the clock recovery circuit 31 and is used to determine the method of adjusting the phase of the first clock, and the method of adjusting the phase of the first clock is to increase the phase of the first clock or to reduce the phase of the first clock. The clock recovery module 30 also includes an analog front end 34, which is electrically connected to the frequency detector 33 and the output end of the signal generation module 20, respectively, and is used to receive the differential analog signal and transmit the differential analog signal to the clock recovery circuit 31.

[0037] Specifically, the method of adjusting the phase of the above-mentioned first clock is determined by a frequency detector and a phase detector, so that the phase interleaver can lock the phase of the first clock of the above-mentioned differential analog signal with the phase of the above-mentioned second clock, that is, adjust the phase of the first clock so that the phase of the first clock is consistent with the phase of the second clock, for example, the frequency of the second clock is the same as the frequency of the first clock.

[0038] In one embodiment of the present application, Figure 1 As shown, the signal generating module 20 includes a signal generator 21 and a transmitter 22; the signal generator 21 is electrically connected to the first output end of the phase-locked loop 10, and the signal generator 21 is used to convert the first clock into random code data; the transmitter 22 is electrically connected to the signal generator 21 and the clock recovery circuit 31, respectively, and the transmitter is used to convert the random code data into a differential analog signal, and send the differential analog signal to the clock recovery circuit.

[0039] Specifically, the transmitter is a driving circuit. Since the load is very light and is only the parasitic capacitance and resistance on the chip, it does not require particularly strong driving capability. At the same time, there is no off-chip routing, so there is no need to consider the transmission line effect, avoiding impedance matching. Only a single-stage differential structure is required, which can increase the area and power consumption of the driver by less than 1%.

[0040] In one embodiment of the present application, Figure 1 As shown, the signal detector 40 also has an output end, and the chip detection circuit also includes an error generator 50 and a controller 60. The error generator 50 is electrically connected to the clock recovery circuit 31, and the error generator 50 is used to output the control code to the clock recovery circuit 31; the controller 60 is electrically connected to the phase-locked loop 10, the output end of the signal detector 40 and the error generator 50, respectively, and the controller 60 is used to wake up the error generator 50 after the signal detector 40 outputs the judgment result.

[0041] Specifically, the control code output by the error generator causes the clock output by the phase interleaver to continuously change in its 256 phases, rather than staying at a fixed phase, which is equivalent to superimposing a fixed frequency deviation on the original phase-locked loop clock, thereby improving the test coverage. The controller wakes up the error generator after the signal detector outputs the judgment result, or wakes up the error generator only when the judgment result is used to characterize the chip abnormality.

[0042] In one embodiment of the present application, Figure 1As shown, the phase-locked loop 10 also has a third output terminal, and the third output terminal of the phase-locked loop 10 is used to output a third clock. The chip detection circuit also includes a frequency comparator 70, and the frequency comparator 70 is electrically connected to the phase interleaver 32 and the third output terminal of the phase-locked loop 10 respectively. The frequency comparator 70 is used to receive the deviation clock output by the phase interleaver 32, and compare the deviation clock with the third clock to obtain a comparison result, wherein the deviation clock is obtained after the phase interleaver 32 locks the phase of the control coded clock with the phase of the second clock.

[0043] Specifically, the above comparison result is used to characterize the difference between the frequency of the deviation clock and the frequency of the third clock. When the above difference is equal to the predetermined difference, the chip is determined to be a normal chip. When the difference is greater than or less than the predetermined difference, the chip is determined to be an abnormal chip. The deviation clock is used to improve the test coverage. When the above difference is greater than or less than the predetermined difference, a bad chip judgment signal is generated and sent to the controller. The frequency of the third clock is the same as the frequency of the first clock.

[0044] In one embodiment of the present application, the chip detection circuit further includes a first serial port, which is electrically connected to the output end of the signal detector and the controller respectively. When the first probe of the controller contacts the first serial port, a judgment result of whether the recovered data is the same as the predetermined data can be obtained.

[0045] In one embodiment of the present application, Figure 1 As shown, the chip detection circuit also includes a serial-to-parallel module 80, which is electrically connected to the input ends of the clock recovery circuit 31 and the signal detector 40, respectively, and is used to down-convert the recovered data to obtain down-converted data. The purpose of down-converting is to allow subsequent digital circuits (i.e., the signal detector 40) to process it. If the frequency is too high, the digital circuit cannot work normally.

[0046] In one embodiment of the present application, the chip detection circuit further includes a second serial port, which is electrically connected to the frequency comparator and the controller respectively. When the second probe of the controller contacts the second serial port, a bad chip judgment signal can be obtained.

[0047] Through the phase-locked loop, signal generation module, clock recovery module and signal detector, it can cover 100% of the analog front end (usually the high-speed receiving circuit requires an analog front end to compensate for the attenuation of the input analog signal and adjust the gain. The analog front end is AFE, Anaglog Front-End), the functions of the frequency detector and serial-to-parallel module, 80% of the phase-locked loop functions, and 50% of the clock recovery circuit and phase interleaver functions. This is because the clock of the phase-locked loop and the data sent by the transmitter are of the same source and there is no frequency deviation, which causes the output clock of the phase interleaver to stay at a fixed phase. In actual applications, the crystal oscillators of the transmitting and receiving chips cannot be absolutely equal. Therefore, through the phase-locked loop, clock recovery module, error generator, frequency comparator and controller, a certain frequency deviation is injected to make the output clock of the phase interleaver switch slowly between the phases, thereby increasing the coverage of the clock recovery circuit and phase interleaver to 100%.

[0048] According to another aspect of an embodiment of the present invention, an electronic device is also provided, which includes any one of the above-mentioned chip detection circuits. The phase of the first clock of the above-mentioned differential analog signal is locked with the phase of the above-mentioned second clock through a clock recovery module to obtain a locked first clock, and then the above-mentioned differential analog signal is recovered to obtain recovered data. The output end of the above-mentioned clock recovery module is used to output the above-mentioned recovered data and the above-mentioned locked first clock. The signal detector then determines whether the above-mentioned recovered data is the same as the predetermined data. When the above-mentioned recovered data is the same as the predetermined data, it is determined that the chip is normal, otherwise it is abnormal, thereby solving the problem of low efficiency in screening out bad chips in the existing solution.

[0049] It should be noted that the above electrical connection can be a direct electrical connection or an indirect electrical connection. Direct electrical connection means that two devices are directly connected, and indirect electrical connection means that other devices such as capacitors and resistors are also connected between the connected A and B.

[0050] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0051] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0052] 1) The chip detection circuit of the present application uses a clock recovery module to lock the phase of the first clock of the above-mentioned differential analog signal with the phase of the above-mentioned second clock to obtain the locked first clock, and then recovers the above-mentioned differential analog signal to obtain the recovered data. The output end of the above-mentioned clock recovery module is used to output the above-mentioned recovered data and the above-mentioned locked first clock. The signal detector then determines whether the above-mentioned recovered data is the same as the predetermined data. When the above-mentioned recovered data is the same as the predetermined data, it is determined that the chip is normal, otherwise it is abnormal, thereby solving the problem of low efficiency in screening out bad chips in the existing solution.

[0053] 2) The electronic device of the present application uses a clock recovery module to lock the phase of the first clock of the above-mentioned differential analog signal with the phase of the above-mentioned second clock to obtain the locked first clock, and then recovers the above-mentioned differential analog signal to obtain the recovered data. The output end of the above-mentioned clock recovery module is used to output the above-mentioned recovered data and the above-mentioned locked first clock. The signal detector then determines whether the above-mentioned recovered data is the same as the predetermined data. When the above-mentioned recovered data is the same as the predetermined data, it is determined that the chip is normal, otherwise it is abnormal, thereby solving the problem of low efficiency in screening out bad chips in the existing solution.

[0054] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip detection circuit, It is characterized in that include: A phase-locked loop, having a first output end and a second output end, the first output end of the phase-locked loop is used to output a first clock, and the second output end of the phase-locked loop is used to output a second clock, wherein the first clock is a clock with the highest frequency of the phase-locked loop, and the frequency of the second clock is equal to the frequency of the first clock; A signal generating module, having an input end and an output end, wherein the input end of the signal generating module is electrically connected to the first output end of the phase-locked loop, and the signal generating module is used to convert the first clock into random code data, and convert the random code data into a differential analog signal; A clock recovery module, comprising a first input end, a second input end and an output end, wherein the first input end of the clock recovery module is electrically connected to the output end of the signal generation module, and the second input end of the clock recovery module is electrically connected to the second output end of the phase-locked loop. The clock recovery module is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain a locked first clock, and then perform recovery processing on the differential analog signal to obtain recovered data. The output end of the clock recovery module is used to output the recovered data and the locked first clock; A signal detector having an input end, wherein the input end of the signal detector is electrically connected to the output end of the clock recovery module, and the signal detector is used to determine whether the recovered data is the same as the predetermined data to obtain a judgment result. When the judgment result is used to characterize that the recovered data is the same as the predetermined data, the chip is determined to be a normal chip; when the judgment result is used to characterize that the recovered data is different from the predetermined data, the chip is determined to be an abnormal chip, wherein the predetermined data is used to characterize that the chip is in a normal state.

2. The chip detection circuit according to claim 1, It is characterized in that The clock recovery module comprises: A clock recovery circuit, electrically connected to the output end of the signal generation module and the input end of the signal detector, respectively, and used for performing recovery processing on the differential analog signal to obtain recovered data; A phase interleaver is electrically connected to the clock recovery circuit and the second output end of the phase-locked loop respectively, and is used to lock the phase of the first clock of the differential analog signal with the phase of the second clock to obtain a locked first clock.

3. The chip detection circuit according to claim 2, It is characterized in that The clock recovery module comprises: A frequency detector and a phase detector are electrically connected to the clock recovery circuit, and are used to determine a method for adjusting the phase of the first clock. The method for adjusting the phase of the first clock is to increase the phase of the first clock or to decrease the phase of the first clock.

4. The chip detection circuit according to claim 2, It is characterized in that The signal generating module comprises: A signal generator, electrically connected to the first output terminal of the phase-locked loop, and configured to convert the first clock into random code data; A transmitter is electrically connected to the signal generator and the clock recovery circuit respectively, and is used to convert the random code data into a differential analog signal and send the differential analog signal to the clock recovery circuit.

5. The chip detection circuit according to claim 2, It is characterized in that The signal detector also has an output terminal, and the chip detection circuit also includes: an error generator, electrically connected to the clock recovery circuit, the error generator being used to output a control code to the clock recovery circuit; The controller is electrically connected to the phase-locked loop, the output end of the signal detector and the error generator respectively, and the controller is used to wake up the error generator after the signal detector outputs the judgment result.

6. The chip detection circuit according to claim 5, It is characterized in that The phase-locked loop also has a third output terminal, and the third output terminal of the phase-locked loop is used to output a third clock. The chip detection circuit also includes: A frequency comparator is electrically connected to the phase interleaver and the third output terminal of the phase-locked loop, respectively. The frequency comparator is used to receive the deviation clock output by the phase interleaver and compare the deviation clock with the third clock to obtain a comparison result, wherein the deviation clock is obtained after the phase interleaver locks the phase of the control coding clock with the phase of the second clock.

7. The chip detection circuit according to claim 5, It is characterized in that The chip detection circuit also includes: The first serial port is electrically connected to the output end of the signal detector and the controller respectively.

8. The chip detection circuit according to claim 2, It is characterized in that The chip detection circuit also includes: The serial-to-parallel module is electrically connected to the input ends of the clock recovery circuit and the signal detector respectively, and is used to perform frequency reduction processing on the recovered data to obtain frequency-reduced data.

9. The chip detection circuit according to claim 6, It is characterized in that The chip detection circuit also includes: The second serial port is electrically connected to the frequency comparator and the controller respectively.

10. An electronic device, It is characterized in that include: A chip detection circuit as claimed in any one of claims 1 to 9.

Images