Digitizer for scintillation pulses, imaging system and chip

Abstract

The application provides a scintillation pulse digitizing device, an imaging system and a chip. The digitizing device comprises a peak value acquisition unit configured to acquire a peak value of an input pulse signal; a peak value holding unit configured to hold the peak value; and a reset unit configured to generate a reset signal according to a start time of the pulse signal and a preset pulse width; wherein the peak value holding unit performs reset according to the reset signal, so that the peak value acquisition unit receives a peak value of a next pulse signal according to a feedback signal sent by the peak value holding unit. The scintillation pulse digitizing device provided by the embodiment of the application does not need to perform pulse signal widening shaping, thereby ensuring that the peak value of the pulse signal is captured without reducing the sensitivity of the system.

Description

Technical Field

[0001] This application relates to the field of signal sampling, and more specifically, to a digitization device for scintillation pulses, an imaging system, and a chip. Background Technology

[0002] In a range of applications involving high-energy radiation, such as positron emission tomography (PET) and radiation detection, high-energy rays, such as gamma rays, are converted into visible light signals by scintillation crystals. These visible light signals are further converted into scintillation pulse signals by photoelectric conversion devices. A series of application images can then be obtained by sampling and processing these scintillation pulse signals. In this process, the digitization quality of the scintillation pulses has a significant impact on the final image quality.

[0003] In recent years, with the development of digital signal processing technologies and methods, directly digitizing scintillation pulses and using software algorithms to replace traditional analog circuits for information extraction, such as particle energy deposition information, has great development potential. Compared with traditional equal-interval sampling methods, the Multi-Voltage Threshold (MVT) method is a more promising digital processing method for scintillation pulses. It combines a pulse mathematical model to fit the pulse, then integrates the pulse to obtain the energy of high-energy photons for sampling and image reconstruction, thereby helping to determine the enrichment sites of radionuclides, enabling the localization of metabolically active regions and activity assessment. During the scintillation pulse digitization process, since the energy of the incident radiation has a linear relationship with the peak value of the pulse, obtaining the peak value of the pulse can equivalently obtain the measured energy of the incident radiation.

[0004] However, because the scintillation pulses output by photodetectors have relatively short rise and decay times, traditional peak sampling circuits typically widen and shape the pulses before capturing the peak value. This approach increases the number of stacking events in the system, thereby reducing its sensitivity. Summary of the Invention

[0005] This application provides a digitization device, imaging system, and chip for scintillation pulses to solve at least one of the above-mentioned problems.

[0006] According to one aspect of this application, a digitization device for a flickering pulse is provided, comprising: a peak acquisition unit for acquiring the peak value of an input pulse signal; a peak holding unit for holding the peak value; and a reset unit for generating a reset signal based on the start time of the pulse signal and a preset pulse width; wherein the peak holding unit performs a reset according to the reset signal, so that the peak acquisition unit receives the peak value of the next pulse signal according to a feedback signal sent by the peak holding unit.

[0007] According to some embodiments, the peak acquisition unit includes a first comparator, wherein a first input terminal of the first comparator receives the pulse signal.

[0008] According to some embodiments, the peak hold unit includes a first capacitor and a first resistor connected in parallel, wherein: the first end of the first capacitor and the first resistor connected in parallel is electrically connected to the output terminal and the second input terminal of the peak hold unit to receive the peak value output by the output terminal of the peak acquisition unit and send the peak value to the second input terminal of the peak acquisition unit; the second end of the first capacitor and the first resistor connected in parallel is grounded.

[0009] According to some embodiments, the reset unit includes a reset signal generation module and a discharge module, wherein: the reset signal generation module generates a reset signal based on the start time of the pulse signal and a preset pulse width or based on the falling edge of the pulse signal; the discharge module includes a first three-terminal switch, the first terminal of the first three-terminal switch receiving the reset signal, the second terminal being electrically connected to the first terminal of the parallel-connected first capacitor and first resistor, and the third terminal being grounded.

[0010] According to some embodiments, the peak acquisition device further includes a peak processing unit, which receives the peak analog value output by the peak holding unit and converts the peak analog value into a digital signal output.

[0011] According to some embodiments, a voltage follower unit is further included between the peak hold unit and the peak processing unit. The voltage follower includes a second comparator, wherein: a first input terminal of the second comparator is electrically connected to a first terminal of the parallel-connected first capacitor and first resistor, a second input terminal is electrically connected to the output terminal of the second comparator, and the output terminal of the second comparator is electrically connected to the peak processing unit.

[0012] According to some embodiments, a peak clamping unit is further included between the peak acquisition unit and the peak holding unit to prevent the falling edge signal of the pulse from flowing back.

[0013] According to some embodiments, the peak clamping unit includes a second three-terminal switch, wherein: the first terminal of the second three-terminal switch is electrically connected to a first power supply, the second terminal is electrically connected to the output terminal of the peak acquisition unit, and the third terminal is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel.

[0014] According to some embodiments, the peak clamping unit further includes a first two-terminal switch, wherein: the first terminal of the first two-terminal switch is electrically connected to the third terminal of the second three-terminal switch, and the second terminal of the first two-terminal switch is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel.

[0015] According to some embodiments, the output of the second comparator is electrically connected to the first terminal of the first two-terminal switch.

[0016] According to some embodiments, the first comparator is a comparator powered by positive and negative power supplies, wherein: the positive power supply terminal of the first comparator is electrically connected to a second power supply, and the positive power supply terminal is grounded through a second capacitor; the negative power supply terminal of the first comparator is electrically connected to a third power supply, and the negative power supply terminal is grounded through a third capacitor.

[0017] According to some embodiments, the second capacitor and the third capacitor comprise one or more capacitors connected in parallel, or a relatively large capacitor and a relatively small capacitor connected in parallel.

[0018] According to some embodiments, the second comparator is a comparator powered by positive and negative power supplies, wherein: the positive power supply terminal of the second comparator is electrically connected to a third power supply, and the positive power supply terminal is grounded through a fourth capacitor; the negative power supply terminal of the second comparator is grounded.

[0019] According to some embodiments, the second capacitor and the third capacitor comprise one or more capacitors connected in parallel, or a relatively large capacitor and a relatively small capacitor connected in parallel.

[0020] According to one aspect of this application, an imaging system is proposed, comprising a digitization device for scintillation pulses as described in any of the preceding claims.

[0021] According to some embodiments, the imaging system further includes a pulse signal fitting device, which uses the peak signal output by the peak acquisition device to fit the pulse waveform.

[0022] According to one aspect of this application, a chip is proposed that includes a digitization device for flashing pulses as described in any of the preceding claims.

[0023] The digitization device, imaging system, and chip for scintillation pulses proposed according to embodiments of this application do not require pulse signal widening and shaping, thereby ensuring that the peak value of the pulse signal is captured without reducing the system sensitivity. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0025] Figure 1 A block diagram of a digitizing device for a blinking pulse according to an example embodiment of this application is shown.

[0026] Figure 2 A circuit diagram of a digitizing device for a blinking pulse according to an example embodiment of this application is shown.

[0027] Figure 3 A block diagram of an imaging system apparatus according to an example embodiment of this application is shown. Detailed Implementation

[0028] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0029] It should be noted that when a component is said to be "fixed to" another component, it can be directly fixed to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The terms “and / or” or “and / or” as used herein include any and all combinations of one or more of the associated listed items.

[0031] The following description, with reference to the accompanying drawings, illustrates some preferred embodiments of the present application. It should be noted that the following description is for illustrative purposes only and is not intended to limit the scope of protection of this application. The flowcharts shown in the drawings are merely illustrative examples and do not necessarily include all contents and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the actual situation.

[0032] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0033] The specific embodiments according to this application will now be described in detail with reference to the accompanying drawings.

[0034] In a range of high-energy radiation applications, the energy of incident high-energy radiation is linearly related to the peak value of the pulse; therefore, the energy of the incident high-energy radiation can be obtained by acquiring the peak value of the pulse. However, in these applications, the scintillation pulses output by photodetectors typically have shorter rise and decay times compared to other types of signals. To obtain the peak value, existing peak sampling circuits often employ a method of first widening and shaping the scintillation pulse before capturing the peak value. This method tends to increase stacking events in the sampling system, thereby reducing the system's sensitivity.

[0035] According to an example embodiment of this application, after the peak acquisition unit acquires the peak value, the peak value is saved using a peak holding unit so that the acquired peak value can be output. A reset unit is then used to reset the peak holding unit so that the peak acquisition unit can acquire the next peak value. During the peak value capture process, there is no need to widen or shape the pulse, thereby ensuring that the peak value of the pulse is captured without reducing the system sensitivity.

[0036] Figure 1 A block diagram of a device for digitizing flashing pulses according to an example embodiment of this application is shown. The following is in conjunction with... Figure 1 The present application provides a detailed description of a device for digitizing flashing pulses according to an example embodiment.

[0037] like Figure 1 The digitization device for the flashing pulse shown includes a peak acquisition unit 101, a peak holding unit 103, and a reset unit 105.

[0038] The peak acquisition unit 101 acquires the peak value of the pulse signal based on the input pulse signal.

[0039] The peak holding unit 103 acquires the peak value output by the peak acquisition unit and saves the peak value so as to output the acquired peak value.

[0040] The reset unit 105 sends a reset signal to the peak holding unit 103 after a preset time, for example, 400 to 500 ns, based on the input pulse signal.

[0041] After receiving the reset signal sent by the reset unit 105, the peak holding unit 103 performs a reset action and sends a feedback signal to the peak acquisition unit 101 after the reset action is completed, so that the peak acquisition unit 101 can acquire the peak value of the next pulse signal.

[0042] According to some embodiments of this application, the peak acquisition unit 101 includes a first comparator, wherein: the first input terminal of the first comparator receives the pulse signal.

[0043] According to other embodiments of this application, the first comparator is a comparator powered by both positive and negative power supplies, thereby improving the stability of the comparator. The positive power supply terminal of the first comparator is electrically connected to the second power supply, and the positive power supply terminal is grounded through the second capacitor; the negative power supply terminal of the first comparator is electrically connected to the third power supply, and the negative power supply terminal is grounded through the third capacitor. The second and third capacitors are filter capacitors, placed near the first comparator on the printed circuit board to eliminate high-frequency noise from the power supply.

[0044] According to some embodiments, the second and third capacitors comprise one or more capacitors connected in parallel, or a relatively large capacitor and a relatively small capacitor connected in parallel, for example, a 0.1uF capacitor and a 10uF capacitor.

[0045] According to an embodiment of this application, the peak hold unit 103 includes a first capacitor and a first resistor connected in parallel. The first terminals of the first capacitor and the first resistor connected in parallel are electrically connected to the output terminal and the second input terminal of the peak hold unit 103 to receive the peak value output by the output terminal of the peak acquisition unit 101 and send the peak value to the second input terminal of the peak acquisition unit 101. The second terminals of the first capacitor and the first resistor connected in parallel are grounded.

[0046] According to some embodiments, the reset unit 105 includes a reset signal generation module and a discharge module. The reset signal generation module receives a pulse signal and generates a reset signal according to the start time of the pulse signal and a preset pulse width. The discharge module includes a first three-terminal switch. The first terminal of the first three-terminal switch receives the reset signal, the second terminal of the first three-terminal switch is electrically connected to the first terminal of a first capacitor and a first resistor connected in parallel, and the third terminal is grounded.

[0047] According to some embodiments, Figure 1The digitization device for the flashing pulse shown also includes a peak processing unit, which receives the peak analog value output by the peak holding unit 103 and converts the peak analog value into a digital signal output.

[0048] According to an embodiment of this application, a voltage follower unit is further included between the peak hold unit 103 and the peak processing unit. The voltage follower unit includes a second comparator, and the first input terminal of the second comparator is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel. The second input terminal is electrically connected to the output terminal of the second comparator, and the output terminal of the second comparator is electrically connected to the peak processing unit.

[0049] According to some embodiments, the second comparator is a comparator powered by both positive and negative power supplies, thereby improving the comparator's stability. The positive power supply terminal of the second comparator is electrically connected to a third power supply, and the positive power supply terminal is grounded through a fourth capacitor. The negative power supply terminal of the second comparator is also grounded. The fourth capacitor is a filter capacitor, placed near the second comparator on the printed circuit board to eliminate high-frequency noise from the power supply.

[0050] According to some embodiments, the fourth capacitor includes one or more capacitors in parallel, or a relatively large capacitor and a relatively small capacitor in parallel, for example, a 0.1uF capacitor and a 10uF capacitor.

[0051] According to an embodiment of this application, a peak clamping unit is further included between the peak acquisition unit 101 and the peak holding unit 103 to prevent the falling edge signal of the pulse from flowing back. The peak clamping unit includes a second three-terminal switch, with its first terminal electrically connected to a first power supply, its second terminal electrically connected to the output terminal of the peak acquisition unit 101, and its third terminal electrically connected to the first terminal of a first capacitor and a first resistor connected in parallel.

[0052] According to some embodiments, the peak clamping unit further includes a first two-terminal switch, wherein the first terminal of the first two-terminal switch is electrically connected to the third terminal of the second three-terminal switch, and the second terminal of the first two-terminal switch is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel.

[0053] According to some embodiments, the output of the second comparator is electrically connected to the first terminal of the first two-terminal switch.

[0054] according to Figure 1 In the illustrated embodiment, after the peak acquisition unit acquires the peak value, the peak value is saved using a peak holding unit for peak value output. A reset unit then resets the peak holding unit so that the peak acquisition unit can acquire the next peak value. During peak value capture, there is no need to widen or shape the pulse, thus ensuring that the peak value of the pulse is captured without reducing system sensitivity.

[0055] Figure 2 A circuit diagram of a digitizing device for blink pulses according to an exemplary embodiment of this application is shown below. Figure 2 The circuitry of the digitization device for flashing pulses according to an example embodiment of this application will be described in detail.

[0056] like Figure 2 As shown, the pulse signal is input from the pulse port and connected to the non-inverting input of comparator U1. Comparator U1 is used to input the acquired pulse information into transistor Q1 during the rising phase of the pulse signal.

[0057] The pulse signal passes sequentially through comparator U1, transistor Q1, and diode D1, and is then supplied to charging capacitor C7 and the inverting input of comparator U1. Once the pulse signal reaches its peak value, comparator U1 stops outputting pulse signals to prevent voltage drop during peak pulse capture. Charging capacitor C7 stores the pulse peak value for later output. Transistor Q1 and diode D1 clamp the signal, preventing backflow on the falling edge of the pulse during peak capture to prevent charge loss from capacitor C7.

[0058] Transistor Q2 acts as a discharge unit. After receiving the reset signal, it sends it to charging capacitor C7. Charging capacitor C7 then performs the discharge operation. Once charging capacitor C7 has finished discharging, the potential at the positive input terminal of comparator U1 is greater than the potential at the negative input terminal, and the next pulse signal is received.

[0059] According to embodiments of this application, comparator U1 is a comparator with both positive and negative power supplies, thereby improving the stability of comparator U1. The non-inverting input terminal of comparator U1 is grounded through resistor R3, where resistor R3 is used for impedance matching to reduce the impact of sudden impedance changes at the back end on the signal. According to some embodiments, R3 is a 50-ohm grounding resistor so that the oscilloscope can measure the pulse signal at the pulse terminal and easily compare it with the output pulse peak value. The positive power supply terminal of comparator U1 is electrically connected to a +5V power supply and grounded through parallel connections of C1, C2, and C3, respectively. The negative power supply terminal is electrically connected to a -5V power supply and grounded through parallel connections of C8, C9, and C10, respectively. C1, C2, C3, C8, C9, and C10 are filter capacitors used to eliminate high-frequency noise from the power supply and are placed close to comparator U1 on the printed circuit board.

[0060] According to some embodiments, the parallel connection of C1, C2, C3 or C8, C9 and C10 can also be replaced by a larger capacitor or a larger capacitor in parallel with a smaller capacitor, for example, a 0.1uF capacitor and a 10uF capacitor.

[0061] like Figure 2As shown, the output signal of comparator U1 is sent to transistor Q1 through resistor R2. Resistor R2 acts as a current-limiting resistor; by controlling the current through resistor R2, noise in comparator U1 can be suppressed.

[0062] According to some embodiments, the transistor Q1 can be a PNP, NPN, NMOS, or PMOS transistor. Figure 2 Taking the NPN transistor shown as an example, the collector 1 of the transistor Q1 is connected to the power supply to control the current magnitude of the base 2 and emitter 3, thereby controlling the charging speed of the charging capacitor C7.

[0063] like Figure 2 As shown, after passing through transistor Q1, the signal passes sequentially through resistor R4, diode D1, and resistor R5. Resistors R4 and R5 function similarly to R2, acting as current-limiting resistors to control the current flow rate and reduce noise interference from comparator U1 on subsequent circuits.

[0064] After passing through resistor R5, the signal is transmitted to charging capacitor C7, resistor R6, and comparator U2. The other ends of charging capacitor C7 and resistor R6 are both grounded. They are also connected to the non-inverting input of amplifier U2 and the inverting input of comparator U1.

[0065] According to some embodiments, the charging capacitor C7 and R6 can be equivalent to an RC series circuit, wherein the resistor R6 is a large resistor, for example, 10M ohms, used to filter high-frequency noise.

[0066] The base of transistor Q2 receives a reset signal through resistor R8, thereby controlling the switching of the transistor's collector and emitter, and thus actively controlling the discharge of the charging capacitor C7. Resistors R8 and R9 are current-limiting resistors to prevent excessive discharge current from damaging transistor Q2.

[0067] According to some embodiments, the resistance values ​​of resistors R8 and R9 can be adjusted according to the current magnitude.

[0068] According to other embodiments, when the current through transistor Q2 is relatively small and will not damage transistor Q1, resistors R8 and R9 can be removed from the circuit.

[0069] Transistor Q2 is used to accelerate the discharge process of charging capacitor C7. According to some embodiments, transistor Q2 can be a PNP, NPN, NMOS or PMOS transistor.

[0070] According to some embodiments of this application, the reset signal is generated by an FPGA. The FPGA receives a pulse signal and outputs a reset signal when it receives the falling edge of the pulse signal, or sends a reset signal to transistor Q2 according to the start time of the pulse signal and a preset pulse width. The start time of the pulse signal is determined using the rising edge of the pulse signal received by the FPGA.

[0071] According to some embodiments, the pulse width is 400–500 ns.

[0072] like Figure 2 As shown, the output of comparator U2 outputs a pulse peak value, which is grounded through a parallel ground resistor R7. The ground resistor R7 is used for impedance matching, reducing signal reflection from the downstream circuitry. In some embodiments, the ground resistor R7 has a resistance of 50 ohms to facilitate the oscilloscope measurement of the pulse signal at the pulse terminal and comparison with the output pulse peak value.

[0073] like Figure 2 As shown, the output of comparator U2 is electrically connected to its inverting input, forming a voltage follower to enhance the circuit's load-carrying capacity and prevent the downstream circuit from affecting the signal. Simultaneously, the output of comparator U2 is electrically connected through resistor R1 between resistor R4 and diode D1 to charge the charging capacitor C7 to retain the pulse peak.

[0074] According to some embodiments, comparator U2 is a comparator with both positive and negative power supplies, thereby improving its stability. The positive power supply terminal of comparator U2 is electrically connected to a +5V power supply and grounded via parallel connections C4, C5, and C6. C4, C5, and C6 are filter capacitors used to eliminate high-frequency noise from the power supply and are placed close to comparator U2 on the printed circuit board.

[0075] according to Figure 2 In the embodiment shown, the peak value of the pulse output by comparator U2 is sent to the peak processing unit, which converts the peak analog value output by comparator U2 into a digital signal output.

[0076] according to Figure 2 The illustrated embodiment proposes a peak acquisition circuit for capturing high-frequency pulses without pulse shaping. It utilizes capacitor C7, transistor Q1, and diode D1 to store the peak value, eliminating the need for pulse widening and shaping during peak acquisition. This ensures that the pulse peak value is captured without reducing system sensitivity. An FPGA actively generates a reset signal so that comparator U1 can acquire the next pulse peak value.

[0077] Figure 3A block diagram of an imaging system apparatus according to an example embodiment of this application is shown. Figure 3 The imaging system shown includes a scintillation pulse digitization device 301 and a pulse signal fitting device 303. The scintillation pulse digitization device 301 performs the peak acquisition function of the scintillation pulse digitization device as described above, and transmits the captured pulse peak value to the pulse signal fitting device 303. The pulse signal fitting device 303 uses the received pulse peak value to form a strong constraint at the peak value, thereby completing the fitting of the final pulse waveform.

[0078] The systems, devices, and units described in the above embodiments can be implemented by semiconductor chips, computer chips, and / or physical entities, or by products with certain functions. For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more chips.

[0079] This application also provides a chip including the aforementioned digitization device for flicker pulses and / or a pulse signal fitting device. The digitization device for flicker pulses performs the peak acquisition function described above and transmits the captured pulse peak value to the pulse signal fitting device. The pulse signal fitting device uses the received pulse peak value to form a strong constraint at the peak value, thus completing the fitting of the final pulse waveform. This chip can be specifically implemented using a semiconductor chip, a computer chip, and / or a physical device, or by a product with a certain function. For ease of description, the above devices are described by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more chips.

[0080] While this application provides the operational steps of the methods described in the above embodiments or flowcharts, the methods may include more or fewer operational steps based on conventional or non-inventive methods. For steps where there is no logically necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application.

[0081] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. The above embodiments are described to facilitate understanding and use of this application by those skilled in the art. Those skilled in the art can readily make various modifications to these embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, this application is not limited to the above embodiments. Improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope of this application should be within the protection scope of this application.

[0082] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, and on the specific implementation methods and application scope of this application, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A digitization device for scintillation pulses, characterized in that, include: A peak acquisition unit acquires the peak value of the input pulse signal. The peak acquisition unit includes a first comparator and a transistor, and the first input terminal of the first comparator receives the pulse signal. A peak holding unit includes a charging capacitor, a first capacitor, and a first resistor. The charging capacitor is used to hold the peak value. The first terminals of the first capacitor and the first resistor are electrically connected to the output terminal and the second input terminal of the peak acquisition unit to receive the peak value output by the output terminal of the peak acquisition unit and send the peak value to the second input terminal of the peak acquisition unit. The reset unit generates a reset signal based on the start time of the pulse signal and a preset pulse width; The peak holding unit performs a reset according to the reset signal, so that the peak acquisition unit receives the peak value of the next pulse signal according to the feedback signal sent by the peak holding unit.

2. The digitization device for scintillation pulses according to claim 1, characterized in that, The first capacitor and the first resistor are connected in parallel, and the second terminals of the first capacitor and the first resistor are grounded.

3. The digitization device for scintillation pulses according to claim 2, characterized in that, The reset unit includes a reset signal generation module and a discharge module, wherein: The reset signal generation module generates a reset signal based on the start time of the pulse signal and a preset pulse width, or based on the falling edge of the pulse signal. The discharge module includes a first three-terminal switch, the first terminal of which receives the reset signal, the second terminal of which is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel, and the third terminal of which is grounded.

4. The digitization device for scintillation pulses according to claim 3, characterized in that, The digitization device further includes a peak processing unit, which receives the peak analog value output by the peak holding unit and converts the peak analog value into a digital signal output.

5. The digitization device for scintillation pulses according to claim 4, characterized in that, A voltage follower unit is further included between the peak hold unit and the peak processing unit, the voltage follower including a second comparator, wherein: The first input terminal of the second comparator is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel, the second input terminal is electrically connected to the output terminal of the second comparator, and the output terminal of the second comparator is electrically connected to the peak processing unit.

6. The digitization device for scintillation pulses according to claim 5, characterized in that, A peak clamping unit is also included between the peak acquisition unit and the peak holding unit to prevent the falling edge signal of the pulse from flowing back.

7. The digitization device for scintillation pulses according to claim 6, characterized in that, The peak clamping unit includes a second three-terminal switch, wherein: The first terminal of the second three-terminal switch is electrically connected to the first power supply, the second terminal is electrically connected to the output terminal of the peak acquisition unit, and the third terminal is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel.

8. The digitization device for scintillation pulses according to claim 7, characterized in that, The peak clamping unit further includes a first two-terminal switch, wherein: The first terminal of the first two-terminal switch is electrically connected to the third terminal of the second three-terminal switch, and the second terminal of the first two-terminal switch is electrically connected to the first terminal of the first capacitor and the first resistor connected in parallel.

9. The digitization device for scintillation pulses according to claim 8, characterized in that, The output of the second comparator is electrically connected to the first terminal of the first two-terminal switch.

10. The digitization device for scintillation pulses according to claim 1, characterized in that, The first comparator is a comparator powered by positive and negative power supplies, wherein: The positive power supply terminal of the first comparator is electrically connected to the second power supply, and the positive power supply terminal is grounded through the second capacitor; The negative power supply terminal of the first comparator is electrically connected to the third power supply, and the negative power supply terminal is grounded through the third capacitor.

11. The digitization device for scintillation pulses according to claim 10, characterized in that, The second capacitor and the third capacitor comprise one or more capacitors connected in parallel, or a relatively large capacitor and a relatively small capacitor connected in parallel.

12. The digitization device for scintillation pulses according to claim 5, characterized in that, The second comparator is a comparator powered by positive and negative power supplies, wherein: The positive power supply terminal of the second comparator is electrically connected to the third power supply, and the positive power supply terminal is grounded through the fourth capacitor; The negative power supply terminal of the second comparator is grounded.

13. The digitization device for scintillation pulses according to claim 12, characterized in that, The fourth capacitor includes one capacitor or several capacitors connected in parallel, or a relatively large capacitor and a relatively small capacitor connected in parallel.

14. An imaging system, characterized in that, A digital device including the scintillation pulse as described in any one of claims 1-13.

15. The imaging system according to claim 14, characterized in that, The imaging system also includes a pulse signal fitting device. The pulse signal fitting device uses the peak signal output by the digitizing device to fit the pulse waveform.

16. A chip, characterized in that, A digital device including the scintillation pulse as described in any one of claims 1-13.

Images