A master-slave board bus communication addressing method

Abstract

The application discloses a master-slave board bus communication addressing system, which comprises a master board and slave boards; the master board comprises an OUT_0 pin; the slave boards comprise INPUT pins and OUT pins, wherein the INPUT pin of a slave board located at the first position in the plurality of slave boards is connected with the OUT_0 pin of the master board, and the OUT pin of a previous slave board is connected with the INPUT pin of a subsequent slave board; the level signal output by the OUT_0 pin of the master board is sent to the INPUT pin of the slave board, and the INPUT pin of the next slave board receives the level signal to complete the addressing after the slave board completes the addressing according to the received level signal; and the application further discloses a master-slave board bus communication addressing method. In the application, the slave boards are connected through two additional IO ports, the OUT pin of a previous slave board is connected with the INPUT pin of a subsequent slave board, and the INPUT pin of the subsequent slave board receives the level signal of the previous slave board to complete the addressing, so that automatic addressing is completed by one board after another, the difficulty of the later maintenance and upgrading of the terminal module is greatly reduced, and the addressing of the slave board is not prone to errors.

Description

Technical Field

[0001] This invention relates to the field of information processing technology, and specifically to a master-slave board bus communication addressing method. Background Technology

[0002] Currently, remote terminal modules are widely used in the fields of signal acquisition and equipment control in industrial fields. In practical applications, many slave boards are usually installed side by side and connected to the motherboard via a bus to provide power supply and internal data communication between the motherboard and the slave boards. When using bus communication, the slave boards must be identified and addressed in order to enable addressing access.

[0003] There are two main addressing methods for existing slave boards: one is through DIP switches, for example, there are 4 DIP switches, and the 16 states of the DIP switches determine the different identities of the slave boards; the other is that the slave board's address is fixed in the program according to different applications. When the master and slave devices enter the setting mode, the master sends the setting command, and the user presses the setting button on the slave board in sequence. After the setting is completed, the slave board stores its own address and can be used directly without resetting after power-on.

[0004] As the number of slave boards increases, the management of slave board addresses becomes increasingly difficult for technicians. Therefore, the above addressing method not only causes some trouble for the maintenance and upgrade of subsequent terminal modules, but also easily leads to confusion in the use of slave board addresses, resulting in errors in slave board addressing.

[0005] To address the shortcomings of existing slave board addressing methods, a different approach has emerged in the industry. This method incorporates a sampling module in each slave board. It samples the constant current output from the motherboard's power module, then uses a voltage acquisition module to collect the voltage. Finally, it identifies different slave board addresses based on the different voltage values ​​collected. While this method reduces the complexity of slave board address management and the error rate, it requires voltage verification, places higher demands on hardware, and is more complex to program, making it more difficult to implement. Summary of the Invention

[0006] The purpose of this invention is to provide a master-slave board bus communication addressing method that is easier to maintain and upgrade later and has a low error rate in addressing.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A master-slave board bus communication addressing system includes a motherboard and several slave boards;

[0009] The motherboard includes an OUT_0 pin;

[0010] The slave board includes an INPUT pin and an OUT pin, wherein the INPUT pin of the first slave board among the plurality of slave boards is connected to the OUT_0 pin of the main board, and the OUT pin of the preceding slave board is connected to the INPUT pin of the following slave board.

[0011] The level signal output by the OUT_0 pin of the motherboard is sent to the INPUT pin of the slave board. After the slave board completes the addressing according to the received level signal, the next slave board INPUT pin receives the level signal to complete the addressing.

[0012] Furthermore, the motherboard sends encoded instructions to each of the slave boards via UART_TX, and the slave boards send waiting address commands to the motherboard via UART_RX.

[0013] Furthermore, the number of slave boards is two or more, and each slave board communicates with the main board via UART_TX and UART_RX respectively.

[0014] Furthermore, the motherboard also includes an INPUT_END pin, and the OUT pin of the last slave board among the plurality of slave boards is connected to the INPUT_END pin of the motherboard.

[0015] Furthermore, the OUT_0 pin of the motherboard outputs a low level. After the previous slave board completes the addressing based on the received low-level signal, the INPUT pin of the next slave board receives a low-level signal to complete the addressing.

[0016] A master-slave board bus communication addressing method includes:

[0017] After the motherboard and slave board are powered on, the motherboard sends the addressing command via broadcast;

[0018] The motherboard outputs a level signal from its OUT_0 pin and sends it to the slave board's INPUT pin. The slave board then automatically addresses the slave board based on the received level signal.

[0019] After the previous slave board completes its automatic addressing, the next slave board receives a level signal on its INPUT pin and performs automatic addressing, and so on, completing the automatic addressing of each slave board in sequence.

[0020] Based on the above scheme, the OUT_0 pin of the motherboard outputs a low level, and the OUT pin of each slave board outputs a high level;

[0021] When the first slave board in each slave board detects that its INPUT_1 pin is low and determines that the timing value t1 is between (0 and 0.1) seconds, the first slave board will take the address received at this time as address 01. After a delay of (0.1-t1) seconds, the first slave board will output a low level on its OUT_1 pin.

[0022] When the next slave board detects that its INPUT_2 pin is low and determines that the timing value t2 is between (0.1 and 0.2) seconds, the next slave board will take the address received at this time as address 02. After a delay of (0.2-t2) seconds, the next slave board will output a low level on its OUT_2 pin.

[0023] This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command it sent, at which point the addressing process ends.

[0024] Based on the above scheme, the OUT_0 pin of the motherboard outputs a low level, and the OUT pin of each slave board outputs a high level;

[0025] When the first slave board in each slave board detects that its INPUT_1 pin is low, the motherboard sends an addressing instruction of 01 to the first slave board. After receiving the code, the first slave board sets its address to 01 and saves it. At this time, the INPUT pins of the other slave boards are high and no addressing action is performed because they are not selected. After the first slave board completes the encoding, it sends a deaddressing command to the motherboard. The motherboard sets the OUT_0 pin to high (the INPUT_1 pin becomes low), and the OUT_1 pin of the slave board outputs a low level.

[0026] When the next slave board detects that its INPUT_2 pin is low, the motherboard sends an addressing instruction of 02 to the next slave board. After receiving the code, the next slave board sets its address to 02 and saves it. At this time, the INPUT pins of other slave boards are high and no addressing action is performed because they are not selected. After the next slave board completes the encoding, it sends a deaddressing command to the motherboard. The motherboard sets the OUT_1 pin to high and the OUT_2 pin of the next slave board outputs a low level.

[0027] This process continues until all slave boards are addressed.

[0028] Based on the above scheme, after the slave board detects that its INPUT pin is low, it sends a waiting address command to the motherboard via UART_RX. The motherboard sends an coded addressing instruction to the slave board via UART_TX. After receiving the code, the slave board sets its address to the corresponding code and saves it. When the motherboard's INPUT_END pin receives a low level, or when the addressing command sent by the motherboard is completed, the addressing of all slave boards ends.

[0029] Based on the above scheme, the OUT_0 pin of the motherboard outputs a low level, and the OUT pin of each slave board outputs a high level;

[0030] The motherboard's OUT_0 pin outputs a high level and a 01 code. After the first slave board detects that its INPUT_1 pin is low, it saves the 01 code value and sets its address to 01. The OUT_1 pin outputs the 02 code value.

[0031] After the next slave board detects that its INPUT_2 pin is low, it saves the 02 encoding value, sets its address to 02, and outputs the 03 encoding value on the OUT_2 pin.

[0032] This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command it sent, at which point the addressing process ends.

[0033] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0034] 1. In this invention, each slave board is connected through two additional I / O ports (INPUT pin and OUT pin). The OUT pin of the previous slave board is connected to the INPUT pin of the next slave board. The INPUT pin of the next slave board receives the level signal of the previous slave board to complete the addressing. In this way, the boards can automatically complete the addressing one after another without human intervention, reducing the user's setting operation, greatly reducing the difficulty of later maintenance and upgrade of the terminal module, and the addressing of the slave board is not prone to errors.

[0035] 2. In this invention, the motherboard sends the level signal to the slave board, and the slave board completes the addressing based on the received level signal. There is no requirement for voltage judgment, and the microcontroller does not need to have a voltage detection module. A general microcontroller can handle this task. The hardware requirements are low, and the software programming is also easy. Programming is simple, no storage is required, and the implementation difficulty is low. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the connection between the motherboard and the slave board in this invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] Example 1

[0039] refer to Figure 1 As shown, the present invention discloses a master-slave board bus communication addressing system, including a motherboard and several slave boards.

[0040] The motherboard includes an OUT_0 pin; the slave board includes an INPUT pin and an OUT pin, wherein the INPUT pin of the first slave board among the plurality of slave boards is connected to the OUT_0 pin of the motherboard, and the OUT pin of the preceding slave board is connected to the INPUT pin of the following slave board.

[0041] The level signal output by the OUT_0 pin of the motherboard is sent to the INPUT pin of the slave board. After the slave board completes the addressing according to the received level signal, the next slave board INPUT pin receives the level signal to complete the addressing.

[0042] Furthermore, the motherboard sends encoded instructions to each of the slave boards via UART_TX, and the slave boards send waiting address commands to the motherboard via UART_RX.

[0043] Furthermore, the number of slave boards is two or more, and each slave board communicates with the main board via UART_TX and UART_RX respectively.

[0044] Furthermore, the motherboard also includes an INPUT_END pin, and the OUT pin of the last slave board among the plurality of slave boards is connected to the INPUT_END pin of the motherboard.

[0045] Furthermore, the OUT_0 pin of the motherboard outputs a low level. After the previous slave board completes the addressing based on the received low-level signal, the INPUT pin of the next slave board receives a low-level signal to complete the addressing.

[0046] In this invention, each slave board is connected through two additional I / O ports (INPUT pin and OUT pin). The OUT pin of the previous slave board is connected to the INPUT pin of the next slave board. The INPUT pin of the next slave board receives the level signal from the previous slave board to complete the addressing. In this way, the boards can automatically complete the addressing one after another without human intervention, reducing the user's setting operations. At the same time, the software of expansion boards (slave boards) with the same function is also the same, avoiding the need for personnel to set the addressing during subsequent maintenance and upgrades. This greatly reduces the difficulty of later maintenance and upgrades of the terminal module, and the addressing of the slave boards is not prone to errors.

[0047] Furthermore, this addressing method only starts when the system is powered on, and the time is very short. It takes less than 1 second to complete the addressing of 10 slave boards. It does not even require the microcontroller to have a storage function. Once the address is set, it will be retained as long as there is no power failure. After the next power-on, the system will re-address and can be used normally.

[0048] Example 2

[0049] refer toFigure 1 As shown, the present invention also discloses a master-slave board bus communication addressing method. After the motherboard and slave board are powered on, the motherboard sends an addressing command in the form of broadcast. The OUT_0 pin of the motherboard outputs a level signal and sends it to the INPUT pin of the slave board. The slave board automatically addresses according to the received level signal. After the previous slave board is automatically addressed, the next slave board receives the level signal at the INPUT pin and performs automatic addressing. The automatic addressing of each slave board is completed in this way.

[0050] Based on the above scheme, this embodiment adopts a timing-based addressing method. After the motherboard and slave board are powered on, when the slave board receives the addressing command, it starts timing (the timing values ​​of each board are t1, t2, t3...n), and the motherboard also starts timing at the same time.

[0051] The motherboard's OUT_0 pin outputs a low level, while each slave board's OUT pin outputs a high level. The first slave board detects that its INPUT_1 pin is low and determines that the timing value t1 is between (0 and 0.1) seconds. Then, the first slave board takes the address received at this time as address 01. After a delay of (0.1-t1) seconds, the first slave board outputs a low level on its OUT_1 pin.

[0052] When the next slave board detects that its INPUT_2 pin is low and determines that the timing value t2 is between (0.1 and 0.2) seconds, the next slave board will take the address received at this time as address 02. After a delay of (0.2-t2) seconds, the next slave board will output a low level on its OUT_2 pin.

[0053] When the third slave board detects that its INPUT_3 pin is low and determines that the timing value t3 is between (0.2 and 0.3) seconds, the third slave board will take the address received at this time as address 03. After a delay of (0.3-t3) seconds, the third slave board will output a low level on its OUT_3 pin.

[0054] This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command it sent, at which point the addressing process ends.

[0055] Example 3

[0056] The difference between this embodiment and embodiment two is that the addressing method of the board is different. This embodiment uses the motherboard communication addressing method.

[0057] Specifically, the motherboard outputs a low level on its OUT_0 pin, and each slave board outputs a high level on its OUT pin. When the first slave board detects that its INPUT_1 pin is low, the motherboard sends an addressing instruction of 01 to the first slave board. After receiving the code, the first slave board sets its address to 01 and saves it. At this time, the INPUT pins of other slave boards are high and no addressing action is performed because they are not selected. After the first slave board completes the encoding, it sends a deaddressing command to the motherboard. The motherboard sets its OUT_0 pin to high (the INPUT_1 pin becomes low), and the slave board outputs a low level on its OUT_1 pin.

[0058] When the next slave board detects that its INPUT_2 pin is low, the motherboard sends an addressing instruction of 02 to the next slave board. After receiving the code, the next slave board sets its address to 02 and saves it. At this time, the INPUT pins of other slave boards are high and no addressing action is performed because they are not selected. After the next slave board completes the encoding, it sends a deaddressing command to the motherboard. The motherboard sets the OUT_1 pin to high and the OUT_2 pin of the next slave board outputs a low level, so that the third slave board enters the selected state.

[0059] After the third slave board detects that its INPUT_3 pin is low, the motherboard sends an addressing instruction of 03 to the third slave board. After receiving the code, the third slave board sets its address to 03 and saves it. At this time, the INPUT pins of other slave boards are high and no addressing action is performed because they are not selected. After the third slave board completes the encoding, it sends a deaddressing command to the motherboard. The motherboard sets the OUT_2 pin to high and the OUT_3 pin of the third slave board outputs a low level, so that the fourth slave board enters the selected state.

[0060] This process continues until all slave boards are addressed. Specifically, after the last slave board completes its encoding, it sends a deaddress command to the motherboard. The motherboard then commands the OUT_n-1 pin of the preceding slave board to output a high level to deselect the last slave board. Once the motherboard receives this command, the addressing process is complete.

[0061] Based on the above scheme, after the slave board detects that its INPUT pin is low, it sends a waiting address command to the motherboard via UART_RX. The motherboard sends an coded addressing instruction to the slave board via UART_TX. After receiving the code, the slave board sets its address to the corresponding code and saves it. When the motherboard's INPUT_END pin receives a low level, or when the addressing command sent by the motherboard is completed, the addressing of all slave boards ends.

[0062] Example 4

[0063] The difference between this embodiment and embodiment two is that the addressing method of the slave board is different. This embodiment adopts the slave board interconnection addressing method.

[0064] Specifically, the OUT_0 pin of the motherboard outputs a low level, and the OUT pins of each slave board output a high level; the OUT_0 pin of the motherboard outputs a high level and 01 encoding. After the first slave board detects that its INPUT_1 pin is low, it saves the 01 encoding value and sets its address to 01. The OUT_1 pin outputs the 02 encoding value.

[0065] When the next slave board detects that its INPUT_2 pin is low, it saves the 02 encoding value, sets its address to 02, and outputs the 03 encoding value on the OUT_2 pin.

[0066] After the third slave board detects that its INPUT_3 pin is low, it saves the 03 encoding value, sets its address to 03, and outputs the 04 encoding value on the OUT_3 pin.

[0067] This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command it sent, at which point the addressing process ends.

[0068] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A master-slave board bus communication addressing method, characterized in that, The system includes a motherboard and several slave boards. The motherboard includes an OUT_0 pin. Each slave board includes an INPUT pin and an OUT pin. The INPUT pin of the first slave board is connected to the OUT_0 pin of the motherboard, and the OUT pin of the preceding slave board is connected to the INPUT pin of the following slave board. The level signal output by the OUT_0 pin of the motherboard is sent to the INPUT pin of the slave board. After the slave board completes addressing based on the received level signal, the INPUT pin of the next slave board receives the level signal to complete addressing. The motherboard also includes an INPUT_END pin, and the OUT pin of the last slave board in the plurality of slave boards is connected to the INPUT_END pin of the motherboard. After the motherboard and slave boards are powered on, the motherboard sends the addressing command via broadcast. The motherboard outputs a level signal on its OUT_0 pin and sends it to the slave board's INPUT pin. The slave board automatically addresses the slave board based on the received level signal. After the previous slave board completes its automatic addressing, the next slave board receives the level signal on its INPUT pin and performs automatic addressing. This process is repeated sequentially to complete the automatic addressing of each slave board. The motherboard's OUT_0 pin outputs a low level, while each slave board's OUT pin outputs a high level. The first slave board detects its INPUT_1 pin is low and determines that the timer value t1 is between 0 and 0.1 seconds. The first slave board then uses the received address as address 01. After a delay of 0.1-t1 seconds, it outputs a low level on its OUT_1 pin. The next slave board detects its INPUT_2 pin is low and determines that the timer value t2 is between 0.1 and 0.2 seconds. The next slave board uses the received address as address 02. After a delay of 0.2-t2 seconds, it outputs a low level on its OUT_2 pin. This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command, at which point the addressing process ends.

2. The master-slave board bus communication addressing method as described in claim 1, characterized in that, The motherboard sends encoded instructions to each of the slave boards via UART_TX, and the slave boards send waiting address commands to the motherboard via UART_RX.

3. The master-slave board bus communication addressing method as described in claim 2, characterized in that, The number of slave boards is two or more, and each slave board communicates with the main board via UART_TX and UART_RX respectively.

4. The master-slave board bus communication addressing method as described in claim 1, characterized in that, The OUT_0 pin of the motherboard outputs a low level. After the previous slave board completes the addressing based on the received low-level signal, the INPUT pin of the next slave board receives a low-level signal to complete the addressing.

5. A master-slave board bus communication addressing method, characterized in that, The system includes a motherboard and several slave boards. The motherboard includes an OUT_0 pin. Each slave board includes an INPUT pin and an OUT pin. The INPUT pin of the first slave board is connected to the OUT_0 pin of the motherboard, and the OUT pin of the preceding slave board is connected to the INPUT pin of the following slave board. The level signal output by the OUT_0 pin of the motherboard is sent to the INPUT pin of the slave board. After the slave board completes addressing based on the received level signal, the INPUT pin of the next slave board receives the level signal to complete addressing. The motherboard also includes an INPUT_END pin, and the OUT pin of the last slave board in the plurality of slave boards is connected to the INPUT_END pin of the motherboard. After the motherboard and slave boards are powered on, the motherboard sends the addressing command via broadcast. The motherboard outputs a level signal on its OUT_0 pin and sends it to the slave board's INPUT pin. The slave board automatically addresses the slave board based on the received level signal. After the previous slave board completes its automatic addressing, the next slave board receives the level signal on its INPUT pin and performs automatic addressing. This process is repeated sequentially to complete the automatic addressing of each slave board. The motherboard's OUT_0 pin outputs a low level, while each slave board's OUT pin outputs a high level. When the first slave board detects that its INPUT_1 pin is low, the motherboard sends an addressing instruction of 01 to it. Upon receiving the code, the first slave board sets its address to 01 and saves it. At this time, the INPUT pins of the other slave boards are high, indicating they are not selected and no addressing operation is performed. After the first slave board completes the encoding, it sends a deaddress command to the motherboard. The motherboard then sets its OUT_0 pin high and its INPUT_1 pin low. When the next slave board detects that its INPUT_2 pin is low, the main board sends an addressing instruction of 02 to the next slave board. After receiving the code, the next slave board sets its address to 02 and saves it. At this time, the INPUT pins of other slave boards are high and no addressing action is performed because they are not selected. After the next slave board completes the encoding, it sends a deaddressing command to the main board. The main board sets its OUT_1 pin to high and the OUT_2 pin of the next slave board outputs a low level. This process continues until all slave boards are addressed.

6. The master-slave board bus communication addressing method as described in claim 5, characterized in that, After the slave board detects that its INPUT pin is low, it sends a waiting addressing command to the motherboard via UART_RX. The motherboard sends an coded addressing instruction to the slave board via UART_TX. After receiving the code, the slave board sets its address to the corresponding code and saves it. When the motherboard's INPUT_END pin receives a low level, or when the addressing command sent by the motherboard is completed, the addressing of all slave boards ends.

7. A master-slave board bus communication addressing method, characterized in that, The system includes a motherboard and several slave boards. The motherboard includes an OUT_0 pin. Each slave board includes an INPUT pin and an OUT pin. The INPUT pin of the first slave board is connected to the OUT_0 pin of the motherboard, and the OUT pin of the preceding slave board is connected to the INPUT pin of the following slave board. The level signal output by the OUT_0 pin of the motherboard is sent to the INPUT pin of the slave board. After the slave board completes addressing based on the received level signal, the INPUT pin of the next slave board receives the level signal to complete addressing. The motherboard also includes an INPUT_END pin, and the OUT pin of the last slave board in the plurality of slave boards is connected to the INPUT_END pin of the motherboard. After the motherboard and slave boards are powered on, the motherboard sends the addressing command via broadcast. The motherboard outputs a level signal on its OUT_0 pin and sends it to the slave board's INPUT pin. The slave board automatically addresses the slave board based on the received level signal. After the previous slave board completes its automatic addressing, the next slave board receives the level signal on its INPUT pin and performs automatic addressing. This process is repeated sequentially to complete the automatic addressing of each slave board. The motherboard's OUT_0 pin outputs a low level, while each slave board's OUT pin outputs a high level. The motherboard's OUT_0 pin outputs a high level and a 01 code. When the first slave board detects its INPUT_1 pin is low, it saves the 01 code value, sets its address to 01, and outputs the 02 code value on its OUT_1 pin. The next slave board detects its INPUT_2 pin is low, saves the 02 code value, sets its address to 02, and outputs the 03 code value on its OUT_2 pin. This process continues until the motherboard's INPUT_END pin receives a low level, or the motherboard completes the addressing command, at which point the addressing process ends.

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