Chip Verification System, Method and Computer Readable Storage Medium

Abstract

The present invention discloses a chip verification system, method and computer-readable storage medium. The system includes: an intelligent terminal, a chip under test, an external device, and an EDA verification module. The intelligent terminal is communicatively connected to the EDA verification module, and the chip under test is communicatively connected to the intelligent terminal and the external device respectively; the chip verification system further includes: an FPGA data acquisition module, and the FPGA data acquisition module is communicatively connected to the chip under test; the FPGA data acquisition module is configured to, when detecting an abnormal signal, obtain each real data of the external device to obtain a real data set; the intelligent terminal is configured to load the real data set into the EDA verification module; the EDA verification module is configured to test the real data to obtain a verification result of the chip under test. Through the chip verification system in the present invention, problems existing in the chip can be located quickly and accurately, and the efficiency of chip verification is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a chip verification system, method, and computer-readable storage medium. Background Art

[0002] In the whole process of chip development, chip verification is an essential and important link. Chip verification refers to the verification personnel verifying the design functions of the chip, discovering design defects, and handing them over to the design personnel for correction. The currently commonly used chip verification system includes FPGA (Field Programmable Gate Array) prototype verification.

[0003] Among them, unexpected excitation data may appear during the FPGA prototype verification process, and unexpected excitation data often means that there are defects in the chip design. Unfortunately, the debuggability of FPGA is very poor, and it is impossible to obtain the waveforms of all signals inside the chip when problems occur. Therefore, it is very difficult to locate the specific problems and defects of the chip. In order to locate the problems of the chip, the existing solutions often verify the chip by adding probes when synthesizing the FPGA version, re-synthesizing, placing and routing, and generating an FPGA bit file to capture waveforms on the FPGA board. And the time cost of compiling the FPGA version is often very high, usually more than 8 hours is normal. This results in very low efficiency of the FPGA prototype verification in locating chip problems, seriously affecting the progress of chip verification. Summary of the Invention

[0004] The main purpose of the present invention is to provide a chip verification system, method, and computer-readable storage medium, aiming to solve the technical problem that the existing FPGA prototype verification is very inefficient in locating chip problems.

[0005] To achieve the above object, the present invention provides a chip verification system. The chip verification system includes an intelligent terminal, a chip under test, an external device, and an EDA verification module. The intelligent terminal is communicatively connected to the EDA verification module, and the chip under test is communicatively connected to the intelligent terminal and the external device respectively; the chip verification system further includes: an FPGA data acquisition module communicatively connected to the chip under test;

[0006] The FPGA data acquisition module is configured to obtain each real data of the external device to obtain a real data set when detecting an abnormal signal;

[0007] The intelligent terminal is configured to load the real data set into the EDA verification module;

[0008] The EDA verification module is used to test the real data to obtain the verification result of the chip under test.

[0009] Optionally, the FPGA data acquisition module is in an FPGA prototype verification environment, including: a trigger detection unit, a data acquisition unit, and a first storage unit;

[0010] The trigger detection unit is used to detect an abnormal signal and activate the data acquisition unit when the abnormal signal is detected;

[0011] The data acquisition unit is used to obtain each real data of the external device and store each real data in the first storage unit.

[0012] Optionally, the intelligent terminal includes: a central processing unit; the EDA verification module includes: a second storage unit, and the EDA verification module is in an EDA verification environment;

[0013] The central processing unit is used to load the real data set into the second storage unit.

[0014] Optionally, the intelligent terminal is further used to obtain the device type of the external device and determine the test case corresponding to the device type;

[0015] The EDA verification module is further used to test the real data according to the test case to obtain the verification result of the chip under test.

[0016] Optionally, the EDA verification module further includes: an FPGA data sending module, a design under test module;

[0017] The FPGA data sending module is used to send the real data set in the second storage unit to the design under test module;

[0018] The design under test module is used to test the real data to obtain the verification result of the chip under test.

[0019] Optionally, the EDA verification module further includes: a data selector;

[0020] The FPGA data sending module is further used to sequentially send each real data in the real data set in the second storage unit to the data selector according to a preset clock cycle;

[0021] The data selector is used to send each real data to the design under test module corresponding to the test case in the EDA verification module.

[0022] Optionally, the EDA verification module is further used to obtain the simulation data of the external device;

[0023] The data selector is further configured to forward the analog data to the device under test module in the EDA verification module;

[0024] The device under test module is further configured to test the analog data to obtain a verification result of the chip under test.

[0025] Optionally, the EDA verification module further includes a device identification unit and an EDA verification component;

[0026] The device identification unit is configured to obtain the device type of the external device and determine the EDA verification component corresponding to the device type;

[0027] The EDA verification component is configured to obtain the analog data of the external device.

[0028] In addition, to achieve the above object, the present invention further provides a chip verification method, which is applied to a chip verification system, and the method includes the following steps:

[0029] When an abnormal signal is detected, obtain each real data of the external device to obtain a real data set;

[0030] Load the real data set into a preset EDA verification module;

[0031] Test the real data through the EDA verification module to obtain a verification result of the chip under test.

[0032] In addition, to achieve the above object, the present invention further provides an intelligent device, including a processor, a memory, and a chip verification program stored on the memory and executable by the processor. When the chip verification program is executed by the processor, the steps of the chip verification method described above are implemented.

[0033] The present invention further provides a computer-readable storage medium, on which a chip verification program is stored. When the chip verification program is executed by a processor, the steps of the chip verification method described above are implemented.

[0034] In the chip verification system of the technical solution of the present invention, it includes: an intelligent terminal, a chip to be tested, an external device, and an EDA verification module. The intelligent terminal is communicatively connected to the EDA verification module, and the chip to be tested is communicatively connected to the intelligent terminal and the external device respectively. The chip verification system further includes: an FPGA data acquisition module, which is communicatively connected to the chip to be tested. The FPGA data acquisition module is used to obtain each real data of the external device to obtain a real data set when an abnormal signal is detected. The intelligent terminal is used to load the real data set into the EDA verification module. The EDA verification module is used to test the real data to obtain the verification result of the chip to be tested. The present invention will only obtain the real data of the external device when it detects that there is a problem with the chip, avoiding the increase and waste of a large amount of useless data on the load of the intelligent terminal during chip verification. The real data set obtained in the FPGA prototype verification environment is loaded into the EDA verification module in the EDA verification environment, so that the EDA verification module verifies the real data of the external device. These real data can be efficiently verified by the EDA verification module to quickly discover various problems existing in the chip to be tested. The present invention mainly overcomes the obstacle that it is difficult to integrate the two in technology by transforming and integrating the traditional FPGA prototype verification environment and EDA verification environment, and cleverly combines the two verification methods. Thus, it not only overcomes the defect that the efficiency of locating chip problems in the FPGA prototype verification is extremely low, but also overcomes the defect that the EDA verification cannot truly and completely reflect the chip problems, ensuring the accuracy of locating chip problems during the chip verification process and greatly improving the efficiency of chip verification. Description of the Drawings

[0035] Figure 1 It is a schematic diagram of the terminal structure of the hardware operating environment of the intelligent device related to the solution of the embodiment of the present invention;

[0036] Figure 2 It is a schematic flowchart of the first embodiment of the chip verification method of the present invention;

[0037] Figure 3 It is a schematic diagram of the framework structure of the chip verification system of the present invention;

[0038] Figure 4 It is a schematic diagram of the FPGA verification environment framework related to the chip verification system of the present invention;

[0039] Figure 5 It is a schematic diagram of the EDA verification environment framework related to the chip verification system of the present invention;

[0040] Figure 6This is a schematic diagram of a specific data interaction scenario between a chip under test applied to a USB and an external device in the chip verification system of the present invention;

[0041] Figure 7 This is a schematic diagram of the framework process of the FPGA verification environment applied to a USB in the chip verification system of the present invention;

[0042] Figure 8 This is a schematic diagram of the EDA verification environment framework applied to a USB in the chip verification system of the present invention;

[0043] Figure 9 This is a schematic diagram of the overall integrated process of the chip verification system of the present invention.

[0044] Explanation of the reference numerals in the drawings:

[0045] Label Name Label Name 1 Intelligent terminal 2 Chip under test 3 External device 4 FPGA data acquisition module 5 EDA verification module 6 Device under test module 7 FPGA data transmission module 8 Data selector 9 Device under test module 10 EDA verification component 41 Trigger detection unit 42 Data acquisition unit 43 First storage unit 71 Second storage unit 72 Data transmission unit

[0046] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0047] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] Overview of the technical solution of the present invention:

[0049] The present invention mainly modifies the existing FPGA prototype verification environment, creates an FPGA data acquisition module in the FPGA prototype verification environment to start acquiring the excitation data sent by the external device when an abnormality occurs in the FPGA prototype verification. This excitation data is the real data of the external device. Also, an FPGA data sending module is created in the EDA verification environment to send the real data acquired by the FPGA data acquisition module to the DUT (design under test) in the preset EDA verification module, so that the EDA verification module in the EDA verification environment tests the real data of the external device to quickly obtain the verification result regarding the chip problem.

[0050] Based on the technical solution of the present invention, by certain means, the real data on the FPGA is acquired and output to the DUT for verification in the EDA simulation. The present invention improves the disadvantage of untrue excitation data in the EDA simulation verification and can be used to enrich the EDA verification scenario and improve the problem location efficiency on the FPGA.

[0051] An embodiment of the present invention proposes an intelligent device. The intelligent device may include intelligent devices such as personal computers, mobile phones, tablets, etc., and is not limited herein.

[0052] Such asFigure 1 As shown Figure 1 It is a schematic structural diagram of the hardware operating environment of the intelligent device involved in the embodiment of the present invention.

[0053] As Figure 1 shown, the intelligent device may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display (Display) and an input unit such as a control panel. Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WIFI interface). The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001. As a computer storage medium, the memory 1005 may include a chip verification program.

[0054] Those skilled in the art can understand that Figure 1 the hardware structure shown in does not constitute a limitation on the device, and it may include more or fewer components than shown, or combine some components, or arrange different components.

[0055] Continuing to refer to Figure 1 , Figure 1 the memory 1005 as a computer-readable storage medium in may include an operating system, a user interface module, a network communication module, and a chip verification program.

[0056] In Figure 1 , the network communication module is mainly used to connect to the server and communicate with the server for data; and the processor 1001 may call the chip verification program stored in the memory 1005 and execute the steps in the following respective embodiments.

[0057] Based on the above hardware structure of the controller, various embodiments of the chip verification system of the present invention are proposed.

[0058] The embodiment of the present invention provides a chip verification system.

[0059] Please refer to Figure 3 , Figure 3Schematic diagram of the framework structure of the chip verification system of the present invention; in the first embodiment of the present invention, the chip verification system includes: an intelligent terminal 1, a chip under test 2, an external device 3, and an EDA verification module 5. The intelligent terminal 1 is communicatively connected to the EDA verification module 5, and the chip under test 2 is communicatively connected to the intelligent terminal 1 and the external device 3 respectively. The chip verification system further includes: an FPGA data acquisition module 4, and the FPGA data acquisition module 4 is communicatively connected to the chip under test 2;

[0060] The FPGA data acquisition module 4 is configured to obtain various real data of the external device 3 to obtain a real data set when an abnormal signal is detected;

[0061] The intelligent terminal 1 is configured to load the real data set into the EDA verification module 5;

[0062] The EDA verification module 5 is configured to test the real data to obtain a verification result of the chip under test 2.

[0063] In this embodiment, the intelligent terminal 1 includes, but is not limited to, devices such as personal computers, mobile phones, and tablet computers that require chip processing of data.

[0064] In the process of data interaction between the chip under test 2 (FPGA chip) and the external device 3, taking the personal computer of the intelligent terminal 1 as an example, the FPGA verification program in the personal computer can identify which data is normal and which data is abnormal. Specifically, each data is compared with a preset database to determine which data is abnormal. When it is determined that the data is abnormal, it can be considered that the FPGA verification program detects an abnormal signal. At this time, the preset FPGA data acquisition module 4 is triggered to start obtaining various real data of the external device 3 to obtain a real data set. The real data can be not only the output data of the external device 3 but also the input data of the external device 3.

[0065] In one embodiment, the FPGA data acquisition module 4 is in an FPGA prototype verification environment and includes: a trigger detection unit 41, a data acquisition unit 42, and a first storage unit 43;

[0066] The trigger detection unit 41 is configured to detect an abnormal signal and activate the data acquisition unit 42 when the abnormal signal is detected;

[0067] The data acquisition unit 42 is configured to obtain various real data of the external device 3 and store each real data in the first storage unit 43.

[0068] Among them, the preset FPGA data acquisition module 4 can be developed and implemented by Verilog or SystemVerilog language. To facilitate understanding of the role of the FPGA data acquisition module 4 in the present invention, reference can be made to Figure 4 , Figure 4 which is a schematic diagram of the FPGA verification environment framework involved in the chip verification system of the present invention. As Figure 4 shown, in the FPGA verification environment of this embodiment, it at least includes a DUT (design under test) module (the device under test module 6), where DUT can also be translated as "device under test"; the FPGA data acquisition module 4, where the FPGA data acquisition module 4 includes a trigger detection unit 41, a data acquisition unit 42, and a first storage unit 43. Here, the first storage unit 43 can be an SRAM (Static Random-Access Memory) inside the FPGA chip or an externally connected DDRSDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). Which specific memory to choose can be determined according to the amount of data to be collected; an external device 3, which can be a USB flash drive, a hard disk, a gamepad, etc. Among them, the DUT and the external device 3 communicate and transmit through a signal transmission line. The signal transmission line includes, in the direction indicated by the arrow in the figure: a DUT-external device transmission line and an external device-DUT transmission line. The DUT-external device transmission line sends data from the DUT to the external device 3, and the external device-DUT transmission line sends data from the external device 3 to the DUT. Among them, the DUT-external device transmission line is connected to the trigger detection unit 41, and the external device-DUT transmission line is respectively connected to the trigger detection unit 41 and the data acquisition unit 42. It should also be noted that the FPGA verification environment not only includes virtual modules but also includes the FPGA chip and various circuit devices connected to the FPGA chip on the same board, etc.

[0069] During the process of data interaction between the DUT and the external device 3, abnormal data (abnormal signals) between the DUT and the external device 3 are detected through trigger detection. When an abnormal signal is detected, the entire FPGA data acquisition module 4 is activated, and the data acquisition unit 42 in the FPGA data acquisition module 4 starts to obtain each real data of the external device 3. Here, the real data can be each actual excitation data sent by the external device 3 to the DUT through the external device-DUT transmission line. After the data acquisition unit 42 obtains the real data according to the preset clock cycle, each real data is stored in the first storage unit 43 according to the preset clock cycle.

[0070] It should be noted that the reason for obtaining the real data of the external device 3 only when an abnormal signal is detected is as follows:

[0071] When collecting data in the FPGA verification environment, a starting point is required. Otherwise, a large amount of invalid data will be captured when there is no abnormality and data capture is not required. The invalid data is not helpful for locating chip problems.

[0072] In a specific application embodiment, taking the above DUT as a USB2.0 Host (a master device using USB2.0) project as an example, that is, the test case or test project for verifying the chip under test 2 is USB2.0 Host. In FPGA verification, usually the interface between the USB HOST (a USB master device, such as a personal computer) and the PHY (a USB to Ethernet chip, as the chip under test 2) is connected to an external board. There is an external device 3 of USB (such as a USB flash drive) on the external board. There is an 8-bit interface of UTMI (USB2.0 Transceiver Macrocell Interface, a high-speed device detection protocol of USB2.0) between the USBHOST and the PHY. For some signals between the USB2.0 Host and the external device 3, please refer to Figure 6 , Figure 6 is a schematic diagram of a specific data interaction scenario between the chip under test 2 applied to USB and the external device 3 in the chip verification system of the present invention. The signals (data) therein include: utm_clk, utm_txvalid, utm_txready, utm_txdata, utm_rxvalid, utm_rxdata, utm_rxerror, utm_rxactive, etc.

[0073] Please refer to Figure 7 , Figure 7 is a schematic diagram of the framework process of the FPGA verification environment applied to USB in the chip verification system of the present invention; the main difference between the FPGA verification environment applied to USB and the above general FPGA verification environment is that the DUT is determined to be a test case of USB2.0 Host, and the FPGA data acquisition module 4 is a USB FPGA data acquisition module 4. The entire FPGA verification environment includes the DUT (the design under test USB2.0 Host), the external device 3, and the USB FPGA data acquisition module 4.

[0074] The USB FPGA data acquisition module 4 includes: a USB trigger detection unit 41, a USB data acquisition unit 42, a cfg configuration unit, and a first storage unit 43 module. Among them:

[0075] Cfg configuration unit: used to generate cfg_data configuration information, which acts on the trigger detection module. Through this configuration, the trigger conditions can be flexibly set.

[0076] USB trigger detection unit 41: Detects the commands issued by the HOST, and generates the trigger conditions for the detection module through the utm_txvalid / utm_txreay / utm_txdata signals (data). That is, the set of these signals can be abnormal signals. Specifically, when utm_txvalid and utm_txready are both valid and utm_txdata = cfg_data, the data acquisition of the real data sent by the external device 3 to the DUT is started.

[0077] USB data acquisition unit 42: After the USB data acquisition is started, it starts data acquisition, acquires the data sent by the external device 3 to the DUT (including data such as utm_rxvalid, utm_rxactive, utm_rxerror, utm_rxdata sent by the external device 3 to the DUT), and writes the data to the first storage unit 43 in clock order (time order) after packing.

[0078] The first storage unit 43: Used to store the real data of data acquisition.

[0079] In an embodiment, the intelligent terminal 1 includes: a central processing unit; the EDA verification module 5 includes: a second storage unit 71, and the EDA verification module 5 is in an EDA verification environment;

[0080] The central processing unit is used to load the real data set into the second storage unit 71.

[0081] Since the EDA verification environment is completely a virtual verification environment that depends on intelligent terminals 1 such as personal computers, the real data set composed of each real data in the first storage unit 43 in the FPGA verification environment can be read onto the intelligent terminal 1 through the CPU (central processing unit) in the intelligent terminal 1. Specifically, the real data set can be loaded into the second storage unit 71 in the EDA verification module 5 (EDA verification environment) through the backdoor. This EDA verification environment can be a UVM architecture verification environment. To facilitate the understanding of the EDA verification environment in this embodiment, reference can be made to Figure 5 , Figure 5 which is a schematic diagram of the EDA verification environment framework involved in the chip verification system of the present invention. As Figure 5 shown, Figure 5It includes a DUT, where the DUT here is a DUT in an EDA verification environment, which is different from the DUT in the above-mentioned FPGA verification environment; an FPGA data sending module 7, which also includes a trigger detection unit 41, which has basically the same function as the trigger detection unit 41 in the above-mentioned FPGA data acquisition module 4, except that the trigger detection unit 41 activates a data sending unit 72 after detecting an abnormal signal, and the data sending unit 72 is used to send the real data in the second storage unit 71 to a MUX (multiplexer, data selector 8); the MUX is used to select and receive the real data sent by the data sending module or the simulated data of the external device 3 sent by the EDA verification component 10; the EDA verification component 10 is used to simulate the real data sent by the external device 3 to the DUT in the FPGA verification environment in the EDA verification environment. The EDA verification module 5 can be implemented by an EDA verification program, and the EDA verification program can be selected as needed, which is not limited here.

[0082] In one embodiment, the intelligent terminal 1 is further used to obtain the device type of the external device 3 and determine the test case corresponding to the device type;

[0083] The EDA verification module 5 is further used to test the real data according to the test case to obtain a verification result of the chip to be tested 2.

[0084] After the external device 3 establishes a connection with the smart terminal 1, the device type of the external device 3 can be easily learned by the smart terminal 1. For example, if the external device 3 is a U disk or a wired mouse that adopts the USB2.0 protocol, then the corresponding test case can be the USB2.0 Host, and the DUT in the EDA verification environment where the corresponding EDA verification module 5 is located is the design under test for the USB2.0 Host, that is, the test case is the USB2.0 Host, and then based on the corresponding test case, the real data sent by the external device 3 is tested, so that based on the verification function of the EDA verification module 5, the problem of the chip 2 under test can be efficiently located. It is not difficult to understand that in the design under test of the USB2.0 Host, the chip 2 under test is a chip that can realize multiple USB2.0 functions.

[0085] In one embodiment, the EDA verification module 5 further includes: an FPGA data sending module 7 and a design under test module 9;

[0086] The FPGA data sending module 7 is used to send the real data set in the second storage unit 71 to the tested design module 9;

[0087] The DUT (Design Under Test) module 9 is used to test the real data to obtain the verification result of the chip under test 2.

[0088] In this embodiment, briefly speaking, specifically, after being activated by the trigger detection unit 41 in the EDA verification module 5, the FPGA data sending module 7 in the EDA verification module 5 reads the real data set in the second storage unit 71 in sequence according to a preset clock cycle, that is, reads each real data in the real data set in sequence according to the first-in-first-out principle and sends them to the corresponding DUT (Design Under Test module 9) in sequence, so as to test each real data through the DUT in the EDA verification environment to obtain the verification result of the chip under test 2.

[0089] It should be noted that the trigger detection unit 41 in the EDA verification environment also needs to receive the same abnormal signal as in the FPGA verification environment to activate the FPGA data sending module 7 to start sending data.

[0090] It should be noted that the reason for sending the real data in the second storage unit 71 only when an abnormal signal is detected is as follows:

[0091] When sending data from the EDA verification environment to the DUT, a starting point is required. For example: The USB host (USB master device, USB controller) interacts with the external device 3. When reading the external device 3 in the FPGA verification environment, an error occurs and the peripheral data in the FPGA verification environment is captured. If the starting point is not judged in the EDA verification environment, it is possible to send the data obtained from the FPGA verification environment to the DUT in the EDA verification environment before the USB controller starts sending the read command, which is obviously meaningless. The trigger detection unit 41 realizes the alignment of time points: When it detects that the USB host has sent a read command (covering the abnormal signal), it sends the data in the FPGA verification environment to the USB host. According to the specific interface protocol, the trigger detection unit 41 can detect the signal sent by the chip under test 2 to the external device 3, that is, the signal sent by the DUT in the EDA verification environment to the external device 3, and can also detect the signal sent by the external device 3 to the chip under test 2. In the example of the USB controller, it is necessary to detect the data sent by the chip under test 2.

[0092] In another embodiment, the EDA verification module 5 further includes: a data selector 8;

[0093] The FPGA data sending module 7 is further configured to send each real data in the real data set in the second storage unit 71 to the data selector 8 in sequence according to a preset clock cycle;

[0094] The data selector 8 is used to send each piece of real data to the device under test module 9 corresponding to the test case in the EDA verification module 5.

[0095] In this embodiment, it mainly involves a MUX, that is, the data selector 8. During the process that the FPGA data sending module 7 sends each piece of real data in the real data set in the second storage unit 71 to the device under test module 9 in sequence according to a preset clock cycle, it is necessary to first select through the data selector 8 and then forward it to the device under test module 9. The purpose of doing this is to select real data and simulated data, and it can be verified only based on EDA without abnormal signals, ensuring the verification efficiency. In the case of abnormal signals, based on the real data obtained by the FPGA and the verification efficiency of EDA at the same time, it ensures the consistency of the excitation data in the EDA verification environment and the FPGA verification environment, and reproduces the real situation on the FPGA to the greatest extent on the EDA, so that the problems of the chip under test 2 in the FPGA verification environment can be quickly reproduced, that is, to balance between the accuracy and efficiency of verification, and ensure that the chip verification task can be completed quickly and well.

[0096] To further understand the above EDA verification module 5 (EDA verification environment), reference can be made to Figure 8 for the description of the specific implementation method:

[0097] Figure 8 This is a schematic diagram of the EDA verification environment framework applied to USB in the chip verification system of the present invention.

[0098] As Figure 8 shown, compared with the EDA verification environments in the above various embodiments, the EDA verification environment applied to USB is also different in that the DUT is determined to be a USB2.0 Host, the EDA verification component 10 is Testbench_USB, the FPGA data sending module 7 is a USB FPGA data sending module 7, the trigger detection unit 41 is a USB trigger detection unit 41, and in addition, it also includes a cfg configuration unit.

[0099] Reference can continue to be made to Figure 7 and the embodiments regarding USB2.0 Host in the above text.

[0100] Cfg configuration module: Its function is the same as that of the Cfg configuration module in the above text.

[0101] USB trigger detection unit 41: The same as above.

[0102] Second storage unit 71: In the EDA verification environment, the data captured in the FPGA verification environment (stored in the first storage unit 43) is loaded into the second storage unit 71 through the backdoor method.

[0103] Data sending unit 72: After the data sending unit 72 is activated and started, it reads the data in the second storage unit 71 and caches it into rx_data_fpga (which can be considered as a partition).

[0104] MUX: A two-to-one data selector 8. When an abnormal signal appears, the FPGA problem reproduction mode is enabled and the trigger detection unit 41 is activated, the MUX selects the data of rx_data_fpga (rx_data_fpga contains the data of the USB external device 3 packed in sequence, and it only needs to be unpacked in sequence and sent to the DUT). Otherwise, it selects the data sent out by Testbench_USB (EDA verification component 10).

[0105] The chip verification system in the technical solution of the present invention includes: an intelligent terminal 1, a chip under test 2, an external device 3, and an EDA verification module 5. The intelligent terminal 1 is communicatively connected to the EDA verification module 5, and the chip under test 2 is communicatively connected to the intelligent terminal 1 and the external device 3 respectively; the chip verification system further includes: an FPGA data acquisition module 4, and the FPGA data acquisition module 4 is communicatively connected to the chip under test 2; the FPGA data acquisition module 4 is configured to obtain each real data of the external device 3 to obtain a real data set when detecting an abnormal signal; the intelligent terminal 1 is configured to load the real data set into the EDA verification module 5; the EDA verification module 5 is configured to test the real data to obtain the verification result of the chip under test 2. The present invention only obtains the real data of the external device 3 when detecting that there is a problem with the chip, avoiding the increase and waste of a large amount of useless data in the load of the intelligent terminal 1 during chip verification. The real data set obtained in the FPGA prototype verification environment is loaded into the EDA verification module 5 in the EDA verification environment, so that the EDA verification module 5 verifies the real data of the external device 3, and these real data can be efficiently verified by the EDA verification module 5 to quickly and timely discover various problems existing in the chip under test 2. The present invention mainly overcomes the obstacle that it is difficult to integrate the two in technology by transforming and integrating the traditional FPGA prototype verification environment and the EDA verification environment, and combines the two verification methods skillfully, thereby not only overcoming the defect that the efficiency of locating chip problems in the FPGA prototype verification is extremely low, but also overcoming the defect that the EDA verification cannot truly and completely reflect the chip problems, ensuring the accuracy of locating chip problems in the chip verification process, and at the same time greatly improving the efficiency of chip verification.

[0106] Furthermore, a second embodiment of the chip verification system of the present invention is proposed based on the above-mentioned various embodiments of the chip verification system of the present invention. In this embodiment, the EDA verification module 5 is further configured to obtain the simulation data of the external device 3;

[0107] The data selector 8 is further configured to forward the simulation data to the design under test module 9 in the EDA verification module 5;

[0108] The design under test module 9 is further configured to test the simulation data to obtain the verification result of the chip under test 2.

[0109] In this embodiment, reference may continue to be made to Figure 5 When the trigger detection unit 41 in the EDA verification environment does not detect an abnormal signal. For example, for the above-mentioned USB2.0 Host design under test: The trigger condition of the detection module is generated through the utm_txvalid / utm_txreay / utm_txdata signals (data), that is, the set of these signals can be an abnormal signal. Specifically, when one of the conditions that utm_txvalid and utm_txready are both valid and utm_txdata = cfg_data is not satisfied, it can be considered that no abnormal signal is detected. At this time, there is no need to obtain the real data of the external device 3 through the FPGA verification environment. Only the EDA verification module 5 needs to simulate the data input by the external device 3 to obtain the simulation data of the external device 3, and directly forward the obtained simulation data to the design under test module 9 in the EDA verification module 5 through the data selector 8, so as to test the simulation data through the design under test module 9 to obtain the verification result of the chip under test 2.

[0110] Through this embodiment, in the case that no abnormality occurs during the FPGA prototype verification process, there is no need to obtain the real data of the external device 3 when an abnormal signal appears, and the problems of the chip under test 2 can be quickly detected and located directly through EDA simulation verification, thereby improving the efficiency of chip verification.

[0111] In an embodiment, the EDA verification module 5 further includes a device identification unit and an EDA verification component 10;

[0112] The device identification unit is configured to obtain the device type of the external device 3 and determine the EDA verification component 10 corresponding to the device type;

[0113] The EDA verification component 10 is configured to obtain the simulation data of the external device 3.

[0114] Reference may continue to be made to Figure 5For how the EDA verification environment simulates the data input by different external devices 3, the device type of the external device 3 can be obtained first. For the smart terminal 1, this can generally be achieved when the external device 3 is connected to the smart terminal 1. After determining the device type, the corresponding EDA verification component 10 can be determined for the external device 3, that is, the EDA verification module 5 (EDA verification environment) in this application can include multiple different EDA verification components 10.

[0115] For the real data input by the external device 3, the EDA verification component 10 can be used to simulate it to obtain the simulated data of the external device 3. The simulated data can largely reflect the problems existing in the chip under test 2, so as to quickly verify the chip under test 2.

[0116] In addition, please refer to Figure 2 , Figure 2 is a schematic flowchart of the first embodiment of the chip verification method of the present invention. The present invention also provides a chip verification method, characterized in that the chip verification method is applied to the chip verification system as described in claim 1, and the method includes the following steps:

[0117] Step S10, when an abnormal signal is detected, obtain each real data of the external device to obtain a real data set;

[0118] Step S20, load the real data set into a preset EDA verification module;

[0119] Step S30, test the real data through the EDA verification module to obtain the verification result of the chip under test.

[0120] Among them, the chip verification method can refer to each embodiment of the chip verification system of the present invention, which will not be elaborated here.

[0121] In order to further understand the above-mentioned various embodiments of the present invention and the complete process of the present invention, reference can be made to Figure 9 .

[0122] 01: Develop the FPGA data acquisition and FPGA data sending modules. Usually implemented in Verilog or SystemVerilog language. Since the trigger detection unit and the first storage unit are exactly the same, the data acquisition unit and the data sending unit can be implemented in one module, or separately implemented in 2 independent modules;

[0123] 02: Integration of the FPGA code, integrate the FPGA data acquisition module into the FPGA verification environment or inside the DUT in the FPGA verification environment;

[0124] 03: The FPGA version is synthesized, placed and routed to generate a bitstream;

[0125] 04: Conduct on-board testing. Download the FPGA bit file into the FPGA verification environment for testing. When the trigger condition (abnormal signal) is satisfied, capture the data and write it into the first storage unit;

[0126] 05: Export the captured data to a personal computer. Generally, there is a CPU in a SOC (System on Chip) chip, which can read it out through the CPU and print it to the personal computer through the serial port. Thus, the acquisition of FPGA data (real data input by external devices) is completed;

[0127] 06: Integrate the FPGA data sending module into the EDA verification environment, and the EDA verification environment can be of the UVM standard architecture;

[0128] 07: Compile the EDA verification environment;

[0129] 08: Start the simulation and import the FPGA data into the second storage unit (which can be implemented using the $readmemh function in Verilog language);

[0130] 09: Execute the test case and wait for triggering;

[0131] 10: After triggering, the FPGA data sending module reads the data in the second storage unit and sends it to the DUT in the EDA verification environment by cycle (clock cycle), thus completing the test;

[0132] 11: Check the simulation results or analyze the waveforms to locate problems.

[0133] The present invention ensures the consistency between the EDA verification environment and the excitation data on the FPGA, and reproduces the real situation on the FPGA to the greatest extent, so that problems on the FPGA can be quickly reproduced.

[0134] In addition, the present invention also provides a computer-readable storage medium. A chip verification program is stored on the computer-readable storage medium of the present invention. When the chip verification program is executed by a processor, the steps of the chip verification method as described above are implemented.

[0135] Wherein, the method implemented when the chip verification program is executed can refer to the various embodiments of the chip verification system of the present invention, and will not be elaborated here.

[0136] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0138] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0140] It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words may be interpreted as names.

[0141] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made by those skilled in the art once they learn the basic inventive concept. Therefore, the appended claims are intended to be construed to cover the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0142] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made by using the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A chip verification system, characterized in that, The chip verification system includes an intelligent terminal, a chip under test, an external device, and an EDA verification module. The intelligent terminal is communicatively connected to the EDA verification module, and the chip under test is communicatively connected to both the intelligent terminal and the external device. The chip verification system further includes: an FPGA data acquisition module communicatively connected to the chip under test; The FPGA data acquisition module is configured to, when an abnormal signal is detected, obtain various real data of the external device to obtain a real data set, where the real data includes the input data and output data of the external device; The intelligent terminal is configured to load the real data set into the EDA verification module; The EDA verification module is configured to test the real data to obtain a verification result of the chip under test. The FPGA data acquisition module is in an FPGA prototype verification environment and includes: a trigger detection unit, a data acquisition unit, and a first storage unit; The trigger detection unit is configured to detect an abnormal signal and activate the data acquisition unit when the abnormal signal is detected. The data acquisition unit is configured to obtain various real data of the external device and store each piece of the real data in the first storage unit.

2. The chip verification system according to claim 1, wherein The intelligent terminal includes: a central processing unit. The EDA verification module includes: a second storage unit, and the EDA verification module is in an EDA verification environment; The central processing unit is configured to load the real data set into the second storage unit.

3. The chip verification system according to claim 2, wherein, The intelligent terminal is further configured to obtain the device type of the external device and determine a test case corresponding to the device type; The EDA verification module is further configured to test the real data according to the test case to obtain a verification result of the chip under test.

4. The chip verification system according to claim 3, characterized in that, The EDA verification module further includes: an FPGA data sending module and a design under test module; The FPGA data sending module is configured to send the real data set in the second storage unit to the design under test module; The design under test module is configured to test the real data to obtain a verification result of the chip under test.

5. The chip verification system according to claim 4, wherein The EDA verification module further includes: a data selector; The FPGA data sending module is further configured to sequentially send each piece of the real data in the real data set in the second storage unit to the data selector according to a preset clock cycle; The data selector is configured to send each piece of the real data to the design under test module corresponding to the test case in the EDA verification module.

6. The chip verification system according to claim 5, wherein, The EDA verification module is further configured to obtain simulation data of the external device; The data selector is further configured to forward the simulation data to the design under test module in the EDA verification module; The design under test module is further configured to test the simulation data to obtain a verification result of the chip under test.

7. The chip verification system according to claim 6, wherein The EDA verification module further includes a device identification unit and an EDA verification component; The device recognition unit is used to obtain the device type of the external device and determine the EDA verification component corresponding to the device type; The EDA verification component is used to obtain the analog data of the external device.

8. A chip verification method, characterized in that, The chip verification method is applied to the chip verification system according to claim 1, and the method includes the following steps: When an abnormal signal is detected, obtain each real data of the external device to obtain a real data set; Load the real data set into a preset EDA verification module, where the real data includes the input data and output data of the external device; Test the real data through the EDA verification module to obtain the verification result of the chip to be tested.

9. A computer-readable storage medium, characterized in that, A chip verification program is stored on the computer-readable storage medium, where when the chip verification program is executed by a processor, the steps of the chip verification method according to claim 8 are implemented.

Images