A driving circuit, a driving method thereof, and a display device

Abstract

The present application provides a driving circuit, a driving method thereof, and a display device, relating to the field of display technologies. The driving circuit can effectively reduce the number of signal lines, accelerate the design time of the display device, and reduce the design error rate, etc. The driving circuit includes: a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The first control signal line is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes multiple electrical signals.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a driving circuit, a driving method thereof, and a display device. Background Art

[0002] With the development of technology, display devices integrate more and more functions. In current display devices, there are multiple signal lines between a Tcon (Timing Controller) and a display screen to transmit various different signals. The larger the number of signal lines, the greater the design complexity of the display device, and it may also widen the border of the display device. Summary of the Invention

[0003] Embodiments of the present application provide a driving circuit, a driving method thereof, and a display device. The driving circuit can effectively reduce the number of signal lines, shorten the design time of the display device, and reduce the design error rate, etc.

[0004] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, a driving circuit is provided. The driving circuit includes: a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The first control signal line is configured to be able to transmit a first control signal to the source driver, where the first control signal includes multiple types of electrical signals.

[0006] Optionally, the driving circuit includes one first control signal line, and the first control signal line is configured to be able to transmit the first control signal to the source driver, where the first control signal includes at least some types of electrical signals.

[0007] Optionally, the driving circuit includes multiple first control signal lines. Each first control signal line is configured to be able to transmit the first control signal to the source driver, where the first control signal includes multiple types of electrical signals; the number of types of electrical signals included in each first control signal line is at least partially the same;

[0008] Or, the number of types of electrical signals included in each first control signal line is different.

[0009] Optionally, the first control signal includes a first electrical signal and a second electrical signal, and the types of the first electrical signal and the second electrical signal are different;

[0010] The source driver is configured to: receive and parse the first control signal, obtain the first electrical signal according to the first pulse and the single pulse of the pulse cluster in the first control signal; and obtain the second electrical signal according to the number of pulses in the pulse cluster in the first control signal; wherein the first control signal includes at least one single pulse and at least one pulse cluster.

[0011] Optionally, the driving circuit further includes at least one second control signal line, one end of the second control signal line is electrically connected to the controller and the other end is electrically connected to the source driver, and the second control signal line is configured to be able to transmit a second control signal to the source driver, wherein the second control signal includes an electrical signal, and the second control signal is different from the first control signal.

[0012] Optionally, the first electrical signal is a synchronization signal at the start and end of each row, and the second signal is a polarity inversion signal;

[0013] The source driver is further configured to: obtain the positive-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being even and the last pulse of the even number of pulse clusters remaining for a preset time; obtain the negative-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being odd and the last pulse of the odd number of pulse clusters remaining for the preset time; and maintain the polarity of the polarity inversion signal according to the single pulse in the first control signal.

[0014] Optionally, the driving circuit includes one second control signal line, one end of the second control signal line is electrically connected to the controller and the other end is electrically connected to one source driver, and the second control signal includes a control signal for data transmission direction and sequence;

[0015] The driving circuit further includes a third control signal line, and adjacent source drivers are electrically connected through the third control signal line, and the third control signal line is configured to be able to transmit the control signal for data transmission direction and sequence between adjacent source drivers.

[0016] Optionally, the driving circuit further includes a data signal line, one end of the data signal line is electrically connected to the controller and the other end is electrically connected to the source driver, and the data signal line is configured to be able to transmit a data signal to the source driver according to the control signal for data transmission direction and sequence;

[0017] The source driver is further configured to: end the reception of the data signals of the first row according to the rising edge of the first pulse of the pulse cluster in the first control signal and the rising edge of the single pulse in the first control signal; and start the reception of the data signals of the second row according to the falling edge of the first pulse of the pulse cluster in the first control signal and the falling edge of the single pulse in the first control signal.

[0018] Optionally, the driving circuit includes a plurality of the source drivers, which are electrically connected between adjacent source drivers; each of the source drivers includes a storage address; the first control signal includes a first electrical signal.

[0019] The source driver is configured to: receive and parse the first control signal, and determine whether the source driver of the storage address receives the first electrical signal according to different pulses in the first control signal.

[0020] Optionally, the driving circuit further includes a data signal line, one end of the data signal line is electrically connected to the controller and the other end is electrically connected to the source driver, and the data signal line is configured to transmit data signals to the source driver.

[0021] The source driver is further configured to: determine whether the source driver of the storage address receives the data signal according to different pulses in the first control signal.

[0022] Optionally, the first electrical signal is a synchronization signal for the start and end of each row.

[0023] The driving circuit further includes a second control signal line, one end of the second control signal line is electrically connected to the controller and the other end is electrically connected to the source driver, and the second control signal line is configured to be able to transmit a second control signal to the source driver, wherein the second control signal includes an electrical signal, and the second control signal is a polarity inversion signal.

[0024] On the other hand, a display device is provided, including a display panel and the above driving circuit, and the source driver in the driving circuit is electrically connected to the display panel and is configured to be able to drive the display panel.

[0025] On yet another hand, a driving method for the above driving circuit is provided, the driving circuit includes a controller, a source driver and at least one first control signal line, one end of the first control signal line is electrically connected to the controller and the other end is electrically connected to the source driver;

[0026] The driving method includes:

[0027] The controller transmits a first control signal to the source driver through the first control signal line; wherein, the first control signal includes multiple types of electrical signals.

[0028] An embodiment of the present application provides a driving circuit, which includes: a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The first control signal line is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes multiple types of electrical signals. Thus, the transmission of multiple types of electrical signals can be achieved through one first control signal line. Compared with the related art where one signal line can only transmit one type of electrical signal, the driving circuit provided by the embodiment of the present application can effectively reduce the number of signal lines. This can not only speed up the design time of the display device, reduce the design error rate, but also reduce the influence between signal lines, enhance the anti-aging and wear resistance of the display device, and improve the performance of the display device; in addition, it can also enable the display device to achieve a narrow border and provide a good user experience.

[0029] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically listed below. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0031] Figure 1 A schematic structural diagram of a display device provided by an embodiment of the present application;

[0032] Figure 2 For Figure 1 The timing diagram of the first control signal in the shown display device including the synchronization signal TP at the start and end of each row and the polarity inversion signal POL;

[0033] Figure 3 A schematic structural diagram of another display device provided by an embodiment of the present application;

[0034] Figure 4 For Figure 3 The timing diagram of the first control signal in the shown display device including the synchronization signal TP at the start and end of each row;

[0035] Figure 5 A schematic structural diagram of a display device in a related art provided by an embodiment of the present application;

[0036] Figure 6 is Figure 5 A timing diagram of the synchronization signal TP and the polarity inversion signal POL at the start and end of each row in the display device shown;

[0037] Figure 7 is Figure 5 A timing diagram of the synchronization signal TP and the control signal LR for the data transmission direction and order at the start and end of each row in the display device shown. Specific embodiments

[0038] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0039] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects, only for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0040] In the embodiments of the present application, the meaning of "multiple" is two or more, and the meaning of "at least one" is one or more, unless otherwise clearly and specifically defined.

[0041] In the embodiments of the present application, the orientation or positional relationship indicated by terms such as "upper" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0042] In the embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components; "electrically connected" may refer to electrical connection through wires, or may refer to electrical connection through radio signals.

[0043] The embodiments of the present application provide a driving circuit. Refer to Figure 1 and Figure 3As shown, the driving circuit includes: a controller 1, a source driver, and at least one first control signal line 3. One end of the first control signal line 3 is electrically connected to the controller 1, and the other end is electrically connected to the source driver. The first control signal line 3 is configured to be able to transmit a first control signal to the source driver, where the first control signal includes multiple types of electrical signals.

[0044] Here, no specific limitations are imposed on the structure, type, quantity, etc. of the above-mentioned controller. By way of example, the above-mentioned controller may include a Tcon. By way of example, the quantity of the above-mentioned controller may be one; or, the quantity of the above-mentioned controller may be multiple. Figure 1 and Figure 3 Taking one controller 1 controlling four source drivers as an example for illustration. Of course, it is also possible to set the quantity of the controller to be the same as the quantity of the source driver, that is, when the quantity of the source driver is Figure 1 and Figure 3 the four shown, the quantity of the controller may also be four. At this time, each controller independently controls one source driver, thereby enabling the source driver to achieve zonal control of the display device.

[0045] Here, no specific limitations are imposed on the structure, type, quantity, etc. of the above-mentioned source driver. By way of example, the above-mentioned source driver may include an SIC (Source Integrated circuit). By way of example, the quantity of the above-mentioned source driver may be one; or, the quantity of the above-mentioned source driver may be multiple. Figure 1 and Figure 3 Taking one controller 1 controlling four source drivers, specifically one controller 1 controlling source driver 21, source driver 22, source driver 23, and source driver 24 as an example for illustration. Of course, it is also possible to set the quantity of the source driver to be the same as the quantity of the controller. That is, when the quantity of the controller is one, the quantity of the source driver is also one. At this time, this controller controls this one source driver, specifically subject to actual applications.

[0046] The above-mentioned first control signal includes multiple types of electrical signals. Here, no specific limitations are imposed on the types of electrical signals, the quantity of electrical signals included in each type of electrical signal, etc. By way of example, the above-mentioned electrical signals may include multiple and any combination of the synchronization signal TP at the start and end of each row, the polarity inversion signal POL, the control signal LR for the data transmission direction and sequence, etc. By way of example, each type of electrical signal may include one electrical signal; or, each type of electrical signal may include multiple electrical signals, specifically subject to actual applications.

[0047] The above driving circuit includes at least one first control signal line, and the specific number of the first control signal lines is not limited herein. By way of example, the first control signal line may be one, and at this time, the first control signal transmitted by the first control signal line to the source driver may include partial electrical signals or all electrical signals; or, the first control signal line may be multiple, and at this time, the first control signals transmitted by each first control signal line to the source driver may include partial electrical signals.

[0048] With the development of technology, display products have been more and more widely used. Among them, LCD (Liquid Crystal Display) and OLED (Organic Light Emitting Diode) display devices are extremely widely used. Taking LCD as an example for illustration, refer to Figure 5 as shown, between the Tcon and the source drivers (specifically the source drivers 11, 12, 13, and 14 shown in Figure 5 ), the mini-LVDS technology is generally used to transmit the data signal DATA. In addition, some control signals may also be used, such as: the control signal LR for the data transmission direction and sequence, the synchronization signal TP at the start and end of each row, the polarity inversion signal POL, etc. At this time, multiple signal lines are required to transmit the above various different signals. Figure 5 shows that signal lines for transmitting the data signal DATA, signal lines for transmitting the control signal LR for the data transmission direction and sequence, signal lines for transmitting the synchronization signal TP at the start and end of each row, and signal lines for transmitting the polarity inversion signal POL are provided between the Tcon and the source drivers 11, 12, 13, and 14 respectively. The more the number of signal lines, the greater the complexity caused to the design of the display device, and it will also widen the border of the display device.

[0049] And, refer to Figure 5 as shown, the transmission of the control signal LR for the data transmission direction and sequence requires not only the signal line between the Tcon and the source driver 11, but also the signal lines between adjacent source drivers, specifically the control signal LR1 for transmitting the data transmission direction and sequence, the control signal LR2 for transmitting the data transmission direction and sequence, and the control signal LR3 for transmitting the data transmission direction and sequence shown in Figure 5 . These signal lines are relatively long, and at the edge of the display panel 7 (specifically, the signal lines are arranged in the non-display area BB of the display panel 7), they are easily interfered with and damaged. It should be noted that Figure 1 、 Figure 3 and Figure 5 the display area of the display panel 7 is marked as AA.

[0050] To solve the above problems, in the driving circuit provided by the embodiments of the present application, the first control signal line is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes multiple types of electrical signals. Thus, the transmission of multiple types of electrical signals can be achieved through one first control signal line. Compared with the related art in which only one type of electrical signal can be transmitted through one signal line, the driving circuit provided by the embodiments of the present application can effectively reduce the number of signal lines. This can not only speed up the design time of the display device, reduce the design error rate, but also reduce the influence between signal lines, enhance the anti-aging and wear resistance of the display device, and improve the performance of the display device; in addition, it can also enable the display device to achieve a narrow bezel, providing a good user experience.

[0051] Optionally, referring to Figure 1 and Figure 3 As shown, the driving circuit includes a first control signal line 3, and the first control signal line 3 is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes at least some types of electrical signals.

[0052] The statement that the above first control signal includes at least some types of electrical signals means that: the above first control signal includes some types of electrical signals; or, the above first control signal includes all types of electrical signals, and no specific limitation is made here.

[0053] The driving circuit provided by the embodiments of the present application includes a first control signal line, which can transmit at least some types of electrical signals, thereby reducing the number of signal lines. Especially when one first control signal line can transmit all types of electrical signals, the number of signal lines can be minimized to the greatest extent, the design time of the display device can be accelerated more, the design error rate can be reduced more, the influence between signal lines can be reduced more effectively, the anti-aging and wear resistance of the display device can be increased better, and the performance of the display device can be improved better; in addition, it can also enable the display device to achieve a narrower bezel, providing a good user experience.

[0054] Optionally, the driving circuit includes multiple first control signal lines, and each first control signal line is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes multiple types of electrical signals; the number of types of electrical signals included in each first control signal line is at least partially the same.

[0055] That the types of electrical signals included in each of the above-mentioned first control signal lines are at least partially the same means that: the types of electrical signals included in each of the above-mentioned first control signal lines are partially the same; or, the types of electrical signals included in each of the above-mentioned first control signal lines are all the same, and no specific limitation is made here. By way of example, the driving circuit includes two first control signal lines. One of the first control signal lines includes one type of electrical signal, for example: the control signal LR for the data transmission direction and sequence. The other first control signal line also includes one type of electrical signal, for example: the synchronization signal TP for the start and end of each row. At this time, the number of types of electrical signals included in the two first control signal lines is one type each.

[0056] Or, the types of electrical signals included in each of the first control signal lines are all different.

[0057] By way of example, the driving circuit includes two first control signal lines. One of the first control signal lines includes one type of electrical signal, for example: the control signal LR for the data transmission direction and sequence. The other first control signal line includes two types of electrical signals, for example: the synchronization signal TP for the start and end of each row and the polarity inversion signal POL. At this time, the number of types of electrical signals included in the two first control signal lines is different.

[0058] In the driving circuit provided by the embodiment of the present application, the types of electrical signals included in each of the first control signal lines are at least partially the same or all different, so that the electrical signals transmitted by the first control signal lines can be flexibly designed, enabling the display device to be diversified.

[0059] Optionally, the first control signal includes a first electrical signal and a second electrical signal, and the types of the first electrical signal and the second electrical signal are different.

[0060] The source driver is configured to: receive and parse the first control signal, obtain the first electrical signal according to the first pulse and the single pulse in the pulse cluster in the first control signal; and obtain the second electrical signal according to the number of pulses in the pulse cluster in the first control signal; wherein, the first control signal includes at least one single pulse and at least one pulse cluster. Thus, the first electrical signal or the second electrical signal can be obtained through the type and number of pulses, etc., which is simple and easy to implement.

[0061] No specific limitation is made here for the types of the above-mentioned first signal and second signal. By way of example, the above-mentioned first signal and second signal can both include any one of the control signal LR for the data transmission direction and sequence, the synchronization signal TP for the start and end of each row, the polarity inversion signal POL, etc., as long as the first signal is different from the second signal.

[0062] The above-mentioned pulse cluster refers to multiple pulses, and no specific limitation is made here for the number of pulses in the pulse cluster. By way of example, the above-mentioned pulse cluster can include double pulses, triple pulses, etc.

[0063] Taking the first signal as the synchronization signal TP at the start and end of each line and the second signal as the polarity inversion signal POL as an example, combined with Figure 2 the timing diagram shown below for illustration. Refer to Figure 2 As shown, the first control signal includes two single pulses and three pulse clusters. During the first line time (1 line time), first, the source driver receives a double pulse. At this time, the source driver obtains the synchronization signal TP at the start and end of each line according to the first pulse in the double pulse, and the source driver obtains the polarity inversion signal POL according to the number of pulses in the double pulse being two. Secondly, the source driver receives a single pulse. At this time, the source driver obtains the synchronization signal TP at the start and end of each line according to the single pulse. Thirdly, the source driver receives a triple pulse. At this time, the source driver obtains the synchronization signal TP at the start and end of each line according to the first pulse in the triple pulse, and the source driver obtains the polarity inversion signal POL according to the number of pulses in the triple pulse being three. Then, the source driver receives a single pulse. At this time, the source driver obtains the synchronization signal TP at the start and end of each line. Then, the source driver receives a double pulse. At this time, the source driver obtains the synchronization signal TP at the start and end of each line according to the first pulse in the double pulse, and the source driver obtains the polarity inversion signal POL according to the number of pulses in the double pulse being two.

[0064] It should be noted that, first, the above is only an illustration taking the first control signal including two single pulses and three pulse clusters as an example. Of course, the pulses included in the first control signal line are not limited to this, and others can refer to the above to obtain the first electrical signal and the second electrical signal, which will not be elaborated here.

[0065] Second, Figure 6 shows Figure 5 the timing diagram of the transmission of the synchronization signal TP at the start and end of each line and the polarity inversion signal POL through the synchronization signal line at the start and end of each line between the Tcon and the source driver in Figure 6 . Since the synchronization signal TP at the start and end of each line and the polarity inversion signal POL are transmitted through their respective independent signal lines, therefore Figure 6 the timing of the synchronization signal TP at the start and end of each line and the polarity inversion signal POL in

[0066] is independent. Refer to Figure 1 and Figure 3As shown, the driving circuit further includes at least one second control signal line 4. One end of the second control signal line 4 is electrically connected to the controller, and the other end is electrically connected to the source driver. The second control signal line 4 is configured to be able to transmit a second control signal to the source driver. Among them, the second control signal includes an electrical signal, and the second control signal is different from the first control signal. Thus, at least one electrical signal can be independently transmitted through the second control signal line.

[0067] Here, the number of the above-mentioned second control signal lines is not specifically limited. By way of example, the above-mentioned second control signal line can be one as shown in Figure 1 and Figure 3 shown; or, the above-mentioned second control signal lines can be multiple, specifically subject to the actual application.

[0068] Here, the above-mentioned second control signal is not specifically limited. By way of example, the above-mentioned second control signal can include any one of a control signal LR for data transmission direction and order, a synchronization signal TP for the start and end of each row, a polarity inversion signal POL, etc. Figure 1 Taking the control signal LR for data transmission direction and order as an example of the second control signal for illustration.

[0069] Optionally, the first electrical signal is a synchronization signal for the start and end of each row, and the second signal is a polarity inversion signal.

[0070] The source driver is further configured to: obtain a positive-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being even and the last pulse of the even number of pulse clusters remaining for a preset time; obtain a negative-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being odd and the last pulse of the odd number of pulse clusters remaining for a preset time; and maintain the polarity of the polarity inversion signal according to the single pulse in the first control signal.

[0071] The necessity of setting the polarity inversion signal POL is illustrated below by taking an LCD as an example. An LCD is a display device using liquid crystal as a material. Liquid crystal is a class of organic compounds between solid and liquid states, showing both the fluidity of a liquid and the optical anisotropy of a crystal at room temperature. When heated, the liquid crystal will become a transparent liquid state, and when cooled, it will become a crystalline turbid solid state. Under the action of an electric field, the liquid crystal molecules will change in arrangement, thereby affecting the intensity change of the incident light beam passing through the liquid crystal. This change in light intensity is further manifested as a change in brightness through the action of a polarizer. Accordingly, by controlling the liquid crystal electric field, the brightness change of light can be realized, thereby achieving the purpose of information display.

[0072] However, the driving voltage of the liquid crystal molecules cannot be fixed at a certain value, otherwise, over time, the liquid crystal molecules will undergo polarization and gradually lose their optical rotation characteristics. Therefore, in order to avoid damage to the characteristics of the liquid crystal molecules, the driving voltage of the liquid crystal molecules must be subjected to polarity transformation. This requires dividing the display voltage of the LCD into two polarities, one is the positive polarity and the other is the negative polarity. At this time, a polarity inversion signal POL is required to control the display of different polarities. There are four common polarity transformation methods, namely the frame-by-frame inversion method, the line-by-line inversion method, the column-by-column inversion method, and the point-by-point inversion method. The polarity inversion control method provided by the embodiments of the present application is applicable to any one of the polarity transformation methods.

[0073] Reference Figure 2 As shown, the first control signal includes two single pulses and three pulse clusters. During the first row time (1linetime), first, after the source driver responds to the second pulse of the double pulse and holds for a period of time t, after this period of time, the source driver identifies that the number of pulses in this pulse cluster is 2, and obtains a positive polarity inversion signal POL (sets the output polarity to positive); secondly, the source driver responds to the single pulse. After the falling edge of the single pulse has passed for more than time t, the source driver identifies that the number of pulses is 1, so it still obtains a positive polarity inversion signal POL (the output polarity remains unchanged); thirdly, after the source driver responds to the second and third pulses of the triple pulse and holds for a period of time t, after this period of time, the source driver identifies that the number of pulses in this pulse cluster is 3, and obtains a negative polarity inversion signal POL (sets the output polarity to negative); then, the source driver responds to the single pulse. After the falling edge of the single pulse has passed for more than time t, the source driver identifies that the number of pulses is 1, so it still obtains a negative polarity inversion signal POL (the output polarity remains unchanged); then, after the source driver responds to the second pulse of the double pulse and holds for a period of time t, after this period of time, the source driver identifies that the number of pulses in this pulse cluster is 2, and obtains a positive polarity inversion signal POL (sets the output polarity to positive). In this way, it repeats continuously. Thus, the source driver completes both the start and end functions of a row and the polarity inversion function through one control line.

[0074] It should be noted that a single pulse needs to be set between any adjacent multi-pulses so that the source driver can maintain receiving the synchronization signal TP for the start and end of each row.

[0075] In the driving circuit provided by the embodiment of the present application, instead of separately configuring the synchronization signal lines and polarity inversion signal lines at the beginning and end of each row, the two types of signal lines are combined into one. Through a single control signal line, the synchronization signal TP and polarity inversion signal POL at the beginning and end of each row can be transmitted, thereby effectively reducing the number of control signal lines. At the same time, different polarity inversion signals can be output according to the number of pulses in each pulse cluster, and the polarity of the polarity inversion signal of the pulse cluster before the single pulse can be maintained during the single pulse, reducing or avoiding the polarization phenomenon of the liquid crystal in the liquid crystal display device and improving the performance of the display device.

[0076] Optionally, referring to Figure 1 As shown, the driving circuit includes a second control signal line 4. One end of the second control signal line 4 is electrically connected to the controller 1 and the other end is electrically connected to a source driver ( Figure 1 the source driver 21 described above), and the second control signal includes a control signal for the data transmission direction and sequence.

[0077] Referring to Figure 1 As shown, the driving circuit further includes a third control signal line 5. The adjacent source drivers are electrically connected through the third control signal line 5, and the third control signal line 5 is configured to be able to transmit the control signal for the data transmission direction and sequence between the adjacent source drivers.

[0078] Here, the number of the above-mentioned third control signal lines is not specifically limited. For example, the above-mentioned third control signal line can be one; or, the above-mentioned third control signal line can be multiple, specifically subject to the actual application.

[0079] In the driving circuit provided by the embodiment of the present application, since a second control signal line is provided between the controller and the source driver, and a third control signal line is provided between the adjacent source drivers, and the third control signal line transmits the same type of electrical signal as the second control signal line, that is, transmits the control signal for the data transmission direction and sequence, the transmission direction of other electrical signals can be limited by transmitting the control signal for the data transmission direction and sequence, which is simple and easy to implement.

[0080] Optionally, referring to Figure 1 and Figure 2 As shown, the driving circuit further includes a data signal line 6. One end of the data signal line 6 is electrically connected to the controller 1 and the other end is electrically connected to the source driver, and the data signal line 6 is configured to be able to transmit a data signal to the source driver according to the control signal for the data transmission direction and sequence.

[0081] The source driver is further configured to: end the reception of the first row of data signals according to the rising edge of the first pulse in the pulse cluster in the first control signal and the rising edge of the single pulse in the first control signal; and start the reception of the second row of data signals according to the falling edge of the first pulse in the pulse cluster in the first control signal and the falling edge of the single pulse in the first control signal.

[0082] Here, the number of the above data signal lines is not specifically limited. For example, the above data signal line can be one; or, the above data signal lines can be multiple, specifically subject to the actual application.

[0083] Here, the transmission mode of the above data signals is not specifically limited. For example, the controller can transmit the data signal DATA to the source driver through the mini-LVDS technology.

[0084] Reference Figure 2 As shown, the first control signal includes two single pulses and three pulse clusters. During the first row time (1linetime), first, the source driver responds to the rising edge of the first pulse of the double pulse to end the reception of the data signal DATA of the first row (i.e., the previous row), and starts the reception of the data signal DATA of the second row (i.e., the next row) at the falling edge of the first pulse; second, the source driver responds to the rising edge of the single pulse to end the reception of the data signal DATA of the first row (i.e., the previous row), and starts the reception of the data signal DATA of the second row (i.e., the next row) at the falling edge of the single pulse; third, the source driver responds to the rising edge of the first pulse of the triple pulse to end the reception of the data signal DATA of the first row (i.e., the previous row), and starts the reception of the data signal DATA of the second row (i.e., the next row) at the falling edge of the first pulse; then, the source driver responds to the rising edge of the single pulse to end the reception of the data signal DATA of the first row (i.e., the previous row), and starts the reception of the data signal DATA of the second row (i.e., the next row) at the falling edge of the single pulse; then, the source driver responds to the rising edge of the first pulse of the double pulse to end the reception of the data signal DATA of the first row (i.e., the previous row), and starts the reception of the data signal DATA of the second row (i.e., the next row) at the falling edge of the first pulse. The same applies to the remaining number of pulse clusters, which will not be elaborated here.

[0085] In the driving circuit provided by the embodiment of the present application, the transmission direction of the data signal can be limited by the control signal of the data transmission direction and sequence, and which row of data signals to receive can be determined by the rising edge and falling edge of the first pulse in any pulse cluster, which is simple and easy to implement.

[0086] Optionally, as shown in Figure 3 the driving circuit includes multiple source drivers ( Figure 3The source drivers 21, 22, 23, and 24), are electrically connected between adjacent source drivers; each source driver includes a storage address; the first control signal includes a first electrical signal.

[0087] The source driver is configured to: receive and parse the first control signal, and determine whether the source driver with the storage address receives the first electrical signal according to different pulses in the first control signal.

[0088] Here, the specific manner of electrical connection between the adjacent source drivers is not specifically limited. For example, the adjacent source drivers can be directly electrically connected; or, the adjacent source drivers can be electrically connected through other structures.

[0089] Here, the specific manner of setting the storage address of the source driver is not specifically limited. For example, the storage address can be set by setting pins on the source driver. Specifically, two pins can be set on each source driver, and the other ends of these two pins can be electrically connected to the PCB (Printed Circuit Boards) respectively. At this time, the addresses are set for these two pins through the PCB. For example: when there are pins A and B on the source driver, and both pins A and B are at low level, it represents address 00; when pin A is at low level and pin B is at high level, it represents address 01; when pin A is at high level and pin B is at low level, it represents address 10; when both pins A and B are at high level, it represents address 11, so as to distinguish the four source drivers.

[0090] Here, the above first signal is not specifically limited. For example, the first signal can include any one of the control signal LR for data transmission direction and sequence, the synchronization signal TP for the start and end of each line, the polarity inversion signal POL, etc.

[0091] Next, taking Figure 3 the first signal transmitted by the first control signal line 3 in as the synchronization signal TP for the start and end of each line, combined with Figure 4 the timing diagram of for illustration. First, the four source drivers are distinguished by setting addresses through pins. Specifically, there are pins A and B on each source driver. When both pins A and B are at low level, it represents address 00, which is the storage address of the source driver 21 shown in Figure 3 ; when pin A is at low level and pin B is at high level, it represents address 01, which is the storage address of the source driver 22 shown in Figure 3 ; when pin A is at high level and pin B is at low level, it represents address 10, which is the storage address of the source driver shown in Figure 3The storage address of the source driver 23 shown; when both pin A and pin B are at high level, it represents address 11, which is Figure 3 The storage address of the source driver 24 shown. The number of pulses of the first control signal determines which source driver the synchronization signal TP at the start and end of each line is transmitted to: Refer to Figure 4 As shown, when the source driver receives double pulses, the pulse counts of all source drivers are cleared, and at this time, the source driver 21 with storage address 00 starts to receive the synchronization signal TP at the start and end of each line; when the driving source driver receives the 1st single pulse, the pulse counts of all source drivers become 1, and the source driver 22 with storage address 01 starts to receive the synchronization signal TP at the start and end of each line; when the driving source driver receives the 2nd single pulse, the pulse counts of all source drivers become 2, and the source driver 23 with storage address 10 starts to receive the synchronization signal TP at the start and end of each line; when the driving source driver receives the 3rd single pulse, the pulse counts of all source drivers become 3, and the source driver 24 with storage address 11 starts to receive the synchronization signal TP at the start and end of each line.

[0092] In the driving circuit provided by the embodiment of the present application, by setting specific storage addresses for each source driver in multiple source drivers and determining which source driver receives the synchronization signal TP at the start and end of each line according to the number of pulses of the first control signal, it is possible to determine the transmission direction of the synchronization signal TP at the start and end of each line on the basis of omitting the signal lines between adjacent source drivers, thereby effectively reducing the number of signal lines.

[0093] It should be noted that, first, the above first control signal may further include a first electrical signal and a second electrical signal. For example: the first electrical signal is the synchronization signal TP at the start and end of each line, and the second electrical signal is the control signal LR for the data transmission direction and sequence.

[0094] Second, different waveforms of the first control signal can also be designed to determine which source driver with a storage address receives the electrical signal. By way of example, it can be designed that when the source driver receives triple pulses, the source driver 21 with storage address 00 starts to receive the electrical signal; of course, other waveforms are also applicable to determine which source driver with a storage address starts to receive the electrical signal, which shall be subject to actual needs and will not be elaborated here.

[0095] Third, Figure 7 Shows Figure 5The timing diagram of the control signal LR for the data transfer direction and sequence transmitted between the Tcon and the source driver through the control signal line for the data transfer direction and sequence, and the control signal LR for the data transfer direction and sequence transmitted between adjacent source drivers through the control signal line for the data transfer direction and sequence. Since Figure 5 the control signal LR for the data transfer direction and sequence shown is transmitted through one signal line, and the control signal LR for the data transfer direction and sequence is also required to be transmitted through the signal line between adjacent source drivers to determine the transmission direction of other electrical signals, so Figure 7 the waveform diagram shown is obtained.

[0096] Optionally, as shown in Figure 3 the driving circuit further includes a data signal line 6. One end of the data signal line 6 is electrically connected to the controller 1 and the other end is electrically connected to the source driver. The data signal line 6 is configured to transmit a data signal to the source driver.

[0097] The source driver is further configured to: determine whether the source driver for storing the address receives the data signal according to different pulses in the first control signal.

[0098] Next, taking Figure 3 the first signal transmitted by the first control signal line 3 in as the synchronization signal TP at the start and end of each row, combined with Figure 4 the timing diagram is described. First, the four source drivers are distinguished by setting addresses through pins. Specifically, pins A and B are provided on each source driver. When both pins A and B are connected to a low level, it represents address 00, which is the Figure 3 storage address of the source driver 21 shown; when pin A is connected to a low level and pin B is connected to a high level, it represents address 01, which is the Figure 3 storage address of the source driver 22 shown; when pin A is connected to a high level and pin B is connected to a low level, it represents address 10, which is the Figure 3 storage address of the source driver 23 shown; when both pins A and B are connected to a high level, it represents address 11, which is the Figure 3 storage address of the source driver 24 shown. The number of pulses of the synchronization signal TP at the start and end of each row determines which source driver the data signal DATA is transmitted to: Refer to Figure 4As shown, when the source driver receives a double pulse, it represents the start of a row of data. The pulse counts of all source drivers are cleared. At this time, the source driver 21 with the storage address 00 starts to receive the data signal DATA. When the driving source driver receives the first single pulse, the pulse counts of all source drivers become 1, and the source driver 22 with the storage address 01 starts to receive the data signal DATA. When the driving source driver receives the second single pulse, the pulse counts of all source drivers become 2, and the source driver 23 with the storage address 10 starts to receive the data signal DATA. When the driving source driver receives the third single pulse, the pulse counts of all source drivers become 3, and the source driver 24 with the storage address 11 starts to receive the data signal DATA. The rest can be deduced by analogy and will not be elaborated here.

[0099] In the driving circuit provided by the embodiment of the present application, by setting storage addresses for each of the multiple source drivers and determining which source driver receives the data signal DATA according to the number of pulses of the first control signal, it is possible to omit the signal lines between adjacent source drivers and also determine the transmission direction of the data signal DATA, thereby effectively reducing the number of signal lines. This can not only speed up the design time of the display device, reduce the error rate, but also increase the anti-aging and wear resistance of the display device, providing a good user experience.

[0100] Optionally, the first electrical signal is a synchronization signal for the start and end of each row.

[0101] The driving circuit further includes a second control signal line. One end of the second control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The second control signal line is configured to be able to transmit a second control signal to the source driver. Among them, the second control signal includes an electrical signal, and the second control signal is a polarity inversion signal.

[0102] In the driving circuit provided by the embodiment of the present application, on the one hand, through one control signal line, it is possible to transmit the synchronization signal TP for the start and end of each row and the control signal LR for the data transmission direction and sequence, and achieve the cascading between adjacent source drivers, thereby reducing the number of control signal lines. This can not only speed up the design time of the display device, reduce the design error rate, but also effectively achieve a narrow border, reduce the influence between control signal lines, increase the anti-aging and wear resistance of the display device, improve the performance of the display device, and provide a good user experience. On the other hand, it also realizes polarity inversion, reducing or avoiding the polarization problem of the liquid crystal display device.

[0103] The embodiment of the present application also provides a display device. Refer to Figure 1 and Figure 3As shown, it includes a display panel 7 and the above-mentioned driving circuit. The source driver in the driving circuit is electrically connected to the display panel 7 and is configured to be able to drive the display panel 7.

[0104] Here, the type of the above-mentioned display panel is not specifically limited. For example, the above-mentioned display panel can be an LCD; or, the above-mentioned display panel can be an OLED, such as: AMOLED. For both LCD and OLED, the materials of the active layer can include a-Si (amorphous silicon), LTPS (Low Temperature Poly-silicon), oxides, etc.

[0105] Here, the setting position of the above-mentioned source driver on the display panel is not specifically limited. For example, referring to Figure 1 and Figure 3 As shown, the source driver 21, the source driver 22, the source driver 23, and the source driver 24 can all be set in the non-display area BB of the display panel 7.

[0106] The above-mentioned display device can be a flexible display device (also known as a flexible screen), or a rigid display device (i.e., a non-bendable display screen), which is not limited here. The above-mentioned display device can be an OLED display device or an LCD display device. The above-mentioned display device can be any product or component with a display function such as a TV, a digital camera, a mobile phone, a tablet computer, etc.; the above-mentioned display device can also be applied to fields such as identity recognition and medical devices. Products that have been promoted or have good promotion prospects include security identity authentication, smart door locks, medical image acquisition, etc. This display device has the advantages of fewer signal lines, shorter design time, lower error rate, stronger anti-aging and wear resistance, ability to achieve narrow borders, good display effect, long lifespan, high stability, high contrast, good imaging quality, and high product quality.

[0107] Another embodiment of the present application provides a driving method for the above-mentioned driving circuit. The driving circuit includes a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver.

[0108] The driving method includes:

[0109] S1. The controller transmits a first control signal to the source driver through the first control signal line; wherein, the first control signal includes multiple electrical signals.

[0110] By performing the above-mentioned step S1, the transmission of multiple electrical signals can be achieved through a single first control signal line, thereby effectively reducing the number of signal lines. This can not only accelerate the design time of the display device, reduce the design error rate, but also reduce the interference between signal lines, enhance the anti-aging and anti-wear capabilities of the display device, and improve the performance of the display device. Additionally, it can enable the display device to achieve a narrow border and provide a good user experience.

[0111] The following will specifically describe a driving method in conjunction with Figure 1 and Figure 2 . Referring to Figure 1 as shown, there is a first control signal line 3 (the first control signal transmitted includes the synchronization signals TP at the start and end of each row and the second signal is the polarity inversion signal POL), a data signal line 6 (transmitting the data signal DATA), a second control signal line 4, and a third control signal line 5 (transmitting the control signal LR for the data transmission direction and sequence) between the Tcon and the source driver.

[0112] The Tcon transmits the control signal LR for the data transmission direction and sequence to the source driver 21, and then the source driver 21 transmits the control signal LR for the data transmission direction and sequence to the source driver 22, the source driver 22 transmits it to the source driver 23, and the source driver 23 transmits it to the source driver 24 in sequence, thereby limiting the transmission direction of, for example, the data signal DATA.

[0113] The Tcon transmits the first control signal to each source driver. First, each source driver receives a double pulse. According to the rising edge of the first pulse in the double pulse, the reception of the data signal DATA in the first row ends, and according to the falling edge of the first pulse in the double pulse, the reception of the data signal DATA in the second row starts (the order in which the source driver ends or receives the data signal DATA is determined by the above-mentioned control signal LR for the data transmission direction and sequence); after each source controller receives the second pulse of the double pulse and passes through time t, each source controller obtains the positive-polarity polarity inversion signal POL in the first control signal.

[0114] Then, each source driver receives a single pulse. According to the rising edge of the single pulse, the reception of the data signal DATA in the first row ends, and according to the falling edge of the single pulse, the reception of the data signal DATA in the second row starts; at this time, since it is a single pulse, the polarity of the polarity inversion signal POL is not changed, that is, each source controller still obtains the positive-polarity polarity inversion signal POL.

[0115] Then, each source driver receives three pulses. According to the rising edge of the first pulse in the three pulses, the reception of the data signal DATA of the first row ends, and according to the falling edge of the first pulse in the three pulses, the reception of the data signal DATA of the second row starts; after the second pulse and the third pulse of the three pulses are received by each source controller and after a time t, each source controller obtains the polarity inversion signal POL of the negative polarity in the first control signal.

[0116] Subsequently, each source driver receives a single pulse. According to the rising edge of the single pulse, the reception of the data signal DATA of the first row ends, and according to the falling edge of the single pulse, the reception of the data signal DATA of the second row starts; at this time, since it is a single pulse, the polarity of the polarity inversion signal POL is not changed, that is, each source controller still obtains the polarity inversion signal POL of the negative polarity.

[0117] Finally, each source driver receives a double pulse. According to the rising edge of the first pulse in the double pulse, the reception of the data signal DATA of the first row ends, and according to the falling edge of the first pulse in the double pulse, the reception of the data signal DATA of the second row starts; after the second pulse of the double pulse is received by each source controller and after a time t, each source controller obtains the polarity inversion signal POL of the positive polarity in the first control signal.

[0118] For the structural descriptions of the controller, source driver, etc. in the embodiments of the present application, reference may be made to the foregoing embodiments, which will not be elaborated here.

[0119] As used herein, the term "embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present application.

[0120] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that, It includes a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The first control signal line is configured to be able to transmit a first control signal to the source driver, wherein the first control signal includes multiple types of electrical signals; The first control signal includes a first electrical signal and a second electrical signal; The source driver is configured to: receive and parse the first control signal, obtain the first electrical signal according to the first pulse and single pulse of the pulse cluster in the first control signal; and obtain the second electrical signal according to the number of pulses in the pulse cluster in the first control signal; wherein the first control signal includes at least one single pulse and at least one pulse cluster.

2. The drive circuit according to claim 1, characterized in that The driving circuit includes one first control signal line, and the first control signal line is configured to be able to transmit the first control signal to the source driver, wherein the first control signal includes at least some types of electrical signals.

3. The drive circuit according to claim 1, characterized in that, The driving circuit includes multiple first control signal lines, and each first control signal line is configured to be able to transmit the first control signal to the source driver, wherein the first control signal includes multiple types of electrical signals; the number of types of electrical signals included in each first control signal line is at least partially the same; Alternatively, the number of types of electrical signals included in each first control signal line is different.

4. The drive circuit according to claim 2, characterized in that, The types of the first electrical signal and the second electrical signal are different.

5. The drive circuit according to claim 4, wherein The driving circuit further includes at least one second control signal line. One end of the second control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The second control signal line is configured to be able to transmit a second control signal to the source driver, wherein the second control signal includes one type of electrical signal, and the second control signal is different from the first control signal.

6. The drive circuit according to claim 5, characterized in that, The first electrical signal is a synchronization signal at the start and end of each row, and the second signal is a polarity inversion signal; The source driver is further configured to: obtain the positive-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being even and the last pulse of the even number of pulse clusters remaining for a preset time; obtain the negative-polarity polarity inversion signal according to the number of pulses in each pulse cluster in the first control signal being odd and the last pulse of the odd number of pulse clusters remaining for the preset time; and maintain the polarity of the polarity inversion signal according to the single pulse in the first control signal.

7. The drive circuit according to claim 6, characterized in that, The driving circuit includes one second control signal line. One end of the second control signal line is electrically connected to the controller, and the other end is electrically connected to one source driver. The second control signal includes a control signal for the data transmission direction and sequence; The driving circuit further includes a third control signal line. Adjacent source drivers are electrically connected through the third control signal line, and the third control signal line is configured to be able to transmit the control signal for the data transmission direction and sequence between adjacent source drivers.

8. The drive circuit according to claim 7, wherein The driving circuit further includes a data signal line, one end of the data signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The data signal line is configured to transmit a data signal to the source driver according to a control signal for controlling the data transmission direction and sequence; The source driver is further configured to: end the reception of the data signal of the first row according to the rising edge of the first pulse of the pulse cluster in the first control signal and the rising edge of the single pulse in the first control signal; and start the reception of the data signal of the second row according to the falling edge of the first pulse of the pulse cluster in the first control signal and the falling edge of the single pulse in the first control signal.

9. The drive circuit according to claim 2, wherein The driving circuit includes a plurality of the source drivers, and adjacent source drivers are electrically connected; each of the source drivers includes a storage address; the first control signal includes a first electrical signal; The source driver is configured to: receive and analyze the first control signal, and determine whether the source driver of the storage address receives the first electrical signal according to different pulses in the first control signal.

10. The drive circuit according to claim 9, wherein, The driving circuit further includes a data signal line, one end of the data signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The data signal line is configured to transmit a data signal to the source driver; The source driver is further configured to: determine whether the source driver of the storage address receives the data signal according to different pulses in the first control signal.

11. The drive circuit according to claim 10, wherein The first electrical signal is a synchronization signal for the start and end of each row; The driving circuit further includes a second control signal line, one end of the second control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver. The second control signal line is configured to be able to transmit a second control signal to the source driver, wherein the second control signal includes an electrical signal, and the second control signal is a polarity inversion signal.

12. A display device, characterized in that, It includes a display panel and the driving circuit according to any one of claims 1-11. The source driver in the driving circuit is electrically connected to the display panel and is configured to be able to drive the display panel.

13. A driving method for a driving circuit according to any one of claims 1-11, characterized in that, The driving circuit includes a controller, a source driver, and at least one first control signal line. One end of the first control signal line is electrically connected to the controller, and the other end is electrically connected to the source driver; The driving method includes: The controller transmits a first control signal to the source driver through the first control signal line; wherein, the first control signal includes multiple electrical signals.

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