A memory idle time refresh method and system for resisting single event upset effect accumulation

Abstract

A memory idle-time refresh method and system that resists the accumulation of single-particle upset effects. When the processor accesses the memory sparsely or idle, a read operation is initiated to refresh the data in the memory, and the data that has experienced a single-particle upset is checked and corrected. The error site is recorded and an interrupt is sent to the processor. The error address, the read source data, and the check code are stored in the corresponding register to be read and judged by the processor. The refresh process is executed by the programmable memory autonomous access component. During the refresh period, the processor can execute other operation programs except memory access. After the refresh process is completed, the processor can access the memory normally. The present invention can autonomously complete the memory refresh task without occupying the processor's computing resources when the processor accesses the memory sparsely or idle, thereby preventing the accumulation of errors caused by single-particle upsets in memory in space applications, and preventing single-bit errors from becoming double-bit errors or multi-bit errors.

Description

Technical Field

[0001] The present invention relates to a method and system for refreshing a memory in idle time and capable of resisting accumulation of single-particle upset effects, and belongs to the technical field of radiation-resistant integrated circuit design. Background Art

[0002] As memory cells like SRAM and SDRAM become increasingly sensitive to single-event upsets (SEEs) in space radiation environments, SEEs are prone to accumulating errors in space applications, shifting from single-bit errors to double-bit or multi-bit errors. Therefore, it is necessary to design an idle refresh mechanism to prevent SEE errors from accumulating in memory cells that have not been accessed for a long time, ensuring that the number of erroneous bits in a memory cell is less than the error correction capability of the parity check code.

[0003] The traditional method of using processor access operations to refresh memory is generally to directly use the processor to periodically suspend the execution of normal tasks, access and refresh the memory, and continue to execute normal tasks after the refresh is completed. This method has the problem of a large amount of processor computing resources being occupied, affecting the execution of normal program tasks. The present invention designs and implements a memory refresh method that is resistant to the accumulation of single-particle flip effects. It can complete the memory refresh task autonomously without occupying the processor's computing resources when the processor access memory tasks are sparse or idle, and prevent the accumulation of errors caused by single-particle flips in memory in space applications, which turn single-bit errors into double-bit errors or multi-bit errors. The "programmable memory autonomous access component" in the present invention can be independently designed according to system integration requirements, or mature programmable components in the system can be reused to reduce the design and production costs of the system. Summary of the Invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the existing technology and provide a memory idle refresh method and system that is resistant to the accumulation of single-particle upset effects. When the processor accesses the memory sparsely or is idle, it does not occupy the processor's computing resources and can independently complete the memory refresh task, thereby preventing the accumulation of errors caused by single-particle upsets in the memory in space applications and ensuring that the number of bits where errors occur in the storage unit is less than the error correction capability of the check code.

[0005] The technical solution of the present invention is: a memory idle time refresh method that resists accumulation of single event upset effects, comprising:

[0006] Step 1: When the processor accesses the memory sparsely or is idle, it sends a memory refresh start instruction to the programmable memory autonomous access component;

[0007] Step 2: After receiving the memory refresh start instruction, the programmable memory autonomous access component loads the memory refresh program from the specified address configured by the processor and starts executing the program;

[0008] Step 3: The programmable memory autonomous access component starts to read the data in the current refresh address memory;

[0009] Step 4: The data error correction component in the memory control interface verifies the read memory data to determine whether the read data is correct, that is, detects whether a single event upset occurs in the memory;

[0010] Step 5: If the read data is correct in step 4, then determine whether the memory refresh program has been completed. If it is determined that the execution is completed, then the current round of memory refresh process ends;

[0011] Step 6: If it is determined in step 5 that the memory refresh program has not been completed, the current refresh address is accumulated and the process jumps to step 3 to continue execution;

[0012] Step 7: If the read data is judged to be incorrect in step 4, that is, a single event upset occurs in the memory, then determine whether the type of the data error is a correctable error;

[0013] Step 8: If the data error type is determined to be an uncorrectable error in step 7, the data error correction component will record the error scene, that is, store the error address, the read source data and the check code in the corresponding register for the processor to read and judge; otherwise, jump to step 11;

[0014] Step 9: The data error correction component sends an uncorrectable error interrupt to the processor, and performs error handling according to a preset error handling strategy;

[0015] Step 10: Jump to step 5 to determine whether the memory refresh program has been completed.

[0016] Step 11: The data error correction component records the error scene, that is, stores the error occurrence address, the read source data and the check code into the corresponding register, waiting for reading and judgment in the system error handling strategy;

[0017] Step 12: Determine whether the correctable error in step 11 needs to be corrected autonomously. If the system is set to require autonomous correction, write the corrected data provided by the data error correction component back to the memory to complete the error correction autonomously; otherwise, jump directly to step 13;

[0018] Step 13: The data error correction component sends a correctable error interrupt to the processor, and performs error handling according to a preset error handling strategy;

[0019] Step 14: Jump to step 5 to determine whether the memory refresh program has been completed.

[0020] Furthermore, the memory access is organized in the form of data and check code.

[0021] Furthermore, the memory refresh program is a cyclic address accumulation read access memory, and the starting address is specified by the processor or stored when the last memory refresh task is completed.

[0022] Furthermore, the access word length for accessing the memory is specified by the processor or fixed in the program.

[0023] A memory idle time refresh system resistant to single event upset effect accumulation includes a memory, a processor, a programmable memory autonomous access component, and a data error correction component connected via a data interconnection bus;

[0024] When the processor accesses the memory sparsely or is idle, it sends a memory refresh start instruction to the programmable memory autonomous access component;

[0025] After receiving the memory refresh start instruction, the programmable memory autonomous access component loads the memory refresh program from the specified address configured by the processor, starts executing the program, and reads the data in the current refresh address memory;

[0026] The data error correction and detection component is located at the memory control interface and is used to verify the read memory data to determine whether the read data is correct, that is, to detect whether a single-particle upset has occurred in the memory; if the read data is determined to be correct, then it is determined whether the memory refresh program has been completed, and if it is determined to be completed, then the current round of memory refresh process ends; if it is determined that the memory refresh program has not been completed, then the current refresh address is accumulated, and then the programmable memory autonomous access component re-reads the data in the refresh address memory; if it is determined that the read data is wrong, that is, a single-particle upset has occurred in the memory, then it is determined whether the type of data error is a correctable error; if the data error type is determined to be an uncorrectable error, then the data error correction and detection component will record the error scene, that is, the address where the error occurred, the source data read and the check code Store it in the corresponding register, waiting for the processor to read and judge; send an uncorrectable error interrupt to the processor, perform error handling according to the preset error handling strategy, and re-judge whether the memory refresh program has been executed; if the data error type is determined to be a correctable error, the error scene will be recorded, that is, the address where the error occurred, the read source data and the check code will be stored in the corresponding register, waiting for reading and judgment in the system error handling strategy; judge whether the correctable error needs to be corrected autonomously. If the system is set to require autonomous correction, the corrected data will be generated and written back to the memory to complete the error correction autonomously; if the correctable error does not need to be corrected autonomously, a correctable error interrupt will be sent to the processor, and error handling will be performed according to the preset error handling strategy; then re-judge whether the memory refresh program has been executed.

[0027] Furthermore, the memory access is organized in the form of data and check code.

[0028] Furthermore, the memory refresh program is a cyclic address accumulation read access memory, and the starting address is specified by the processor or stored when the last memory refresh task is completed.

[0029] Furthermore, the access word length for accessing the memory is specified by the processor or fixed in the program.

[0030] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a method for refreshing a memory in idle time to resist accumulation of single-particle upset effects.

[0031] A memory idle time refresh device capable of resisting accumulation of single-particle upset effects comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of a memory idle time refresh method capable of resisting accumulation of single-particle upset effects are implemented.

[0032] The advantages of the present invention compared with the prior art are:

[0033] (1) The present invention provides a memory refresh method that is resistant to the accumulation of single-particle upset effects. The method can autonomously complete the memory refresh task without occupying the processor's computing resources when the processor's memory access tasks are sparse or idle, thereby preventing the accumulation of errors caused by single-particle upsets in memory in space applications and ensuring that the number of bits in which errors occur in the storage unit is less than the error correction capability of the check code.

[0034] (2) The "programmable memory autonomous access component" described in the present invention can be independently coded and designed according to system integration requirements, or it can reuse mature programmable components in the system to reduce the design and production costs of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the principle of a memory refresh method for resisting single event upset effect accumulation according to the present invention;

[0036] Figure 2 The present invention is a flow chart showing the principle of a memory refresh method for resisting single event upset effect accumulation. DETAILED DESCRIPTION

[0037] In order to better understand the above technical solution, the technical solution of the present application is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0038] The following is a further detailed description of a memory idle time refresh method and system for resisting single event upset effect accumulation provided by the embodiment of the present application in conjunction with the accompanying drawings (eg Figures 1-2 shown).

[0039] In the solution provided in the embodiment of the present application, Figure 1 The schematic diagram of the principle of a memory refresh method that resists the accumulation of single-particle upset effects of the present invention is shown. The method of the present invention adds a "programmable memory autonomous access component" to the system bus, which can start a read operation to refresh the data in the memory when the processor accesses the memory sparsely or is idle, and check and correct the data that has undergone a single-particle upset, and record the error site and send an interrupt to the processor, and store the error address, the read source data and the check code in the corresponding register to be read and judged by the processor; the refresh process is executed by the programmable memory autonomous access component, which does not occupy processor resources. During the refresh period, the processor can execute other operation programs except memory access; after the refresh process is completed, the processor can access the memory normally. The "programmable memory autonomous access component" can be independently coded and designed according to the system integration requirements, or it can reuse mature programmable components in the system. For example, in one example of the present invention, the existing general programmable direct memory access (DMA) module in the system is reused to reduce the design and production costs of the system. Compared with the existing technology, the method of the present invention solves the problem that the traditional use of processor access operations to refresh the memory requires the suspension of normal task execution, and the processor computing resources are occupied in large quantities. The method of the present invention is described in detail below with reference to the accompanying drawings. Figure 2 The method of the present invention comprises the following steps:

[0040] Step 1: When the processor in the system accesses the memory sparsely or is idle, it sends a "start memory refresh instruction" to the "programmable memory autonomous access component";

[0041] Step 2: After receiving the "start memory refresh instruction", the "programmable memory autonomous access component" loads the memory refresh program from the specified address configured by the processor and starts executing the program;

[0042] Step 3, the "programmable memory autonomous access component" starts to read the data in the current refresh address memory;

[0043] Step 4: The "data error correction component" in the "memory control interface" verifies the read memory data to determine whether the read data is correct, that is, to detect whether a single event upset has occurred in the memory;

[0044] Step 5: If the read data is correct in step 4, then determine whether the memory refresh program has been completed. If it is determined that the execution is completed, then the current round of memory refresh process ends;

[0045] Step 6: If it is determined in step 5 that the memory refresh program has not been completed, the current refresh address is accumulated and the process jumps to step 3 to continue execution;

[0046] Step 7: If the read data is judged to be incorrect in step 4, that is, a single event upset occurs in the memory, then determine whether the type of the data error is a "correctable error";

[0047] Step 8: If the data error type is determined to be "uncorrectable error" in step 7, the "data error correction component" will record the error scene, that is, store the error address, the read source data and the check code in the corresponding register, and wait for the processor to read and judge;

[0048] Step 9: The "data error correction component" sends an uncorrectable error interrupt to the processor, and performs error handling according to the error handling strategy designed by the system;

[0049] Step 10: Jump to step 5 to determine whether the memory refresh program has been completed.

[0050] Step 11: If the data error type is determined to be a "correctable error" in step 7, the "data error correction component" will record the error scene, that is, store the error address, the read source data and the check code in the corresponding register, waiting for reading and judgment in the system error handling strategy;

[0051] Step 12: Determine whether the "correctable error" in step 11 needs to be corrected autonomously. If the system is set to require autonomous correction, write the corrected data provided by the "data error correction component" back to the memory to complete the error correction autonomously; otherwise, jump directly to step 13;

[0052] Step 13: The "data error correction component" sends a correctable error interrupt to the processor, and performs error handling according to the error handling strategy designed by the system;

[0053] Step 14: Jump to step 5 to determine whether the memory refresh program has been completed.

[0054] Furthermore, in a possible implementation, the memory access is organized in the form of data + check code, with the ability to perform error detection and correction on the data through the check code;

[0055] In one possible implementation, the memory refresh program is designed to access the memory by cyclic address accumulation, with the starting address specified by the processor or stored at the end of the last memory refresh task; the access word length is specified by the processor or fixed in the program;

[0056] Optionally, in a possible implementation, the "programmable memory autonomous access component" can be autonomously coded and designed according to the above functional description, or mature programmable components in the system can be reused.

[0057] like Figure 1 , based on Figure 2 With the same inventive concept, the present invention also provides a memory refresh system that is resistant to accumulation of single event upset effects, comprising a memory, a processor, a programmable memory autonomous access component, and a data error correction component connected via a data interconnect bus;

[0058] When the processor accesses the memory sparsely or is idle, it sends a memory refresh start instruction to the programmable memory autonomous access component;

[0059] After receiving the memory refresh start instruction, the programmable memory autonomous access component loads the memory refresh program from the specified address configured by the processor, starts executing the program, and reads the data in the current refresh address memory;

[0060] The data error correction and detection component is located at the memory control interface and is used to verify the read memory data to determine whether the read data is correct, that is, to detect whether a single-particle upset has occurred in the memory; if the read data is determined to be correct, then it is determined whether the memory refresh program has been completed, and if it is determined to be completed, then the current round of memory refresh process ends; if it is determined that the memory refresh program has not been completed, then the current refresh address is accumulated, and then the programmable memory autonomous access component re-reads the data in the refresh address memory; if it is determined that the read data is wrong, that is, a single-particle upset has occurred in the memory, then it is determined whether the type of data error is a correctable error; if the data error type is determined to be an uncorrectable error, then the data error correction and detection component will record the error scene, that is, store the error address, the read source data and the check code to the corresponding register, waiting for the processor to read and judge; send an uncorrectable error interrupt to the processor, perform error handling according to the preset error handling strategy, and re-judge whether the memory refresh program has been executed; on the contrary, if the data error type is determined to be a correctable error, the error scene will be recorded, that is, the error address, the read source data and the check code will be stored in the corresponding register, waiting for the system error handling strategy to read and judge; judge whether the correctable error needs to be corrected autonomously. If the system is set to require autonomous correction, the corrected data will be generated and written back to the memory to complete the error correction autonomously; if the correctable error does not need to be corrected autonomously, a correctable error interrupt will be sent to the processor, and error handling will be performed according to the preset error handling strategy; then re-judge whether the memory refresh program has been executed.

[0061] Furthermore, the memory access is organized in the form of data+check code.

[0062] In a possible implementation, the memory refresh program is a cyclic address accumulation read access memory, and the starting address is specified by the processor or stored when the last memory refresh task is completed.

[0063] In a possible implementation, the access word length for accessing the memory is specified by a processor or fixed in a program.

[0064] The present application provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer executes Figure 1 The method described.

[0065] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0066] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0067] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0069] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

[0070] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A memory idle time refresh method to resist single event upset effect accumulation, characterized in that: include: Step 1: When the processor accesses the memory sparsely or is idle, it sends a memory refresh start instruction to the programmable memory autonomous access component; Step 2: After receiving the memory refresh start instruction, the programmable memory autonomous access component loads the memory refresh program from the specified address configured by the processor and starts executing the program; Step 3: The programmable memory autonomous access component starts to read the data in the current refresh address memory; Step 4: The data error correction component in the memory control interface verifies the read memory data to determine whether the read data is correct, that is, detects whether a single event upset occurs in the memory; Step 5: If the read data is correct in step 4, then determine whether the memory refresh program has been completed. If it is determined that the execution is completed, then the current round of memory refresh process ends; Step 6: If it is determined in step 5 that the memory refresh program has not been completed, the current refresh address is accumulated and the process jumps to step 3 to continue execution; Step 7: If the read data is judged to be incorrect in step 4, that is, a single event upset occurs in the memory, then determine whether the type of the data error is a correctable error; Step 8: If the data error type is determined to be an uncorrectable error in step 7, the data error correction component will record the error scene, that is, store the error address, the read source data and the check code in the corresponding register for the processor to read and judge; otherwise, jump to step 11; Step 9: The data error correction component sends an uncorrectable error interrupt to the processor, and performs error handling according to a preset error handling strategy; Step 10: Jump to step 5 to determine whether the memory refresh program has been completed. Step 11: The data error correction component records the error scene, that is, stores the error occurrence address, the read source data and the check code into the corresponding register, waiting for reading and judgment in the system error handling strategy; Step 12: Determine whether the correctable error in step 11 needs to be corrected autonomously. If the system is set to require autonomous correction, write the corrected data provided by the data error correction component back to the memory to complete the error correction autonomously. Otherwise, jump directly to step 13; Step 13: The data error correction component sends a correctable error interrupt to the processor, and performs error handling according to a preset error handling strategy; Step 14: Jump to step 5 to determine whether the memory refresh program has been completed.

2. The memory idle time refresh method for resisting single event upset effect accumulation according to claim 1, characterized in that: The memory access is organized in the form of data and check code.

3. The memory refresh method for resisting single event upset effect accumulation according to claim 1, characterized in that: The memory refresh program is a cyclic address accumulation read access memory, and the starting address is specified by the processor or stored when the last memory refresh task is completed.

4. The method for refreshing a memory device during idle time to resist accumulation of single event upset effects according to claim 3, wherein: The access word length for accessing the memory is specified by the processor or fixed in the program.

5. A memory refresh system that is resistant to single event upset effect accumulation during idle time, characterized in that: It includes a memory, a processor, a programmable memory autonomous access component, and a data error correction component connected through a data interconnection bus; When the processor accesses the memory sparsely or is idle, it sends a memory refresh start instruction to the programmable memory autonomous access component; After receiving the memory refresh start instruction, the programmable memory autonomous access component loads the memory refresh program from the specified address configured by the processor, starts executing the program, and reads the data in the current refresh address memory; The data error correction component is located at the memory control interface and is used to verify the read memory data to determine whether the read data is correct, that is, to detect whether a single event upset has occurred in the memory; if the read data is determined to be correct, it is determined whether the memory refresh program has been completed, and if it is determined to be completed, the current round of memory refresh process ends; If it is determined that the memory refresh program has not been completed, the current refresh address is accumulated, and the programmable memory autonomous access component re-reads the data in the refresh address memory; if it is determined that the read data is wrong, that is, a single event upset occurs in the memory, it is determined whether the type of data error is a correctable error; If the data error type is determined to be an uncorrectable error, the data error correction component will record the error scene, that is, store the error address, the read source data and the check code in the corresponding register for the processor to read and judge; Send an uncorrectable error interrupt to the processor, perform error handling according to the preset error handling strategy, and re-determine whether the memory refresh program has been executed; If the data error type is determined to be a correctable error, the error scene will be recorded, that is, the error address, the read source data and the check code will be stored in the corresponding register, waiting for the system error handling strategy to read and judge; determine whether the correctable error needs to be corrected autonomously. If the system is set to require autonomous correction, the corrected data will be generated and written back to the memory to complete the error correction autonomously; If the correctable error does not require autonomous correction, a correctable error interrupt is sent to the processor, and the error is handled according to the preset error handling strategy; Then re-judge whether the memory refresh program has been completed.

6. The memory idle time refresh system resistant to single event upset effect accumulation according to claim 5, characterized in that: The memory access is organized in the form of data and check code.

7. The memory idle time refresh system resistant to single event upset effect accumulation according to claim 5, characterized in that: The memory refresh program is a cyclic address accumulation read access memory, and the starting address is specified by the processor or stored when the last memory refresh task is completed.

8. The memory idle time refresh system resistant to single event upset effect accumulation according to claim 7, characterized in that: The access word length for accessing the memory is specified by the processor or fixed in the program.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

10. A memory idle refresh device resistant to single event upset effect accumulation, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

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