Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate comprising a plurality of active regions and a first isolation layer arranged along a first direction; a plurality of groups of recess structures in the substrate, the plurality of recess structures arranged along a third direction and penetrating the plurality of active regions along the first direction, the third direction being perpendicular to the second direction, the recess structure comprising: a first recess, a second recess and a third recess arranged in parallel, the third direction being at an acute angle with the first direction; a dummy gate structure in the first recess; a first word line gate structure in the second recess; a second word line gate structure in the third recess; a second isolation layer between the first word line gate structure and the second word line gate structure, the second isolation layer penetrating the plurality of active regions along the first direction; a plurality of capacitor structures on a first surface of the substrate; and a plurality of bit lines arranged along the first direction and parallel to the third direction on a second surface of the substrate. The forming process of the semiconductor structure is simplified.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] A basic memory cell in Dynamic Random Access Memory (DRAM) consists of a storage transistor and a storage capacitor, while a memory array consists of multiple storage cells. The storage capacitor stores the charge representing the stored information, and the storage transistor acts as a switch controlling the inflow and outflow of charge from the storage capacitor. The storage transistor is also connected to the internal circuitry within the memory and receives control signals from the internal circuitry. Each storage transistor contains an active region, a drain region, and a gate. The gate controls the current flow between the source and drain regions and connects to the word line. The drain region forms the bit line contact region to connect to the bit line, and the source region forms the memory node contact region to connect to the storage capacitor. With the continuous development of integrated circuit manufacturing technology, there is a need to further increase the device density of memory chips to achieve greater data storage capacity.

[0004] In conclusion, existing dynamic random access memory (DRAM) still needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of memory.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate having a first surface and a second surface opposite to each other; the substrate including a plurality of active regions arranged along a first direction and a first isolation layer, the first isolation layer being located between adjacent active regions; the projection pattern of each active region on the first surface or the second surface being elongated, and the elongated shape having a long side parallel to the second direction; and a plurality of groove structures located within the substrate, the groove structures extending from the first surface to the second surface, the plurality of groove structures being arranged along a third direction, and the groove structures penetrating the plurality of active regions along the first direction, the third direction being perpendicular to the first direction; the groove structure including: a first groove, a second groove, and a third groove arranged parallel to each other along the third direction. A third recess, wherein the first, second, and third recesses are mutually independent, and the third direction forms an acute angle with the second direction; a dummy gate structure located in the first recess; a first word line gate structure located in the second recess; a second word line gate structure located in the third recess; a second isolation layer located between the first and second word line gate structures, the second isolation layer penetrating several active regions along a first direction, the first and second word line gate structures being adjacent to the second isolation layer respectively; several capacitor structures located on the first surface of the substrate, the several capacitor structures being electrically connected to the corresponding active layers; several bit lines located on the second surface of the substrate, the bit lines being parallel to the third direction and arranged along the first direction, each bit line being electrically connected to several active regions.

[0007] Optionally, it further includes: a first source / drain doped region located in the active region on the first surface of the substrate; the capacitor structure is electrically connected to the first source / drain doped region, and the projection of the capacitor structure on the first surface of the substrate at least coincides with a portion of the first source / drain doped region.

[0008] Optionally, the second isolation layer extends from the first surface of the substrate to the second surface; the depth of the second isolation layer is greater than the depth of the first word line gate structure and the second word line gate structure.

[0009] Optionally, it also includes: a bit line plug located between the active region and the bit line, the bit line plug being located on the active region between the first word line gate structure and the second word line gate structure.

[0010] Optionally, the second isolation layer extends from the second surface of the substrate to the first surface; the distance between the second isolation layer and the first surface of the substrate is less than the distance between the first word line gate structure and the second word line gate structure and the first surface of the substrate.

[0011] Optionally, the capacitor structure is located on the active regions on both sides of the dummy gate structure.

[0012] Optionally, the second surface of the substrate exposes the bottom surface of the first isolation layer.

[0013] Optionally, it also includes: a second source / drain doped region located in the active region on the second surface of the substrate, wherein the bit line is electrically connected to the second source / drain doped region.

[0014] Optionally, the thickness of the second source / drain doped region is greater than the thickness of the first isolation layer at the bottom of the first word line gate structure and the bottom of the second word line gate structure.

[0015] Optionally, the top surfaces of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are lower than the first surface of the substrate.

[0016] Optionally, the bottom surface of the first source / drain doped region is lower than the top surface of the pseudo gate structure, the first word line gate structure, and the second word line gate structure.

[0017] Optionally, the bottom planes of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are higher than the bottom plane of the first isolation layer.

[0018] Optionally, the materials of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include polysilicon.

[0019] Optionally, the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, wherein the composite structure includes a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

[0020] Optionally, the angle between the third direction and the second direction is greater than or equal to 0 degrees and less than or equal to 45 degrees.

[0021] Optionally, the spacing between adjacent first word line gate structures and second word line gate structures is smaller than the spacing between adjacent pseudo gate structures and first word line gate structures.

[0022] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a first surface and a second surface opposite to each other; the substrate including a plurality of active regions arranged along a first direction and a first isolation layer; the first isolation layer being located between adjacent active regions; the projection pattern of each active region on the first surface or the second surface being elongated, and the elongated shape having a long side, the direction of which is parallel to the second direction; forming a plurality of sets of groove structures within the substrate; the groove structures extending from the first surface to the second surface; the plurality of groove structures being arranged along a third direction; and the groove structures penetrating the plurality of active regions along the first direction, the third direction being perpendicular to the first direction; the groove structure including: a first groove, a second groove, and a third groove arranged parallel to each other along the third direction. A third groove, wherein the first, second, and third grooves are mutually independent, and the third direction forms an acute angle with the second direction; a dummy gate structure is formed in the first groove; a first word line gate structure is formed in the second groove; a second word line gate structure is formed in the third groove; a second isolation layer is formed between the first and second word line gate structures, the second isolation layer penetrating several active regions along a first direction, and the first and second word line gate structures are respectively adjacent to the second isolation layer; several capacitor structures are formed on the first surface of the substrate, and the several capacitor structures are electrically connected to the corresponding active layers; several bit lines are formed on the second surface of the substrate, the bit lines are parallel to the third direction and arranged along the first direction, and each bit line is electrically connected to several active regions.

[0023] Optionally, before forming a plurality of capacitor structures on the first surface of the substrate, the method further includes: forming a first source / drain doped region in the active region of the first surface of the substrate; the capacitor structure is electrically connected to the first source / drain doped region, and the projection of the capacitor structure on the first surface of the substrate at least coincides with a portion of the first source / drain doped region.

[0024] Optionally, the second isolation layer extends from the first surface of the substrate to the second surface; the depth of the second isolation layer is greater than the depth of the first word line gate structure and the second word line gate structure.

[0025] Optionally, the method for forming the second isolation layer includes: after forming a pseudo gate structure, a first word line gate structure, and a second word line gate structure, forming a fourth groove in the substrate, the fourth groove extending from a first surface of the substrate to a second surface of the substrate, the fourth groove penetrating a plurality of active regions along a first direction, the fourth groove exposing the sidewall surfaces of the first word line gate structure and the second word line gate structure; and forming a second isolation layer in the fourth groove.

[0026] Optionally, it further includes: forming a bit line plug located between the active region and the bit line, the bit line plug being located on the active region between the first word line gate structure and the second word line gate structure.

[0027] Optionally, the second isolation layer extends from the second surface of the substrate to the first surface; the distance between the second isolation layer and the first surface of the substrate is less than the distance between the first word line gate structure and the second word line gate structure and the first surface of the substrate.

[0028] Optionally, the method for forming the second isolation layer includes: after forming a pseudo-gate structure, a first word line gate structure, a second word line gate structure, and a capacitor structure on a first surface of a substrate, thinning the second surface of the substrate until the bottom surface of the first isolation layer is exposed; after thinning the second surface of the substrate, forming a fourth groove in the substrate, the fourth groove extending from the second surface of the substrate to the first surface of the substrate, the fourth groove penetrating a plurality of active regions along a first direction, the fourth groove exposing the sidewall surfaces of the first word line gate structure and the second word line gate structure; forming a second isolation layer in the fourth groove; and after forming the second isolation layer, forming a plurality of bit lines on the second surface of the substrate.

[0029] Optionally, the capacitor structure is located on the active regions on both sides of the dummy gate structure.

[0030] Optionally, before forming a plurality of bit lines on the second surface of the substrate, the method further includes: thinning the second surface of the substrate until the bottom surface of the first isolation layer is exposed.

[0031] Optionally, after thinning the second surface of the substrate and before forming a plurality of bit lines on the second surface of the substrate, the method further includes: forming a second source / drain doped region in the active region of the second surface of the substrate, wherein the bit lines are electrically connected to the second source / drain doped region.

[0032] Optionally, the thickness of the second source / drain doped region is greater than the thickness of the first isolation layer at the bottom of the first word line gate structure and the bottom of the second word line gate structure.

[0033] Optionally, the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are formed simultaneously; the top surfaces of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are lower than the first surface of the substrate.

[0034] Optionally, the bottom surface of the first source / drain doped region is lower than the top surface of the pseudo gate structure, the first word line gate structure, and the second word line gate structure.

[0035] Optionally, the bottom planes of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are higher than the bottom plane of the first isolation layer.

[0036] Optionally, the materials of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include polysilicon.

[0037] Optionally, the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, wherein the composite structure includes a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

[0038] Optionally, the angle between the third direction and the second direction is greater than or equal to 0 degrees and less than or equal to 45 degrees.

[0039] Optionally, the spacing between adjacent first word line gate structures and second word line gate structures is smaller than the spacing between adjacent pseudo gate structures and first word line gate structures.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] The technical solution of the present invention has two aspects. On the one hand, the bit line and the capacitor structure are formed on two sides of the substrate, which reduces the difficulty of forming the bit line and capacitor structure, thereby simplifying the process flow and improving production efficiency. On the other hand, the second isolation layer electrically isolates the first word line gate structure and the second word line gate structure, so that only one side of the first word line gate structure and the second word line gate structure are in contact with the active region, thereby generating a channel during operation. This allows the transistor to meet performance requirements, making it easy to control when it is turned on and off, thereby reducing leakage current.

[0042] Furthermore, the projection pattern of the active region onto the first or second surface is elongated, and the elongated shape has two parallel long sides, the direction of which is parallel to the second direction. The angle between the third direction and the second direction is greater than or equal to 0 degrees and less than or equal to 45 degrees. This further increases the integration density of the semiconductor structure and improves the chip's integration level.

[0043] Furthermore, the spacing between adjacent first word line gate structures and second word line gate structures is smaller than the spacing between adjacent dummy gate structures and first word line gate structures. Consequently, when forming the capacitor structure laterally, the capacitor structure is located on the active regions on both sides of the dummy gate structure, and the spacing between adjacent first word line gate structures and second word line gate structures is reduced. This allows the capacitor structure of the entire semiconductor structure to be arranged more uniformly, effectively utilizing space to form a larger capacitor and improving product performance. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the semiconductor structure in one embodiment;

[0045] Figures 2 to 19 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention;

[0046] Figures 20 to 26 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0047] As described in the background section, existing dynamic random access memories (DRAMs) still need improvement. This will now be analyzed and explained in conjunction with specific embodiments.

[0048] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment.

[0049] Please refer to Figure 1 It includes: a substrate 100; a word line gate structure 101 located within the substrate 100; a source doped region 103 and a drain doped region 102 located within the substrate 100 on both sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 via a source plug 104; and a capacitor structure 107 electrically connected to the drain doped region 102 via a capacitor plug 106.

[0050] The semiconductor structure is formed as follows: first, source doped region 103 and drain doped region 102 are formed; then, word line gate structure 101 is formed in substrate 100; next, source plug 104 and bit line structure 105 are formed; then, capacitor plug 106 is formed; and finally, capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, with source doped region 103 and drain doped region 102 located on the horizontal sides of word line gate structure 101. Bit line structure 105 and capacitor structure 107 are on the same side of the transistor and are both located above the substrate in terms of processing technology. The capacitor plug 106 of capacitor structure 107 needs to pass through bit line structure 105, which increases the overall process complexity and places extremely high demands on photolithography and alignment, hindering the development of chip integration.

[0051] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method. On one hand, the bit lines and capacitor structures are formed on opposite sides of the substrate, reducing the difficulty of their formation and simplifying the process flow, thereby improving production efficiency. On the other hand, the second isolation layer electrically isolates the first word line gate structure and the second word line gate structure, ensuring that only one side of each structure contacts the active region, thus creating a channel during operation. This allows the transistor to meet performance requirements, making its on / off state easy to control and reducing leakage current.

[0052] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figures 2 to 19This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0054] Please refer to Figures 2 to 4 , Figure 2 for Figure 3 and Figure 4 Top view, Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along section line AA1. Figure 4 for Figure 2 A cross-sectional structural schematic diagram along the section line BB1 ​​shows a substrate 200. The substrate 200 has a first surface S1 and a second surface S2. The substrate 200 includes a plurality of active regions 201 arranged along a first direction X and a first isolation layer 202. The first isolation layer 202 is located between adjacent active regions 201. The projection pattern of each active region 201 on the first surface S1 or the second surface S2 is a strip shape, and the strip shape has two parallel long sides, the direction of which is parallel to the second direction Y.

[0055] The elongated shape has two parallel long sides, and the elongated shape includes a parallelogram or the two short sides of the elongated shape are arcs.

[0056] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate 200 may be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0057] Please refer to Figure 5 and Figure 6 , Figure 5 In order to be in Figure 3 A structural diagram based on the basic structure. Figure 6 In order to be in Figure 4 The structural diagram shows that several sets of groove structures are formed within the substrate 200. The groove structures extend from the first surface S1 to the second surface S2. The groove structures are arranged along a third direction Z, and the groove structures penetrate several active regions 201 along a first direction X. The third direction Z is perpendicular to the first direction X. The groove structure includes a first groove 203, a second groove 204, and a third groove 205 arranged parallel to each other along the third direction Z. The first groove 203, the second groove 204, and the third groove 205 are independent of each other. The third direction Z forms an acute angle α with the second direction Y.

[0058] In this embodiment, the angle α between the third direction Z and the second direction Y is greater than or equal to 0 degrees and less than or equal to 45 degrees. This further increases the integration density of the semiconductor structure and improves the chip's integration level.

[0059] The process for forming the groove structure includes one or a combination of dry etching and wet etching. In this embodiment, the groove structure is formed using dry etching. Dry etching is advantageous for forming a better groove morphology.

[0060] Please refer to Figures 7 to 9 , Figure 7 for Figure 8 and Figure 9 Top view, Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure along section line AA1. Figure 9 for Figure 7 A cross-sectional view along the BB1 ​​direction shows that a pseudo-gate structure 206 is formed in the first groove 203; a first word line gate structure 207 is formed in the second groove 204; and a second word line gate structure 208 is formed in the third groove 205.

[0061] In this embodiment, the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are formed simultaneously.

[0062] The first word line gate structure 207 and the second word line gate structure 208 are subsequently used to apply a positive operating voltage to enable the transistor to conduct; the pseudo gate structure 206 is subsequently used to apply a negative voltage to provide electrical isolation.

[0063] In this embodiment, the method further includes: forming a gate dielectric layer (not shown) on the sidewall surface and bottom surface of the first groove 203; forming a gate dielectric layer (not shown) on the sidewall surface and bottom surface of the second groove 204; and forming a gate dielectric layer (not shown) on the sidewall surface and bottom surface of the third groove 205.

[0064] The method for forming the pseudo-gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 includes: forming a gate dielectric material layer (not shown) on the sidewall surface and bottom surface of the first groove 203, the second groove 204, and the third groove 205, and on the first surface S1 of the substrate 200; forming a gate material layer (not shown) on the gate dielectric material layer; planarizing the gate material layer and the gate dielectric material layer until the first surface S1 of the substrate 200 is exposed, and forming an initial word line gate structure in the first groove 203, the second groove 204, and the third groove 205; etching back the initial word line gate structure until a portion of the sidewall of the first groove 203, the second groove 204, and the third groove 205 is exposed, forming a gate dielectric layer, and forming a pseudo-gate structure 206 in the first groove 203, forming a first word line gate structure 207 in the second groove 204, and forming a second word line gate structure 208 in the third groove 205.

[0065] In this embodiment, the top surfaces of the dummy gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are lower than the surface of the first surface S1 of the substrate 200. This provides physical space for the subsequent formation of the first source / drain doped region on the first surface S1 of the active region 201.

[0066] In this embodiment, the bottom planes of the dummy gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are higher than the bottom plane of the first isolation layer 202. This provides physical space for the subsequent formation of a second source / drain doped region within the active region on the second surface of the substrate.

[0067] In this embodiment, the materials of the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 include polysilicon; the material of the gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material.

[0068] In another embodiment, the material of the gate dielectric layer includes a high dielectric constant material with a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the materials of the pseudo gate structure, the first word line gate structure, and the second word line gate structure include metals, and the metals include tungsten.

[0069] In another embodiment, the initial word line gate structure further includes an initial work function layer located between the initial gate dielectric layer and the initial gate layer. The initial work function layer is made of an N-type work function material or a P-type work function material; the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0070] In other embodiments, the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, the composite structure including a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

[0071] In this embodiment, the spacing between adjacent first word line gate structures 207 and second word line gate structures 208 is smaller than the spacing between adjacent dummy gate structures 206 and first word line gate structures 207. Consequently, when forming the capacitor structure laterally, the capacitor structure is located on the active regions 201 on both sides of the dummy gate structure 206, and the spacing between adjacent first word line gate structures 207 and second word line gate structures 208 is reduced. This allows the capacitor structure of the entire semiconductor structure to be arranged more uniformly, effectively utilizing space to form a larger capacitor and improving product performance.

[0072] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 Top view, Figure 11 for Figure 10 A cross-sectional view along the BB1 ​​direction shows that a second isolation layer 209 is formed between the first word line gate structure 207 and the second word line gate structure 208. The second isolation layer 209 penetrates several active regions 201 along the first direction X. The first word line gate structure 207 and the second word line gate structure 208 are respectively adjacent to the second isolation layer 209.

[0073] In this embodiment, the second isolation layer 209 extends from the first surface S1 to the second surface S2 of the substrate 200. The depth of the second isolation layer 209 is greater than the depth of the first word line gate structure 207 and the second word line gate structure 208. This is so that the second isolation layer 209 completely isolates the first word line gate structure 207 and the second word line gate structure 208, ensuring that only one side of each of the first word line gate structure 207 and the second word line gate structure 208 contacts the active region 201. This creates a channel during operation, allowing the transistor to meet performance requirements, making turn-on and turn-off easy to control, thereby reducing leakage current.

[0074] The method of forming the second isolation layer 209 includes: forming a fourth groove (not shown) in a substrate 200, the fourth groove extending from a first surface S1 of the substrate 200 to a second surface S2 of the substrate 200, the fourth groove penetrating a plurality of active regions 201 along a first direction X, the fourth groove exposing the sidewall surfaces of the first word line gate structure 207 and the second word line gate structure 208; and forming a second isolation layer 209 in the fourth groove.

[0075] The material of the second isolation layer 209 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0076] In this embodiment, the material of the second isolation layer 209 includes silicon oxide.

[0077] Please refer to Figure 12 and Figure 13 , Figure 12 for Figure 13 Top view, Figure 13 for Figure 12 A cross-sectional view along the direction of section line BB1 ​​shows that a first source / drain doped region 210 is formed in the active region 201 of the first surface S1 of the substrate 200.

[0078] The process for forming the first source / drain doped region 210 includes ion implantation.

[0079] The first source / drain doped region 210 contains doped ions, which are of the N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0080] In this embodiment, the bottom surface of the first source / drain doped region 210 is lower than the bottom surfaces of the dummy gate structure 206, the first word line gate structure 207, and the second word line gate structure 208. This allows the first source / drain doped region 210 to contact the gate dielectric layer of the sidewall of the first word line gate structure 207, and also allows it to contact the gate dielectric layer of the sidewall of the second word line gate structure 208, thereby ensuring that the first source / drain doped region 210, the channel, and the subsequently formed second source / drain doped region are conductive.

[0081] Please continue to refer to this. Figure 12 and Figure 13 A plurality of capacitor structures 212 are formed on the first surface S1 of the substrate 200, and the capacitor structures 212 are electrically connected to the first source and drain doped region 210.

[0082] In this embodiment, the capacitor structure 212 is located on the active regions 201 on both sides of the dummy gate structure 206, and the projection of the capacitor structure 212 on the first surface of the substrate 200 coincides with at least a portion of the first source-drain doped region 210.

[0083] In this embodiment, it further includes forming a capacitor plug 211 located between the capacitor structure 212 and the first source / drain doped region 210.

[0084] The method of the capacitor plug 211 and the plurality of capacitor structures 212 includes: forming a first dielectric layer (not shown) on a first surface S1 of a substrate 200, the first dielectric layer being located on the dummy gate structure 206, the first word line gate structure 207, and the second word line gate structure 208; forming a first opening (not shown) in the first dielectric layer; forming a groove (not shown) in the first opening, the groove exposing a portion of the surface of the first source / drain doped region 210; forming a capacitor plug 211 in the groove; forming capacitor structures 212 in the first opening, each capacitor structure 212 being electrically connected to a first source / drain doped region 210.

[0085] The capacitor structure 212 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0086] The material of the first electrode layer includes: a metal or a metal nitride; the material of the second electrode layer includes: a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0087] The material of the capacitor plug 211 includes: metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0088] In another embodiment, the capacitor plug can be omitted, and the capacitor structure is directly electrically connected to the first source / drain doped region.

[0089] The method for forming the capacitor structure includes: forming a first dielectric layer on a first surface of a substrate, the first dielectric layer being located on a pseudo-gate structure, a first word line gate structure, and a second word line gate structure; forming a first opening in the first dielectric layer, the first opening exposing a portion of the surface of a first source / drain doped region; and forming a capacitor structure within the first opening.

[0090] Please refer to Figures 14 to 16 , Figure 14 for Figure 15 and Figure 16 Top view, Figure 15 for Figure 14 A schematic diagram of the cross-sectional structure along section line AA1. Figure 16 for Figure 14 A cross-sectional view along the direction of section line BB1 ​​shows that the second surface S2 of the substrate 200 is thinned until the bottom surface of the first isolation layer 202 is exposed.

[0091] The method for thinning the second side S2 of the substrate 200 includes: providing a substrate (not shown) whose surface is bonded to the surface of a first dielectric layer; flipping the substrate and the substrate to thin the second side S2 of the substrate 200 until the bottom surface of the first isolation layer 202 is exposed.

[0092] The thinning process for the second surface S2 of substrate 200 includes chemical mechanical polishing.

[0093] Please continue to refer to this. Figures 14 to 16 After thinning the second surface S2 of the substrate 200, a second source / drain doped region 213 is formed in the active region 201 of the second surface S2 of the substrate 200.

[0094] The thickness of the second source / drain doped region 213 is greater than the thickness of the first isolation layer 202 at the bottom of the first word line gate structure 207 and the bottom of the second word line gate structure 208, so that the second source / drain doped region 213 can contact the gate dielectric layer at the bottom of the first word line gate structure 207 and the gate dielectric layer at the bottom of the second word line gate structure 208, thereby ensuring that the first source / drain doped region 210, the channel and the second source / drain doped region 213 can be turned on.

[0095] The second source / drain doped region 213 contains doped ions, which are of the N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0096] In this embodiment, the conductivity type of the doped ions in the second source / drain doped region 213 is the same as that of the doped ions in the first source / drain doped region 210.

[0097] Please refer to Figures 17 to 19 , Figure 17 for Figure 18 and Figure 19 Top view, Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along section line AA1. Figure 19 for Figure 17 A cross-sectional view along the direction of section line BB1 ​​shows that several bit lines 215 are formed on the second surface S2 of the substrate 200. The bit lines 215 are parallel to the third direction Z and arranged along the first direction X. Each bit line 215 is electrically connected to several active regions 201.

[0098] In this embodiment, the bit line 215 is electrically connected to a column of second source / drain doped regions 213.

[0099] In this embodiment, a bit line plug 214 is also formed between the active region 201 and the bit line 215. The bit line plug 214 is located on the active region 201 between the first word line gate structure 207 and the second word line gate structure 208.

[0100] The bit line 215 is made of a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride; the bit line plug 214 is made of a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0101] In other embodiments, the bit line plug can be omitted.

[0102] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 17 to 19 ,include:

[0103] The substrate 200 has a first surface S1 and a second surface S2 facing each other. The substrate 200 includes a plurality of active regions 201 arranged along a first direction X and a first isolation layer 202. The first isolation layer 202 is located between adjacent active regions 201. The projection pattern of each active region 201 on the first surface S1 or the second surface S2 is a strip shape, and the strip shape has a long side, the direction of which is parallel to the second direction Y.

[0104] A plurality of groove structures are located within the substrate 200, the groove structures extending from the first surface S1 to the second surface S2, the plurality of groove structures being arranged along a third direction Z, and the groove structures penetrating a plurality of active regions 201 along a first direction X, the third direction Z being perpendicular to the first direction X, the groove structure including: a first groove, a second groove and a third groove arranged in parallel along the third direction Z, the first groove, the second groove and the third groove being independent of each other, the third direction Z forming an acute angle α with the second direction Y;

[0105] The dummy gate structure 206 is located in the first groove;

[0106] The first word line gate structure 207 is located in the second recess;

[0107] The second word line gate structure 208 is located within the third recess;

[0108] A second isolation layer 209 is located between the first word line gate structure 207 and the second word line gate structure 208. The second isolation layer 209 penetrates a plurality of active regions 201 along the first direction X. The first word line gate structure 207 and the second word line gate structure 208 are respectively adjacent to the second isolation layer 202.

[0109] A plurality of capacitor structures 212 are located on the first surface S1 of the substrate 200, and the plurality of capacitor structures 212 are electrically connected to the corresponding active layer 201.

[0110] A plurality of bit lines 215 are located on the second surface S2 of the substrate 200. The bit lines 215 are parallel to the third direction Z and arranged along the first direction X. Each bit line 215 is electrically connected to a plurality of active regions 201.

[0111] In the semiconductor structure, the pseudo-gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are located within the substrate 200. The bit line 215 and the capacitor structure 212 are located on opposite sides of the substrate 200, which reduces the difficulty of forming the bit line 215 and the capacitor structure 212, thereby simplifying the process flow and improving production efficiency.

[0112] In this embodiment, it further includes: a first source / drain doped region 210 located in the active region 201 of the first surface S1 of the substrate 200; the capacitor structure 212 is electrically connected to the first source / drain doped region 210, and the projection of the capacitor structure 212 on the first surface of the substrate 200 at least coincides with a portion of the first source / drain doped region 210.

[0113] In this embodiment, the second isolation layer 209 extends from the first surface S1 of the substrate 200 to the second surface S2; the depth of the second isolation layer 209 is greater than the depth of the first word line gate structure 207 and the second word line gate structure 208.

[0114] In this embodiment, it further includes a bit line plug 214 located between the active region 201 and the bit line 215, the bit line plug 214 being located on the active region 201 between the first word line gate structure 207 and the second word line gate structure 208.

[0115] In this embodiment, the capacitor structure 212 is located on the active regions 201 on both sides of the dummy gate structure 206, and the projection of the capacitor structure 212 on the first surface of the substrate 200 coincides with at least a portion of the first source-drain doped region 210.

[0116] In this embodiment, the second surface S2 of the substrate 200 exposes the bottom surface of the first isolation layer 202.

[0117] In this embodiment, it further includes a second source / drain doped region 213 located in the active region 201 of the second surface S2 of the substrate 200, and the bit line 215 is electrically connected to the second source / drain doped region 213.

[0118] In this embodiment, the thickness of the second source / drain doped region 213 is greater than the thickness of the first isolation layer 202 at the bottom of the first word line gate structure 207 and the bottom of the second word line gate structure 208.

[0119] In this embodiment, the top surfaces of the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are lower than the first surface S1 of the substrate 200.

[0120] In this embodiment, the bottom surface of the first source / drain doped region 210 is lower than the bottom surfaces of the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208.

[0121] In this embodiment, the bottom planes of the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 are higher than the bottom plane of the first isolation layer 202.

[0122] In this embodiment, the materials of the pseudo gate structure 206, the first word line gate structure 207, and the second word line gate structure 208 include polysilicon.

[0123] In other embodiments, the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, the composite structure including a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

[0124] In this embodiment, the angle between the third direction Z and the second direction Y is greater than or equal to 0 degrees and less than or equal to 45 degrees.

[0125] In this embodiment, the spacing between adjacent first word line gate structures 207 and second word line gate structures 208 is smaller than the spacing between adjacent pseudo gate structures 206 and first word line gate structures 207.

[0126] The semiconductor structure has two aspects. First, the bit lines and capacitor structures are formed on opposite sides of the substrate, which reduces the difficulty of forming the bit lines and capacitor structures, thereby simplifying the process and improving production efficiency. Second, the second isolation layer electrically isolates the first word line gate structure and the second word line gate structure, so that only one side of the first word line gate structure and the second word line gate structure is in contact with the active region, thereby generating a channel during operation. This allows the transistor to meet performance requirements, making it easy to control when it is turned on and off, thereby reducing leakage current.

[0127] Figures 20 to 26 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0128] Please refer to Figure 20 and Figure 21 , Figure 20 In order to be in Figure 7 A basic diagram. Figure 21 for Figure 20 A cross-sectional view along the BB1 ​​direction shows that after forming the pseudo-gate structure 206, the first word line gate structure 207, and the second word line gate structure 208, a first source / drain doped region 310 is formed in the active region 201 of the first surface S1 of the substrate 200; a plurality of capacitor structures 312 are formed on the first surface S1 of the substrate 200, and a capacitor plug 311 is formed between the capacitor structures 312 and the first source / drain doped region 310, wherein the capacitor structures 312 are electrically connected to the first source / drain doped region 310.

[0129] For the formation process of the first source / drain doped region 310, the capacitor plug 311, and the capacitor structure 312, please refer to [reference needed]. Figure 12 and Figure 13 This will not be elaborated upon here.

[0130] In other embodiments, the capacitor plug can be omitted.

[0131] Please refer to Figure 22 and Figure 23 , Figure 22 for Figure 23 Top view, Figure 23 for Figure 22 A cross-sectional view along the direction of section line BB1 ​​shows that the second surface S2 of the substrate 200 is thinned until the bottom surface of the first isolation layer 202 is exposed. After thinning the second surface S2 of the substrate 200, a second isolation layer 309 is formed in the substrate 200. The second isolation layer 309 extends from the second surface S2 of the substrate 200 to the first surface S1 of the substrate 200. The second isolation layer 309 penetrates several active regions 201 along the first direction X.

[0132] The method of forming the second isolation layer 309 includes: forming a fourth groove (not shown) in a substrate 200, the fourth groove extending from the second surface S2 of the substrate 200 to the first surface S1 of the substrate 200, the fourth groove penetrating a plurality of active regions 201 along a first direction X, the fourth groove exposing the sidewall surfaces of the first word line gate structure 207 and the second word line gate structure 208; and forming a second isolation layer 309 in the fourth groove.

[0133] In this embodiment, the distance between the second isolation layer 309 and the first surface S1 of the substrate 200 is smaller than the distance between the first word line gate structure 207 and the second word line gate structure 208 and the first surface S1 of the substrate 200. This ensures that the second isolation layer 309 completely isolates the first word line gate structure 207 and the second word line gate structure 208, so that only one side of each of the first word line gate structure 207 and the second word line gate structure 208 contacts the active region 201. This creates a channel during operation, allowing the transistor to meet performance requirements, making its on / off state easy to control, and thus reducing leakage current.

[0134] Please continue to refer to this. Figure 22 and Figure 23 After the second isolation layer 309 is formed, a second source / drain doped region 313 is formed in the active region 201 on the second surface S2 of the substrate 200. The formation process of the second source / drain doped region 313 is described in [reference needed]. Figures 14 to 16 This will not be elaborated upon here.

[0135] Please refer to Figures 24 to 26 , Figure 24 for Figure 25 and Figure 26 Top view, Figure 25 for Figure 24 A schematic diagram of the cross-sectional structure along the section line CC1. Figure 26 for Figure 24 A cross-sectional view along the BB1 ​​direction shows that several bit lines 315 and bit line plugs 314 located between the bit lines 315 and the second source / drain doped region 313 are formed on the second surface S2 of the substrate 200.

[0136] Please refer to the process of forming the bit line 315 and bit line plug 314. Figures 17 to 19 This will not be elaborated upon here.

[0137] In other embodiments, the bit line plug can be omitted.

[0138] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 24 to 26 , Figures 24 to 26 semiconductor structure and Figures 17 to 19The difference in the semiconductor structure is that the second isolation layer 309 extends from the second surface S2 of the substrate 200 to the first surface S1 of the substrate 200; the distance between the second isolation layer 309 and the first surface S1 of the substrate 200 is smaller than the distance between the first word line gate structure 207 and the second word line gate structure 208 and the first surface S1 of the substrate 200.

[0139] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate has a first surface and a second surface opposite to each other. The substrate includes a plurality of active regions arranged along a first direction and a first isolation layer. The first isolation layer is located between adjacent active regions. The projection pattern of each active region on the first surface or the second surface is a strip shape, and the strip shape has two parallel long sides, the direction of which is parallel to the second direction. The substrate contains several sets of groove structures, each groove structure extending from a first surface to a second surface. The groove structures are arranged along a third direction and penetrate several active regions along a first direction. The third direction is perpendicular to the first direction. Each groove structure includes a first groove, a second groove, and a third groove arranged in parallel along the third direction. The first groove, the second groove, and the third groove are independent of each other. The third direction forms an acute angle with the second direction. The pseudo-gate structure is located within the first groove; The first word line gate structure located within the second recess; The second word line gate structure located in the third groove has a spacing between adjacent first word line gate structures and the second word line gate structure that is smaller than the spacing between adjacent pseudo gate structures and the first word line gate structure. A second isolation layer is located between the first word line gate structure and the second word line gate structure. The second isolation layer penetrates several active regions along a first direction. The first word line gate structure and the second word line gate structure are respectively adjacent to and in contact with the second isolation layer. A plurality of capacitor structures are located on the first surface of the substrate, and the plurality of capacitor structures are electrically connected to the corresponding active regions. The capacitor structures are located on the active regions on both sides of the pseudo-gate structure. A plurality of bit lines are located on the second surface of the substrate, the bit lines being parallel to a third direction and arranged along a first direction, and each bit line being electrically connected to a plurality of active regions.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first source / drain doped region is located within the active region on the first surface of the substrate; the capacitor structure is electrically connected to the first source / drain doped region, and the projection of the capacitor structure on the first surface of the substrate at least partially coincides with the first source / drain doped region.

3. The semiconductor structure as described in claim 2, characterized in that, The second isolation layer extends from the first surface of the substrate to the second surface; the depth of the second isolation layer is greater than the depth of the first word line gate structure and the second word line gate structure.

4. The semiconductor structure as described in claim 3, characterized in that, Also includes: A bit line plug is located between the active region and the bit line, the bit line plug being located on the active region between the first word line gate structure and the second word line gate structure.

5. The semiconductor structure as described in claim 2, characterized in that, The second isolation layer extends from the second surface of the substrate to the first surface; the distance between the second isolation layer and the first surface of the substrate is less than the distance between the first word line gate structure and the second word line gate structure and the first surface of the substrate.

6. The semiconductor structure as described in claim 5, characterized in that, The capacitor structure is located on the active regions on both sides of the pseudo-gate structure.

7. The semiconductor structure as described in claim 1, characterized in that, The second side of the substrate exposes the bottom surface of the first isolation layer.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: The second source / drain doped region is located in the active region on the second side of the substrate, and the bit line is electrically connected to the second source / drain doped region.

9. The semiconductor structure as described in claim 8, characterized in that, The thickness of the second source / drain doped region is greater than the thickness of the first isolation layer at the bottom of the first word line gate structure and the bottom of the second word line gate structure.

10. The semiconductor structure as described in claim 2, characterized in that, The top surfaces of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are lower than the first surface of the substrate.

11. The semiconductor structure as claimed in claim 10, characterized in that, The bottom surface of the first source / drain doped region is lower than the top surface of the pseudo gate structure, the first word line gate structure, and the second word line gate structure.

12. The semiconductor structure as claimed in claim 1, characterized in that, The bottom planes of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are higher than the bottom plane of the first isolation layer.

13. The semiconductor structure as claimed in claim 1, characterized in that, The materials of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include polycrystalline silicon.

14. The semiconductor structure as claimed in claim 1, characterized in that, The pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, wherein the composite structure includes a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

15. The semiconductor structure as claimed in claim 1, characterized in that, The angle between the third direction and the second direction is greater than or equal to 0 degrees and less than or equal to 45 degrees.

16. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first surface and a second surface opposite to each other, the substrate including a plurality of active regions arranged along a first direction and a first isolation layer, the first isolation layer being located between adjacent active regions, the projection pattern of each active region on the first surface or the second surface being an elongated shape, and the elongated shape having two parallel long sides, the direction of the long sides being parallel to the second direction; A plurality of groove structures are formed in the substrate. The groove structures extend from a first surface to a second surface. The plurality of groove structures are arranged along a third direction and penetrate a plurality of active regions along a first direction. The third direction is perpendicular to the first direction. The groove structure includes a first groove, a second groove, and a third groove arranged in parallel along the third direction. The first groove, the second groove, and the third groove are independent of each other. The third direction forms an acute angle with the second direction. A pseudo-gate structure is formed within the first groove; A first word line gate structure is formed within the second groove; A second word line gate structure is formed in the third groove, and the spacing between the adjacent first word line gate structure and the second word line gate structure is smaller than the spacing between the adjacent pseudo gate structure and the first word line gate structure. A second isolation layer is formed between the first word line gate structure and the second word line gate structure. The second isolation layer penetrates several active regions along a first direction. The first word line gate structure and the second word line gate structure are respectively adjacent to and in contact with the second isolation layer. A plurality of capacitor structures are formed on the first surface of the substrate, and the plurality of capacitor structures are electrically connected to the corresponding active regions. The capacitor structures are located on the active regions on both sides of the pseudo-gate structure. A plurality of bit lines are formed on the second surface of the substrate. The bit lines are parallel to a third direction and arranged along a first direction. Each bit line is electrically connected to a plurality of active regions.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, Before forming a plurality of capacitor structures on the first surface of the substrate, the method further includes: forming a first source / drain doped region in the active region of the first surface of the substrate; the capacitor structures are electrically connected to the first source / drain doped region, and the projection of the capacitor structures on the first surface of the substrate at least coincides with a portion of the first source / drain doped region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The second isolation layer extends from the first surface of the substrate to the second surface; the depth of the second isolation layer is greater than the depth of the first word line gate structure and the second word line gate structure.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method for forming the second isolation layer includes: after forming a pseudo gate structure, a first word line gate structure, and a second word line gate structure, forming a fourth groove in a substrate, the fourth groove extending from a first surface of the substrate to a second surface of the substrate, the fourth groove penetrating a plurality of active regions along a first direction, the fourth groove exposing the sidewall surfaces of the first word line gate structure and the second word line gate structure; and forming a second isolation layer in the fourth groove.

20. The method for forming a semiconductor structure as described in claim 18, characterized in that, Also includes: A bit line plug is formed between the active region and the bit line, the bit line plug being located on the active region between the first word line gate structure and the second word line gate structure.

21. The method for forming a semiconductor structure as described in claim 17, characterized in that, The second isolation layer extends from the second surface of the substrate to the first surface; the distance between the second isolation layer and the first surface of the substrate is less than the distance between the first word line gate structure and the second word line gate structure and the first surface of the substrate.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The method for forming the second isolation layer includes: after forming a pseudo-gate structure, a first word line gate structure, a second word line gate structure, and a capacitor structure on a first surface of a substrate, thinning the second surface of the substrate until the bottom surface of the first isolation layer is exposed; after thinning the second surface of the substrate, forming a fourth groove in the substrate, the fourth groove extending from the second surface of the substrate to the first surface of the substrate, the fourth groove penetrating a plurality of active regions along a first direction, the fourth groove exposing the sidewall surfaces of the first word line gate structure and the second word line gate structure; forming a second isolation layer in the fourth groove; and after forming the second isolation layer, forming a plurality of bit lines on the second surface of the substrate.

23. The method for forming a semiconductor structure as described in claim 17, characterized in that, The capacitor structure is located on the active regions on both sides of the pseudo-gate structure.

24. The method for forming a semiconductor structure as described in claim 16, characterized in that, Before forming a plurality of bit lines on the second surface of the substrate, the method further includes: thinning the second surface of the substrate until the bottom surface of the first isolation layer is exposed.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, After thinning the second surface of the substrate and before forming a plurality of bit lines on the second surface of the substrate, the method further includes: forming a second source / drain doped region in the active region of the second surface of the substrate, wherein the bit lines are electrically connected to the second source / drain doped region.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, The thickness of the second source / drain doped region is greater than the thickness of the first isolation layer at the bottom of the first word line gate structure and the bottom of the second word line gate structure.

27. The method for forming a semiconductor structure as described in claim 17, characterized in that, The pseudo-gate structure, the first word line gate structure, and the second word line gate structure are formed simultaneously; the top surfaces of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are lower than the first surface of the substrate.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The bottom surface of the first source / drain doped region is lower than the top surface of the pseudo gate structure, the first word line gate structure, and the second word line gate structure.

29. The method for forming a semiconductor structure as described in claim 27, characterized in that, The bottom planes of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure are higher than the bottom plane of the first isolation layer.

30. The method for forming a semiconductor structure as described in claim 27, characterized in that, The materials of the pseudo-gate structure, the first word line gate structure, and the second word line gate structure include polycrystalline silicon.

31. The method for forming a semiconductor structure as described in claim 27, characterized in that, The pseudo-gate structure, the first word line gate structure, and the second word line gate structure include a composite structure, wherein the composite structure includes a first gate layer and a second gate layer located on the first gate layer; the material of the first gate layer includes polysilicon, and the material of the second gate layer includes tungsten.

32. The method for forming a semiconductor structure as described in claim 16, characterized in that, The angle between the third direction and the second direction is greater than or equal to 0 degrees and less than or equal to 45 degrees.

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