Display panel

Abstract

This invention provides a display panel comprising a plurality of sub-pixels and a plurality of thin-film transistors (TFTs) corresponding to the sub-pixels. Each sub-pixel includes at least two sub-sub-pixels, and each sub-sub-pixel is electrically connected to the TFT via a connection trace. At least two sub-sub-pixels of the same color are electrically connected to the same TFT via corresponding connection traces. By dividing a sub-pixel into at least two sub-sub-pixels, and allowing the same TFT to control at least two sub-sub-pixels of the same color, this invention reduces the area of ​​abnormal light emission caused by short circuits, avoids the generation of large blanking spots or bright spots, and improves the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels, as a new generation of display technology, have advantages such as low power consumption, high color gamut, high brightness, high resolution, wide viewing angle, and high response speed, and are widely favored by the market. Compared with the use of fine metal masks and vacuum evaporation to fabricate OLED devices, inkjet printing technology has attracted much attention due to its precise alignment, elimination of the need for fine metal masks, and material utilization rate of up to 95%, making it the mainstream trend for the future fabrication of large-size OLED devices.

[0003] Organic light-emitting diode (OLED) pixel arrangement typically consists of multiple pixels, each containing red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, arranged in a cyclical pattern to form a matrix. Because the organic functional layer of an OLED device is very thin, typically only 150nm–200nm, the presence of conductive particles between the cathode and anode can cause a short circuit, rendering the entire pixel a dead zone and affecting product performance and yield.

[0004] Therefore, it is necessary to provide a technical solution to solve the above problems. Summary of the Invention

[0005] This invention provides a display panel that solves the problem in existing display panels where conductive particles between the cathode and anode cause short circuits in the entire pixel, resulting in a dead pixel and affecting product performance and yield.

[0006] To solve the above problems, the technical solution provided by the present invention is as follows:

[0007] This invention provides a display panel including a plurality of sub-pixels and a plurality of thin-film transistors disposed corresponding to the plurality of sub-pixels. Each sub-pixel includes at least two sub-sub-pixels, and each sub-sub-pixel is electrically connected to the thin-film transistors through a connection trace.

[0008] In this configuration, at least two sub-pixels of the same color are electrically connected to the same thin-film transistor via corresponding connection traces.

[0009] Optionally, in some embodiments of the present invention, each sub-pixel includes an anode layer, an organic light-emitting functional layer, and a cathode layer stacked together. The anode layer includes anode blocks that correspond one-to-one with the sub-pixels, and adjacent anode blocks are insulated and separated by a spacer layer.

[0010] Optionally, in some embodiments of the present invention, different sub-subpixels located within the same sub-pixel have the same color, wherein the anode blocks corresponding to the same sub-pixel are all electrically connected to the thin-film transistor corresponding to the sub-pixel.

[0011] Optionally, in some embodiments of the present invention, in a first direction, two adjacent sub-pixels have the same color, and a portion of the anode block of one sub-pixel is electrically connected to the thin-film transistor corresponding to the sub-pixel, and the remaining portion of the anode block of the sub-pixel is electrically connected to the thin-film transistor corresponding to the adjacent sub-pixel, wherein each anode block corresponds to only one thin-film transistor, and the first direction is the arrangement direction of a row or column of sub-pixels.

[0012] Optionally, in some embodiments of the present invention, each sub-pixel includes a first anode block and a second anode block spaced apart. In a first direction, the first anode blocks and the second anode blocks of a plurality of sub-pixels are arranged alternately, and two adjacent sub-pixels form a sub-pixel group.

[0013] In the sub-pixel group, the first anode block of two sub-pixels is electrically connected to one thin-film transistor, and the second anode block of two sub-pixels is electrically connected to the other thin-film transistor;

[0014] Alternatively, in the sub-pixel group, the first anode block of one sub-pixel and the second anode block of another sub-pixel are electrically connected to the same thin-film transistor.

[0015] Optionally, in some embodiments of the present invention, each sub-pixel includes at least three anode blocks, the at least three anode blocks are arranged at intervals along a first direction, and the thin-film transistor is located between two adjacent sub-pixels, wherein the anode block closer to the thin-film transistor corresponding to the sub-pixel is electrically connected to the thin-film transistor corresponding to the adjacent sub-pixel, and the remaining anode blocks of the sub-pixel are electrically connected to the thin-film transistor corresponding to the sub-pixel.

[0016] Optionally, in some embodiments of the present invention, the connection traces are provided in a one-to-one correspondence with the anode blocks, and one end of each connection trace is electrically connected to the corresponding anode block, and the other end of each connection trace is electrically connected to the drain of the thin-film transistor.

[0017] Optionally, in some embodiments of the present invention, the display panel includes a light-emitting area corresponding to the sub-pixel and a non-light-emitting area located around the sub-pixel, the anode block is located in the light-emitting area, and the connecting trace is located in the non-light-emitting area.

[0018] Optionally, in some embodiments of the present invention, an insulating layer is provided between the anode layer and the drain of the thin-film transistor, and the connection trace includes a first connection trace and a second connection trace. The first connection trace is on the same layer as the anode layer, and the second connection trace is on the same layer as the drain. The first connection trace and the second connection trace are electrically connected through a via penetrating the insulating layer.

[0019] Optionally, in some embodiments of the present invention, the distance between two adjacent sub-pixels is greater than the distance between two adjacent sub-sub-pixels.

[0020] The beneficial effects of the present invention are as follows: The display panel provided by the present invention divides a sub-pixel into at least two sub-sub-pixels, and the same thin film transistor can control at least two sub-sub-pixels of the same color. When a part of the sub-sub-pixels of a sub-pixel is short-circuited, the line between the corresponding short-circuited sub-sub-pixel and the thin film transistor can be cut off, and the remaining sub-sub-pixels of the sub-pixel can still emit light normally. Therefore, the present invention can reduce the area of ​​the abnormal light emission area caused by short circuit, avoid the generation of large extinction points or bright spots, and improve the display effect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of the display panel provided in Embodiment 1 of the present invention;

[0023] Figure 2 This is a plan view of a display panel provided in Embodiment 2 of the present invention;

[0024] Figure 3 This is a plan view of another display panel provided in Embodiment 2 of the present invention;

[0025] Figure 4 This is a plan view of another display panel provided in Embodiment 2 of the present invention;

[0026] Figures 5A-5D This is a schematic diagram illustrating the manufacturing process of the display panel provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0028] In a typical display panel, each sub-pixel corresponds to an anode. If there are conductive particles between the cathode and anode of an OLED device, it will cause a short circuit between the cathode and anode, meaning that the sub-pixel will not emit light. When displaying an image, a blanking point or dark spot will be generated at the corresponding position, which will seriously affect the display effect.

[0029] Please see Figures 1-4 This invention provides a display panel comprising a plurality of sub-pixels P and a plurality of thin-film transistors 202 corresponding to the plurality of sub-pixels P. Each sub-pixel P includes at least two sub-sub-pixels, and each sub-sub-pixel is electrically connected to the thin-film transistor 202 via a connection trace 80. Specifically, at least two sub-sub-pixels of the same color are electrically connected to the same thin-film transistor 202 via corresponding connection traces 80.

[0030] This application divides a sub-pixel P into at least two sub-sub-pixels, and each of the at least two sub-sub-pixels can be electrically connected to the thin-film transistor 202 via their respective corresponding connection lines 80. In this way, when a short circuit occurs between the cathode and anode of some sub-sub-pixels of a sub-pixel P, the connection line 80 between the short-circuited sub-sub-pixel and the thin-film transistor 202 can be cut off, and the remaining sub-sub-pixels of the sub-pixel P can still emit light normally. Therefore, this invention can reduce the area of ​​the abnormal light emission region caused by the short circuit between the cathode and anode of the sub-pixel, avoid the generation of large extinction points or bright spots, and improve the display effect.

[0031] The display panel of the present invention will be described in detail below with reference to specific embodiments, and the details are as follows.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the display panel provided in Embodiment 1 of the present invention. It should be noted that... Figure 1The diagram only illustrates the structure of one sub-pixel and its corresponding thin-film transistor. The structures of the other sub-pixels and their corresponding thin-film transistors in the display panel of this invention are similar. Figure 1 The structure is consistent with that in the figure, and the sub-pixel can be one of red sub-pixels, green sub-pixels, and blue sub-pixels. Specifically, the display panel includes a substrate 10 and a thin film transistor layer 20, a pixel definition layer 30, an anode layer 40, an organic light-emitting functional layer 50, and a cathode layer 60 stacked on the substrate 10. The thin film transistor layer 20 includes an insulating layer 201 and thin film transistors 202 located in the insulating layer 201. The thin film transistor 202 includes an active layer, a gate, a source, and a drain. It should be noted that the figure is only a simple illustration and does not represent the specific structure of the thin film transistor 202.

[0033] In this embodiment, a sub-pixel includes three sub-sub-pixels, namely a first sub-sub-pixel P11, a second sub-sub-pixel P12, and a third sub-sub-pixel P13, which are spaced apart.

[0034] Each sub-pixel includes a stacked anode layer 40, an organic light-emitting functional layer 50, and a cathode layer 60. The anode layer 40 includes anode blocks 401 corresponding to each sub-pixel, and adjacent anode blocks 401 are insulated and separated by spacers 70. The organic light-emitting functional layer 50 is disposed on the side of the organic light-emitting functional layer 50 facing away from the substrate 10, corresponding to each sub-pixel. The cathode layer 60 is disposed entirely on the side of the organic light-emitting functional layer 50 facing away from the substrate 10.

[0035] In one embodiment, the spacer layer 70 is made of the same material as the pixel definition layer 30, and the spacer layer 70 is formed simultaneously during the patterning process of the pixel definition layer 30.

[0036] In this embodiment, different sub-subpixels located within the same sub-pixel have the same color; that is, the first sub-subpixel P11, the second sub-subpixel P12, and the third sub-subpixel P13 have the same color. In this embodiment, multiple anode blocks 401 corresponding to the same sub-pixel are electrically connected to the thin-film transistor 202 corresponding to the sub-pixel. Specifically, the display panel further includes connection traces 80, each corresponding to one of the anode blocks 401. One end of each connection trace 80 is electrically connected to the corresponding anode block 401, and the other end of each connection trace 80 is electrically connected to the drain of the thin-film transistor 202 through a via penetrating the insulating layer 201.

[0037] In this embodiment, the anode of a sub-pixel is patterned to form at least two spaced anode blocks 401. These at least two anode blocks 401 are electrically connected to the same thin-film transistor 202 via their respective connection traces 80. The thin-film transistor 202 can simultaneously control the light emission of all sub-sub-pixels of the sub-pixel. When a short circuit occurs between the cathode layer 60 and the anode block 401 of one or more sub-sub-pixels in the sub-pixel, the connection trace 80 between the short-circuited sub-sub-pixel and the thin-film transistor 202 can be severed. The remaining un-short-circuited sub-sub-pixels of the sub-pixel can still emit light normally. Therefore, the area of ​​the abnormal light emission region caused by the short circuit can be reduced, avoiding large disappearance or bright spots and improving the display effect.

[0038] In one embodiment, since different sub-subpixels located within the same sub-pixel have the same color, the spacer layer 70 can be made of transparent material, that is, the position corresponding to the spacer layer 70 is a light-transmitting area, thereby improving the aperture ratio of the display panel.

[0039] In one embodiment, the spacer layer 70 is a reflective material, or the surface of the spacer layer 70 is provided with a reflective coating, which can reflect the light emitted by the organic light-emitting functional layer 50 toward the spacer layer 70 and then emit it out of the display panel, thereby improving the light efficiency of the display panel.

[0040] Please see Figures 2-4 , Figures 2-4 This is a planar schematic diagram of three different display panels provided in Embodiment 2 of the present invention. The display panel includes multiple sub-pixels P and multiple thin-film transistors 202 corresponding to the multiple sub-pixels P. Each sub-pixel P includes at least two sub-sub-pixels (P11, P12), and each sub-sub-pixel is electrically connected to the thin-film transistor 202 via a connecting trace 80. The display panel of this embodiment has a similar structure to the display panel of Embodiment 1 above, except that: in the first direction, adjacent sub-pixels P have the same color, and a portion of the anode block 401 of one sub-pixel P (P1) is electrically connected to the thin-film transistor 202 (202a) corresponding to the sub-pixel P (P1), and the remaining portion of the anode block 401 of the sub-pixel P (P1) is electrically connected to the thin-film transistor 202 (202b) corresponding to the adjacent sub-pixel P (P2). Each anode block 401 is electrically connected to only one thin-film transistor 202, and the first direction is the arrangement direction of a row or column of sub-pixels P.

[0041] The display panel includes a light-emitting area corresponding to the sub-pixels (P11, P12) and a non-light-emitting area located around the sub-pixels (P11, P12). The anode block 401 is located in the light-emitting area, and the connecting trace 80 is located in the non-light-emitting area.

[0042] In one embodiment, the connection trace 80 includes a first connection trace 801 and a second connection trace 802. The first connection trace 801 is on the same layer as the anode layer (i.e., anode block 401), and the second connection trace 802 is on the same layer as the drain of the thin film transistor 202. The first connection trace 801 and the second connection trace 802 are electrically connected through a via penetrating the insulating layer.

[0043] Specifically, such as Figure 2 As shown, each sub-pixel P includes a first anode block 401a and a second anode block 401b spaced apart. In a first direction, the first anode blocks 401a and second anode blocks 401b of a plurality of sub-pixels P are arranged alternately, and two adjacent sub-pixels P form a sub-pixel group P'. In each sub-pixel group P', the first anode blocks 401a of two sub-pixels P are electrically connected to one thin-film transistor 202a, and the second anode blocks 401b of two sub-pixels P are electrically connected to another thin-film transistor 202b.

[0044] The spacing between two adjacent sub-pixels P is greater than the spacing between two adjacent sub-sub-pixels (P11, P12). In other words, the space between two adjacent sub-pixels P is larger, so the thin film transistor 202 can be positioned between two adjacent sub-pixels P.

[0045] In this embodiment, instead of connecting two adjacent first anode blocks 401a and second anode blocks 401b within the same sub-pixel P to the same thin-film transistor 202, the first anode blocks 401a of two adjacent sub-pixels P are electrically connected to one thin-film transistor 202a, and the second anode blocks 401b of the two sub-pixels P are electrically connected to another thin-film transistor 202b. This increases the length of the connection trace 80, providing more space for laser cutting to sever the connection trace 80 corresponding to the short-circuited sub-pixel when a sub-pixel is short-circuited, thus reducing the difficulty of repair.

[0046] In addition, since the sub-pixels P in the same row of this embodiment have the same color, and all the sub-pixels P in the same row are scanned simultaneously during the row-by-row scanning process of the gate driver, the sharing of the same thin-film transistor 202 by the sub-sub-pixels of two adjacent sub-pixels P will not affect the normal display of the display panel.

[0047] like Figure 3 As shown, Figure 3 The provided display panel and Figure 2 The provided display panels have similar structures, with the only difference being: Figure 3 In the provided display panel, in each of the sub-pixel groups P', the first anode block 401a of one sub-pixel P and the second anode block 401b of another sub-pixel P are electrically connected to the same thin-film transistor 202. Specifically, the first anode block 401a of sub-pixel P1 and the second anode block 401b of the adjacent sub-pixel P2 are electrically connected to the thin-film transistor 202b, and the second anode block 401b of sub-pixel P1 and the first anode block 401a of the adjacent sub-pixel P2 are electrically connected to the thin-film transistor 202a.

[0048] In this embodiment, the large space between two adjacent sub-pixels P is utilized, and two far apart anode blocks 401 share a thin film transistor 202, reducing the difficulty of repairing the connection traces 80 by laser cutting.

[0049] like Figure 4 As shown, Figure 4 The provided display panel and Figure 2 The provided display panels have similar structures, with the only difference being: Figure 4 Each sub-pixel P of the provided display panel includes at least three anode blocks 401, which are spaced apart along a first direction. The thin-film transistors 202 are located between two adjacent sub-pixels P. The anode block 401 closest to the thin-film transistor 202 corresponding to the sub-pixel P is electrically connected to the thin-film transistor 202 corresponding to the adjacent sub-pixel P. The remaining anode blocks 401 of the sub-pixel P are electrically connected to the thin-film transistor 202 corresponding to the sub-pixel P.

[0050] Specifically, sub-pixels P1 and P2 are two adjacent sub-pixels in a first direction. Each sub-pixel P includes a first anode block 401a, a second anode block 401b, and a third anode block 401c, which are spaced apart in the first direction. Specifically, the first anode block 401a and the third anode block 401c of sub-pixel P1 are electrically connected to the thin-film transistor 202a corresponding to sub-pixel P1 via the connection trace 80, and the second anode block 401b of sub-pixel P1 is electrically connected to the thin-film transistor 202b corresponding to sub-pixel P2 via the connection trace 80; similarly, the first anode block 401a and the third anode block 401c of sub-pixel P2 are electrically connected to the thin-film transistor 202b corresponding to sub-pixel P2 via the connection trace 80, and the second anode block 401b of sub-pixel P2 is electrically connected to the thin-film transistor 202a corresponding to sub-pixel P1 via the connection trace 80.

[0051] In this embodiment, the anode block 401 of a sub-pixel P near its corresponding thin-film transistor 202 is electrically connected to the thin-film transistor 202 corresponding to the adjacent sub-pixel P. This can solve the problem that the repair is difficult due to the small space between the thin-film transistor 202 and the anode block 401 near the thin-film transistor 202.

[0052] In the above embodiments, the total number of anode blocks is equal to N times the number of thin-film transistors, where N is a positive integer greater than or equal to 2. The more anode blocks there are, the greater the loss in aperture ratio of the sub-pixel. Preferably, the total number of anode blocks is equal to 2 or 3 times the number of thin-film transistors.

[0053] Furthermore, the area of ​​the anode block corresponding to the red and green sub-pixels is 70*34um or 47*34um, and the area of ​​the anode block corresponding to the blue sub-pixel is 70*80um or 47*80um. The specific area can be set according to the actual area of ​​the different color sub-pixels.

[0054] Please see Figures 5A-5D The display panel provided by the present invention can be obtained by the following method:

[0055] Step 1: Provide a substrate 10, and fabricate a thin film transistor layer 20 on the substrate 10.

[0056] The thin-film transistor layer 20 includes an insulating layer 201 and a thin-film transistor 202 located in the insulating layer 201. The thin-film transistor 202 can be a low-temperature polycrystalline silicon thin-film transistor or a metal oxide thin-film transistor. The insulating layer 201 can include multiple inorganic film layers.

[0057] Furthermore, during the fabrication of the thin-film transistor layer 20, a second connection trace (such as...) is also formed on the same layer as the drain of the thin-film transistor 202 and electrically connected. Figure 2 (as shown in 802).

[0058] Step 2: Fabricate an anode layer 40 on the thin-film transistor layer 20.

[0059] The anode layer 40 includes a plurality of anode blocks 401 arranged at intervals.

[0060] Furthermore, during the fabrication of the anode block 401, a first connection trace (such as...) can also be formed on the same layer as the anode block 401 and electrically connected. Figure 2 (As shown in 801). The first connection trace and the second connection trace are electrically connected through vias to form a connection trace for connecting the anode block 401 and the thin-film transistor 202. The specific connection relationship between the anode block 401 and the thin-film transistor 202 can be referred to the above description. Figures 1-4 The description will not be repeated here.

[0061] Step 3: Fabricate a pixel definition layer 30 and a spacing layer 70 on the anode layer 40.

[0062] The pixel definition layer 30 is patterned to form a plurality of sub-pixel openings 301 corresponding to sub-pixels, with one sub-pixel opening 301 corresponding to one sub-pixel. Each sub-pixel opening 301 is provided with at least two anode blocks 401, and the spacer layer 70 is formed between two adjacent anode blocks 401 to insulate the two adjacent anode blocks 401 and to divide the sub-pixel into at least two sub-sub-pixels.

[0063] The spacer layer 70 may be made of the same material as the pixel definition layer 30, and the spacer layer 70 may be formed simultaneously during the patterning process of the pixel definition layer 30.

[0064] In the direction parallel to the display panel, the length of the pixel definition layer 30 is greater than the length of the anode block 401. In the direction perpendicular to the display panel, the pixel definition layer 30 and the anode block 401 do not coincide.

[0065] Step 4: An organic light-emitting functional layer 50 is formed on the anode layer 40 and the spacer layer 70.

[0066] The organic light-emitting functional layer 50 includes a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. Each sub-pixel opening 301 corresponds to one color of the organic light-emitting functional layer 50.

[0067] Step 5: Fabricate a cathode layer 60 on the organic light-emitting functional layer 50.

[0068] The cathode layer 60 can be fabricated entirely on the organic light-emitting functional layer 50. The above steps complete the fabrication of the display panel of this invention. Of course, after the cathode layer 60 is fabricated, other conventional film layers can also be fabricated, such as thin-film encapsulation layers, which will not be elaborated here.

[0069] In summary, the display panel provided by the present invention, by dividing a sub-pixel into at least two sub-sub-pixels, and with the same thin-film transistor controlling at least two sub-sub-pixels of the same color, can cut off the line between the short-circuited sub-sub-pixel and the thin-film transistor when some sub-sub-pixels of a sub-pixel are short-circuited, while the remaining sub-sub-pixels of the sub-pixel can still emit light normally. Therefore, the present invention can reduce the area of ​​abnormal light emission caused by short circuit, avoid producing large dead pixels or bright pixels, and improve the display effect.

[0070] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels and multiple thin-film transistors disposed corresponding to the multiple sub-pixels. Each sub-pixel includes at least two sub-sub-pixels, and each sub-sub-pixel is electrically connected to the thin-film transistors through a connection trace. In this configuration, at least two sub-pixels of the same color are electrically connected to the same thin-film transistor via corresponding connection traces. Each sub-pixel includes a stacked anode layer, an organic light-emitting functional layer, and a cathode layer. The anode layer includes anode blocks that correspond one-to-one with the sub-pixels, and adjacent anode blocks are insulated and separated by a spacer layer. In a first direction, two adjacent sub-pixels have the same color, and a portion of the anode block of a sub-pixel is electrically connected to the thin-film transistor corresponding to the sub-pixel, while the remaining portion of the anode block of the sub-pixel is electrically connected to the thin-film transistor corresponding to the adjacent sub-pixel. Each anode block is electrically connected to only one thin-film transistor, and the first direction is the arrangement direction of a row or column of sub-pixels. Different sub-pixels located within the same sub-pixel have the same color; The distance between two adjacent sub-pixels is greater than the distance between two adjacent sub-sub-pixels.

2. The display panel according to claim 1, characterized in that, Each of the sub-pixels includes a first anode block and a second anode block spaced apart. In a first direction, the first anode blocks and the second anode blocks of a plurality of sub-pixels are arranged alternately, and two adjacent sub-pixels form a sub-pixel group. In the sub-pixel group, the first anode block of two sub-pixels is electrically connected to one thin-film transistor, and the second anode block of two sub-pixels is electrically connected to the other thin-film transistor; Alternatively, in the sub-pixel group, the first anode block of one sub-pixel and the second anode block of another sub-pixel are electrically connected to the same thin-film transistor.

3. The display panel according to claim 1, characterized in that, Each sub-pixel includes at least three anode blocks, which are spaced apart along a first direction. The thin-film transistors are located between two adjacent sub-pixels. The anode block closest to the thin-film transistor of the sub-pixel is electrically connected to the thin-film transistor of the adjacent sub-pixel, and the remaining anode blocks of the sub-pixel are electrically connected to the thin-film transistor of the sub-pixel.

4. The display panel according to claim 1, characterized in that, The connection traces are configured one-to-one with the anode blocks, and one end of each connection trace is electrically connected to the corresponding anode block, while the other end of each connection trace is electrically connected to the drain of the thin-film transistor.

5. The display panel according to claim 4, characterized in that, The display panel includes a light-emitting area corresponding to the sub-pixel and a non-light-emitting area located around the sub-pixel. The anode block is located in the light-emitting area, and the connecting trace is located in the non-light-emitting area.

6. The display panel according to claim 4, characterized in that, An insulating layer is provided between the anode layer and the drain of the thin-film transistor. The connection trace includes a first connection trace and a second connection trace. The first connection trace is on the same layer as the anode layer, and the second connection trace is on the same layer as the drain. The first connection trace and the second connection trace are electrically connected through a via that penetrates the insulating layer.

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