Driving backplane and manufacturing method thereof, and display device

Abstract

A driving backplane and a preparation method thereof, and a display device. The driving backplane comprises a substrate (100), a first gate (1) arranged on one side of the substrate (100), an active layer (2) arranged on a side of the first gate (1) away from the substrate (100), and a second gate (3) arranged on a side of the active layer (2) away from the substrate (100), wherein the orthographic projection of the second gate (3) on the substrate (100) is located in the orthographic projection of the first gate (1) on the substrate (100), and in a direction parallel to the substrate (100), the edge of the orthographic projection of the first gate (1) on the substrate (100) extends beyond the edge of the orthographic projection of the second gate (3) on the substrate (100).

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a driving backplane and a preparation method thereof, and a display device. Background Art

[0002] Micro LED (micro light emitting diode) is a new generation of display technology, which has higher brightness, better luminous efficiency and lower power consumption than the existing OLED technology. The organic materials used in existing OLED display devices age faster than the inorganic materials used in LCD display devices, and OLED display devices will leave residual images when displaying a static image for a long time, which is the screen burn-in phenomenon of OLED display devices. Micro LED uses inorganic luminescent materials, which have higher stability and lifespan.

[0003] Micro LED is a self-luminous pixel-level technology that miniaturizes the traditional inorganic LED array. Each LED pixel with a size of several microns can be independently addressed and lit. Therefore, Micro LED has more advantages than the existing OLED technology.

[0004] Micro LED is a current-type device, and the accuracy of its light emission is particularly sensitive to the stability of current, which puts higher requirements on the existing LTPS (low-temperature polycrystalline silicon) technology. Summary of the invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] A driving backplane comprises a base substrate, a first gate arranged on one side of the base substrate, an active layer arranged on a side of the first gate away from the base substrate, and a second gate arranged on a side of the active layer away from the base substrate, wherein the orthographic projection of the second gate on the base substrate is located in the orthographic projection of the first gate on the base substrate, and in a direction parallel to the base substrate, the edge of the orthographic projection of the first gate on the base substrate extends beyond the edge of the orthographic projection of the second gate on the base substrate.

[0007] In an exemplary embodiment, the driving backplane further comprises a gate insulating layer disposed on a side of the active layer away from the base substrate, wherein a first via is disposed in the gate insulating layer for exposing at least a portion of the first gate; and / or, the driving backplane further comprises an interlayer dielectric layer disposed on a side of the second gate away from the base substrate, wherein a second via is disposed in the interlayer dielectric layer for exposing at least a portion of the first gate and a third via is disposed for exposing at least a portion of the second gate.

[0008] In an exemplary embodiment, a first via hole exposing at least a partial region of the first gate is disposed in the gate insulating layer, and the second gate is connected to the first gate through the first via hole.

[0009] In an exemplary embodiment, a distance between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to a process tolerance.

[0010] In an exemplary embodiment, a distance between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to 1.5 um.

[0011] In an exemplary embodiment, a second via exposing at least a portion of the first gate and a third via exposing at least a portion of the second gate are provided in the interlayer dielectric layer, and the driving backplane also includes a first source and drain layer provided on a side of the interlayer dielectric layer away from the substrate, and the first source and drain layer is bridged to the first gate and the second gate respectively through the second via and the third via.

[0012] In an exemplary embodiment, a first via is provided in the gate insulating layer to expose at least a portion of the first gate; a second via is provided in the interlayer dielectric layer to expose at least a portion of the first gate and a third via is provided to expose at least a portion of the second gate, and the second gate is connected to the first gate through the first via, and the driving backplane also includes a first source and drain layer provided on a side of the interlayer dielectric layer away from the base substrate, and the first source and drain layer is bridged with the first gate and the second gate through the second via and the third via, respectively.

[0013] In an exemplary embodiment, a distance between an edge of an orthographic projection of the first gate on the base substrate and an edge of an orthographic projection of the second gate on the base substrate is 0.5 um-5 um.

[0014] In an exemplary embodiment, a fourth via hole is opened in the interlayer dielectric layer to expose at least a partial area of ​​the active layer, and the driving backplane also includes a first source and drain layer arranged on a side of the interlayer dielectric layer away from the base substrate, and the first source and drain layer is connected to the active layer through the fourth via hole.

[0015] In an exemplary embodiment, the first source-drain electrode layer is made of copper, and a seed layer is disposed between the first source-drain electrode layer and the active layer.

[0016] In an exemplary embodiment, a back circuit layer is disposed on a side of the base substrate away from the first gate, and a binding electrode is disposed on a side of the base substrate away from the back circuit layer, and the binding electrode is connected to the back circuit layer.

[0017] In an exemplary embodiment, the back circuit layer includes a wire layer disposed on a side of the base substrate away from the first gate and a connection electrode disposed on a side of the wire layer away from the base substrate, and the binding electrode is connected to the connection electrode through the wire layer.

[0018] A display device comprises the aforementioned driving backplane.

[0019] A method for preparing a driving backplane, comprising:

[0020] forming a first gate on one side of the substrate;

[0021] forming an active layer on a side of the first gate away from the substrate;

[0022] forming a gate insulating layer on a side of the active layer away from the substrate;

[0023] forming a second gate on a side of the gate insulating layer away from the base substrate;

[0024] forming an interlayer dielectric layer on a side of the second gate away from the substrate;

[0025] Forming a first source-drain electrode layer on a side of the interlayer dielectric layer away from the substrate;

[0026] The orthographic projection of the second gate on the substrate is located in the orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, the edge of the orthographic projection of the first gate on the substrate extends beyond the edge of the orthographic projection of the second gate on the substrate.

[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0029] Figure 1 A top view of a driving backplane according to an exemplary embodiment of the present disclosure;

[0030] Figure 2 for Figure 1 Section view of A-A' Figure 1 ;

[0031] Figure 3 for Figure 1 Section view of A-A' Figure 2 ;

[0032] Figure 4 for Figure 1 Sectional view along line B-B';

[0033] Figure 5 FIG. 4 is a cross-sectional view of a back circuit layer in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0035] In the drawings, the size of the constituent elements, the thickness of the layer, or the area may be exaggerated for the sake of clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0036] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion among constituent elements rather than to limit the quantity.

[0037] In this document, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.

[0038] In this document, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0039] In this article, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the state where the angle is greater than 85° and less than 95°.

[0040] The term "about" as used herein refers to values ​​that are not strictly limited and allow for process and measurement errors.

[0041] A single-gate transistor has only one gate, which can be located on the side of the active layer away from the substrate or on the side of the active layer close to the substrate. A dual-gate transistor has gates on both sides of the active layer, and the channel region is sandwiched between the two gates. The inventors have found that under the condition that the channel region has the same width (W) to length (L) ratio, the saturation current of the dual-gate transistor is greater than that of the single-gate transistor. Exemplarily, the driving transistor disclosed in the present invention is a dual-gate transistor.

[0042] The driving backplane in the related art includes a first gate, a second gate and an active layer arranged between the first gate and the second gate. The preparation process of the driving backplane includes: first preparing and forming the first gate, then preparing and forming the active layer on the first gate, and finally preparing and forming the second gate on the active layer. When preparing the channel region of the active layer, first precipitate a layer of amorphous silicon film, and then crystallize the amorphous silicon film through dehydrogenation, excimer laser annealing (ELA) and other processes to form the channel region of the active layer. Since the edge of the first gate has a slope, the buffer layer located on the first gate is uneven at the edge of the first gate, so that the channel region of the active layer has a step difference at the edge of the first gate, and then during the crystallization process, the amorphous silicon film located at the edge of the first gate has a laser focal plane difference, resulting in poor crystallization quality of the amorphous silicon film, affecting the performance of the active layer.

[0043] The present disclosure provides a driving backplane, comprising a base substrate, a first gate arranged on one side of the base substrate, an active layer arranged on a side of the first gate away from the base substrate, and a second gate arranged on a side of the active layer away from the base substrate, wherein the orthographic projection of the second gate on the base substrate is located in the orthographic projection of the first gate on the base substrate, and in a direction parallel to the base substrate, the edge of the orthographic projection of the first gate on the base substrate extends out from the edge of the orthographic projection of the second gate on the base substrate.

[0044] The driving backplane of the embodiment of the present invention extends the edge of the positive projection of the first gate on the substrate beyond the edge of the positive projection of the second gate on the substrate, so as to avoid the existence of a discontinuity at the edge of the first gate in the active layer during the crystallization process, thereby ensuring the crystallization quality of the active layer.

[0045] The structure, principle and effect of the array substrate provided by the present disclosure are further explained and illustrated below in conjunction with the accompanying drawings.

[0046] Figure 1 A top view of a driving backplane according to an exemplary embodiment of the present disclosure; Figure 2 for Figure 1 Section view of A-A' Figure 1 .like Figure 1 and Figure 2 As shown, the driving backplane includes a substrate 100, a first buffer layer 4 disposed on one side of the substrate 100, a first gate 1 disposed on the first buffer layer 4 away from the substrate 100, a second buffer layer 5 disposed on the side of the first gate 1 away from the substrate 100, an active layer 2 disposed on the side of the second buffer layer 5 away from the substrate 100, and a gate insulating layer 6 disposed on the side of the active layer 2 away from the substrate 100, a second gate 3 disposed on the side of the gate insulating layer 6 away from the substrate 100, and an interlayer dielectric layer 7 disposed on the side of the second gate 3 away from the substrate 100. The orthographic projection of the second gate 3 on the substrate 100 is located in the orthographic projection of the first gate 1 on the substrate 100, and in a direction parallel to the substrate 100, the edge of the orthographic projection of the first gate 1 on the substrate 100 extends beyond the edge of the orthographic projection of the second gate 3 on the substrate 100.

[0047] The substrate 100 may be a substrate 100 of an inorganic material, or may be a substrate 100 of an organic material. In one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate 100 may be polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the base substrate 100 may also be a flexible base substrate 100, for example, the material of the base substrate 100 may be polyimide (PI). The base substrate 100 may also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the base substrate 100 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0048] The first buffer layer 4 may include an inorganic insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. For example, in one embodiment of the present disclosure, the first buffer layer 4 includes a silicon nitride layer and a silicon oxide layer sequentially stacked on the base substrate 100, wherein the thickness of the silicon nitride layer is 40 to 60 nanometers, and the thickness of the silicon oxide layer is 180 to 220 nanometers.

[0049] The materials of the first gate 1 and the second gate 3 can be selected from conductive materials, for example, metals, conductive metal oxides, conductive polymers, conductive composite materials or combinations thereof can be selected. Exemplarily, the metal can be selected from platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese or combinations thereof. Exemplarily, the conductive metal oxide can be selected from indium oxide, tin oxide, indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide or combinations thereof. Exemplarily, the conductive polymer can be selected from polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT / PSS) or combinations thereof, and dopants such as acids (such as hydrochloric acid, sulfuric acid, sulfonic acid, etc.), Lewis acids (such as phosphorus fluoride, arsenic fluoride, ferric chloride, etc.), halogens, alkali metals, etc. can also be added to the conductive polymer. Exemplarily, the conductive composite material can be selected from conductive composite materials dispersed with carbon black, graphite powder, metal microparticles, etc.

[0050] The first gate 1 and the second gate 3 may be a layer of conductive material or a stack of multiple conductive materials. For example, in one embodiment of the present disclosure, the first gate 1 and the second gate 3 may include a first conductive material layer, a second conductive material layer and a first conductive material layer stacked in sequence, that is, presenting a sandwich structure. Among them, the first conductive material layer may be made of a corrosion-resistant metal or alloy, such as molybdenum or titanium; the second conductive material layer may be made of a metal or alloy with high conductivity, such as copper, aluminum, silver, etc. For another example, in another embodiment of the present disclosure, the first gate 1 and the second gate 3 may include a layer of conductive material, for example, the material of the first gate 1 and the second gate 3 may be molybdenum. The thickness of the first gate 1 and the second gate 3 may be 30 to 300 nm.

[0051] Optionally, a gate material layer may be first formed on one side of the base substrate 100, and then the gate material layer may be patterned to form the first gate 1 or the second gate. Optionally, the first gate 1 and the second gate 3 may be formed by magnetron sputtering. In some other embodiments, the first gate 1 and the second gate 3 may also be directly formed by screen printing or other methods.

[0052] In one embodiment of the present disclosure, the second buffer layer 5 can be made of an organic or inorganic insulating material. Optionally, the material of the second buffer layer 5 can be silicon oxide, silicon nitride, silicon oxynitride or other inorganic insulating materials. For example, in one embodiment of the present disclosure, the material of the second buffer layer 5 can be silicon oxide, and the thickness can be 0.5um-5um.

[0053] Optionally, the second buffer layer 5 can be formed by physical vapor deposition, chemical vapor deposition, spin coating, screen printing or other methods, which are not limited in the present disclosure. For example, in one embodiment of the present disclosure, a layer of silicon dioxide can be deposited on the side of the first gate 1 away from the substrate 100 by plasma enhanced chemical vapor deposition (PECVD) to form the second buffer layer 5.

[0054] The active layer 2 is disposed on a side of the second buffer layer 5 away from the substrate 100 , and may include amorphous silicon semiconductor material, low temperature polysilicon semiconductor material, single crystal silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials.

[0055] Figure 4 for Figure 1 The cross-sectional view of B-B'. Figure 1 and Figure 4 As shown, the driving backplane also includes a first source-drain layer 8 disposed on the side of the interlayer dielectric layer 7 away from the substrate 100. A fourth via 703 is provided in the interlayer dielectric layer 7 to expose at least a portion of the active layer 2. The active layer 2 may include a channel region and a source contact region and a drain contact region located on both sides of the channel region. The fourth via 703 exposes the source contact region and the drain contact region, respectively. The first source-drain layer 8 includes a source 801 and a drain 802. The source 801 is electrically connected to the source contact region through the fourth via 703, and the drain 802 is electrically connected to the drain contact region through the fourth via 703. The orthographic projection of the channel region on the substrate overlaps with the orthographic projection of the first gate 1 on the substrate and the orthographic projection of the second gate 3 on the substrate 100, respectively, so that the channel region is fully controlled by the first gate 1 and the second gate 3, and the floating body effect of the driving backplane can be eliminated.

[0056] Optionally, the first source-drain electrode layer 8 may be formed by magnetron sputtering or electroplating, so that the first source-drain electrode layer 8 is connected to the source contact region and the drain contact region of the active layer.

[0057] In an exemplary embodiment, the material of the first source-drain electrode layer 8 is copper, and a seed layer is provided between the first source-drain electrode layer 8 and the active layer 2, and the seed layer prevents the copper material of the first source-drain electrode layer 8 from diffusing into the active layer 2. Specifically, a seed layer is formed on the active layer 2 by a magnetron sputtering method, and then a first source-drain electrode layer 8 made of copper is formed on the seed layer by an electroplating process. The seed layer may be metal titanium or metal molybdenum, which can form a good contact with the polysilicon material of the active layer 2 and prevent the diffusion of the copper material. The thickness of the first source-drain electrode layer 8 is 1-10um. Preferably, an anti-diffusion layer may also be provided between the seed layer and the first source-drain electrode layer, and the material of the anti-diffusion layer may be a copper alloy. The first source-drain electrode layer in the present disclosure is made of copper, which can effectively reduce the resistance and voltage drop (IR Drop) of the driving backplane.

[0058] In an exemplary embodiment, the edge of the orthographic projection of the first gate 1 on the substrate substrate 100 extends beyond the edge of the orthographic projection of the channel region on the substrate substrate 100, and the distance between the edge of the orthographic projection of the channel region on the substrate substrate 100 and the edge of the orthographic projection of the first gate 1 on the substrate substrate 100 is 0.5um-5um, thereby avoiding the formation of a step difference in the amorphous silicon layer at the edge of the first gate 1 when the amorphous silicon layer is scanned with an excimer laser, thereby affecting the crystallization quality of the channel region.

[0059] In an exemplary embodiment, the material of the active layer 2 may include low temperature polysilicon. Further, the thickness of the active layer 2 is 30-60 nanometers to avoid reducing the saturation current of the driving backplane due to the thickness being too small.

[0060] In an exemplary embodiment, an amorphous silicon layer is formed on the side of the second buffer layer 5 away from the base substrate 100 by plasma enhanced chemical vapor deposition, and then the amorphous silicon layer is scanned by an excimer laser to crystallize the amorphous silicon layer into a low-temperature polycrystalline silicon layer to form a channel region of the active layer.

[0061] like Figure 1 and Figure 2 As shown, a first via hole 601 exposing at least a portion of the first gate 1 is provided in the gate insulating layer 6, and the first via hole 601 penetrates the gate insulating layer 6 and the second buffer layer 5, and the orthographic projection of the first via hole 601 on the base substrate 100 is located on the orthographic projection of the first gate layer 1 on the base substrate 100. The second gate 3 is connected to the first gate 1 through the first via hole 601. Among them, the material and thickness of the gate insulating layer 6 may be the same as or different from those of the second buffer layer 5. In one embodiment of the present disclosure, the material of the gate insulating layer 6 is silicon oxide, and the thickness is 60 to 200 nanometers. The gate insulating layer 6 can be formed by plasma enhanced chemical vapor deposition.

[0062] In the embodiment of the present disclosure, the second gate is connected to the first gate through the first via, so that the first gate and the second gate can have the same voltage, which can effectively isolate the active layer and the substrate, avoid the formation of capacitance and charge accumulation between the active layer and the substrate, and thus weaken or eliminate the floating effect of the driving backplane. When the first gate and the second gate are loaded with a driving signal related to the data voltage, the electric field generated by the first gate and the second gate can act on the channel area of ​​the driving backplane at the same time, so that the channel area can respond to the data voltage more effectively and accurately and output the driving current. Not only that, the first gate and the second gate are electrically connected to each other, which can also avoid the formation of parasitic capacitance between the first gate and the second gate, and avoid the influence of parasitic capacitance on the driving backplane.

[0063] In an exemplary embodiment, the distance between the edge of the first via 601 close to the active layer 2 and the edge of the active layer 2 close to the first via 601 is greater than or equal to the process tolerance, so as to avoid the first via 601 breaking through the active layer 2 due to the process tolerance during the formation of the first via 601; and to avoid the electric field formed by the metal electrode connecting the first gate and the second gate in the first via 601, which affects the carrier distribution in the active layer.

[0064] In an exemplary embodiment, the distance between the edge of the first via hole 601 close to the active layer 2 and the edge of the active layer 2 close to the first via hole 601 is greater than or equal to 1.5um. In the process of punching the first via hole 601 in the gate insulating layer 6, the process tolerance of the punching is generally 0.6um. The present disclosure effectively avoids the first via hole 601 from punching through the active layer 2 due to the process tolerance by making the distance between the edge of the first via hole 601 and the edge of the active layer 2 greater than or equal to 1.5um.

[0065] Figure 3 for Figure 1 Section view of A-A' Figure 2 .like Figure 1 and Figure 3 As shown, the interlayer dielectric layer 7 in the driving backplane of the embodiment of the present disclosure is provided with a second via 701 exposing at least a portion of the first gate 1 and a third via 702 exposing at least a portion of the second gate 3. In other words, when the interlayer dielectric material layer is patterned, the second via and the third via can be formed. The second via penetrates the interlayer dielectric layer 7, the gate insulating layer 6 and the second buffer layer 5. The orthographic projection of the second via on the substrate 100 is located on the orthographic projection of the first gate 1 on the substrate 100. The third via penetrates the interlayer dielectric layer 7, and the orthographic projection of the third via on the substrate 100 is located on the orthographic projection of the second gate 3 on the substrate 100.

[0066] The first source-drain layer 8 includes a bridging electrode 803, one end of the bridging electrode 803 in the first source-drain layer 8 is connected to the first gate 1 through the second via 701, and the other end of the bridging electrode 803 in the first source-drain layer 8 is connected to the second gate 3 through the third via 702, so that the first gate 1 and the second gate 3 are bridged through the first source-drain layer 8.

[0067] In some embodiments, a first via is provided in the gate insulating layer in the driving backplane to expose at least a portion of the first gate, a second via is provided in the interlayer dielectric layer to expose at least a portion of the first gate and a third via is provided to expose at least a portion of the second gate, the second gate is connected to the first gate through the first via, and at the same time, the bridging electrode in the first source-drain layer is bridged to the first gate and the second gate through the second via and the third via, respectively.

[0068] In an exemplary embodiment, the interlayer dielectric layer 7 is disposed on a side of the second gate 3 away from the base substrate 100 to isolate the second gate 3 from the first source and drain electrode layer 8. Optionally, the material of the interlayer dielectric layer 7 may be an inorganic insulating material.

[0069] The interlayer dielectric layer 7 may include a layer of insulating material or a plurality of stacked insulating materials. For example, in one embodiment of the present disclosure, the interlayer dielectric layer 7 may include a silicon nitride layer and a silicon oxide layer stacked sequentially on the side of the second gate 3 away from the substrate 100, wherein the thickness of the silicon nitride layer is 150 to 250 nanometers, and the thickness of the silicon oxide layer is 250 to 350 nanometers.

[0070] Optionally, an interlayer dielectric material layer may be first formed on the side of the second gate 3 away from the substrate 100, and then patterned to form the interlayer dielectric layer 7. Preferably, the interlayer dielectric material layer may be formed by plasma enhanced chemical vapor deposition.

[0071] Figure 5 FIG. 2 is a cross-sectional view of the back circuit layer in an exemplary embodiment of the present disclosure. Figure 5 As shown, a back circuit layer 200 is provided on the side of the substrate 100 away from the first gate 1, and a signal lead and a binding electrode connected to the signal lead are provided on the side of the substrate 100 away from the back circuit layer 200. The binding electrode is connected to the back circuit layer 200, so that the IC / output port, etc. are transferred to the back circuit layer 200, so as to realize the preparation of a borderless display device, so that the display device can be seamlessly spliced ​​to form a large-screen display device. The size of the display device is no longer limited by the size of the preparation equipment, and can be used for custom splicing and define any size.

[0072] The back circuit layer 200 includes a wire layer 201, a passivation layer 202 and a connection electrode 203 which are sequentially arranged on the base substrate. A fifth via hole is provided in the passivation layer 202 to expose the wire layer 201. The connection electrode 203 is connected to the wire layer 201 through the fifth via hole. The wire layer 201 is connected to the binding electrode 14 to realize the input of the signal.

[0073] In one embodiment of the present disclosure, the back circuit layer 200 further includes an alignment mark layer 204 . The alignment mark layer 204 is disposed on the same layer as the wire layer 201 . The alignment mark layer 204 is made of a light-transmitting material, such as ITO, SiNx or SiOx.

[0074] A display device includes the aforementioned driving backplane. The display device of the embodiment of the present invention can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0075] A method for preparing a driving backplane, comprising:

[0076] forming a first gate on one side of the substrate;

[0077] forming an active layer on a side of the first gate away from the substrate;

[0078] forming a gate insulating layer on a side of the active layer away from the substrate;

[0079] forming a second gate on a side of the gate insulating layer away from the base substrate;

[0080] forming an interlayer dielectric layer on a side of the second gate away from the substrate;

[0081] The orthographic projection of the second gate on the substrate is located in the orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, the edge of the orthographic projection of the first gate on the substrate extends beyond the edge of the orthographic projection of the second gate on the substrate.

[0082] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A driving backplane, characterized in that: The invention comprises a substrate, a first gate arranged on one side of the substrate, an active layer arranged on a side of the first gate away from the substrate, and a second gate arranged on a side of the active layer away from the substrate, wherein the orthographic projection of the second gate on the substrate is located in the orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, the edge of the orthographic projection of the first gate on the substrate extends out of the edge of the orthographic projection of the second gate on the substrate; the driving backplane also comprises a gate insulating layer arranged on a side of the active layer away from the substrate, and a gate insulating layer is provided in the gate insulating layer to A first via hole exposing at least a portion of the first gate, a spacing between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to a process tolerance, and a spacing between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to 1.5um; and / or, the driving backplane also includes an interlayer dielectric layer arranged on a side of the second gate away from the substrate, and a second via hole exposing at least a portion of the first gate and a third via hole exposing at least a portion of the second gate are arranged in the interlayer dielectric layer.

2. The driving backplane according to claim 1, characterized in that: A first via hole exposing at least a portion of the first gate is disposed in the gate insulating layer, and the second gate is connected to the first gate through the first via hole.

3. The driving backplane according to claim 1, characterized in that: The interlayer dielectric layer is provided with a second via hole exposing at least a portion of the first gate and a third via hole exposing at least a portion of the second gate. The driving backplane also includes a first source and drain layer arranged on a side of the interlayer dielectric layer away from the substrate. The first source and drain layer is bridged with the first gate and the second gate respectively through the second via hole and the third via hole.

4. The driving backplane according to claim 1, characterized in that: The gate insulating layer is provided with a first via hole exposing at least a portion of the first gate; the interlayer dielectric layer is provided with a second via hole exposing at least a portion of the first gate and a third via hole exposing at least a portion of the second gate, the second gate is connected to the first gate through the first via hole, and the driving backplane also includes a first source and drain layer arranged on a side of the interlayer dielectric layer away from the substrate, and the first source and drain layer is bridged with the first gate and the second gate through the second via hole and the third via hole, respectively.

5. The driving backplane according to any one of claims 1 to 4, characterized in that: A distance between an edge of an orthographic projection of the first gate on the substrate and an edge of an orthographic projection of the second gate on the substrate is 0.5 um-5 um.

6. The driving backplane according to any one of claims 1 to 4, characterized in that: A fourth via hole is opened in the interlayer dielectric layer to expose at least a portion of the active layer. The driving backplane also includes a first source and drain layer arranged on a side of the interlayer dielectric layer away from the base substrate. The first source and drain layer is connected to the active layer through the fourth via hole.

7. The driving backplane according to claim 6, characterized in that: The first source-drain electrode layer is made of copper, and a seed layer is disposed between the first source-drain electrode layer and the active layer.

8. The driving backplane according to any one of claims 1 to 4, characterized in that: A back circuit layer is disposed on a side of the base substrate away from the first grid electrode, and a binding electrode is disposed on a side of the base substrate away from the back circuit layer, and the binding electrode is connected to the back circuit layer.

9. The driving backplane according to claim 8, characterized in that: The back circuit layer includes a wire layer arranged on a side of the base substrate away from the first gate and a connecting electrode arranged on a side of the wire layer away from the base substrate, and the binding electrode is connected to the connecting electrode through the wire layer.

10. A display device, characterized in that: A drive backplane comprising any one of claims 1 to 9.

11. A method for preparing a driving backplane, characterized in that: include: forming a first gate on one side of the substrate; forming an active layer on a side of the first gate away from the substrate; forming a gate insulating layer on a side of the active layer away from the base substrate; forming a second gate on a side of the gate insulating layer away from the base substrate; forming an interlayer dielectric layer on a side of the second gate away from the substrate; The orthographic projection of the second gate on the substrate is located in the orthographic projection of the first gate on the substrate, and in a direction parallel to the substrate, the edge of the orthographic projection of the first gate on the substrate extends out of the edge of the orthographic projection of the second gate on the substrate; The gate insulating layer is provided with a first via hole exposing at least a portion of the first gate, the distance between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to a process tolerance, and the distance between an edge of the first via hole close to the active layer and an edge of the active layer close to the first via hole is greater than or equal to 1.5 um; And / or, a second via hole exposing at least a portion of the first gate and a third via hole exposing at least a portion of the second gate are provided in the interlayer dielectric layer.

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