Method for programming and controlling a plurality of slaves in a daisy chain using a master

Abstract

Embodiments of the invention disclose a method for programming and controlling a plurality of slave devices in a daisy chain using a master device, comprising: sending an initialization data packet from the master device in serial fashion through the plurality of slave devices, assigning a unique slave address to each of the plurality of slave devices; storing the assigned slave address in each of the plurality of slave devices; defining a data packet; and transmitting the data packet in serial fashion to one or more of the plurality of slave devices. The data packet has a target slave address, a read / write command, a start address, and optionally a register address and an increment value.

Description

TECHNICAL FIELD

[0001] The present invention provides a method for programming and control of Serial Peripheral Interface or SPI, in particular a method for programming and control of SPI in daisy chain configuration. BACKGROUND

[0002] SPI is one of the popular serial interfaces. SPI devices communicate in full-duplex mode with a master-slave architecture, usually with only one host device. The host device ("master") initiates frames for reading and writing. Multiple slave devices ("slaves") can be supported by selecting using a single chip select (CS) line (sometimes called slave select (SS) line). Some SPI slaves have a built-in address. In standalone SPI connection (e.g. Figure 2 ), chip select (CS) is used to select one slave from all slave devices with the same built-in address. The master has a dedicated CS (e.g. CS1, CS2, CS3) and each slave has only one CS pin to receive the connection from the master. In daisy chain SPI connection (e.g. Figure 3 ), the master has only one CS pin, which is connected in parallel with all CS pins of the slaves, the first slave output is connected to the second slave input, and so on. Therefore, daisy chain SPI connection reduces the number of CS lines. For daisy chain connection, the data packet includes information for identifying the target slave, read / write operation (R / W), and data.

[0003] Generally, there are two methods available for identifying a target slave in a daisy chain SPI connection: each slave has its own address pin, or, each slave has its internal fixed address and the address is unique. Encapsulating each slave with an address pin increases the size of the encapsulation, and assigning each slave an internal fixed and unique address also increases the cost of manufacturing the slave. Therefore, the industry uses a dual field method to communicate with a serial peripheral interface that has no pre-assigned address in a daisy chain setup. That is, two fields are used to locate the target slave. One field is the "target slave address field" and the other field is the "chain field". When the two fields are passed from the master to the slaves along the chain, each slave that receives the two fields compares the values of the two fields to find a match. If the comparison is positive, the slave will hold the data. Otherwise, the slave will not hold the data, the value of the chain field is incremented by "1" while keeping the target slave address field unchanged, and the two fields are passed to the subsequent slave. Eventually, the data packet (including the two fields) reaches the slave where the values of the two fields are equal. This method is reliable, but it is cumbersome in terms of using a large data bandwidth (i.e., the two fields) to identify the slave and the extra operation (i.e., incrementing the value of the chain field) to pass along each chain. Therefore, there is a need to reduce the operation cost associated with the dual field method to communicate in a daisy chain setup of a series of unaddressed interfaces. SUMMARY

[0004] The present invention shows a method of programming and controlling a plurality of slaves in series in a daisy chain configuration using a master. The method includes assigning a unique slave address to each of the plurality of slaves by sending an initialization data packet from the master in a serial fashion through the plurality of slaves, storing the assigned slave address in each of the plurality of slaves, defining a data packet, wherein the data packet defines a target slave address, a read / write command, and a start address, and transmitting the data packet to one or more of the plurality of slaves.

[0005] According to some embodiments, the data packet also defines a register address. According to some embodiments, when the target slave address is not equal to a predefined broadcast address or the register address is not equal to a predefined location of the slave address, a normal operation is performed. According to some embodiments, during the normal operation, the plurality of slaves receives the target slave address, and when the target slave address is equal to the predefined broadcast address, a read / write operation is performed on the plurality of slaves. According to some embodiments, when the target slave address is equal to the slave address stored in a particular slave, a read / write operation is performed on the particular slave. According to some embodiments, when the target slave address is not equal to the slave address stored in a particular slave, then the data packet is transmitted to a subsequent slave connected in series in a daisy chain; and the target slave address is compared with the slave address stored in the subsequent slave. According to some embodiments, when the target slave address is equal to the predefined broadcast address and the register address is equal to a predefined location of the slave address, a slave address programming operation is performed. According to some embodiments, the data packet also defines an increment value. According to some embodiments, the increment value is an integer of 1 or greater than 1. According to some embodiments, the data packet also defines an incremented address, the value of which is equal to the start address plus the increment value. According to some embodiments, the method further comprises: updating the incremented address in the subsequent slave by adding the increment value to the incremented address. BRIEF DESCRIPTION OF DRAWINGS

[0006] The teachings of the present application can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 A parallel interface and a serial interface are shown in schematic form.

[0008] Figure 2 An SPI normal connection (e.g. parallel connection) is shown in schematic form.

[0009] Figure 3 An SPI daisy chain connection (e.g. sequential connection) is shown in schematic form.

[0010] Figure 4 An example of the composition of a data packet in an SPI daisy chain connection is shown in schematic form.

[0011] Figure 5 An example of how a target is located in a slave chain in an SPI daisy chain connection in the prior art is shown in schematic form.

[0012] Figure 6 A byte used in one way of programming all slave addresses is described.

[0013] Figure 7 An example of how a target is located in a slave chain in an SPI daisy chain connection is shown in schematic form. Figure 6The bytes described in the example above are used to assign addresses to each slave and to program all slave addresses.

[0014] Figure 8 An example of the result of programming all slave addresses is shown in the schematic diagram. Figure 7

[0015] Figure 9 Another way of programming all slave addresses is described.

[0016] Figure 10 Another example of how to program all slave addresses using the bytes described in the example above is shown in the schematic diagram. Figure 9 Another example of how to program all slave addresses using the bytes described in the example above is shown in the schematic diagram.

[0017] Figure 11 An example of the result of programming all slave addresses is shown in the schematic diagram. Figure 10

[0018] Another example of how to program all slave addresses using different starting addresses (e.g., "0x01") and custom increment values (e.g., "2") is shown in the schematic diagram. Figure 12

[0019] An example of the result of programming addresses is shown in the schematic diagram. Figure 13 Figure 12

[0020] A flowchart illustrating a read / write method in a serial peripheral interface daisy chain connection is shown. Figure 14 DETAILED DESCRIPTION Serial communication is the process of sending data one bit at a time over a communication channel or computer bus. In contrast, parallel communication is the process of sending several bits at a time over a link with several parallel channels. Serial communication reduces the number of wires between the transmitter and receiver, because all receivers are connected in series, so an additional receiver can be connected to the last receiver in the existing series of receivers.

[0021] Serial Peripheral Interface ("SPI") is a synchronous serial communication interface specification, primarily used for short distance communication, for example, in embedded systems. Typical applications of SPI include secure digital cards and liquid crystal displays.

[0022]

[0023] ​​​SPI devices use a master-slave architecture to communicate in full-duplex mode, typically executing a single master, however, some Atmel devices can support dynamic role changes according to an external (SS) pin. The master or controller generates frames for reading and writing. Multiple slaves can be supported by selecting with separate chip select ("CS") lines, which are sometimes referred to as slave select ("SS") lines.

[0024] SPI is also known as a four-wire serial bus compared to three-wire, two-wire, and one-wire serial buses. SPI can be described as a synchronous serial interface; however, it is different from the Synchronous Serial Interface ("SSI") protocol, which is also a four-wire synchronous serial communication protocol. The SSI protocol implements differential signaling and provides only a simplex communication channel. SPI implements a master-multiple slave communication for any given process. In the present invention, "slave" and "slave device" are used interchangeably, while "master" and "master device" are used interchangeably.

[0025] The SPI bus implements four logical signals: SCLK: serial clock (output from master); MOSI: master output slave input (data output from master); MISO: master input slave output (data output from slave); CS / SS: chip / slave select (usually active low, master output indicates data is being sent). MOSI on the master is connected to MOSI on the slave. MISO on the master is connected to MISO on the slave. Slave select has the same function as chip select, its implementation replaces the addressing concept. For example, on a slave-only device, MOSI can be labeled SDI (serial data input), while MISO can be labeled SDO (serial data output).

[0026] The above signal names can be used to label the master and slave pins and the signal lines between them. Pin names are always capitalized, for example, "Chip Select," not "chip select."

[0027] For example, to initiate communication, the bus master device configures the clock by using a frequency supported by the slave device, which is typically up to several MHz. Then, the master selects the slave according to the standard of a logic level of 0 on the selection line. If a wait time is required, for example, analog-to-digital conversion, the master waits at least for a period of time before issuing a clock cycle.

[0028] In each SPI clock cycle, full-duplex data transfer occurs. The master sends a bit on the MOSI line, which the slave reads, while the slave sends a bit on the MISO line, which the master reads. This order is maintained even if only one-way data transfer is anticipated.

[0029] Transfers typically involve two shift registers of a particular word length, for example eight bits, one in the master and one in the slave; they are connected in a virtual ring topology. Data is usually shifted out of the most significant bit first. At the clock edge, both master and slave shift out a bit and output it to the other over the transfer line. At the next clock edge, at each receiver, the bit is sampled from the transfer line and set as the new least significant bit of the shift register. After the register bits have been shifted out, the master and slave exchange register values. If more data is required to be exchanged, the shift registers are reloaded and the process is repeated. Transfers can continue for any number of clock cycles. When complete, the master stops toggling the clock signal and usually deselects the slave.

[0030] Transfers are usually made using eight-bit words. However, other word lengths are common, for example, 16-bit word lengths for touch-screen controllers or audio codecs, or 12-bit word lengths for many digital-to-analogue or analogue-to-digital converters. Multiple SPI devices can also be connected in a daisy chain to save the number of pins.

[0031] Each slave on the bus that is not activated using the chip select line must ignore the input clock and MOSI signals, and should not drive MISO, which means it must have a tri-state output, although some devices require an external tri-state buffer to achieve this.

[0032] Figure 1 Parallel and serial interfaces are shown in schematic form. Figure 2 An SPI normal connection configuration 2000 (parallel connection) is shown in schematic form, which is a typical SPI bus configuration or SPI normal connection, having one master 2100 and three slaves 2200, 2300 and 2400. In the configuration 2000, the SCLK of the SPI master 2100 is connected to the SCLK of the first SPI slave 2200, the SCLK of the second SPI slave 2300 and the SCLK of the third SPI slave 2400 simultaneously in parallel; the MOSI of the SPI master 2100 is connected to the MOSI of the first SPI slave 2200, the MOSI of the second SPI slave 2300 and the MOSI of the third SPI slave 2400 simultaneously in parallel; the MISO of the first SPI slave 2200, the MISO of the second SPI slave 2300 and the MISO of the third SPI slave 2400 are connected to the MISO of the SPI master 2100 simultaneously in parallel. The CS1 of the SPI master 2100 is connected to the CS of the first SPI slave 2200, the CS2 of the SPI master 2100 is connected to the CS of the second SPI slave 2300, and the CS3 of the SPI master 2100 is connected to the CS of the third SPI slave 2400.

[0033] In a standalone slave configuration, each slave has a separate chip select (CS) line, which is the usual way SPI is used. The master can only have one chip select CS active at a time.

[0034] Figure 3 An SPI daisy chain connection configuration 3000 (sequential connection) is shown in schematic form. Configuration 3000 is a daisy chain configuration with one master 3100 and three cooperating slaves 3200, 3300, and 3400. In configuration 3000, the SCLK of SPI master 3100 is connected simultaneously and in parallel to the SCLK of first SPI slave 3200, the SCLK of second SPI slave 3300, and the SCLK of third SPI slave 3400. The MOSI and MISO of the master and three slaves are connected in a daisy chain configuration, for example, the MOSI of SPI master 3100 is connected to the MOSI of first SPI slave 3200, while the MISO of first SPI slave 3200 is connected to the MOSI of second SPI slave 3300, then the MISO of second SPI slave 3300 is connected to the MOSI of third SPI slave 3400, then the MISO of third SPI slave is connected back to the MISO of SPI master 3100, thus completing the daisy chain from the master, through the three slaves, and back to the master. The CS of SPI master 3100 is connected simultaneously to the CS of first SPI slave 3200, the CS of second SPI slave 3300, and the CS of third SPI slave 3400.

[0035] The SPI port of each slave is configured to send an exact copy of the data it received during the first set of clock pulses during the second set of clock pulses. The entire chain acts as a communication shift register; a daisy chain is typically implemented through a shift register, providing a set of inputs or outputs through SPI. Each slave will copy the input to the output at the next clock cycle until the active CS line goes high. This feature requires only a single CS line from the master device, rather than a separate CS line for each slave device as shown above. Figure 2

[0036] Figure 4 An example of the composition of a data packet in an SPI daisy chain connection is shown in schematic form. In this example, 4100 is the clock, 4200 is the CS or chip select signal, 4300 is an example of the MOSI data structure, the first 7 bits are the target slave address, the next bit is the W / R, where 0 is write and 1 is read, and the register address and data byte are stored in the remaining data. Figure 4

[0037] ​​Each slave device has its own unique address so that it can identify whether the data it receives is intended for it. One way to accomplish this is to require the slave device to be equipped with an address pin that is hardwired, which adds cost.

[0038] For example, in a parallel configuration of Figure 2 the first slave 2200 has an address of address #1, the second slave 2300 has an address of address #2, and the third slave has an address of address #3. If the target slave address field in MOSI 4300 is address #1, then the first slave 2200 will receive the data in MOSI 4300. By analogy, referring back to Figure 4 if the target slave address field in MOSI 4300 is address #2, then the data in MOSI 4300 will be received by the second slave 2300, and if the target slave address field in MOSI 4300 is address #3, then the data in MOSI 4300 will be received by the third slave 2400. For example, if address #1 is 000, address #2 is 001, and address #3 is 010, and if the target slave address in 4300 is 001, then the data in 4300 will be received by the second slave 2300. Similarly, if the target slave address is 010, then the data in 4300 will be received by the third slave 2400.

[0039] Figure 5 An example of how to locate a target in a chain of slave devices in a known SPI daisy chain connection is shown in schematic form. As shown in Figure 5 a field is added to the "data packet", referred to herein as a "chain field". The "chain field" from the master device will be set to "0x00", on the one hand. When the data packet passes through a slave device, the "chain field" will be incremented by "1" and pushed to SDO.

[0040] The slave device compares the "chain field" to the "target slave address field". If the addresses match, a target is located, and the slave device is the target of the "data packet". While this method can locate a target slave device, the additional "chain field" takes up additional bandwidth.

[0041] Referring again to Figure 5,5100 is the clock, 5200 is the CS. MOSI 5300 implements an extra chaining field after the 7-bit target slave address and 1-bit W / R. The chaining field is followed by the register address and data bytes. In a daisy chain configuration, when MOSI is transmitted to the first slave device, it is shifted to the right. For example, MOSI / SDI_0 5400 is shifted right to SDO_0 / SDI_1 5500, and then it is shifted right to SDO_1 / SDI_2, as shown in Figure 5 In this example, the 7-bit target slave address is 0x02 and the chaining field is 0x00. During the shifting, the chaining field is compared to the target slave address, and once the chaining field matches the target slave address, the target slave device is located and the data is transmitted to it. As mentioned before, the extra "chaining field" takes up extra bandwidth and is a waste of resources.

[0042] Figure 3 Data in a middle daisy chain configuration is transmitted differently. For example, the target slave address in 5300 is address #3 and the chaining field in 5300 is address #1, then MOSI 5300 is sent from the master 3100 to the first slave 3200, and in accordance with Figure 3 In a daisy chain arrangement in 3300, when the data MOSI / SDI_0 5400 is sent from the first slave 3300, the chaining field is incremented and becomes address #2, and then a comparison is made between the target slave address and the chaining field address. If there is a match, then the target slave device is located. Otherwise, the data is transmitted to the next slave in the daisy chain until a match is found and the target slave is located. For example, SDO_0 / SDI_1 5500 is sent to the next slave 3400 and the chaining field is further incremented to become address #3 which matches the target slave address #3, and then the target slave is located and it is the third slave 3400. For example, the chaining field is 000, the target slave address is 002, address #1 is 000, address #2 is 001, and address #3 is 002, then when SDO_0 / SDI_1 comes out of the first slave, the chaining field 000 is incremented by 1 to become 001, and SDO_0 / SDI_1 is sent to the second slave 3300. When it comes out of the second slave 3300, the chaining field 001 is incremented by 1 again to become 002. When it is sent to the third slave 3400, a comparison is made between the chaining field and the target slave address field, and a match is found, which means that the data is for the third slave 3400. In the above implementation, an extra data field chaining field is needed which takes up extra storage and bandwidth. The goal of the present invention is to avoid such an extra chaining field to save storage and bandwidth.

[0043] Figure 6The bytes used in one way of programming all slave addresses are described. By contrast, Figure 9 The bytes used in another way of programming all slave addresses are described, in which one additional byte (e.g. the 3rd byte) is used to specify a custom increment value different from the default value "1".

[0044] Correspondingly, Figure 7 An example of how to program all slave addresses by assigning addresses to each slave using the bytes described in Figure 6 is shown in schematic form; and Figure 8 An example of the result of programming all slave addresses as shown in Figure 7 is shown in schematic form. In general, Figures 6-8 A first embodiment is shown.

[0045] For the bytes used in another way of programming all slave addresses as shown in Figure 9 there are two embodiments, Figure 10 and Figure 11 corresponding to the second embodiment (together with Figure 9 ), Figure 12 and Figure 13 corresponding to the third embodiment (together with Figure 9 ). More specifically, Figure 10 Another example of how to program all slave addresses by assigning addresses to each slave using the bytes described in Figure 9 is shown in schematic form, and Figure 11 An example of the result of programming all slave addresses as shown in Figure 10 is shown in schematic form. By contrast, Figure 12 Another example of how to program all slave addresses using a different starting address (e.g. "0x01") and a custom increment value (e.g. "2") is shown in schematic form, Figure 9 is shown in schematic form. Figure 13 The result of programming the addresses as shown in Figure 12 is shown in schematic form.

[0046] Figures 6-8 A first embodiment of the inventive method is shown, in which all slave devices can be assigned their unique address, and the master device can control the slave devices as if the slave devices were hardwired at their respective address pins.

[0047] Figure 6 The bytes used in one way of programming all slave addresses are described. According to Figure 6The 0x7F in the "Target Slave Address" field (byte #1) defines a command that is broadcast to all slaves in the daisy chain. The "Register" field (byte #2) defines the specific location where the slave address of this slave is stored. The "Slave Address" field (byte #3) is filled in by the first slave address in the daisy chain.

[0048] Figure 7 An example of how all slave addresses are programmed by assigning addresses to each slave using the bytes described in Figure 6 Figure 7 In, 7100 is the clock signal, chip select CS is 7200, MOSI 7300 includes the first 7 bits of the slave address, followed by the next bit W / R, followed by the register address and the starting address. For example, 7400 MOSI / SDI_0 includes the first 7 bits of the slave address 111_111, followed by the next bit 0 (W), followed by the register address 0xFF, and then the starting address 0x00 for slave #1 8100. In a daisy chain configuration, MOSI / SDI_0 is transmitted to the next slave, so it is shifted to the right to become SDO_0 / SDI_1. By default, the increment is 1, and the starting address 0x00 is incremented by 1 to become 0x01 in slave #2 8200. SDO_0 / SDI_1 is further shifted to the right to become SDO_1 / SDI_2, and the starting address 0x01 is incremented by 1 to become 0x02 in slave #3 8300. Figure 8 The same process is described differently, where the SPI chain starts at 0x00 and increments by 0x01.

[0049] To avoid using a chained field, a "program address" or "address programming" operation is performed on all slave devices to enable the initialization or programming of the slave devices. This "program address" only needs to be performed once at power up. For example, when the slave devices are powered up, the addresses are stored in the "register address" field of 7300 at initialization. For example, at the address 0xFF of the first slave 3200, address #1 is stored, at the address 0xFF of the second slave 3300, address #2 is stored, and at the address 0xFF of the third slave 3400, address #3, the starting address, is stored. The slave addresses address #1, address #2, and address #3 are programmed and stored in the slave addresses of the corresponding slave devices.

[0050] ​In a programming operation of the address, address #1 is stored at 0xFF address in the first slave 3200, then address #1 is incremented to address #2 to be transmitted to the next slave 3300, then address #2 is stored at address 0Xff of the second slave 3300. Then, address #2 is incremented again to become address #3 to be sent to the third slave 3400, and address #3 is stored at 0xFF of the third slave 3400. For example, address #1 is 000,000 is stored at 0xFF of the first slave 3200, then 000 is incremented by 1 to become 001 and is sent to the second slave 3300, 001 is stored at 0xFF of the second slave 3300. Then, 001 is further increased by 1 to become 002 to be sent to the third slave 3400, 002 is stored at 0xFF of the third slave 3400. Therefore, in subsequent transmissions, the chain field is no longer needed in the daisy chain configuration, only the target field is needed, thereby saving storage and bandwidth.

[0051] Figure 8 An example of the result of programming all slave addresses shown in Figure 7 is shown in the form of a schematic diagram, where the SPI daisy chain starts from address "0x00", and by default, the address value is increased by a default increment value "1" each time through, thereby generating three addresses "0x00000000", "0x0000001", and "0x00000010" for the three slaves on the chain, respectively.

[0052] As shown in Figure 7 and 8 When a slave device receives a data packet and identifies that the data packet is for programming the slave address, it stores the "slave address" (byte #3) in the register defined in the register field (byte #2). At the same time, the slave address (byte #3) will be increased by "1", and pushed to SDO. In normal operation, after all slaves have been programmed and assigned their respective slave addresses (i.e., address #1, address #2, and address #3), the first field in the data packet is the "target slave address", which performs read and write operations on the corresponding slave. The LSB (least significant bit) of the target slave address field defines the read / write operation. The slave receiving the "target slave address" compares the received target slave address with the stored slave address to check for a match. If there is a match, the read / write operation is performed. However, when the "target slave address" matches a predefined broadcast address, the read / write operation is performed in all slaves.

[0053] Figure 9 A byte for another way of programming all slave addresses is described, in which there is an additional byte (3rd byte) for specifying a custom increment value different from the default value "1". Figures 9-11A second embodiment of the disclosed method is shown. Figure 9 , 12 A third embodiment of the disclosed method is shown. In comparison to the first embodiment, the second and third embodiments use an additional field - the "increment" field (byte #3) which defines the increment of the slave address. The "increment" field and the "slave address" enable the system to allocate multiple slave chains with different addresses.

[0054] As shown in Figures 10-11 , in the first chain (SPI chain 1), the increment is 0x02 and the initial slave address is 0x00. As shown in Figures 12-13 , in the second chain (SPI chain 2), the increment is 0x02 and the initial slave address is 0x01. Thus, the slave addresses in SPI chain 1 are 0x00, 0x02, 0x04,..., etc. However, the slave addresses in SPI chain 2 become 0x01, 0x03, 0x05,..., etc. The increment can be adjusted to accommodate more than two SPI chains.

[0055] Figure 10 Another example of how all slave addresses are programmed by using the bytes described in Figure 9 to allocate addresses to each slave is shown in schematic form. Figure 10 An example of how all slave addresses for all slaves are programmed is shown. Signal 10100 is the clock, chip select CS is 10200, MOSI 10300 includes the first 7 bits as the slave address, followed by the next bit which is W / R, followed by the register address and the starting address. For example, 10400 MOSI / SDI_0 includes the first 7 bits of slave address 111_1111, followed by the next bit 0 (W), followed by the register address 0xFF, and then the starting address 0x02 for slave #1 11100. In a daisy chain configuration, MOSI / SDI_0 is transmitted to the next slave and thus shifted to the right to become SDO_0 / SDI_1, as shown in Figure 10 The increment is 2 and the starting address 0x00 in slave #2 11200 is incremented by 2 to become 0x02. SDO_0 / SDI_1 is further shifted to the right to become SDO_1 / SDI_2 and the starting address 0x02 is incremented by 2 to become 0x04 in slave #3 11300.

[0056] In the address programming operation, the first field is the "predefined broadcast address" and the LSB defines the "write" operation. Another field defines the location in the memory (e.g. 0xFF) where the "slave address" (e.g. address #1) is stored. This location can be the address of a register or an address in the slave's memory. When the "location" is predefined, this field becomes optional. The "increment" is defined in another field of the slave address and again, if the increment is predefined, this "increment" is optional. Another field defines the "start address" of the MOSI which is the host output and slave input. Another field defines the "increment address" which is the slave output.

[0057] In the address programming operation, if the slave device acknowledges the packet for the programming operation of the slave address, the first slave stores the "slave address" in the "location" (e.g. 0xFF) of the first slave. And the "start address" is given the "increment value" to become the incremented address which is transmitted to the second slave. When the packet is sent from the second slave to the third slave device, the same operation is performed, and so on.

[0058] In the address programming operation, once the slave (except the first slave) acknowledges the packet for the programming of the slave address, the slave stores the "increment address" in the "location" and adds the "increment value" to the "increment address" to obtain the updated "increment address".

[0059] Figure 11 An example of the result of programming all slave addresses is shown in the form of a schematic diagram Figure 10 where the SPI daisy chain starts from the address "0x00" and increases the address value by a custom increment value "2" at each pass, resulting in three addresses "0x000000000", "0x000000010" and "0x000000100" in the SPI chain 1 respectively, the data transmission starts from 0x 00 with an increment of 0x02. Figure 11 An example is shown where the SPI chain 1 starts from 0x01 with an increment of 0x02. Corresponding to the illustration in Figure 10 the register values of slave #1 11100, slave #2 11200 and slave #3 11300 are shown. Overall, Figures 9-11 A second embodiment is shown.

[0060] Figure 12 Another example of how all slave addresses can be programmed using a different start address (e.g. "0x01") and a custom increment value (e.g. "2") is shown schematically. Referring to Figure 12 , the start address can be 0x01 instead of Figure 10shown. In MOSI / SDI_0, the starting address of 12400 is 0x00, in 12500 SDO_0 / SDI_1, the address is shifted right and incremented by 2, becoming 0x01, in 12600 SDO_1 / SDI_2, the address is further shifted right and incremented by 2, becoming 0x02.

[0061] Figure 13 shown in schematic form Figure 12 shown. In MOSI / SDI_0, the starting address of 12400 is 0x00, in 12500 SDO_0 / SDI_1, the address is shifted right and incremented by 2, becoming 0x01, in 12600 SDO_1 / SDI_2, the address is further shifted right and incremented by 2, becoming 0x02. Figure 13 shown. In MOSI / SDI_0, the starting address of 12400 is 0x00, in 12500 SDO_0 / SDI_1, the address is shifted right and incremented by 2, becoming 0x01, in 12600 SDO_1 / SDI_2, the address is further shifted right and incremented by 2, becoming 0x02. Figure 12 shown. In MOSI / SDI_0, the starting address of 12400 is 0x00, in 12500 SDO_0 / SDI_1, the address is shifted right and incremented by 2, becoming 0x01, in 12600 SDO_1 / SDI_2, the address is further shifted right and incremented by 2, becoming 0x02. Figure 12 and 13 shown. In MOSI / SDI_0, the starting address of 12400 is 0x00, in 12500 SDO_0 / SDI_1, the address is shifted right and incremented by 2, becoming 0x01, in 12600 SDO_1 / SDI_2, the address is further shifted right and incremented by 2, becoming 0x02. Figure 9 、 12 -13 collectively show a third embodiment.

[0062] Figure 14To the flowchart 1400, which illustrates a method of communication between devices arranged in a serial peripheral interface daisy chain connection. According to some embodiments, in a first step 1410, the target slave address is compared to a predefined broadcast address, which can be for example 0x7F. If the target slave address is equal to the predefined broadcast address, then the next step is 1420. Otherwise, the target slave address is not equal to the predefined broadcast address, and the next step is 1480. In step 1420, the register address is compared to a predefined location of the slave address. If the register address matches the predefined location of the slave address, then the next step is 1430, which performs an address programming operation. When the register address does not match the predefined location of the slave address, then the next step is 1510, which performs one of the normal operations, i.e., sending the same data packet to all slaves, i.e., broadcasting. When the address programming operation is performed in step 1430, a determination is made in step 1440 whether the increment of the slave address is predefined or stored in the data packet. If the increment of the slave address is not predefined, then the next step is 1450, and the increment of the slave address is defined in the "increment" field of the data packet, while the increment address can be calculated as: increment address = start address + increment field. If the increment of the slave address is predefined, for example with a default value of 1, then the next step is 1460, and the increment address can be calculated as: increment address = start address + predefined increment. For example, when the predefined increment is the default value of 1, then the increment address can be calculated as: increment address = start address + 1. When the increment address is obtained from step 1450 or 1460, a new data packet is sent to the next slave in the daisy chain.

[0063] In step 1480, the target slave address is compared to the slave address stored in the current slave. If the target slave address is equal to the slave address stored in the current slave, then a matching address is found with the current slave, and a read / write operation is performed on the current slave. As previously described, a write operation is performed on the current slave when the corresponding read / write bit is 0, while a read operation is performed on the current slave when the corresponding read / write bit is 1. When the target slave address does not match the slave address stored in the current slave, then in the next step 1500, the target slave address is sequentially compared to the slave address stored in the next slave in the daisy chain until a matching address is found.

[0064] The above embodiments have various modifications. The scope of protection is not limited to the embodiments described herein. The scope of protection is only limited by the claims. The scope of the claims should include all equivalents of the claims.

Claims

1. A method of programming and controlling a plurality of slaves in a daisy chain using a master, characterized by, The method comprises: assigning a unique slave address to each of a plurality of slaves by sending an initialization packet from a master in serial fashion through the plurality of slaves; storing the slave address in each of the plurality of slaves; defining a data packet, wherein the data packet defines a target slave address, a read / write command, and a start address; and transmitting the data packet to one or more of the plurality of slaves; the data packet further defines a register address, and when the target slave address is not equal to a predefined broadcast address or the register address is not equal to a predefined location of the slave address, a normal operation is performed.

2. The method of claim 1, wherein, During normal operation, the plurality of slaves receives the target slave address, and when the target slave address is equal to a predefined broadcast address, a read / write operation is performed on the plurality of slaves.

3. The method of claim 1, wherein, When the target slave address is equal to the slave address stored in one of the plurality of slaves, a read / write operation is performed on the one of the plurality of slaves.

4. The method of claim 1, wherein, When the target slave address is not equal to the slave address stored in a particular slave, the data packet is sent to a subsequent slave connected in series in the daisy chain; and the target slave address is compared to the slave address stored in the subsequent slave.

5. The method of claim 1, wherein, When the target slave address is equal to a predefined broadcast address and the register address is equal to a predefined location of the slave address, a slave address programming operation is performed.

6. The method of claim 5, wherein, The data packet further defines an increment value.

7. The method of claim 6, wherein, The increment value is an integer of 1 or greater.

8. The method of claim 6, wherein, The data packet further defines an increment address, the value of which is equal to the start address plus the increment value.

9. The method of claim 8, wherein, Further comprising: updating the increment address in a subsequent slave connected in series in the daisy chain by adding the increment value to the increment address.

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