Display device and display panel driving method

Abstract

The embodiment of the present invention provides a display device and a driving method of a display panel, which relates to the field of display technology and is used to improve undesirable phenomena such as screen flickering or uneven display. The display device includes a display panel, the display panel includes a display area, the display area includes a plurality of pixel circuits, the pixel circuit includes a driving transistor and a voltage regulating module, wherein the voltage regulating module is used to adjust the node voltage of the driving transistor using the voltage provided by the voltage regulating signal line; wherein the data refresh frequency of the pixel circuit includes a first frequency and a second frequency, and the first frequency is greater than the second frequency; when the pixel circuit refreshes data at the first frequency, the voltage regulating signal line provides a first voltage, and when the pixel circuit refreshes data at the second frequency, the voltage regulating signal line provides a second voltage, and the first voltage is not equal to the second voltage.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display device and a driving method of a display panel. [Background technology]

[0002] With the continuous development of display technology, the driving modes of display panels are becoming more and more diversified. For example, during the display process of the display panel, the pixel circuit can perform data refresh at different data refresh frequencies.

[0003] However, at different data refresh frequencies, the light emitting brightness of the light emitting elements varies, which may cause the display panel to easily experience undesirable phenomena such as screen flickering or uneven display. [Summary of the invention]

[0004] In view of this, embodiments of the present invention provide a display device and a method for driving a display panel to improve undesirable phenomena such as screen flickering or uneven display.

[0005] On the one hand, an embodiment of the present invention provides a display device, including a display panel, the display panel including a display area, the display area including a plurality of pixel circuits, the pixel circuit including a driving transistor and a voltage regulating module, wherein the voltage regulating module is used to adjust the node voltage of the driving transistor using the voltage provided by the voltage regulating signal line;

[0006] Wherein, the data refresh frequency of the pixel circuit includes a first frequency and a second frequency, and the first frequency is greater than the second frequency;

[0007] When the pixel circuit refreshes data at the first frequency, the voltage adjustment signal line provides a first voltage. When the pixel circuit refreshes data at the second frequency, the voltage adjustment signal line provides a second voltage. The first voltage is different from the second voltage.

[0008] On the other hand, an embodiment of the present invention provides a method for driving a display panel, wherein the display panel includes a display area, the display area includes a plurality of pixel circuits, the pixel circuit includes a driving transistor and a voltage regulating module, wherein the voltage regulating module is used to adjust a node voltage of the driving transistor using a voltage provided by a voltage regulating signal line;

[0009] Wherein, the data refresh frequency of the pixel circuit includes a first frequency and a second frequency, and the first frequency is greater than the second frequency;

[0010] The driving method comprises:

[0011] When controlling the pixel circuit to refresh data at the first frequency, controlling the voltage adjustment signal line to provide a first voltage;

[0012] When the pixel circuit is controlled to perform data refresh at the second frequency, the voltage adjustment signal line is controlled to provide a second voltage, wherein the first voltage is not equal to the second voltage.

[0013] One of the above technical solutions has the following beneficial effects:

[0014] Based on the technical solution provided by the embodiment of the present invention, the display panel can adjust the node voltage of the driving transistor in a specific period corresponding to different driving frequencies by differentially designing the voltage provided by the voltage adjustment signal line, so that the driving transistor is in a specific bias state. For example, by adjusting the first voltage or the second voltage, the bias state of the driving transistor in the high-frequency writing period under high-frequency driving can be adjusted to increase the driving current converted by the driving transistor, or the bias state of the driving transistor in the holding period under low-frequency driving can be adjusted to reduce the driving current converted by the driving transistor, thereby weakening the difference in luminous brightness of the light-emitting element in the high-frequency writing period and the holding period.

[0015] Furthermore, when the display panel needs to switch from low-frequency drive to high-frequency drive during display, the screen flickering phenomenon caused by the transition from the low-frequency drive holding period to the high-frequency drive writing period can be effectively weakened. Alternatively, when the display panel needs to perform zone-by-zone frequency control, the brightness difference between different zones can be effectively weakened, thereby effectively improving display uniformity.

Brief Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a working period corresponding to when a pixel circuit provided by an embodiment of the present invention performs data refresh at a first frequency and a second frequency;

[0018] Figure 2 A top view of a display device provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention;

[0020] Figure 4Another top view of the display device provided by the embodiment of the present invention;

[0021] Figure 5 A top view of a display panel provided by an embodiment of the present invention;

[0022] Figure 6 Another top view of the display panel provided by the embodiment of the present invention;

[0023] Figure 7 Another top view of the display device provided by the embodiment of the present invention

[0024] Figure 8 for Figure 3 A corresponding timing diagram;

[0025] Fig. 9 Another top view of the display device provided by the embodiment of the present invention;

[0026] Fig.10 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0027] Fig.11 for Fig.10 A corresponding timing diagram;

[0028] Fig.12 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0029] Fig.13 for Fig.12 A corresponding timing diagram;

[0030] Fig.14 Another top view of the display device provided by the embodiment of the present invention;

[0031] Fig.15 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0032] Fig.16 for Fig.15 A corresponding timing diagram;

[0033] Fig.17 Another top view of the display device provided by the embodiment of the present invention;

[0034] Fig.18 for Figure 3 Another corresponding timing diagram;

[0035] Fig.19 Another top view of the display device provided by the embodiment of the present invention;

[0036] Fig. 20A flow chart of a driving method provided by an embodiment of the present invention. [Specific implementation method]

[0037] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] It is understandable that the driving frequency of the display panel is the data refresh frequency of the pixel circuit in the display panel, which refers to the frequency of writing data voltage to the pixel circuit, that is, the charging frequency of the driving transistor in the pixel circuit.

[0042] like Figure 1 As shown, Figure 1 A schematic diagram of the working period corresponding to the data refresh of the pixel circuit provided by the embodiment of the present invention at the first frequency and the second frequency. When the display panel is driven at a high frequency at the first frequency f1, the data refresh period of the pixel circuit is t1. The data refresh period t1 is defined as a high-frequency writing period WF_H in the embodiment of the present invention. In the high-frequency writing period WF_H, the pixel circuit at least performs a reset operation, a charging operation and a light emitting operation in sequence.

[0043] When the display panel is driven at a low frequency with the second frequency f2, the data refresh period of the pixel circuit is t2. t2>t1. The data refresh period t2 includes a low-frequency writing period WF_L and a plurality of holding periods HF. In the low-frequency writing period WF_L, the pixel circuit at least performs a reset operation, a charging operation and a light-emitting operation in sequence, while in the holding period HF, the pixel circuit no longer performs a reset operation and a charging operation. The holding period HF uses the data voltage written in the low-frequency writing period WF_L to realize light emission.

[0044] Taking f1=120Hz, f2=1Hz as an example, under high frequency drive, That is, the duration of the high-frequency writing period WF_H is Under low-frequency driving, t2=1s, the data refresh period t2 of the pixel circuit includes a low-frequency writing period WF_L and 119 holding periods HF, and the durations of the low-frequency writing period WF_L and the single holding period HF are respectively

[0045] Since the holding period HF differs from the low-frequency writing period WF_L and the high-frequency writing period WF_H in whether the data voltage is written to the driving transistor, there is a difference in the bias state of the driving transistor in the holding period HF and the low-frequency writing period WF_L and the high-frequency writing period WF_H, which makes the luminous brightness of the light-emitting element in the holding period HF higher than the luminous brightness of the light-emitting element in the low-frequency writing period WF_L and the high-frequency writing period WF_H.

[0046] In one case, if the display panel needs to switch from low-frequency drive to high-frequency drive during the display process, then when the low-frequency drive holding period HF enters the high-frequency drive high-frequency write period WF_H, the display panel will produce obvious flickering, which will have an adverse effect on the display effect of the display panel.

[0047] In another case, if the display panel needs to perform zone-by-zone frequency control, for example, when the display panel displays a picture, it is necessary to perform low-frequency driving on one zone in the display area and high-frequency driving on another zone. Since the brightness of the holding period HF in the low-frequency driving is higher than the brightness of the high-frequency writing period WF_H in the high-frequency driving, and the low-frequency driving process includes multiple holding periods HF, the brightness of different zones will be greatly different, resulting in uneven display problems.

[0048] In this regard, an embodiment of the present invention provides a display device, such as Figure 2 and Figure 3 As shown, Figure 2 A top view of a display device provided by an embodiment of the present invention, Figure 3A structural schematic diagram of a pixel circuit 2 provided in an embodiment of the present invention, the display device includes a display panel 100, the display panel 100 includes a display area 1, the display area 1 includes a plurality of pixel circuits 2, the pixel circuit 2 includes a driving transistor M0 and a voltage regulation module 3, wherein the voltage regulation module 3 is used to adjust the node voltage of the driving transistor M0 using the voltage provided by the voltage regulation signal line 4.

[0049] It should be noted that, in the pixel circuit 2, the gate of the driving transistor M0 is electrically connected to the first node N1, the first electrode of the driving transistor M0 is electrically connected to the second node N2, and the second electrode of the driving transistor M0 is electrically connected to the third node N3. The node voltage of the driving transistor M0 includes the voltage of the gate of the driving transistor M0 (the voltage of the first node N1), the voltage of the first electrode of the driving transistor M0 (the voltage of the second node N2), and / or the voltage of the second electrode of the driving transistor M0 (the voltage of the third node N3).

[0050] The data refresh frequency of the pixel circuit 2 includes a first frequency and a second frequency, and the first frequency is greater than the second frequency. When the pixel circuit 2 performs data refresh at the first frequency, the voltage adjustment signal line 4 provides a first voltage, and when the pixel circuit 2 performs data refresh at the second frequency, the voltage adjustment signal line 4 provides a second voltage, and the first voltage is not equal to the second voltage.

[0051] Based on the technical solution provided by the embodiment of the present invention, the display panel 100 can adjust the node voltage of the driving transistor M0 in a specific period corresponding to different driving frequencies by differentially designing the voltage provided by the voltage adjustment signal line 4 under different driving frequencies, so that the driving transistor M0 is in a specific bias state. For example, by adjusting the first voltage or the second voltage, the bias state of the driving transistor M0 in the high-frequency writing period WF_H under high-frequency driving can be adjusted to increase the driving current converted by the driving transistor M0, or the bias state of the driving transistor M0 in the holding period HF under low-frequency driving can be adjusted to reduce the driving current converted by the driving transistor M0, thereby weakening the difference in luminous brightness of the light-emitting element D in the high-frequency writing period WF_H and the holding period HF.

[0052] Furthermore, when the display panel 100 needs to switch from low-frequency drive to high-frequency drive during the display process, the screen flickering phenomenon caused by the low-frequency drive holding period HF entering the high-frequency drive high-frequency writing period WF_H can be effectively weakened. Alternatively, when the display panel 100 needs to perform partition frequency control, the brightness difference between different partitions can be effectively weakened, thereby effectively improving the display uniformity. This technical solution is more suitable for medium and large-sized split-screen display products.

[0053] In one driving method, the display panel 100 can have multiple display modes: for example, when the display panel 100 is required to display dynamic images such as videos and games, the display panel 100 can be in a high-frequency driving display mode, thereby controlling the pixel circuit 2 to refresh data at a higher frequency to improve the smoothness of the picture; when the display panel 100 is required to be in standby mode or only needs to display text and other images, the display panel 100 can be in a low-frequency driving display mode, thereby controlling the pixel circuit 2 to refresh data at a lower frequency to save power consumption.

[0054] Based on this, in a feasible implementation, the display panel 100 has a first mode and a second mode, wherein the first mode may correspond to a high-frequency driven display mode, and the second mode may correspond to a low-frequency driven display mode.

[0055] See again Figure 2 The display device further includes a first driving module 200, which can be specifically a processor in a driving chip. The first driving module 200 is used to: in a first mode, control the pixel circuit 2 in the display area 1 to perform data refresh at a first frequency, and control the voltage regulating signal line 4 electrically connected to the pixel circuit 2 in the display area 1 to provide a first voltage; in a second mode, control the pixel circuit 2 in the display area 1 to perform data refresh at a second frequency, and control the voltage regulating signal line 4 electrically connected to the pixel circuit 2 in the display area 1 to provide a second voltage.

[0056] It should be noted that when the pixel circuits 2 in the display area 1 are all used to control the light-emitting elements D to emit light, in the first mode, the first driving module 200 can control all the pixel circuits 2 in the display area 1 to refresh data at a first frequency, and control the voltage adjustment signal lines 4 electrically connected to all the pixel circuits 2 to provide a first voltage. In the second mode, the first driving module 200 can control all the pixel circuits 2 in the display area 1 to refresh data at a second frequency, and control the voltage adjustment signal lines 4 electrically connected to all the pixel circuits 2 to provide a second voltage.

[0057] When the display panel 100 has different display modes, the embodiment of the present invention can adjust the bias state of the driving transistor M0 in a specific period in different display modes to different degrees by differentially designing the voltage provided by the voltage adjustment signal line 4 in different display modes, thereby adjusting the size of the driving current that can be converted by the driving transistor M0 in different display modes. For example, the driving current converted by the driving transistor M0 can be increased in the first mode to weaken the difference in the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H and the holding period HF, and then when the display panel 100 switches from the second mode to the first mode, the flickering phenomenon during the screen switching (jumping from the holding period HF to the high-frequency writing period WF_H) can be effectively improved to optimize the display effect.

[0058] In another driving mode, when the display panel 100 displays a picture, different positions of the display area 1 can be used to display different contents. At this time, the display panel 100 can also be driven in different areas and frequencies: for example, part of the display area 1 is used to display videos, games and other contents. To improve the smoothness of the picture, this part of the area can be driven at high frequency, and the pixel circuit 2 in the area can be controlled to refresh data at a higher frequency such as 360Hz, 240Hz, 120Hz, etc. Another part of the area is used to display keyboards, time and other contents. Since this type of picture has a lower demand for display effects, in order to reduce power consumption, this part of the area can be driven at low frequency, and the pixel circuit 2 in the area can be controlled to refresh data at a lower frequency such as 30Hz, 10Hz, 1Hz, etc.

[0059] Based on this, in a feasible implementation mode, Figure 4 As shown, Figure 4 This is another top view of the display device provided by the embodiment of the present invention. The display device further includes a second driving module 300. The second driving module 300 may specifically be a processor in a driving chip.

[0060] The second driving module 300 is used to: when the display panel 100 displays a picture, control the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency, and the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the first partition 5 provides a first voltage; and control the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency, and the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the second partition 6 provides a second voltage.

[0061] The first partition 5 corresponds to a region in the display area 1 that needs to be driven at a high frequency, and the second partition 6 corresponds to a region in the display area 1 that needs to be driven at a low frequency.

[0062] Taking the first frequency as 120 Hz and the second frequency as 1 Hz as an example, the data refresh period t1 of the first pixel circuit 2 is The data refresh period t2 of the second pixel circuit 2 is 1s. Within 1s, the pixel circuit 2 in the first partition 5 performs 120 rounds of data refresh, corresponding to 120 high-frequency writing periods WF_H, while the pixel circuit 2 in the second partition 6 performs only 1 round of data refresh, corresponding to 1 low-frequency writing period WF_L and 119 holding periods HF. If the brightness difference between the holding period HF and the high-frequency writing period WF_H is large, then within a certain period of time, for example, within 1s, the overall display brightness of the second partition 6 will be significantly higher than the overall display brightness of the first partition 5, and a split screen phenomenon will occur.

[0063] The embodiment of the present invention can perform differential design on the voltage provided by the voltage regulating signal line 4 electrically connected to the pixel circuit 2 in the first partition 5 and the second partition 6, so as to regulate the bias state of the driving transistor M0 in the first partition 5 and the second partition 6 in a specific period to different degrees, and then regulate the magnitude of the driving current that can be converted by the driving transistor M0 in the first partition 5 and the second partition 6. For example, the driving current converted by the driving transistor M0 in the first partition 5 can be increased to weaken the difference in the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5 and the holding period HF corresponding to the second partition 6, and then the overall display brightness difference between the first partition 5 and the second partition 6 can be significantly weakened during the display process, effectively improving the display uniformity of the display panel 100 and improving the split screen phenomenon.

[0064] When the display panel 100 is driven by division and frequency, in a feasible implementation manner, refer again to Figure 4 When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 are fixed. That is, no matter what picture the display panel 100 displays, the positions of the first partition 5 and the second partition 6 do not change. The first partition 5 is always driven at a high frequency, while the second partition 6 is always driven at a low frequency.

[0065] This setting is more suitable for display devices in which a local area is used to display a specific picture. For example, in a type of medium-to-large-sized display device, the top corner of the display device only needs to display time information such as a clock, so the local area at the top corner can be set as the second partition 6, and the other area can be set as the first partition 5. At this time, the second driving module 300 only needs to differentially control the refresh frequency of the pixel circuits 2 in the first partition 5 and the second partition 6 according to the fixed position information of the first partition 5 and the second partition 6, and differentially control the voltage provided by the voltage adjustment signal line 4 electrically connected to the pixel circuits 2 in the first partition 5 and the second partition 6.

[0066] Further, see Figure 3The pixel circuit 2 also includes a data writing module 7 and a threshold compensation module 8, wherein the data writing module 7 is electrically connected to the third scanning signal line S3, the data line Data and the first electrode of the driving transistor M0, respectively, and the threshold compensation module 8 is electrically connected to the fourth scanning signal line S4, the second electrode of the driving transistor M0 and the gate of the driving transistor M0, respectively.

[0067] See also Figure 4 The display panel 100 also includes a first shift register 9 and a second shift register 10, the first shift register 9 is electrically connected to the fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the first partition 5, and the second shift register 10 is electrically connected to the fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the second partition 6.

[0068] When the display panel 100 displays different pictures, the second driving module 300 is also used to: control the first shift register 9 to output the fourth scanning signal to the fourth scanning signal line S4 electrically connected thereto at the first frequency, and control the second shift register 10 to output the fourth scanning signal to the fourth scanning signal line S4 electrically connected thereto at the second frequency.

[0069] As mentioned above, when the display panel 100 is driven at a low frequency at the second frequency, the data refresh period t2 of the pixel circuit 2 includes a low frequency writing period WF_L and a holding period HF. When the pixel circuit 2 includes the data writing module 7 and the threshold compensation module 8, in one configuration, Figure 8 , the third scanning signal line S3 and the fourth scanning signal line S4 are both scanned at the second frequency. At this time, in the low-frequency writing period WF_L, the data writing module 7 writes the data voltage V provided by the data line Data to Data The threshold compensation module 8 writes the data voltage V Data The gate of the driving transistor M0 is further written and threshold compensation is performed on the driving transistor M0. At this time, the charging frequency of the gate of the driving transistor M0 is the second frequency, that is, the pixel circuit 2 performs data refresh at the second frequency.

[0070] In another setup, combined with Fig.18, the fourth scanning signal line S4 is scanned at the second frequency, and the third scanning signal line S3 is scanned at a frequency higher than the second frequency. For example, the third scanning signal line S3 can be scanned at the first frequency. At this time, in the holding period HF, the bias voltage provided by the data line Data can be written into the first electrode of the driving transistor M0 by the data writing module 7 to adjust the bias state of the driving transistor M0. However, it should be noted that since the fourth scanning signal line S4 is still scanned at the second frequency, the threshold compensation module 8 does not work in the holding period HF, and the bias voltage cannot be further written into the gate of the driving transistor M0 via the threshold compensation module 8. At this time, the charging frequency of the driving transistor M0 is still the second frequency, that is, the pixel circuit 2 is still refreshing the data at the second frequency.

[0071] In summary, the data refresh frequency of the pixel circuit 2 corresponds to the scan frequency of the fourth scan signal line S4.

[0072] When the positions of the first partition 5 and the second partition 6 are fixed, the fourth scanning signal line S4 corresponding to the pixel circuit 2 in the first partition 5 and the fourth scanning signal line S4 corresponding to the pixel circuit 2 in the second partition 6 are driven separately by using two independent shift registers. When the display panel 100 displays the picture, the first shift register 9 and the second shift register 10 only need to work independently and output signals at different frequencies to control the pixel circuits 2 in different partitions to refresh data at different frequencies. This driving method can control the driving frequencies of the two partitions separately, and the two do not interfere with each other, and the control is simple and more accurate.

[0073] Further, see Figure 4 The display panel 100 further includes a first voltage bus 11 and a second voltage bus 12. The first voltage bus 11 is electrically connected to the voltage regulating signal line 4 electrically connected to the pixel circuit 2 in the first partition 5, and the first voltage bus 11 is used to provide a first voltage; the second voltage bus 12 is electrically connected to the voltage regulating signal line 4 electrically connected to the pixel circuit 2 in the second partition 6, and the second voltage bus 12 is used to provide a second voltage.

[0074] It should be noted that Figure 4 The positions of the first voltage bus 11 and the second voltage bus 12 shown are for schematic illustration only. In other optional settings, the first voltage bus 11 and the second voltage bus 12 may also be located at the lower frame. In this case, some connecting lines that intersect with the extension direction of the voltage regulation signal line 4 may be set in the display area 1, and these connecting lines are used to realize the electrical connection between the voltage regulation signal line 4 and the first voltage bus 11 or the second voltage bus 12.

[0075] In the above configuration, the voltage regulation signal lines 4 corresponding to different partitions are electrically connected to different voltage buses, respectively. By controlling different voltage buses to provide different voltages, it can be ensured that: when the first partition 5 is driven at a high frequency, the voltage regulation signal line 4 in the first partition 5 can continuously and stably output the first voltage; when the second partition 6 is driven at a low frequency, the voltage regulation signal line 4 in the second partition 6 can continuously and stably output the second voltage during low-frequency driving. In addition, the bias state of the driving transistor M0 can be stably and reliably regulated by using the first voltage and the second voltage.

[0076] Moreover, under this setting, the first voltage bus 11 and the second voltage bus 12 only need to continuously provide a constant voltage signal, and no voltage jump is required on the voltage bus, thereby avoiding the problem of inaccurate control of the bias state of the driving transistor M0 in the partition due to premature or late voltage jump.

[0077] When the positions of the first partition 5 and the second partition 6 are fixed, in a feasible implementation manner, as Figure 5 As shown, Figure 5 FIG. 1 is a top view of a display panel 100 provided in an embodiment of the present invention, wherein the first partition 5 and the second partition 6 are arranged along a first direction x. Figure 6 As shown, Figure 6 This is another top view of the display panel 100 provided in an embodiment of the present invention, in which the first partition 5 surrounds the second partition 6, and the first partition 5 and the second partition 6 overlap in the second direction y, wherein the second direction y is the extension direction of the fourth scanning signal line S4, and the first direction x intersects the second direction y.

[0078] When the first partition 5 and the second partition 6 are arranged along the first direction x, the display panel 100 can be regarded as being split into upper and lower screens. For example, the upper half of the screen is used to display games, videos and the like, and the lower half of the screen is used to display keyboards and the like. At this time, the fourth scan signal line S4 in the first partition 5 and the second partition 6 are both conventionally set entire lines, and there is no need to disconnect the fourth scan signal line S4.

[0079] When the first partition 5 surrounds the second partition 6, and the first partition 5 and the second partition 6 overlap in the second direction y, illustratively, when the top corner of the display panel 100 is used to display time information such as a clock, and other positions are used to display other dynamic images, the display panel 100 can be split-screen displayed at the top corner. At this time, it is equivalent to disconnecting the entire conventional fourth scan signal line S4 at the junction of the first partition 5 and the second partition 6, so that the fourth scan signal lines S4 in the first partition 5 and the second partition 6 are independent of each other, so as to realize electrical connection with the corresponding shift registers.

[0080] When the display panel 100 is driven by division and frequency, in another feasible implementation manner, as shown in FIG. Figure 7 As shown, Figure 7 This is another top view of the display device provided by the embodiment of the present invention. When the display panel 100 displays different images, the positions of the first partition 5 and the second partition 6 are not fixed.

[0081] At this time, the second driving module 300 includes a dividing unit 301 and a control unit 302. The dividing unit 301 and the control unit 302 may be processing units in a driving chip processor for realizing different functions.

[0082] The division unit 301 is used to divide the display area 1 into a first partition 5 and a second partition 6 according to the content to be displayed in different areas of the display panel 100 , and generate position information of the first partition 5 and the second partition 6 .

[0083] The control unit 302 is electrically connected to the division unit 301, and the control unit 302 is used to: according to the position information of the first partition 5 and the second partition 6 generated by the division unit 301, control the pixel circuit 2 in the first partition 5 to refresh data at a first frequency, and the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the first partition 5 provides a first voltage; and control the pixel circuit 2 in the second partition 6 to refresh data at a second frequency, and the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the second partition 6 provides a second voltage.

[0084] It should be noted that Figure 7 The positions of the first partition 5 and the second partition 6 are merely schematic representations of positions in a certain picture to be displayed. When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 may be changed.

[0085] In the above-mentioned setting, when the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 are set according to the specific content to be displayed on the picture to be displayed. At this time, the positions of the first partition 5 and the second partition 6 can be flexibly adjusted according to the different displayed pictures, and the position division of the first partition 5 and the second partition 6 is more flexible.

[0086] Furthermore, combined with Figure 3 The pixel circuit 2 further includes a data writing module 7 and a threshold compensation module 8, wherein the data writing module 7 is electrically connected to the third scanning signal line S3, the data line Data and the first electrode of the driving transistor M0, respectively, and the threshold compensation module 8 is electrically connected to the fourth scanning signal line S4, the second electrode of the driving transistor M0 and the gate of the driving transistor M0, respectively. As mentioned above, the data refresh frequency of the pixel circuit 2 corresponds to the scanning frequency of the fourth scanning signal line S4.

[0087] Combination Figure 7 The display panel 100 further includes a third shift register 13, and the third shift register 13 is electrically connected to the fourth scan signal line S4. The control unit 302 is further configured to: when driving the first partition 5, control the third shift register 13 to output a fourth scan signal to the fourth scan signal line S4 electrically connected to the pixel circuit 2 in the first partition 5 at a first frequency, and when driving the second partition 6, control the third shift register 13 to output a fourth scan signal to the fourth scan signal line S4 electrically connected to the pixel circuit 2 in the second partition 6 at a second frequency.

[0088] In the above configuration, the fourth scanning signal lines S4 in the entire display area 1 are electrically connected to the same third shift register 13. The control unit 302 only needs to control the third shift register 13 to output signals to the fourth scanning signal lines S4 in different partitions at different frequencies according to the determined position information of the first partition 5 and the second partition 6, thereby controlling the pixel circuits 2 in different partitions to perform data refresh at different frequencies.

[0089] Further, see again Figure 7 , the third shift register 13 is electrically connected to the clock signal line CK. The control unit 302 is further configured to: when driving the first partition 5, control the clock signal line CK to output a clock signal to the third shift register 13 at a first frequency, and when driving the second partition 6, control the clock signal line CK to output a clock signal to the third shift register 13 at a second frequency, so that the third shift register 13 outputs a fourth scanning signal at different frequencies under the drive of clock signals of different frequencies.

[0090] Further, see again Figure 7 The display panel 100 further includes a third voltage bus 14, which is electrically connected to the voltage adjustment signal line 4. The control unit 302 is further configured to: when driving the first partition 5, control the third voltage bus 14 to output the first voltage; when driving the second partition 6, control the third voltage bus 14 to output the second voltage.

[0091] In the above-mentioned setting, the voltage regulation signal lines 4 are all electrically connected to the same third voltage bus 14. The control unit 302 can control the voltage provided by the third voltage bus 14 to jump when controlling the third shift register 13 to jump the output signal frequency, thereby causing the third voltage bus 14 to output its corresponding voltage to the voltage regulation signal lines 4 in different partitions.

[0092] In a possible implementation, combining Figure 3 and Figure 8 , Figure 8 for Figure 3In a corresponding timing diagram, the voltage regulating module 3 includes a gate reset module 15, and the voltage regulating signal line 4 includes a gate reset signal line Ref1. The gate reset module 15 is electrically connected to the first scanning signal line S1, the gate reset signal line Ref1 and the gate of the driving transistor M0 respectively.

[0093] When the pixel circuit 2 refreshes data at a first frequency, the first scanning signal line S1 is scanned at the first frequency, and the gate reset signal line Ref1 provides a first gate reset voltage; when the pixel circuit 2 refreshes data at a second frequency, the first scanning signal line S1 is scanned at a second frequency, and the gate reset signal line Ref1 provides a second gate reset voltage, wherein the first gate reset voltage is greater than the second gate reset voltage.

[0094] Taking the driving transistor M0 as a P-type transistor as an example, when the gate reset module 15 responds to the first scanning signal provided by the first scanning signal line S1 to reset the gate of the driving transistor M0, the gate potential of the driving transistor M0 is the written gate reset voltage, and the source (first electrode) potential of the driving transistor M0 maintains the power supply voltage V PVDD .

[0095] in, Figure 3 The complete working process of the illustrated pixel circuit 2 will be described in detail later.

[0096] Assume the first gate reset voltage is V ref1 , the second gate reset voltage is V ref1 '. In the high-frequency writing period WF_H under high-frequency driving, the gate-source voltage V gs1 =V ref1 -V PVDD , in the low-frequency writing period WF_L under low-frequency driving, the gate-source voltage V gs1 '=V ref1 '-V PVDD . Since V ref1 >V ref1 ', so V gs1 >V gs1 '.

[0097] It should be noted that when the driving transistor M0 is a P-type transistor, the gate reset voltage provided by the gate reset signal line Ref1 is a negative value. Therefore, after resetting the gate of the driving transistor M0, the gate-source voltage of the driving transistor M0 is also a negative value. gs1 >V gs1 ', indicating that V gs1The degree of negative bias is small, that is, the bias state of the driving transistor M0 in the high-frequency writing period WF_H is weaker than the bias state of the driving transistor M0 in the low-frequency writing period WF_L. At this time, in the high-frequency writing period WF_H, the threshold voltage V th The negative offset degree is low, making the threshold voltage V th The gate-source voltage of the driving transistor M0 is higher, which makes it easier for the gate-source voltage of the driving transistor M0 to meet the threshold voltage V th At this time, the driving current converted by the driving transistor M0 can be increased, that is, the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H can be increased.

[0098] After increasing the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H, the brightness difference between the high-frequency writing period WF_H and the holding period HF can be effectively reduced, thereby effectively weakening the screen flickering phenomenon when the display panel 100 performs low-high frequency switching, and effectively weakening the brightness difference between different partitions when the display panel 100 performs partition frequency control, thereby effectively improving display uniformity.

[0099] Furthermore, if Fig. 9 As shown, Fig. 9 This is another top view of the display device provided by the embodiment of the present invention. The display device further includes a second driving module 300 . The second driving module 300 includes a gate reset driving submodule 303 .

[0100] The gate reset driving submodule 303 is used to: when the display panel 100 displays a picture, control the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the first partition 5 is scanned at the first frequency, and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the first partition 5 provides a first gate reset voltage; and control the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the second partition 6 is scanned at the second frequency, and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the second partition 6 provides a second gate reset voltage.

[0101] Combined with the above analysis, the above setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5, thereby effectively weakening the overall display brightness difference between the first partition 5 and the second partition 6, improving the display uniformity of the display panel 100, and improving the split-screen phenomenon.

[0102] It should be noted that when the display panel 100 displays different images, the positions of the first partition 5 and the second partition 6 can be fixed. At this time, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the first partition 5 and the first scanning signal line S1 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to different shift registers, respectively, and driven separately by the shift registers. The gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the first partition 5 and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to different gate reset buses, respectively, to receive voltages provided by different gate reset buses.

[0103] When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 may not be fixed. At this time, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the first partition 5 and the first scanning signal line S1 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to the same shift register, and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the first partition 5 and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to the same gate reset bus. At this time, it is only necessary to control the shift register to change the output signal frequency and control the gate reset bus to change the output voltage when driving different partitions.

[0104] In a feasible implementation manner, the display panel 100 has a third mode and a fourth mode. In the third mode, In the fourth mode, n>m, f1 is the first frequency, f2 is the second frequency. The first scanning signal line S1 electrically connected to the pixel circuit 2 in the first partition 5 provides a first gate reset voltage in the third mode that is greater than the first gate reset voltage in the fourth mode.

[0105] In the third mode, taking f1=120Hz, f2=1Hz, and n=120 as an example, within 1s, the pixel circuit 2 in the first partition 5 performs 120 rounds of data refresh, corresponding to 120 high-frequency write periods WF_H, and the pixel circuit 2 in the second partition 6 performs 1 round of data refresh, corresponding to 1 low-frequency write period WF_L and 119 hold periods HF.

[0106] In the fourth mode, taking f1=120Hz, f2=20Hz, and m=6 as an example, within 1s, the pixel circuit 2 in the first partition 5 performs 120 rounds of data refresh, corresponding to 120 high-frequency write periods WF_H, and the pixel circuit 2 in the second partition 6 performs 20 rounds of data refresh, corresponding to 20 low-frequency write periods WF_L and 100 holding periods HF.

[0107] Since the number of holding periods HF of the second partition 6 in the third mode is greater than the number of holding periods HF of the second partition 6 in the fourth mode in the same time, the light luminance of the second partition 6 in the third mode is higher than the light luminance of the second partition 6 in the fourth mode in the same time. When there is a brightness difference between the holding period HF and the high-frequency writing period WF_H, the brightness difference between the second partition 6 and the first partition 5 in the third mode will be greater.

[0108] In this regard, in the embodiment of the present invention, for the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the first partition 5, the first gate reset voltage V ref1_11 is greater than the first gate reset voltage V provided in the fourth mode ref1_12 , so that: in the high-frequency writing period WF_H in the third mode, the gate-source voltage V of the driving transistor M0 in the pixel circuit 2 in the first partition 5 gs1_1 (V gs1_1 =V ref1_11 -V PVDD ), is greater than the high-frequency writing period WF_H in the fourth mode, the gate-source voltage V of the driving transistor M0 in the pixel circuit 2 in the second partition 6 gs1_2 (V gs1_2 =V ref1_12 -V PVDD ), thereby making the bias state of the driving transistor M0 in the high-frequency writing period WF_H in the third mode weaker, and the driving current converted by the driving transistor M0 larger, thereby improving the overall brightness of the first partition 5 in the third mode to a greater extent, and reducing the brightness difference between the first partition 5 and the second partition 6 in the third mode, thereby making the display panel 100 have a higher display uniformity in different modes.

[0109] In one possible implementation, see again Figure 3 The gate reset module 15 includes a gate reset transistor M1, a gate of the gate reset transistor M1 is electrically connected to the first scanning signal line S1, a first electrode of the gate reset transistor M1 is electrically connected to the gate reset signal line Ref1, and a second electrode of the gate reset transistor M1 is electrically connected to the gate of the driving transistor M0.

[0110] The gate reset transistor M1 is used to be turned on under the action of the enable level provided by the first scanning signal line S1, and write the first gate reset voltage or the second gate reset voltage provided by the gate reset signal line Ref1 into the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0111] In a possible implementation, Figure 10 to Figure 13 As shown, Fig.10Another structural schematic diagram of the pixel circuit 2 provided in an embodiment of the present invention is shown in FIG. Fig.11 for Fig.10 A corresponding timing diagram, Fig.12 FIG. 2 is another structural diagram of the pixel circuit 2 provided in the embodiment of the present invention. Fig.13 for Fig.12 Corresponding to a timing diagram, the voltage regulating module 3 includes a regulating module 16, the voltage regulating signal line 4 includes a bias signal line DVH, and the regulating module 16 is electrically connected to the second scanning signal line S2, the bias signal line DVH and the first electrode of the driving transistor M0 respectively.

[0112] When the pixel circuit 2 refreshes data at a first frequency, the second scanning signal line S2 is scanned at the first frequency, and the bias signal line DVH provides a first bias voltage; when the pixel circuit 2 refreshes data at a second frequency, the second scanning signal line S2 is scanned at the first frequency, and the bias signal line DVH provides a second bias voltage, wherein the second bias voltage is greater than the first bias voltage.

[0113] It should be noted that in Fig.10 In the circuit structure of the pixel circuit 2 shown, the driving transistor M0 is a p-type transistor, the first electrode (source) of the driving transistor M0 is an electrode electrically connected to the power signal line PVDD through the second light emitting control module 18, and the second electrode (drain) of the driving transistor M0 is an electrode electrically connected to the light emitting element D through the first light emitting control module 17. Fig.12 In the circuit structure of the pixel circuit 2 shown, the driving transistor M0 is an n-type transistor, the first pole (source) of the driving transistor M0 is an electrode electrically connected to the light-emitting element D through the first light-emitting control module 17, and the second pole (drain) of the driving transistor M0 is an electrode electrically connected to the power signal line PVDD through the second light-emitting control module 18.

[0114] When the pixel circuit 2 refreshes data at a first frequency, in the high-frequency writing period WF_H, after the pixel circuit 2 performs a charging operation and before the light-emitting operation, the control module 16 can be used to write a first bias voltage to the source (first electrode) of the driving transistor M0 to adjust the bias state of the driving transistor M0.

[0115] When the pixel circuit 2 performs data refresh at the second frequency, in the low-frequency writing period WF_L, after the pixel circuit 2 performs the charging operation and before the light-emitting operation, the second bias voltage can be written to the source (first pole) of the driving transistor M0 by the control module 16 to adjust the bias state of the driving transistor M0. In the holding period HF, before the pixel circuit 2 performs the light-emitting operation, the second bias voltage can also be written to the source (first pole) of the driving transistor M0 by the control module 16 to adjust the bias state of the driving transistor M0.

[0116] in, Fig.10 and Fig.12 The complete working process of the illustrated pixel circuit 2 will be described in detail later.

[0117] Assume the first bias voltage is V DVH , the second bias voltage is V DVH '. In the high-frequency writing period WF_H corresponding to the high-frequency drive, when the pixel circuit 2 performs the bias operation, the gate voltage of the driving transistor M0 is V Data +V th , the source voltage of the driving transistor M0 is V DVH , the gate-source voltage V of the driving transistor M0 gs2 =V Data +Vth-V DVH In the holding period HF corresponding to the low-frequency drive, when the pixel circuit 2 performs the bias operation, the gate voltage of the driving transistor M0 maintains V Data +V th , the source voltage of the driving transistor M0 is V DVH ', the gate-source voltage V of the driving transistor M0 gs2 '=V Data +V th -V DVH '.

[0118] In the embodiment of the present invention, by increasing V DVH ', can reduce V gs2 ', so that the bias state of the driving transistor M0 in the holding period HF is enhanced, thereby reducing the driving current converted by the low driving transistor M0, reducing the luminous brightness of the light-emitting element D in the holding period HF, thereby further reducing the brightness difference between the holding period HF and the high-frequency writing period WF_H, and improving the screen flickering phenomenon or improving the display uniformity to a greater extent.

[0119] Moreover, after reducing the brightness of the holding period HF, the brightness difference between the holding period HF and the low-frequency writing period WF_L can also be reduced. When the display panel 100 is driven at a low frequency, the flickering phenomenon generated when the low-frequency writing period WF_L enters the holding period HF can also be weakened.

[0120] Furthermore, if Fig.14 As shown, Fig.14 This is another top view of the display device provided by the embodiment of the present invention. The display device further includes a second driving module 300 . The second driving module 300 includes a bias driving submodule 304 .

[0121] The bias driving submodule 304 is used for: when the display panel 100 displays a picture, controlling the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the first partition 5 to scan at the first frequency, and the bias signal line DVH electrically connected to the pixel circuit 2 in the first partition 5 to provide a first bias voltage; and controlling the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the second partition 6 to scan at a second frequency, and the bias signal line DVH electrically connected to the pixel circuit 2 in the second partition 6 to provide a second bias voltage.

[0122] As mentioned above, the embodiment of the present invention can reduce the brightness of the holding period HF, thereby reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF to a greater extent. Therefore, when the display panel 100 is partitioned and driven, the overall display brightness difference between the first partition 5 and the second partition 6 can be significantly improved, and the display uniformity of the display panel 100 can be effectively improved.

[0123] It should be noted that when the display panel 100 displays different images, the positions of the first partition 5 and the second partition 6 can be fixed. At this time, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the first partition 5 and the second scanning signal line S2 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to different shift registers, respectively, and driven separately by the shift registers. The bias signal line DVH electrically connected to the pixel circuit 2 in the first partition 5 and the bias signal line DVH electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to different bias buses, respectively, to receive voltages provided by different bias buses.

[0124] When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 may not be fixed. At this time, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the first partition 5 and the second scanning signal line S2 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to the same shift register, and the bias signal line DVH electrically connected to the pixel circuit 2 in the first partition 5 and the bias signal line DVH electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to the same bias bus. At this time, it is only necessary to control the shift register to change the output signal frequency and control the bias bus to change the output voltage when driving different partitions.

[0125] In one possible implementation, see Fig.10 and Fig.12The control module 16 includes a control transistor M2, a gate of the control transistor M2 is electrically connected to the second scan signal line S2, a first electrode of the control transistor M2 is electrically connected to the bias signal line DVH, and a second electrode of the control transistor M2 is electrically connected to the first electrode of the driving transistor M0.

[0126] The regulating transistor M2 is used to be turned on under the action of the enable level provided by the second scanning signal line S2, and transmit the first bias voltage or the second bias voltage provided by the bias signal line DVH to the first electrode of the driving transistor M0, so as to adjust the bias state of the driving transistor M0.

[0127] In a possible implementation, Fig.15 and Fig.16 As shown, Fig.15 2 is another structural diagram of the pixel circuit 2 provided in an embodiment of the present invention. Fig.16 for Fig.15 In a corresponding timing diagram, the voltage regulation module 3 includes a first anode reset module 19, and the voltage regulation signal line 4 includes a first anode reset signal line Ref2_1. The first anode reset module 19 is electrically connected to the fifth scanning signal line S5, the first anode reset signal line Ref2_1 and the anode of the light emitting element D respectively.

[0128] The pixel circuit 2 further includes a data writing module 7, a threshold compensation module 8, a first light emitting control module 17 and a storage capacitor Cst. The data writing module 7 is electrically connected between the data line Data and the first electrode of the driving transistor M0, the threshold compensation module 8 is electrically connected between the second electrode of the driving transistor M0 and the gate of the driving transistor M0, the first light emitting control module 17 is electrically connected between the first electrode of the driving transistor M0 and the anode of the light emitting element D, and the storage capacitor Cst is electrically connected between the gate of the driving transistor M0 and the anode of the light emitting element D.

[0129] When the pixel circuit 2 performs data refresh at the first frequency, the driving cycle of the pixel circuit 2 includes a high-frequency writing period WF_H, and when the pixel circuit 2 performs data refresh at the second frequency, the driving cycle of the pixel circuit 2 includes a low-frequency writing period WF_L. The high-frequency writing period WF_H and the low-frequency writing period WF_L respectively include a reset sub-period t1', a charging sub-period t2', a modulation sub-period t3', and a light-emitting sub-period t4'.

[0130] In the reset sub-period t1', the first anode reset module 19 writes the voltage provided by the first anode reset signal line Ref2_1 into the anode of the light-emitting element D; in the charging sub-period t2', the data writing module 7 writes the data voltage provided by the data line Data into the first electrode of the driving transistor M0, the threshold compensation module 8 writes the data voltage into the gate of the driving transistor M0, and performs threshold compensation on the driving transistor M0; in the modulation sub-period t3', the data writing module 7 writes the data voltage provided by the data line Data into the first electrode of the driving transistor M0, and the first light-emitting control module 17 writes the data voltage of the first electrode of the driving transistor M0 into the anode of the light-emitting element D.

[0131] When the pixel circuit 2 refreshes data at a first frequency, the fifth scanning signal line S5 is scanned at the first frequency, and the first anode reset signal line Ref2_1 provides a first anode reset voltage; when the pixel circuit 2 refreshes data at a second frequency, the fifth scanning signal line S5 is scanned at a second frequency, and the first anode reset signal line Ref2_1 provides a second anode reset voltage, wherein the first anode reset voltage is greater than the second anode reset voltage.

[0132] Taking the driving transistor M0 as an n-type transistor as an example, in the reset sub-period t1', the first anode reset module 19 writes the voltage provided by the first anode reset signal line Ref2_1 into the anode of the light-emitting element D. At this time, the anode potential of the light-emitting element D is the anode reset voltage V ref2 .

[0133] In the charging sub-period t2', the data writing module 7 writes the data voltage V provided by the data line Data to the Data The threshold compensation module 8 writes the data voltage V Data Further write into the gate of the driving transistor M0, and perform threshold compensation on the driving transistor M0. At this time, the gate potential of the driving transistor M0 is V Data +V th .

[0134] In the modulation sub-period t3', the data writing module 7 writes the data voltage V provided by the data line Data to the Data The first light control module 17 writes the data voltage of the first electrode of the driving transistor M0 into the anode of the light emitting element D. At this time, the anode potential of the light emitting element D is V ref2 Jump to V Data , the voltage difference changes to V Data -V ref2 Based on the characteristic of the storage capacitor Cst that the voltage difference between the two ends is maintained unchanged, the potential of the plate in the storage capacitor Cst that is electrically connected to the anode of the light-emitting element D changes to V Data -Vref2 After the change of V, the potential of the plate in the storage capacitor Cst electrically connected to the gate of the driving transistor M0 will also change accordingly. Data -V ref2 changes, so that the gate potential of the driving transistor M0 becomes 2V Data +V th -V ref2 At this time, the gate-source voltage V gs2 =2V Data +V th -V ref2 -V Data =V Data +V th -V ref2 .

[0135] in, Fig.15 The complete working process of the illustrated pixel circuit 2 will be described in detail later.

[0136] Assume the first anode reset voltage is V ref2_1 , the second anode reset voltage is V ref2_1 '. In the high-frequency writing period WF_H under high-frequency driving, before emitting light, the gate-source voltage V gs2 =V Data +V th -V ref2_1 , in the low-frequency writing period WF_L under low-frequency driving, before emitting light, the gate-source voltage V gs2 '=V Data +V th -V ref2 _1'.

[0137] Since V ref2 _1>V ref2 _1', so V gs2 <V gs2 ', indicating V gs2 The degree of positive bias is small, that is, the bias state of the driving transistor M0 in the high-frequency writing period WF_H is weaker than the bias state of the driving transistor M0 in the low-frequency writing period WF_L. At this time, in the high-frequency writing period WF_H, the threshold voltage V th The positive offset is low, making the threshold voltage V th The gate-source voltage of the driving transistor M0 is smaller than the threshold voltage V th , the driving current converted by the driving transistor M0 can be increased, that is, the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H can be increased.

[0138] After increasing the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H, the brightness difference between the high-frequency writing period WF_H and the holding period HF can be effectively reduced, thereby effectively weakening the screen flickering phenomenon when the display panel 100 performs low-high frequency switching, and effectively weakening the brightness difference between different partitions when the display panel 100 performs partition frequency control, thereby effectively improving display uniformity.

[0139] Furthermore, if Fig.17 As shown, Fig.17 This is another top view of the display device provided by the embodiment of the present invention. The display device further includes a second driving module 300 . The second driving module 300 includes an anode reset driving submodule 305 .

[0140] The anode reset driving submodule 305 is used for: when the display panel 100 displays a picture, controlling the pixel circuit 2 of the first partition 5 in the display area 1 to refresh data at a first frequency, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the first partition 5 to scan at the first frequency, and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the first partition 5 to provide a first anode reset voltage; and controlling the pixel circuit 2 of the second partition 6 in the display area 1 to refresh data at a second frequency, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the second partition 6 to scan at the second frequency, and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the second partition 6 to provide a second anode reset voltage.

[0141] Combined with the above analysis, the above setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5, thereby effectively weakening the overall display brightness difference between the first partition 5 and the second partition 6, improving the display uniformity of the display panel 100, and improving the split-screen phenomenon.

[0142] It should be noted that when the display panel 100 displays different images, the positions of the first partition 5 and the second partition 6 can be fixed. At this time, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the first partition 5 and the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to different shift registers, respectively, and driven separately by the shift registers. The first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the first partition 5 and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to different first anode reset buses, respectively, to receive voltages provided by different first anode reset buses.

[0143] When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 may not be fixed. At this time, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the first partition 5 and the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to the same shift register, and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the first partition 5 and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to the same first anode reset bus. At this time, it is only necessary to control the shift register to change the output signal frequency and control the first anode reset bus to change the output voltage when driving different partitions.

[0144] In one possible implementation, see Fig.15 The first anode reset module 19 includes a first anode reset transistor M3, a gate of the first anode reset transistor M3 is electrically connected to the fifth scanning signal line S5, a first electrode of the first anode reset transistor M3 is electrically connected to the first anode reset signal line Ref2_1, and a second electrode of the first anode reset transistor M3 is electrically connected to the anode of the light emitting element D.

[0145] The first anode reset transistor M3 is used to be turned on under the action of the enable level provided by the fifth scan signal line S5, and write the first anode reset voltage or the second anode reset voltage provided by the first anode reset signal line Ref2_1 into the anode of the light emitting element D to achieve resetting of the anode of the light emitting element D.

[0146] In a possible implementation, combining Figure 3 and Fig.18 , Fig.18 for Figure 3 Corresponding to another timing diagram, the pixel circuit 2 further includes a second anode reset module 20, and the second anode reset module 20 is electrically connected to the sixth scanning signal line S6, the second anode reset signal line Ref2_2 and the anode of the light emitting element D respectively.

[0147] When the pixel circuit 2 performs data refresh at the first frequency, the sixth scanning signal line S6 performs scanning at the first frequency, and the second anode reset signal line Ref2_2 provides a third anode reset voltage; when the pixel circuit 2 performs data refresh at the second frequency, the sixth scanning signal line S6 performs scanning at the third frequency, and the second anode reset signal line Ref2_2 provides a fourth anode reset voltage. The third frequency is greater than the second frequency and less than or equal to the first frequency, and the fourth anode reset voltage is less than the third anode reset voltage.

[0148] When resetting the anode of the light-emitting element D, the second anode reset module 20 writes the anode reset voltage provided by the second anode reset signal line Ref2_2 into the anode of the light-emitting element D. Since the third frequency is greater than the second frequency, when the pixel circuit 2 performs data refresh at the second frequency, in at least part of the holding period HF, the second anode reset module 20 also performs a reset operation on the anode of the light-emitting element D. For example, the first frequency and the third frequency are 120 Hz, respectively, and the second frequency is 1 Hz. At this time, in the 119 holding periods HF under 1 Hz driving, the sixth scanning signal line S6 controls the second anode reset module 20 to reset the anode of the light-emitting element D.

[0149] Assume the third anode reset voltage is V ref2_2 , the fourth anode reset voltage is V ref2_2 In the embodiment of the present invention, by making V ref2_2 '<V ref2_2 , the initial voltage of the anode of the light-emitting element D after being reset in the holding period HF can be reduced. In this way, when the driving current converted by the driving transistor M0 is subsequently transmitted to the anode of the light-emitting element D, the anode potential needs to be charged from the lower initial voltage to the light-emitting voltage corresponding to the driving current. In this way, the charging speed of the anode of the light-emitting element D can be slowed down, so that the brightness of the light-emitting element D rises more slowly, thereby reducing the luminous brightness of the light-emitting element D in the holding period HF, and further reducing the brightness difference between the holding period HF and the high-frequency writing period WF_H, thereby further improving the screen flickering phenomenon or further improving the display uniformity.

[0150] Moreover, after reducing the brightness of the holding period HF, the brightness difference between the holding period HF and the low-frequency writing period WF_L can also be reduced. When the display panel 100 is driven at a low frequency, the flickering phenomenon generated when the low-frequency writing period WF_L enters the holding period HF can also be weakened.

[0151] In a feasible configuration, the third anode reset voltage is equal to the first gate reset voltage, and the fourth anode reset voltage is equal to the second gate reset voltage. At this time, the second anode reset module 20 and the gate reset module 15 in the pixel circuit 2 can be electrically connected to the same reset signal line, thereby reducing the number of reset signal lines required and optimizing the wiring design.

[0152] Alternatively, in another feasible setting, the third anode reset voltage is less than the first gate reset voltage, and the fourth anode reset voltage is less than the second gate reset voltage. With this setting, the reset voltage of the anode of the light-emitting element D is lower than the reset voltage of the gate of the driving transistor M0, so a lower voltage can be used to initialize the anode of the light-emitting element D, reducing the voltage difference between the anode and cathode of the light-emitting element D, and avoiding the phenomenon of the light-emitting element D secretly lighting up. The reset voltage of the gate of the driving transistor M0 is slightly higher, which can avoid pulling the gate potential of the driving transistor M0 to too low during reset. In this way, when the gate of the driving transistor M0 is subsequently charged, the data voltage can be written on the basis of a slightly higher potential, reducing the risk of insufficient charging.

[0153] Furthermore, if Fig.19 As shown, Fig.19 This is another top view of the display device provided by the embodiment of the present invention. The display device further includes a third driving module 400. The third driving module 400 may be a processor in a driving chip.

[0154] The third driving module 400 is used for: when the display panel 100 displays a picture, controlling the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency, the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the first partition 5 to scan at the first frequency, and the second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the first partition 5 to provide a third anode reset voltage; and controlling the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency, the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the second partition 6 to scan at a third frequency, and the second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the second partition 6 to provide a fourth anode reset voltage.

[0155] As mentioned above, since the embodiment of the present invention can reduce the brightness of the holding period HF, thereby further reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF, when the display panel 100 is partitioned and frequency-driven, the brightness difference between the high-frequency writing period WF_H and the holding period HF can be effectively reduced, thereby significantly improving the overall display brightness difference between the first partition 5 and the second partition 6, and effectively improving the display uniformity of the display panel 100.

[0156] It should be noted that when the display panel 100 displays different images, the positions of the first partition 5 and the second partition 6 can be fixed. At this time, the sixth scan signal line S6 electrically connected to the pixel circuit 2 in the first partition 5 and the sixth scan signal line S6 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to different shift registers, respectively, and driven separately by the shift registers. The second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the first partition 5 and the second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to different second anode reset buses, respectively, to receive voltages provided by different second anode reset buses.

[0157] When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 may not be fixed. At this time, the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the first partition 5 and the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the second partition 6 can be electrically connected to the same shift register, and the second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the first partition 5 and the second anode reset signal line Ref2_2 electrically connected to the pixel circuit 2 in the second partition 6 can also be electrically connected to the same second anode reset bus. At this time, it is only necessary to control the shift register to change the output signal frequency and control the second anode reset bus to change the output voltage when driving different partitions.

[0158] In a possible implementation manner, the third frequency is equal to the first frequency.

[0159] When the third frequency is equal to the first frequency, in each holding period HF of the low frequency drive, the sixth scanning signal line S6 drives the second anode reset module 20 to use the fourth anode reset voltage V ref2_2 'Reset the anode of the light-emitting element D and pull its initial voltage to a lower level, thereby slowing down the charging speed of the light-emitting element D in each holding period HF, reducing the luminous brightness of each holding period HF, and further improving the screen flickering phenomenon or display uniformity.

[0160] In addition, the anode of the light-emitting element D is initialized before emitting light in each holding period HF, and the consistency of the anode potential of the light-emitting element D before emitting light can be improved in each holding period HF. Then, when the anode of the light-emitting element D is charged, the charging uniformity in different holding periods HF can be guaranteed, thereby improving the light emission uniformity between different holding periods HF.

[0161] In a possible implementation, combining Figure 3 and Fig.18The pixel circuit 2 further includes a data writing module 7, which is electrically connected to the third scanning signal line S3, the data line Data and the first electrode of the driving transistor M0 respectively, wherein the third scanning signal line S3 is multiplexed with the sixth scanning signal line S6.

[0162] When the pixel circuit 2 performs data refresh at the second frequency, the driving cycle of the pixel circuit 2 includes a low-frequency writing period WF_L and a holding period HF, and the data line Data is used to provide a data voltage in the low-frequency writing period WF_L and a bias voltage in the holding period HF.

[0163] In this configuration, the third scanning signal line S3 and the sixth scanning signal line S6 are multiplexed, that is, the third scanning signal is also scanned at the third frequency, at which time the number of scanning signal lines required to be set in the pixel circuit 2 can be reduced, thereby optimizing the wiring. Moreover, in at least part of the holding period HF, when the third scanning signal line S3 provides an enable level to control the second anode reset module 20 to reset the anode of the light-emitting element D, the data writing module 7 will also be turned on in response to the enable level provided by the third scanning signal line S3. At this time, by making the data line Data provide a bias voltage in the holding period HF, the bias state of the driving transistor M0 can be adjusted by the bias voltage to reduce the driving current converted by the driving transistor M0 in the holding period HF, thereby further reducing the brightness of the holding period HF and weakening the brightness difference between the holding period HF and the high-frequency writing period WF_H.

[0164] In a feasible embodiment, the second anode reset module 20 includes a second anode reset transistor M4, the gate of the second anode reset transistor M4 is electrically connected to the sixth scanning signal line S6, the first electrode of the second anode reset transistor M4 is electrically connected to the second anode reset signal line Ref2_2, and the second electrode of the second anode reset transistor M4 is electrically connected to the anode of the light-emitting element D.

[0165] The second anode reset transistor M4 is turned on under the action of the enable level provided by the sixth scan signal line S6, and writes the third anode reset voltage or the fourth anode reset voltage provided by the second anode reset signal line Ref2_2 into the anode of the light emitting element D to reset the anode of the light emitting element D.

[0166] The embodiments of the present invention are as follows Figure 3 , Fig.10 , Fig.12 and Fig.15 Taking the four circuit structures of the pixel circuit 2 as examples, the working process of the pixel circuit 2 is described in detail.

[0167] The first circuit structure:

[0168] See also Figure 3The pixel circuit 2 includes a driving transistor M0, a voltage regulating module 3, a second anode reset module 20, a data writing module 7, a threshold compensation module 8, a first light-emitting control module 17, a second light-emitting control module 18 and a storage capacitor Cst, wherein the voltage regulating module 3 includes a gate reset module 15.

[0169] The gate reset module 15 includes a gate reset transistor M1, a gate of the gate reset transistor M1 is electrically connected to the first scanning signal line S1, a first electrode of the gate reset transistor M1 is electrically connected to the gate reset signal line Ref1, and a second electrode of the gate reset transistor M1 is electrically connected to the gate of the driving transistor M0.

[0170] The second anode reset module 20 includes a second anode reset transistor M4, a gate of which is electrically connected to the sixth scan signal line S6, a first electrode of which is electrically connected to the second anode reset signal line Ref2_2, and a second electrode of which is electrically connected to the anode of the light emitting element D.

[0171] The data writing module 7 includes a data writing transistor M5, a gate of which is electrically connected to the third scanning signal line S3, a first electrode of which is electrically connected to the data line Data, and a second electrode of which is electrically connected to the first electrode of the driving transistor M0.

[0172] The threshold compensation module 8 includes a threshold compensation transistor M6, a gate of which is electrically connected to the fourth scanning signal line S4, a first electrode of which is electrically connected to the second electrode of the driving transistor M0, and a second electrode of which is electrically connected to the gate of the driving transistor M0.

[0173] The first light control module 17 includes a first light control transistor M7, a gate of the first light control transistor M7 is electrically connected to the first light control signal line EM1, a first electrode of the first light control transistor M7 is electrically connected to the second electrode of the driving transistor M0, and a second electrode of the first light control transistor M7 is electrically connected to the anode of the light emitting element D.

[0174] The second light emitting control module 18 includes a second light emitting control transistor M8, a gate of the second light emitting control transistor M8 is electrically connected to the second light emitting control signal line EM2, a first electrode of the second light emitting control transistor M8 is electrically connected to the power signal line PVDD, and a second electrode of the second light emitting control transistor M8 is electrically connected to the first electrode of the driving transistor M0.

[0175] A first plate of the storage capacitor Cst is electrically connected to the power signal line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M0 .

[0176] Among them, in order to reduce the influence of leakage current on the gate potential of the driving transistor M0, the gate reset transistor M1 and the threshold compensation transistor M6 can be n-type indium gallium zinc oxide (IGZO) transistors, and the driving transistor M0, the data writing transistor M5, the second anode reset transistor M4, the first light emission control transistor M7 and the second light emission control transistor M8 can be p-type low temperature polysilicon (LTPS) transistors.

[0177] Based on the above circuit structure, combined with Figure 8 In the illustrated timing, the high-frequency writing period WF_H and the low-frequency writing period WF_L include a reset sub-period t1 , a charging sub-period t2 , and a light-emitting sub-period t3 , respectively.

[0178] In the reset sub-period t1, the first scanning signal line S1 provides a high level, and the gate reset transistor M1 converts the first gate reset voltage V provided by the gate reset signal line Ref1 into a high level. ref1 Or the second gate reset voltage V ref1 'Write to the gate of the driving transistor M0 to reset the gate of the driving transistor M0. At this time, the gate voltage of the driving transistor M0 is V g1 , V g1 =V ref1 or V g1 =V ref1 '.

[0179] In the charging sub-period t2, the third scan signal line S3 provides a low level, the fourth scan signal line S4 provides a high level, and the sixth scan signal line S6 provides a low level. The data write transistor M5 converts the data voltage V provided by the data line Data into Data The first electrode of the write drive transistor M0 is used to write the data voltage V Data Write to the gate of the driving transistor M0 and perform threshold compensation on the driving transistor M0. At this time, the gate voltage of the driving transistor M0 is V g2 , V g1 =V Data +V th At the same time, the second anode reset module 20 converts the third anode reset voltage V provided by the second anode reset signal line Ref2_2 into ref2_1 Or the fourth anode reset voltage V ref2_1 'Write to the anode of the light emitting element D to reset the anode of the light emitting element D. At this time, the anode voltage of the light emitting element D is V o , V o =V ref2_1 or V o =Vref2_1 '.

[0180] In the light-emitting sub-period t3, the first light-emitting control signal line EM1 provides a low level, the second light-emitting control signal line EM2 provides a low level, and the second light-emitting control transistor M8 converts the power supply voltage V provided by the power supply signal line PVDD into PVDD Write the first electrode of the driving transistor M0, the first light emitting control transistor M7 drives the driving transistor M0 according to the power supply voltage V PVDD and data voltage V Data The converted driving current is transmitted to the anode of the light emitting element D, driving the light emitting element D to emit light.

[0181] Based on the above structure, in the embodiment of the present invention, when the pixel circuit 2 performs data refresh at the first frequency, the first gate reset voltage V provided by the gate reset signal line Ref1 is ref1 , can be greater than the second gate reset voltage V provided by the gate reset signal line Ref1 when the pixel circuit 2 performs data refresh at the second frequency ref1 ', to improve the brightness of the high-frequency writing period WF_H; and / or, the fourth anode reset voltage V provided by the second anode reset signal line Ref2_2 when the pixel circuit 2 performs data refresh at the second frequency ref2_1 ', which may be less than the third anode reset voltage V provided by the second anode reset signal line Ref2_2 when the pixel circuit 2 performs data refresh at the first frequency. ref2_1 , to reduce the brightness of HF during the holding period.

[0182] The second circuit structure:

[0183] Compared to Figure 3 The first circuit structure shown in Fig.10 In the second circuit structure shown, the voltage regulating module 3 in the pixel circuit 2 further includes a regulating module 16, which includes a regulating transistor M2, a gate of which is electrically connected to the second scanning signal line S2, a first electrode of which is electrically connected to the bias signal line DVH, and a second electrode of which is electrically connected to the first electrode of the driving transistor M0. Furthermore, the regulating transistor M2 may be a p-type LTPS transistor.

[0184] Based on the above circuit structure, combined with Fig.11 In the timing sequence shown, the high-frequency writing period WF_H and the low-frequency writing period WF_L respectively include a reset sub-period t1, a charging sub-period t2, a bias regulation sub-period t4 and a light emission sub-period t3, and the holding period HF includes a bias regulation sub-period t4 and a light emission sub-period t3. Among them, the working principle of the pixel circuit 2 in the reset sub-period t1, the charging sub-period t2 and the light emission sub-period t3 is the same as the working principle corresponding to the above circuit structure, which will not be repeated here.

[0185] In the bias regulation sub-period t4, the second scan signal line S2 provides a low level, and the regulation transistor M2 converts the first bias voltage V provided by the bias signal line DVH to DVH Or the second bias voltage V DVH ' is written into the first electrode of the driving transistor M0 to achieve regulation of the bias state of the driving transistor M0.

[0186] Based on the above structure, in the embodiment of the present invention, when the pixel circuit 2 performs data refresh at the first frequency, the first gate reset voltage V provided by the gate reset signal line Ref1 is ref1 , can be greater than the second gate reset voltage V provided by the gate reset signal line Ref1 when the pixel circuit 2 performs data refresh at the second frequency ref1 ', to improve the brightness of the high-frequency writing period WF_H; and / or, the second bias voltage V provided by the bias signal line DVH when the pixel circuit 2 performs data refresh at a second frequency DVH ', which may be greater than the first bias voltage V provided by the bias signal line DVH when the pixel circuit 2 performs data refresh at the first frequency. DVH , to reduce the brightness of the holding period HF; and / or, the fourth anode reset voltage V provided by the second anode reset signal line Ref2_2 when the pixel circuit 2 performs data refresh at the second frequency ref2_1 ', which may be less than the third anode reset voltage V provided by the second anode reset signal line Ref2_2 when the pixel circuit 2 performs data refresh at the first frequency. ref2_1 , to reduce the brightness of HF during the holding period.

[0187] It should be noted that in Figure 3 The first circuit structure shown in FIG. Fig.10 In the second circuit structure shown, the third scan signal line S3 and the sixth scan signal line S6 can be multiplexed, that is, the third scan signal line S3 and the sixth scan signal line S6 provide the same signal; the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 can be multiplexed, that is, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 provide the same signal.

[0188] The third circuit structure:

[0189] See also Fig.15 The pixel circuit 2 includes a driving transistor M0, a voltage regulating module 3, a data writing module 7, a threshold compensation module 8, a first light emitting control module 17, a second light emitting control module 18 and a storage capacitor Cst, wherein the voltage regulating module 3 includes a first anode reset module 19.

[0190] Among them, the first anode reset module 19 includes a first anode reset transistor M3, the gate of the first anode reset transistor M3 is electrically connected to the fifth scanning signal line S5, the first electrode of the first anode reset transistor M3 is electrically connected to the first anode reset signal line Ref2_1, and the second electrode of the first anode reset transistor M3 is electrically connected to the anode of the light-emitting element D.

[0191] The data writing module 7 includes a data writing transistor M5, a gate of which is electrically connected to the third scanning signal line S3, a first electrode of which is electrically connected to the data line Data, and a second electrode of which is electrically connected to the first electrode of the driving transistor M0.

[0192] The threshold compensation module 8 includes a threshold compensation transistor M6, a gate of which is electrically connected to the fourth scanning signal line S4, a first electrode of which is electrically connected to the second electrode of the driving transistor M0, and a second electrode of which is electrically connected to the gate of the driving transistor M0.

[0193] The first light emitting control module 17 includes a first light emitting control transistor M7, a gate of the first light emitting control transistor M7 is electrically connected to the first light emitting control signal line EM1, a first electrode of the first light emitting control transistor M7 is electrically connected to the first electrode of the driving transistor M0, and a second electrode of the first light emitting control transistor M7 is electrically connected to the anode of the light emitting element D.

[0194] The second light emitting control module 18 includes a first light emitting control transistor M7, a gate of the second light emitting control transistor M8 electrically connected to the second light emitting control signal line EM2, a first electrode of the second light emitting control transistor M8 electrically connected to the power signal line PVDD, and a second electrode of the second light emitting control transistor M8 electrically connected to the second electrode of the driving transistor M0.

[0195] The first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M0 , and the second plate of the storage capacitor Cst is electrically connected to the anode of the light emitting element D.

[0196] The driving transistor M0 , the first anode reset transistor M3 , the data writing transistor M5 , the first light emission control transistor M7 and the second light emission control transistor M8 may all be n-type IGZO transistors.

[0197] Based on the above circuit structure, combined with Fig.16 In the illustrated timing, the high-frequency writing period WF_H and the low-frequency writing period WF_L respectively include a reset sub-period t1 ′, a charging sub-period t2 ′, a modulation sub-period t3 ′ and a light-emitting sub-period t4 ′.

[0198] In the reset sub-period t1', the fourth scan signal line S4 provides a high level, the fifth scan signal line S5 provides a high level, and the second light-emitting control signal line EM2 provides a high level. The second light-emitting control transistor M8 converts the power supply voltage V provided by the power supply signal line PVDD into PVDD Write the first electrode of the driving transistor M0, the threshold compensation transistor M6 converts the power supply voltage V PVDD Further write into the gate of the driving transistor M0 to achieve the resetting of the gate of the driving transistor M0. At this time, the gate voltage of the driving transistor M0 is V g1 , V g1 =V PVDD At the same time, the first anode reset transistor M3 changes the first anode reset voltage provided by the first anode reset signal line Ref2_1 to V ref2_1 Or the second anode reset voltage is V ref2_1 'Write to the anode of the light emitting element D. At this time, the anode voltage of the light emitting element D is V o , V o =V ref2_1 , or V o =V ref2_1 '.

[0199] In the charging sub-period t2', the third scanning signal line S3 provides a high level, the fourth scanning signal line S4 provides a high level, and the fifth scanning signal line S5 provides a high level. The data writing transistor M5 converts the data voltage V provided by the data line Data into Data The first electrode of the write drive transistor M0 is used to write the data voltage V Data Write to the gate of the driving transistor M0 and perform threshold compensation on the driving transistor M0. At this time, the gate voltage of the driving transistor M0 is V g2 , V g1 =V Data +V th At the same time, the first anode resetting module 19 continues to reset the anode of the light emitting element D.

[0200] In the modulation sub-period t3', the third scanning signal line S3 provides a high level, the first light emitting control signal line EM1 provides a high level, and the data writing transistor M5 converts the data voltage V provided by the data line Data into Data The first electrode of the drive transistor M0 is written, and the first light-emitting control transistor M7 converts the data voltage V Data Further write to the anode of the light-emitting element D, at this time, the anode potential of the light-emitting element D is V ref2_1 or V ref2_1 ' Jump to V Data , the voltage difference of the jump is V Data -V ref2_1 or V Data -Vref2_1 Based on the effect of the storage capacitor Cst, the gate potential of the driving transistor M0 will also change to V Data -V ref2_1 or V Data -V ref2_1 ' changes, at this time, the gate potential of the driving transistor M0 is V g2 , V g2 =2V Data +V th -V ref2_1 , or, V g2 =2V Data +Vth-V ref2_1 '.

[0201] In the light-emitting sub-period t4', the first light-emitting control signal line EM1 provides a high level, the second light-emitting control signal line EM2 provides a high level, and the second light-emitting control transistor M8 converts the power supply voltage V provided by the power supply signal line PVDD into PVDD Write the second electrode of the driving transistor M0, the first light emitting control transistor M7 drives the driving transistor M0 according to the power supply voltage V PVDD and data voltage V Data The converted driving current is transmitted to the anode of the light emitting element D, driving the light emitting element D to emit light.

[0202] Based on the above structure, in the embodiment of the present invention, when the pixel circuit 2 performs data refresh at the second frequency, the second anode reset voltage V provided by the first anode reset signal line Ref2_1 is ref2_1 ', which may be less than the first anode reset voltage V provided by the first anode reset signal line Ref2_1 when the pixel circuit 2 performs data refresh at the first frequency. ref2_1 , to reduce the brightness of HF during the holding period.

[0203] The fourth circuit structure:

[0204] Compared to Fig.15 The first circuit structure shown in Fig.12 In the fourth circuit structure shown, the voltage regulating module 3 in the pixel circuit 2 further includes a regulating module 16, which includes a regulating transistor M2, a gate of which is electrically connected to the second scanning signal line S2, a first electrode of which is electrically connected to the bias signal line DVH, and a second electrode of which is electrically connected to the first electrode of the driving transistor M0. Furthermore, the regulating transistor M2 may be an n-type IGZO transistor.

[0205] Based on the above circuit structure, combined with Fig.13In the timing shown, the high-frequency writing period WF_H and the low-frequency writing period WF_L respectively include a reset sub-period t1', a charging sub-period t2', a modulation sub-period t3', a bias regulation sub-period t5' and a light emission sub-period t4'. The holding period HF includes a bias regulation sub-period t5' and a light emission sub-period t4'. Among them, the working principle of the pixel circuit 2 in the reset sub-period t1', the charging sub-period t2', the modulation sub-period t3' and the light emission sub-period t4' is the same as the working principle corresponding to the above circuit structure, which will not be repeated here.

[0206] In the bias regulation sub-period t5', the first light emission control signal line EM1 provides a low level, the second scan signal line S2 provides a high level, and the regulation transistor M2 converts the first bias voltage V provided by the bias signal line DVH to DVH Or the second bias voltage V DVH ' is written into the first electrode of the driving transistor M0 to achieve regulation of the bias state of the driving transistor M0.

[0207] Based on the above structure, in the embodiment of the present invention, when the pixel circuit 2 performs data refresh at the second frequency, the second anode reset voltage V provided by the first anode reset signal line Ref2_1 is ref2_1 ', which may be less than the first anode reset voltage V provided by the first anode reset signal line Ref2_1 when the pixel circuit 2 performs data refresh at the first frequency. ref2_1 , to reduce the brightness of the holding period HF; and / or, the second bias voltage V provided by the bias signal line DVH when the pixel circuit 2 performs data refresh at a second frequency DVH ', which may be greater than the first bias voltage V provided by the bias signal line DVH when the pixel circuit 2 performs data refresh at the first frequency. DVH , to reduce the brightness of HF during the holding period.

[0208] It should be noted that in Fig.15 The third circuit structure shown and Fig.12 In the fourth circuit structure shown, the fourth scan signal line S4 and the fifth scan signal line S5 can be multiplexed, that is, the fourth scan signal line S4 and the fifth scan signal line S5 provide the same signal.

[0209] Based on the same inventive concept, the embodiment of the present invention further provides a driving method of the display panel 100. Figure 2 and Figure 3 The display panel 100 includes a display area 1, the display area 1 includes a plurality of pixel circuits 2, the pixel circuit 2 includes a driving transistor M0 and a voltage regulating module 3, wherein the voltage regulating module 3 is used to adjust the node voltage of the driving transistor M0 using the voltage provided by the voltage regulating signal line 4.

[0210] The data refresh frequency of the pixel circuit 2 includes a first frequency and a second frequency, and the first frequency is greater than the second frequency.

[0211] like Fig. 20 As shown, Fig. 20 A flow chart of a driving method provided by an embodiment of the present invention, the driving method comprising:

[0212] Step S1: When controlling the pixel circuit 2 to refresh data at a first frequency, the voltage adjustment signal line 4 is controlled to provide a first voltage.

[0213] Step S2: When controlling the pixel circuit 2 to perform data refresh at a second frequency, the voltage adjustment signal line 4 is controlled to provide a second voltage, wherein the first voltage is not equal to the second voltage.

[0214] Based on the technical solution provided by the embodiment of the present invention, the display panel 100 can adjust the node voltage of the driving transistor M0 in a specific period corresponding to different driving frequencies by differentially designing the voltage provided by the voltage adjustment signal line 4 under different driving frequencies, so that the driving transistor M0 is in a specific bias state. For example, by adjusting the first voltage or the second voltage, the bias state of the driving transistor M0 in the high-frequency writing period WF_H under high-frequency driving can be adjusted to increase the driving current converted by the driving transistor M0, or the bias state of the driving transistor M0 in the holding period HF under low-frequency driving can be adjusted to reduce the driving current converted by the driving transistor M0, thereby weakening the difference in luminous brightness of the light-emitting element D in the high-frequency writing period WF_H and the holding period HF.

[0215] Furthermore, when the display panel 100 needs to switch from low-frequency driving to high-frequency driving during display, the screen flickering phenomenon caused by the low-frequency driving holding period HF entering the high-frequency driving high-frequency writing period WF_H can be effectively weakened. Alternatively, when the display panel 100 needs to perform partitioned frequency control, the brightness difference between different partitions can be effectively weakened, thereby effectively improving the display uniformity, especially more suitable for display products with medium and large-sized split-screen displays.

[0216] In a possible implementation, combining Figure 2 , the display panel 100 has a first mode and a second mode.

[0217] When controlling the pixel circuit 2 to refresh data at a first frequency, the process of controlling the voltage adjustment signal line 4 to provide a first voltage includes: in a first mode, controlling the pixel circuit 2 in the display area 1 to refresh data at a first frequency, and controlling the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the display area 1 to provide a first voltage.

[0218] When controlling the pixel circuit 2 to refresh data at a second frequency, the process of controlling the voltage adjustment signal line 4 to provide a second voltage includes: in the second mode, controlling the pixel circuit 2 in the display area 1 to refresh data at a second frequency, and controlling the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the display area 1 to provide a second voltage.

[0219] When the display panel 100 has different display modes, the embodiment of the present invention can adjust the bias state of the driving transistor M0 in a specific period in different display modes to different degrees by differentially designing the voltage provided by the voltage adjustment signal line 4 in different display modes, thereby adjusting the size of the driving current that can be converted by the driving transistor M0 in different display modes. When the display panel 100 switches from the second mode to the first mode, the flickering phenomenon during screen switching (jumping from the holding period HF to the high-frequency writing period WF_H) can be effectively improved to optimize the display effect.

[0220] In a possible implementation, combining Figure 4 The process of controlling the voltage regulation signal line 4 to provide a first voltage when controlling the pixel circuit 2 to refresh data at a first frequency, and controlling the voltage regulation signal line 4 to provide a second voltage when controlling the pixel circuit 2 to refresh data at a second frequency includes: when the display panel 100 displays a picture, controlling the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency, and the voltage regulation signal line 4 electrically connected to the pixel circuit 2 in the first partition 5 provides a first voltage; and controlling the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency, and the voltage regulation signal line 4 electrically connected to the pixel circuit 2 in the second partition 6 provides a second voltage.

[0221] In this configuration, the display panel 100 can be driven in zones and frequencies, wherein the first zone 5 corresponds to a zone in the display area 1 that needs high-frequency driving, and the second zone 6 corresponds to a zone in the display area 1 that needs low-frequency driving.

[0222] The embodiment of the present invention can adjust the bias state of the driving transistor M0 in the first partition 5 and the second partition 6 in a specific period to different degrees by differentially designing the voltage provided by the voltage adjustment signal line 4 electrically connected to the pixel circuit 2 in the first partition 5 and the second partition 6, thereby adjusting the magnitude of the driving current that can be converted by the driving transistor M0 in the first partition 5 and the second partition 6. For example, the driving current converted by the driving transistor M0 in the first partition 5 can be increased to weaken the difference in the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5 and the holding period HF corresponding to the second partition 6, thereby significantly weakening the overall display brightness difference between the first partition 5 and the second partition 6 during the display process, effectively improving the display uniformity of the display panel 100 and improving the split screen phenomenon.

[0223] In a possible implementation, combining Figure 4 When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 are fixed. That is, no matter what picture the display panel 100 displays, the positions of the first partition 5 and the second partition 6 do not change. The first partition 5 is always driven at a high frequency, while the second partition 6 is always driven at a low frequency.

[0224] This setting is more suitable for display devices in which a local area is used to display a specific picture. For example, in a type of medium-to-large-sized display device, the top corner of the display device only needs to display time information such as a clock, so the local area at the top corner can be set as the second partition 6, and the other area can be set as the first partition 5. At this time, the second driving module 300 only needs to differentially control the refresh frequency of the pixel circuits 2 in the first partition 5 and the second partition 6 according to the fixed position information of the first partition 5 and the second partition 6, and differentially control the voltage provided by the voltage adjustment signal line 4 electrically connected to the pixel circuits 2 in the first partition 5 and the second partition 6.

[0225] Furthermore, combined with Figure 3 and Figure 4 The pixel circuit 2 also includes a data writing module 7 and a threshold compensation module 8, wherein the data writing module 7 is electrically connected to the third scanning signal line S3, the data line Data and the first electrode of the driving transistor M0, respectively, and the threshold compensation module 8 is electrically connected to the fourth scanning signal line S4, the second electrode of the driving transistor M0 and the gate of the driving transistor M0, respectively.

[0226] The display panel 100 also includes a first shift register 9 and a second shift register 10. The first shift register 9 is electrically connected to a fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the first partition 5. The second shift register 10 is electrically connected to a fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the second partition 6.

[0227] The process of controlling the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency and the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency includes: controlling the first shift register 9 to output a fourth scanning signal to the fourth scanning signal line S4 electrically connected thereto at the first frequency, and controlling the second shift register 10 to output a fourth scanning signal to the fourth scanning signal line S4 electrically connected thereto at the second frequency.

[0228] When the positions of the first partition 5 and the second partition 6 are fixed, the fourth scanning signal line S4 corresponding to the pixel circuit 2 in the first partition 5 and the fourth scanning signal line S4 corresponding to the pixel circuit 2 in the second partition 6 are driven separately by using two independent shift registers. When the display panel 100 displays the picture, the first shift register 9 and the second shift register 10 only need to work independently and output signals at different frequencies to control the data circuits in different partitions to refresh data at different frequencies. This driving method can control the driving frequencies of the two partitions separately, and the two do not interfere with each other, and the control is simple and more accurate.

[0229] In a possible implementation, combining Figure 7 When the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 are not fixed.

[0230] The driving method further includes: dividing the display area 1 into a first partition 5 and a second partition 6 according to the content to be displayed in different areas of the display panel 100 , and generating position information of the first partition 5 and the second partition 6 .

[0231] In the above-mentioned driving method, when the display panel 100 displays different pictures, the positions of the first partition 5 and the second partition 6 are set according to the specific content to be displayed in the picture to be displayed. At this time, the positions of the first partition 5 and the second partition 6 can be flexibly adjusted according to the different displayed pictures, and the position division of the first partition 5 and the second partition 6 is more flexible.

[0232] Furthermore, combined with Figure 3 and Figure 7 The pixel circuit 2 also includes a data writing module 7 and a threshold compensation module 8, wherein the data writing module 7 is electrically connected to the third scanning signal line S3, the data line Data and the first electrode of the driving transistor M0, respectively, and the threshold compensation module 8 is electrically connected to the fourth scanning signal line S4, the second electrode of the driving transistor M0 and the gate of the driving transistor M0, respectively.

[0233] The display panel 100 further includes a third shift register 13 , and the third shift register 13 is electrically connected to the fourth scan signal line S4 .

[0234] The process of controlling the pixel circuit 2 in the first partition 5 in the display area 1 to refresh data at a first frequency and controlling the pixel circuit 2 in the second partition 6 in the display area 1 to refresh data at a second frequency includes: when driving the first partition 5, controlling the third shift register 13 to output a fourth scanning signal to the fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the first partition 5 at the first frequency; when driving the second partition 6, controlling the third shift register 13 to output a fourth scanning signal to the fourth scanning signal line S4 electrically connected to the pixel circuit 2 in the second partition 6 at the second frequency.

[0235] In the above driving mode, the fourth scanning signal lines S4 in the entire display area 1 are electrically connected to the same third shift register 13. The control unit 302 only needs to control the third shift register 13 to output signals to the fourth scanning signal lines S4 in different partitions at different frequencies according to the determined position information of the first partition 5 and the second partition 6, thereby controlling the pixel circuits 2 in different partitions to perform data refresh at different frequencies.

[0236] In a possible implementation, combining Figure 3 and Figure 8 The voltage regulating module 3 includes a gate reset module 15, the voltage regulating signal line 4 includes a gate reset signal line Ref1, and the gate reset module 15 is electrically connected to the first scanning signal line S1, the gate reset signal line Ref1 and the gate of the driving transistor M0 respectively.

[0237] When controlling the pixel circuit 2 to refresh data at a first frequency, the process of controlling the voltage adjustment signal line 4 to provide a first voltage includes: when controlling the pixel circuit 2 to refresh data at a first frequency, controlling the first scanning signal line S1 to scan at a first frequency, and controlling the gate reset signal line Ref1 to provide a first gate reset voltage.

[0238] When controlling the pixel circuit 2 to refresh data at a second frequency, the process of controlling the voltage adjustment signal line 4 to provide a second voltage includes: when controlling the pixel circuit 2 to refresh data at a second frequency, controlling the first scanning signal line S1 to scan at a second frequency, and controlling the gate reset signal line Ref1 to provide a second gate reset voltage; wherein the first gate reset voltage is greater than the second gate reset voltage.

[0239] Combined with the above analysis, the above setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H, thereby effectively reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF, and then when the display panel 100 performs low-high frequency switching, effectively weaken the screen flickering phenomenon, and when the display panel 100 performs partitioned frequency control, effectively weaken the brightness difference between different partitions, and effectively improve the display uniformity.

[0240] Furthermore, combined with Fig. 9 When the pixel circuit 2 is controlled to refresh data at a first frequency, the first scanning signal line S1 is controlled to scan at a first frequency, and the gate reset signal line Ref1 is controlled to provide a first gate reset voltage. When the pixel circuit 2 is controlled to refresh data at a second frequency, the first scanning signal line S1 is controlled to scan at a second frequency, and the gate reset signal line Ref1 is controlled to provide a second gate reset voltage. The process includes:

[0241] When the display panel 100 displays a picture, the pixel circuit 2 in the first partition 5 in the display area 1 is controlled to refresh data at a first frequency, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the first partition 5 is scanned at the first frequency, and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the first partition 5 provides a first gate reset voltage; and the pixel circuit 2 in the second partition 6 in the display area 1 is controlled to refresh data at a second frequency, the first scanning signal line S1 electrically connected to the pixel circuit 2 in the second partition 6 is scanned at a second frequency, and the gate reset signal line Ref1 electrically connected to the pixel circuit 2 in the second partition 6 provides a second gate reset voltage.

[0242] When the display panel 100 is driven in a partitioned and frequency-controlled manner, the above-mentioned setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5, thereby effectively weakening the overall display brightness difference between the first partition 5 and the second partition 6, improving the display uniformity of the display panel 100, and improving the split-screen phenomenon.

[0243] In a possible implementation, combining Figure 10 to Figure 13 The voltage regulating module 3 includes a regulating module 16, the voltage regulating signal line 4 includes a bias signal line DVH, and the regulating module 16 is electrically connected to the second scanning signal line S2, the bias signal line DVH and the first electrode of the driving transistor M0 respectively.

[0244] When controlling the pixel circuit 2 to refresh data at a first frequency, the process of controlling the voltage adjustment signal line 4 to provide a first voltage includes: when controlling the pixel circuit 2 to refresh data at a first frequency, controlling the second scanning signal line S2 to scan at the first frequency, and controlling the bias signal line DVH to provide a first bias voltage.

[0245] When controlling the pixel circuit 2 to refresh data at a second frequency, the process of controlling the voltage adjustment signal line 4 to provide a second voltage includes: when controlling the pixel circuit 2 to refresh data at a second frequency, controlling the second scanning signal line S2 to scan at a first frequency, and controlling the bias signal line DVH to provide a second bias voltage, wherein the second bias voltage is greater than the first bias voltage.

[0246] Combined with the above analysis, the above setting method can reduce the luminance of the light-emitting element D in the holding period HF, thereby further reducing the brightness difference between the holding period HF and the high-frequency writing period WF_H, so as to further improve the screen flicker phenomenon or further improve the display uniformity. Moreover, after reducing the brightness of the holding period HF, the brightness difference between the holding period HF and the low-frequency writing period WF_L can also be reduced. When the display panel 100 is driven at a low frequency, the flicker phenomenon generated when the low-frequency writing period WF_L enters the holding period HF can also be weakened.

[0247] Furthermore, combined with Fig.14 When the pixel circuit 2 is controlled to refresh data at the first frequency, the second scanning signal line S2 is controlled to scan at the first frequency, and the bias signal line DVH is controlled to provide a first bias voltage; when the pixel circuit 2 is controlled to refresh data at the second frequency, the second scanning signal line S2 is controlled to scan at the first frequency, and the bias signal line DVH is controlled to provide a second bias voltage. The process includes:

[0248] When the display panel 100 displays a picture, the pixel circuit 2 in the first partition 5 in the display area 1 is controlled to refresh data at a first frequency, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the first partition 5 is scanned at the first frequency, and the bias signal line DVH electrically connected to the pixel circuit 2 in the first partition 5 provides a first bias voltage; and the pixel circuit 2 in the second partition 6 in the display area 1 is controlled to refresh data at a second frequency, the second scanning signal line S2 electrically connected to the pixel circuit 2 in the second partition 6 is scanned at a second frequency, and the bias signal line DVH electrically connected to the pixel circuit 2 in the second partition 6 provides a second bias voltage.

[0249] When the display panel 100 is driven in partitioned and frequency-controlled manner, the above-mentioned setting method can reduce the brightness of the holding period HF, thereby further reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF. Therefore, the brightness difference between the high-frequency writing period WF_H and the holding period HF can be effectively reduced, thereby significantly improving the overall display brightness difference between the first partition 5 and the second partition 6, and effectively improving the display uniformity of the display panel 100.

[0250] In a possible implementation, combining Fig.15 and Fig.16 The voltage regulating module 3 includes a first anode reset module 19, the voltage regulating signal line 4 includes a first anode reset signal line Ref2_1, and the first anode reset module 19 is electrically connected to the fifth scanning signal line S5, the first anode reset signal line Ref2_1 and the anode of the light emitting element D respectively.

[0251] The pixel circuit 2 also includes a data writing module 7, a threshold compensation module 8, a first light emitting control module 17 and a storage capacitor Cst, wherein the data writing module 7 is electrically connected between the data line Data and the first electrode of the driving transistor M0, the threshold compensation module 8 is electrically connected between the second electrode of the driving transistor M0 and the gate of the driving transistor M0, the first light emitting control module 17 is electrically connected between the first electrode of the driving transistor M0 and the anode of the light emitting element D, and the storage capacitor Cst is electrically connected between the gate of the driving transistor M0 and the anode of the light emitting element D.

[0252] When the pixel circuit 2 refreshes data at a first frequency, the driving cycle of the pixel circuit 2 includes a high-frequency writing period WF_H. When the pixel circuit 2 refreshes data at a second frequency, the driving cycle of the pixel circuit 2 includes a low-frequency writing period WF_L. The high-frequency writing period WF_H and the low-frequency writing period WF_L respectively include a reset sub-period, a charging sub-period, a modulation sub-period and a light-emitting sub-period.

[0253] When the pixel circuit 2 performs data refresh at the first frequency or the second frequency, the driving method further includes: in the reset sub-period, the first anode reset module 19 writes the voltage provided by the first anode reset signal line Ref2_1 into the anode of the light-emitting element D; in the charging sub-period, the data writing module 7 writes the data voltage provided by the data line Data into the first electrode of the driving transistor M0, the threshold compensation module 8 writes the data voltage into the gate of the driving transistor M0, and performs threshold compensation on the driving transistor M0; in the modulation sub-period, the data writing module 7 writes the data voltage provided by the data line Data into the first electrode of the driving transistor M0, and the first light-emitting control module 17 writes the data voltage of the first electrode of the driving transistor M0 into the anode of the light-emitting element D.

[0254] When controlling the pixel circuit 2 to refresh data at a first frequency, the process of controlling the voltage adjustment signal line 4 to provide a first voltage includes: when controlling the pixel circuit 2 to refresh data at a first frequency, controlling the fifth scanning signal line S5 to scan at the first frequency, and controlling the first anode reset signal line Ref2_1 to provide a first anode reset voltage.

[0255] When controlling the pixel circuit 2 to refresh data at a second frequency, the process of controlling the voltage adjustment signal line 4 to provide a second voltage includes: when controlling the pixel circuit 2 to refresh data at a second frequency, controlling the fifth scanning signal line S5 to scan at a second frequency, and controlling the first anode reset signal line Ref2_1 to provide a second anode reset voltage, wherein the first anode reset voltage is greater than the second anode reset voltage.

[0256] Combined with the above analysis, the above setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H, thereby effectively reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF, and then when the display panel 100 performs low-high frequency switching, effectively weaken the screen flickering phenomenon, and when the display panel 100 performs partitioned frequency control, effectively weaken the brightness difference between different partitions, and effectively improve the display uniformity.

[0257] Further, when the pixel circuit 2 performs data refresh at the first frequency, the fifth scanning signal line S5 is controlled to scan at the first frequency, and the first anode reset signal line Ref2_1 is controlled to provide the first anode reset voltage; when the pixel circuit 2 performs data refresh at the second frequency, the fifth scanning signal line S5 is controlled to scan at the second frequency, and the first anode reset signal line Ref2_1 is controlled to provide the second anode reset voltage. The process includes:

[0258] When the display panel 100 displays a picture, the pixel circuit 2 in the first partition 5 in the display area 1 is controlled to refresh data at a first frequency, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the first partition 5 is scanned at the first frequency, and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the first partition 5 provides a first anode reset voltage; and the pixel circuit 2 in the second partition 6 in the display area 1 is controlled to refresh data at a second frequency, the fifth scanning signal line S5 electrically connected to the pixel circuit 2 in the second partition 6 is scanned at the second frequency, and the first anode reset signal line Ref2_1 electrically connected to the pixel circuit 2 in the second partition 6 provides a second anode reset voltage.

[0259] When the display panel 100 is driven in a partitioned and frequency-controlled manner, the above-mentioned setting method can improve the luminous brightness of the light-emitting element D in the high-frequency writing period WF_H corresponding to the first partition 5, thereby effectively weakening the overall display brightness difference between the first partition 5 and the second partition 6, improving the display uniformity of the display panel 100, and improving the split-screen phenomenon.

[0260] In a possible implementation, combining Figure 3 and Fig.18 The pixel circuit 2 further includes a second anode reset module 20, which is electrically connected to the sixth scan signal line S6, the second anode reset signal line Ref2_2 and the anode of the light emitting element D respectively.

[0261] When the pixel circuit 2 is controlled to perform data refresh at the first frequency, the driving method further includes: controlling the sixth scanning signal line S6 to perform scanning at the first frequency, and controlling the anode reset signal line to provide a first anode reset voltage.

[0262] When controlling the pixel circuit 2 to refresh data at a second frequency, the driving method also includes: controlling the sixth scanning signal line S6 to scan at a third frequency, and controlling the anode reset signal line to provide a second anode reset voltage; wherein the third frequency is greater than the second frequency and less than or equal to the first frequency, and the first anode reset voltage is greater than the second anode reset voltage.

[0263] Combined with the above analysis, the above-mentioned setting method can slow down the charging speed of the anode of the light-emitting element D in the holding period HF, so that the brightness of the light-emitting element D rises more slowly, thereby reducing the luminous brightness of the light-emitting element D in the holding period HF, and further reducing the brightness difference between the holding period HF and the high-frequency writing period WF_H, thereby further improving the screen flickering phenomenon or further improving the display uniformity.

[0264] Moreover, after reducing the brightness of the holding period HF, the brightness difference between the holding period HF and the low-frequency writing period WF_L can also be reduced. When the display panel 100 is driven at a low frequency, the flickering phenomenon generated when the low-frequency writing period WF_L enters the holding period HF can also be weakened.

[0265] Further, when the pixel circuit 2 is controlled to refresh data at the first frequency, the sixth scanning signal line S6 is controlled to scan at the first frequency, and the anode reset signal line is controlled to provide a first anode reset voltage; when the pixel circuit 2 is controlled to refresh data at the second frequency, the sixth scanning signal line S6 is controlled to scan at the third frequency, and the process of controlling the anode reset signal line to provide a second anode reset voltage also includes:

[0266] When the display panel 100 displays a picture, the pixel circuit 2 in the first partition 5 in the display area 1 is controlled to refresh data at a first frequency, the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the first partition 5 is scanned at the first frequency, and the anode reset signal line electrically connected to the pixel circuit 2 in the first partition 5 provides a first anode reset voltage; and the pixel circuit 2 in the second partition 6 in the display area 1 is controlled to refresh data at a second frequency, the sixth scanning signal line S6 electrically connected to the pixel circuit 2 in the second partition 6 is scanned at a third frequency, and the anode reset signal line electrically connected to the pixel circuit 2 in the second partition 6 provides a second anode reset voltage.

[0267] When the display panel 100 is driven in partitioned and frequency-controlled manner, the above-mentioned setting method can reduce the brightness of the holding period HF, thereby further reducing the brightness difference between the high-frequency writing period WF_H and the holding period HF. Therefore, the brightness difference between the high-frequency writing period WF_H and the holding period HF can be effectively reduced, thereby significantly improving the overall display brightness difference between the first partition 5 and the second partition 6, and effectively improving the display uniformity of the display panel 100.

[0268] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0269] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: A display panel is included, the display panel includes a display area, the display area includes a plurality of pixel circuits, the pixel circuit includes a driving transistor and a voltage regulating module, wherein the voltage regulating module is used to adjust the node voltage of the driving transistor using the voltage provided by the voltage regulating signal line; Wherein, the data refresh frequency of the pixel circuit includes a first frequency and a second frequency, and the first frequency is greater than the second frequency; When the pixel circuit performs data refresh at the first frequency, the voltage adjustment signal line provides a first voltage, and when the pixel circuit performs data refresh at the second frequency, the voltage adjustment signal line provides a second voltage, and the first voltage is not equal to the second voltage; in, When the pixel circuit performs data refresh at the first frequency, the data refresh cycle is a high-frequency writing period; during the high-frequency writing period, the pixel circuit at least performs a reset operation, a charging operation and a light-emitting operation in sequence; When the pixel circuit performs data refresh at the second frequency, the data refresh cycle includes at least one low-frequency writing period and multiple holding periods; during the low-frequency writing period, the pixel circuit at least performs a reset operation, a charging operation and a light-emitting operation in sequence; during the holding period, the pixel circuit does not perform a reset operation and a charging operation; When the pixel circuit refreshes data at the first frequency, the voltage adjustment signal line provides a first voltage for adjusting the bias state of the driving transistor within the high-frequency writing period to increase the driving current converted by the driving transistor; or, when the pixel circuit refreshes data at the second frequency, the voltage adjustment signal line provides a second voltage for adjusting the bias state of the driving transistor within the holding period to reduce the driving current converted by the driving transistor.

2. The display device according to claim 1, characterized in that The display panel has a first mode and a second mode; The display device further includes a first driving module, wherein the first driving module is configured to: In the first mode, the pixel circuit in the display area is controlled to perform data refresh at the first frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the display area is controlled to provide the first voltage; In the second mode, the pixel circuits in the display area are controlled to perform data refresh at the second frequency, and the voltage adjustment signal lines electrically connected to the pixel circuits in the display area are controlled to provide the second voltage.

3. The display device according to claim 1, characterized in that The display device further includes a second driving module, wherein the second driving module is configured to: When the display panel displays an image, the pixel circuit in the first partition of the display area is controlled to refresh data at the first frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the first partition provides the first voltage; and the pixel circuit in the second partition of the display area is controlled to refresh data at the second frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the second partition provides the second voltage.

4. The display device according to claim 3, characterized in that: When the display panel displays different pictures, positions of the first partition and the second partition are fixed.

5. The display device according to claim 4, characterized in that: The pixel circuit further includes a data writing module and a threshold compensation module, wherein the data writing module is electrically connected to the third scanning signal line, the data line and the first electrode of the driving transistor respectively, and the threshold compensation module is electrically connected to the fourth scanning signal line, the second electrode of the driving transistor and the gate of the driving transistor respectively; The display panel further includes a first shift register and a second shift register, the first shift register being electrically connected to the fourth scanning signal line electrically connected to the pixel circuit in the first partition, and the second shift register being electrically connected to the fourth scanning signal line electrically connected to the pixel circuit in the second partition; When the display panel displays different pictures, the second driving module is also used to: control the first shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to it at a first frequency, and control the second shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to it at a second frequency.

6. The display device according to claim 4, characterized in that: The display panel further includes a first voltage bus and a second voltage bus; Wherein, the first voltage bus is electrically connected to the voltage regulating signal line electrically connected to the pixel circuit in the first partition, and the first voltage bus is used to provide the first voltage; The second voltage bus is electrically connected to the voltage adjustment signal line electrically connected to the pixel circuit in the second partition, and the second voltage bus is used to provide the second voltage.

7. The display device according to claim 5, characterized in that: The first partition and the second partition are arranged along a first direction; Alternatively, the first partition surrounds the second partition, and the first partition and the second partition overlap in a second direction, wherein the second direction is an extending direction of the fourth scanning signal line, and the first direction intersects with the second direction.

8. The display device according to claim 3, characterized in that: When the display panel displays different pictures, the positions of the first partition and the second partition are not fixed; The second driving module includes a dividing unit and a control unit, wherein: The division unit is used to: divide the display area into the first partition and the second partition according to the content to be displayed in different areas of the to-be-displayed picture of the display panel, and generate position information of the first partition and the second partition; The control unit is electrically connected to the division unit, and is used to: control the pixel circuit in the first partition to refresh data at the first frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the first partition to provide the first voltage according to the position information of the first partition and the second partition generated by the division unit; and control the pixel circuit in the second partition to refresh data at the second frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the second partition to provide the second voltage.

9. The display device according to claim 8, characterized in that: The pixel circuit further includes a data writing module and a threshold compensation module, wherein the data writing module is electrically connected to the third scanning signal line, the data line and the first electrode of the driving transistor respectively, and the threshold compensation module is electrically connected to the fourth scanning signal line, the second electrode of the driving transistor and the gate of the driving transistor respectively; The display panel further includes a third shift register, and the third shift register is electrically connected to the fourth scan signal line; The control unit is also used to: when driving the first partition, control the third shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to the pixel circuit in the first partition at the first frequency; when driving the second partition, control the third shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to the pixel circuit in the second partition at the second frequency.

10. The display device according to claim 9, characterized in that: The third shift register is electrically connected to the clock signal line; The control unit is further used to: when driving the first partition, control the clock signal line to output a clock signal to the third shift register at the first frequency; when driving the second partition, control the clock signal line to output a clock signal to the third shift register at the second frequency.

11. The display device according to claim 8, characterized in that The display panel further comprises a third voltage bus, wherein the third voltage bus is electrically connected to the voltage adjustment signal line; The control unit is further configured to: control the third voltage bus to output the first voltage when driving the first partition, and control the third voltage bus to output the second voltage when driving the second partition.

12. The display device according to claim 1, characterized in that: The voltage regulating module includes a gate reset module, the voltage regulating signal line includes a gate reset signal line, and the gate reset module is electrically connected to the first scanning signal line, the gate reset signal line and the gate of the driving transistor respectively; When the pixel circuit performs data refresh at the first frequency, the first scanning signal line performs scanning at the first frequency, and the gate reset signal line provides a first gate reset voltage; When the pixel circuit performs data refresh at the second frequency, the first scanning signal line performs scanning at the second frequency, and the gate reset signal line provides a second gate reset voltage, wherein the first gate reset voltage is greater than the second gate reset voltage.

13. The display device according to claim 12, characterized in that: The display device further includes a second driving module, the second driving module includes a gate reset driving submodule, and the gate reset driving submodule is used to: When the display panel displays a picture, the pixel circuit in the first subarea in the display area is controlled to refresh data at the first frequency, the first scanning signal line electrically connected to the pixel circuit in the first subarea is scanned at the first frequency, and the gate reset signal line electrically connected to the pixel circuit in the first subarea provides the first gate reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the first scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the gate reset signal line electrically connected to the pixel circuit in the second partition provides the second gate reset voltage.

14. The display device according to claim 13, characterized in that: The display panel has a third mode and a fourth mode. In the third mode, , in the fourth mode, , n>m, f1 is the first frequency, f2 is the second frequency; The first gate reset voltage provided by the first scanning signal line electrically connected to the pixel circuit in the first partition in the third mode is greater than the first gate reset voltage provided in the fourth mode.

15. The display device according to claim 12, characterized in that: The gate reset module includes a gate reset transistor, a gate of the gate reset transistor is electrically connected to the first scanning signal line, a first electrode of the gate reset transistor is electrically connected to the gate reset signal line, and a second electrode of the gate reset transistor is electrically connected to the gate of the driving transistor.

16. The display device according to claim 1, characterized in that: The voltage regulating module includes a regulating module, the voltage regulating signal line includes a bias signal line, and the regulating module is electrically connected to the second scanning signal line, the bias signal line and the first electrode of the driving transistor respectively; When the pixel circuit performs data refresh at the first frequency, the second scanning signal line performs scanning at the first frequency, and the bias signal line provides a first bias voltage; When the pixel circuit performs data refresh at the second frequency, the second scanning signal line performs scanning at the second frequency, and the bias signal line provides a second bias voltage, wherein the second bias voltage is greater than the first bias voltage.

17. The display device according to claim 16, characterized in that: The display device further includes a second driving module, the second driving module includes a bias driving submodule, and the bias driving submodule is used to: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to refresh data at the first frequency, the second scanning signal lines electrically connected to the pixel circuits in the first partition are scanned at the first frequency, and the bias signal lines electrically connected to the pixel circuits in the first partition provide the first bias voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the second scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the bias signal line electrically connected to the pixel circuit in the second partition provides the second bias voltage.

18. The display device according to claim 16, characterized in that: The control module includes a control transistor, a gate of the control transistor is electrically connected to the second scanning signal line, a first electrode of the control transistor is electrically connected to the bias signal line, and a second electrode of the control transistor is electrically connected to the first electrode of the driving transistor.

19. The display device according to claim 1, characterized in that: The voltage regulating module includes a first anode reset module, the voltage regulating signal line includes a first anode reset signal line, and the first anode reset module is electrically connected to the fifth scanning signal line, the first anode reset signal line and the anode of the light emitting element respectively; The pixel circuit further includes a data writing module, a threshold compensation module, a first light emitting control module and a storage capacitor, wherein the data writing module is electrically connected between the data line and the first electrode of the driving transistor, the threshold compensation module is electrically connected between the second electrode of the driving transistor and the gate of the driving transistor, the first light emitting control module is electrically connected between the first electrode of the driving transistor and the anode of the light emitting element, and the storage capacitor is electrically connected between the gate of the driving transistor and the anode of the light emitting element; The high-frequency writing period and the low-frequency writing period respectively include a reset sub-period, a charging sub-period, a modulation sub-period and a light-emitting sub-period; In the reset sub-period, the first anode reset module writes the voltage provided by the first anode reset signal line into the anode of the light-emitting element; in the charging sub-period, the data writing module writes the data voltage provided by the data line into the first electrode of the driving transistor, and the threshold compensation module writes the data voltage into the gate of the driving transistor and performs threshold compensation on the driving transistor; in the modulation sub-period, the data writing module writes the data voltage provided by the data line into the first electrode of the driving transistor, and the first light-emitting control module writes the data voltage of the first electrode of the driving transistor into the anode of the light-emitting element; When the pixel circuit performs data refresh at the first frequency, the fifth scanning signal line performs scanning at the first frequency, and the first anode reset signal line provides a first anode reset voltage; When the pixel circuit performs data refresh at the second frequency, the fifth scanning signal line performs scanning at the second frequency, and the first anode reset signal line provides a second anode reset voltage, wherein the first anode reset voltage is greater than the second anode reset voltage.

20. The display device according to claim 19, characterized in that The display device further includes a second driving module, the second driving module includes an anode reset driving submodule, and the anode reset driving submodule is used to: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to refresh data at the first frequency, the fifth scanning signal line electrically connected to the pixel circuits in the first partition is scanned at the first frequency, and the first anode reset signal line electrically connected to the pixel circuits in the first partition provides the first anode reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the fifth scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the first anode reset signal line electrically connected to the pixel circuit in the second partition provides the second anode reset voltage.

21. The display device according to claim 19, characterized in that The first anode reset module includes a first anode reset transistor, a gate of the first anode reset transistor is electrically connected to the fifth scanning signal line, a first electrode of the first anode reset transistor is electrically connected to the first anode reset signal line, and a second electrode of the first anode reset transistor is electrically connected to the anode of the light-emitting element.

22. The display device according to claim 1, characterized in that The pixel circuit further comprises a second anode reset module, wherein the second anode reset module is electrically connected to the sixth scanning signal line, the second anode reset signal line and the anode of the light emitting element respectively; When the pixel circuit performs data refresh at the first frequency, the sixth scanning signal line performs scanning at the first frequency, and the second anode reset signal line provides a third anode reset voltage; When the pixel circuit refreshes data at the second frequency, the sixth scanning signal line is scanned at a third frequency, and the second anode reset signal line provides a fourth anode reset voltage, wherein the third frequency is greater than the second frequency and less than or equal to the first frequency, and the third anode reset voltage is greater than the fourth anode reset voltage.

23. The display device according to claim 22, characterized in that: The third frequency is equal to the first frequency.

24. The display device according to claim 22, characterized in that: The display device further includes a third driving module, and the third driving module is used for: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to perform data refresh at the first frequency, the sixth scanning signal line electrically connected to the pixel circuits in the first partition is scanned at the first frequency, and the second anode reset signal line electrically connected to the pixel circuits in the first partition provides the third anode reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the sixth scanning signal line electrically connected to the pixel circuit in the second partition to scan at the third frequency, and the second anode reset signal line electrically connected to the pixel circuit in the second partition to provide the fourth anode reset voltage.

25. The display device according to claim 22, characterized in that: The pixel circuit further includes a data writing module, the data writing module is electrically connected to the third scanning signal line, the data line and the first electrode of the driving transistor respectively, wherein the third scanning signal line is multiplexed with the sixth scanning signal line; When the pixel circuit performs data refresh at the second frequency, the driving cycle of the pixel circuit includes a low-frequency writing period and a holding period, and the data line is used to provide a data voltage in the low-frequency writing period and a bias voltage in the holding period.

26. The display device according to claim 22, characterized in that: The second anode reset module includes a second anode reset transistor, a gate of the second anode reset transistor is electrically connected to the sixth scanning signal line, a first electrode of the second anode reset transistor is electrically connected to the second anode reset signal line, and a second electrode of the second anode reset transistor is electrically connected to the anode of the light-emitting element.

27. A method for driving a display panel, characterized in that: The display panel includes a display area, the display area includes a plurality of pixel circuits, the pixel circuit includes a driving transistor and a voltage regulating module, wherein the voltage regulating module is used to adjust the node voltage of the driving transistor using the voltage provided by the voltage regulating signal line; Wherein, the data refresh frequency of the pixel circuit includes a first frequency and a second frequency, and the first frequency is greater than the second frequency; The driving method comprises: When controlling the pixel circuit to refresh data at the first frequency, controlling the voltage adjustment signal line to provide a first voltage; When controlling the pixel circuit to refresh data at the second frequency, controlling the voltage adjustment signal line to provide a second voltage, wherein the first voltage is not equal to the second voltage; in, When the pixel circuit is controlled to perform data refresh at the first frequency, the data refresh cycle is a high-frequency writing period; during the high-frequency writing period, the pixel circuit at least sequentially performs a reset operation, a charging operation, and a light-emitting operation; When the pixel circuit is controlled to perform data refresh at the second frequency, the data refresh cycle includes at least one low-frequency writing period and a plurality of holding periods; during the low-frequency writing period, the pixel circuit at least sequentially performs a reset operation, a charging operation and a light-emitting operation; during the holding period, the pixel circuit does not perform a reset operation and a charging operation; The driving method further includes: Control the voltage adjustment signal line to provide a first voltage for adjusting the bias state of the driving transistor in the high-frequency writing period to increase the driving current converted by the driving transistor; or control the voltage adjustment signal line to provide a second voltage for adjusting the bias state of the driving transistor in the holding period to reduce the driving current converted by the driving transistor.

28. The driving method according to claim 27, characterized in that: The display panel has a first mode and a second mode; When the pixel circuit is controlled to perform data refresh at the first frequency, the process of controlling the voltage adjustment signal line to provide the first voltage includes: in the first mode, controlling the pixel circuit in the display area to perform data refresh at the first frequency, and controlling the voltage adjustment signal line electrically connected to the pixel circuit in the display area to provide the first voltage; When controlling the pixel circuit to refresh data at the second frequency, the process of controlling the voltage adjustment signal line to provide the second voltage includes: in the second mode, controlling the pixel circuit in the display area to refresh data at the second frequency, and controlling the voltage adjustment signal line electrically connected to the pixel circuit in the display area to provide the second voltage.

29. The driving method according to claim 27, characterized in that: The process of controlling the voltage regulating signal line to provide a first voltage when the pixel circuit is controlled to perform data refresh at the first frequency, and controlling the voltage regulating signal line to provide a second voltage when the pixel circuit is controlled to perform data refresh at the second frequency includes: When the display panel displays an image, the pixel circuit in the first partition of the display area is controlled to refresh data at the first frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the first partition provides the first voltage; and the pixel circuit in the second partition of the display area is controlled to refresh data at the second frequency, and the voltage adjustment signal line electrically connected to the pixel circuit in the second partition provides the second voltage.

30. The driving method according to claim 29, characterized in that: When the display panel displays different pictures, positions of the first partition and the second partition are fixed.

31. The driving method according to claim 30, characterized in that: The pixel circuit further includes a data writing module and a threshold compensation module, wherein the data writing module is electrically connected to the third scanning signal line, the data line and the first electrode of the driving transistor respectively, and the threshold compensation module is electrically connected to the fourth scanning signal line, the second electrode of the driving transistor and the gate of the driving transistor respectively; The display panel further includes a first shift register and a second shift register, the first shift register being electrically connected to the fourth scanning signal line electrically connected to the pixel circuit in the first partition, and the second shift register being electrically connected to the fourth scanning signal line electrically connected to the pixel circuit in the second partition; The process of controlling the pixel circuit in the first partition of the display area to refresh data at the first frequency and the pixel circuit in the second partition of the display area to refresh data at the second frequency includes: controlling the first shift register to output a fourth scanning signal to a fourth scanning signal line electrically connected thereto at the first frequency, and controlling the second shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected thereto at the second frequency.

32. The driving method according to claim 29, characterized in that: When the display panel displays different pictures, the positions of the first partition and the second partition are not fixed; The driving method further includes: dividing the display area into the first partition and the second partition according to the content to be displayed in different areas of the to-be-displayed picture of the display panel, and generating position information of the first partition and the second partition.

33. The driving method according to claim 32, characterized in that: The pixel circuit further includes a data writing module and a threshold compensation module, wherein the data writing module is electrically connected to the third scanning signal line, the data line and the first electrode of the driving transistor respectively, and the threshold compensation module is electrically connected to the fourth scanning signal line, the second electrode of the driving transistor and the gate of the driving transistor respectively; The display panel further includes a third shift register, and the third shift register is electrically connected to the fourth scan signal line; The process of controlling the pixel circuit in the first partition of the display area to refresh data at the first frequency and controlling the pixel circuit in the second partition of the display area to refresh data at the second frequency includes: when driving the first partition, controlling the third shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to the pixel circuit in the first partition at the first frequency; when driving the second partition, controlling the third shift register to output a fourth scanning signal to the fourth scanning signal line electrically connected to the pixel circuit in the second partition at the second frequency.

34. The driving method according to claim 27, characterized in that: The voltage regulating module includes a gate reset module, the voltage regulating signal line includes a gate reset signal line, and the gate reset module is electrically connected to the first scanning signal line, the gate reset signal line and the gate of the driving transistor respectively; The process of controlling the voltage regulating signal line to provide the first voltage when the pixel circuit is controlled to refresh data at the first frequency includes: controlling the first scanning signal line to scan at the first frequency and controlling the gate reset signal line to provide the first gate reset voltage when the pixel circuit is controlled to refresh data at the first frequency; The process of controlling the voltage regulating signal line to provide the second voltage when the pixel circuit is controlled to refresh data at the second frequency includes: controlling the first scanning signal line to scan at the second frequency and controlling the gate reset signal line to provide a second gate reset voltage when the pixel circuit is controlled to refresh data at the second frequency; Wherein, the first gate reset voltage is greater than the second gate reset voltage.

35. The driving method according to claim 34, characterized in that: The process of controlling the first scanning signal line to scan at the first frequency and the gate reset signal line to provide a first gate reset voltage when the pixel circuit is controlled to refresh data at the first frequency, and controlling the first scanning signal line to scan at the second frequency and the gate reset signal line to provide a second gate reset voltage when the pixel circuit is controlled to refresh data at the second frequency includes: When the display panel displays a picture, the pixel circuit in the first subarea in the display area is controlled to refresh data at the first frequency, the first scanning signal line electrically connected to the pixel circuit in the first subarea is scanned at the first frequency, and the gate reset signal line electrically connected to the pixel circuit in the first subarea provides the first gate reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the first scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the gate reset signal line electrically connected to the pixel circuit in the second partition provides the second gate reset voltage.

36. The driving method according to claim 27, characterized in that: The voltage regulating module includes a regulating module, the voltage regulating signal line includes a bias signal line, and the regulating module is electrically connected to the second scanning signal line, the bias signal line and the first electrode of the driving transistor respectively; The process of controlling the voltage regulating signal line to provide the first voltage when the pixel circuit is controlled to refresh data at the first frequency includes: controlling the second scanning signal line to scan at the first frequency and controlling the bias signal line to provide the first bias voltage when the pixel circuit is controlled to refresh data at the first frequency; The process of controlling the voltage adjustment signal line to provide a second voltage when controlling the pixel circuit to refresh data at the second frequency includes: controlling the second scanning signal line to scan at the second frequency when controlling the pixel circuit to refresh data at the second frequency, and controlling the bias signal line to provide a second bias voltage, wherein the second bias voltage is greater than the first bias voltage.

37. The driving method according to claim 36, characterized in that: The process of controlling the second scanning signal line to scan at the first frequency when the pixel circuit is controlled to refresh data at the first frequency, controlling the bias signal line to provide a first bias voltage, and controlling the second scanning signal line to scan at the second frequency when the pixel circuit is controlled to refresh data at the second frequency, and controlling the bias signal line to provide a second bias voltage includes: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to refresh data at the first frequency, the second scanning signal lines electrically connected to the pixel circuits in the first partition are scanned at the first frequency, and the bias signal lines electrically connected to the pixel circuits in the first partition provide the first bias voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the second scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the bias signal line electrically connected to the pixel circuit in the second partition provides the second bias voltage.

38. The driving method according to claim 27, characterized in that: The voltage regulating module includes a first anode reset module, the voltage regulating signal line includes a first anode reset signal line, and the first anode reset module is electrically connected to the fifth scanning signal line, the first anode reset signal line and the anode of the light emitting element respectively; The pixel circuit further includes a data writing module, a threshold compensation module, a first light emitting control module and a storage capacitor, wherein the data writing module is electrically connected between the data line and the first electrode of the driving transistor, the threshold compensation module is electrically connected between the second electrode of the driving transistor and the gate of the driving transistor, the first light emitting control module is electrically connected between the first electrode of the driving transistor and the anode of the light emitting element, and the storage capacitor is electrically connected between the anode of the light emitting element and the gate of the driving transistor; The high-frequency writing period and the low-frequency writing period respectively include a reset sub-period, a charging sub-period, a modulation sub-period and a light-emitting sub-period; When the pixel circuit performs data refreshing at the first frequency or the second frequency, the driving method further includes: In the reset sub-period, the first anode reset module writes the voltage provided by the first anode reset signal line into the anode of the light-emitting element; in the charging sub-period, the data writing module writes the data voltage provided by the data line into the first electrode of the driving transistor, and the threshold compensation module writes the data voltage into the gate of the driving transistor and performs threshold compensation on the driving transistor; in the modulation sub-period, the data writing module writes the data voltage provided by the data line into the first electrode of the driving transistor, and the first light-emitting control module writes the data voltage of the first electrode of the driving transistor into the anode of the light-emitting element; The process of controlling the voltage regulating signal line to provide the first voltage when the pixel circuit is controlled to perform data refresh at the first frequency includes: controlling the fifth scanning signal line to scan at the first frequency and controlling the first anode reset signal line to provide the first anode reset voltage when the pixel circuit is controlled to perform data refresh at the first frequency; The process of controlling the voltage adjustment signal line to provide the second voltage when controlling the pixel circuit to refresh data at the second frequency includes: controlling the fifth scanning signal line to scan at the second frequency when controlling the pixel circuit to refresh data at the second frequency, and controlling the first anode reset signal line to provide a second anode reset voltage, wherein the first anode reset voltage is greater than the second anode reset voltage.

39. The driving method according to claim 38, characterized in that: The process of controlling the fifth scanning signal line to scan at the first frequency and controlling the first anode reset signal line to provide a first anode reset voltage when the pixel circuit performs data refresh at the first frequency, and controlling the fifth scanning signal line to scan at the second frequency and controlling the first anode reset signal line to provide a second anode reset voltage when the pixel circuit performs data refresh at the second frequency includes: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to refresh data at the first frequency, the fifth scanning signal line electrically connected to the pixel circuits in the first partition is scanned at the first frequency, and the first anode reset signal line electrically connected to the pixel circuits in the first partition provides the first anode reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the fifth scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the second frequency, and the first anode reset signal line electrically connected to the pixel circuit in the second partition provides the second anode reset voltage.

40. The driving method according to claim 27, characterized in that: The pixel circuit further comprises a second anode reset module, wherein the second anode reset module is electrically connected to the sixth scanning signal line, the second anode reset signal line and the anode of the light emitting element respectively; When controlling the pixel circuit to perform data refresh at the first frequency, the driving method further includes: controlling the sixth scanning signal line to scan at the first frequency, and controlling the anode reset signal line to provide a first anode reset voltage; When controlling the pixel circuit to perform data refresh at the second frequency, the driving method further includes: controlling the sixth scanning signal line to perform scanning at a third frequency, and controlling the anode reset signal line to provide a second anode reset voltage; The third frequency is greater than the second frequency and less than or equal to the first frequency, and the first anode reset voltage is greater than the second anode reset voltage.

41. The driving method according to claim 40, characterized in that: When the pixel circuit is controlled to perform data refresh at the first frequency, the sixth scanning signal line is controlled to scan at the first frequency, and the anode reset signal line is controlled to provide a first anode reset voltage; when the pixel circuit is controlled to perform data refresh at the second frequency, the sixth scanning signal line is controlled to scan at a third frequency, and the anode reset signal line is controlled to provide a second anode reset voltage. The process also includes: When the display panel displays a picture, the pixel circuits in the first partition in the display area are controlled to refresh data at the first frequency, the sixth scanning signal line electrically connected to the pixel circuits in the first partition is scanned at the first frequency, and the anode reset signal line electrically connected to the pixel circuits in the first partition provides the first anode reset voltage; And control the pixel circuit in the second partition of the display area to refresh data at the second frequency, the sixth scanning signal line electrically connected to the pixel circuit in the second partition is scanned at the third frequency, and the anode reset signal line electrically connected to the pixel circuit in the second partition provides the second anode reset voltage.

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