Display panel and display device

Abstract

The present invention discloses a display panel and a display device, belonging to the field of display technology, wherein the display panel includes a plurality of sub-pixels, two data lines are included between two adjacent sub-pixel columns, and a plurality of sub-pixels in the same sub-pixel column are connected to two data lines, which are respectively the first data line and the second data line; the sub-pixel includes a pixel circuit and a light-emitting element; the pixel circuit includes at least a driving transistor, a first data module and a second data module; the first end of the first data module is connected to the first data line, and the second end of the first data module is connected to the first electrode of the driving transistor; the first end of the second data module is connected to the second data line, and the second end of the second data module is connected to the first electrode of the driving transistor; the second electrode of the driving transistor is connected to the anode of the light-emitting element. The display device includes the above-mentioned display panel. The present invention can take into account both high-frequency driving mode and low-frequency driving mode, and can also improve the display quality under different driving modes.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED), as a current-type light-emitting device, is widely used in display devices such as mobile phones and tablet computers because of its many characteristics such as self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates.

[0003] OLED display panels will use different image refresh frequencies for display in different application scenarios. For example, in application scenarios that display dynamic images such as games and videos, the OLED display panel is in high-frequency mode. In this mode, the OLED display panel uses a higher image refresh frequency for display to ensure the smoothness of the displayed image; in application scenarios that display static images such as e-books, the OLED display panel is in low-frequency mode. In this mode, the OLED display panel uses a lower image refresh frequency to reduce the power consumption of the OLED display panel.

[0004] The pixel circuit used to control the light emission of the light-emitting device in the OLED display panel is the core technical content of the OLED display panel and has important research significance. However, in the OLED display panel in the prior art, the low leakage current of the metal oxide transistor such as indium gallium zinc oxide (IGZO) TFT itself is generally used to improve the problem of unstable gate voltage in the low-frequency driving mode. However, the pixel circuit structure of this design has the problem of insufficient charging time at high frequency, that is, the existing display panel design cannot take into account the display quality of the high-frequency driving mode and the display quality of the low-frequency driving mode.

[0005] Therefore, providing a display panel and a display device that can take into account both high-frequency driving mode and low-frequency driving mode while improving the display quality under different driving modes is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In view of this, the present invention provides a display panel and a display device to solve the problem that the display panel in the prior art cannot take into account both the display quality in a high-frequency driving mode and the display quality in a low-frequency driving mode.

[0007] The present invention discloses a display panel, comprising: a plurality of sub-pixels, a plurality of scan lines and a plurality of data lines, wherein the scan lines and the data lines are cross-insulated to define an area where the sub-pixels are located; a plurality of sub-pixels are arranged along a first direction to form sub-pixel rows, and a plurality of sub-pixel rows are arranged along a second direction; a plurality of sub-pixels are arranged along a second direction to form sub-pixel columns, and a plurality of sub-pixel columns are arranged along the first direction; wherein the first direction and the second direction intersect; two data lines are included between two adjacent sub-pixel columns, and a plurality of sub-pixels in the same sub-pixel column are connected to the two data lines, which are the first data line and the second data line respectively; the sub-pixels include an electrically connected pixel circuit and a light-emitting element; the pixel circuit at least includes a driving transistor, a first data module and a second data module; a first end of the first data module is connected to the first data line, and a second end of the first data module is connected to a first electrode of the driving transistor; a first end of the second data module is connected to the second data line, and a second end of the second data module is connected to the first electrode of the driving transistor; and the second electrode of the driving transistor is connected to an anode of the light-emitting element.

[0008] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-mentioned display panel.

[0009] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0010] The display panel of the present invention includes a plurality of sub-pixels, and the sub-pixels may include an electrically connected pixel circuit and a light-emitting element, and the pixel circuit is used to control the light-emitting element to emit light. In the display panel of the present invention, two data lines are included between two adjacent sub-pixel columns, and a plurality of sub-pixels in the same sub-pixel column are connected to the two data lines, and the two data lines electrically connected to the sub-pixels in the same sub-pixel column are named as the first data line and the second data line, respectively. The pixel circuit includes at least a driving transistor, a first data module and a second data module, and the first electrode of the driving transistor is connected to the first data line and the second data line through the first data module and the second data module, respectively. When the display panel is working, in the two data lines corresponding to the same sub-pixel column, the first data module can be used to write the data voltage signal provided by the first data line to the gate of the driving transistor, so that the driving transistor can generate a driving current for driving the light-emitting element according to the voltage of its gate and emit light in the light-emitting stage. The second data module writes the bias voltage signal provided by the second data line to the first electrode of the driving transistor, and controls the second data module to write the bias voltage signal to the first electrode of the driving transistor in the partial working stage of the pixel circuit to adjust the bias state of the driving transistor, improve the threshold drift problem of the driving transistor, and enhance the display effect. Furthermore, during the scanning drive process of the same sub-pixel, a data voltage signal can be written to the sub-pixel of the current sub-image row through the first data line, and the bias state of the driving transistor of the sub-pixel of the sub-image row can be adjusted through the second data module connected to the second data line, so that during the process of writing the data voltage signal to the sub-pixel of the current sub-image row through the first data line, sufficient charging time can be guaranteed, especially in the high-frequency driving mode with a high refresh frequency and a short row scanning time, the data writing of the sub-pixel can be guaranteed to have sufficient charging time, thereby enabling the data voltage signal to be written more fully, which is beneficial to improving the display quality of the display panel in the high-frequency driving mode.

[0011] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0012] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 yes Figure 1A schematic diagram of the electrical connection structure of a part of the neutron pixel column;

[0016] Figure 3 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 yes Figure 3 A schematic diagram of the electrical connection structure of a part of the neutron pixel column;

[0018] Figure 5 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0019] Figure 6 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0020] Figure 7 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0021] Figure 8 yes Figure 7 The driving timing diagram of the pixel circuit in FIG.

[0022] Fig. 9 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0023] Fig.10 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0024] Fig.11 yes Figure 3 A schematic diagram of another electrical connection structure of a partial area of ​​a neutron pixel column;

[0025] Fig.12 yes Fig.11 The driving timing diagram of the pixel circuit in FIG.

[0026] Fig.13 It is a schematic diagram of the planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0029] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0030] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0031] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0032] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 A schematic diagram of the electrical connection structure of a part of the sub-pixel column in FIG. 1 , wherein the display panel 000 provided in this embodiment comprises: a plurality of sub-pixels P, a plurality of scan lines G and a plurality of data lines S, wherein the scan lines G and the data lines S are cross-insulated and define the area where the sub-pixels P are located;

[0033] A plurality of sub-pixels P are arranged along a first direction X to form a sub-pixel row PH, and a plurality of sub-pixel rows PH are arranged along a second direction Y; a plurality of sub-pixels P are arranged along a second direction Y to form a sub-pixel column PL, and a plurality of sub-pixel columns PL are arranged along the first direction X; wherein the first direction X and the second direction Y intersect; optionally, in this embodiment, an example is given in which the first direction X and the second direction Y are perpendicular to each other in a direction parallel to the plane where the display panel 000 is located;

[0034] Two data lines S are included between two adjacent sub-pixel columns PL, and a plurality of sub-pixels P in the same sub-pixel column PL are connected to the two data lines S, which are respectively a first data line S1 and a second data line S2;

[0035] The sub-pixel P includes a pixel circuit 10 and a light emitting element 20 which are electrically connected;

[0036] The pixel circuit 10 at least includes a driving transistor DT, a first data module 101 and a second data module 102; the first end of the first data module 101 is connected to the first data line S1, and the second end of the first data module 101 is connected to the first electrode of the driving transistor DT; the first end of the second data module 102 is connected to the second data line S2, and the second end of the second data module 102 is connected to the first electrode of the driving transistor DT; the second electrode of the driving transistor DT is connected to the anode of the light-emitting element 20.

[0037] Specifically, the display panel 000 of the present embodiment may be an organic light emitting diode display panel, the display panel 000 includes a plurality of sub-pixels P, the scan lines G and the data lines S are cross-insulated to define the area where the sub-pixels P are located, and optionally, the sub-pixels P in the present embodiment may be arranged in an array, that is, a plurality of sub-pixels P are arranged along a first direction X to form a sub-pixel row PH, a plurality of sub-pixel rows PH are arranged along a second direction Y, a plurality of sub-pixels P are arranged along the second direction Y to form a sub-pixel column PL, and a plurality of sub-pixel columns PL are arranged along the first direction X to form an array of sub-pixel P structures. The scan lines G are generally connected to the scan drive circuit in the frame area to provide a scan drive signal for each sub-pixel P, and the data lines S are generally connected to the data drive circuit in the frame area to provide a data voltage signal for each sub-pixel P. Each sub-pixel P may include an electrically connected pixel circuit 10 and a light emitting element 20, and the pixel circuit 10 is used to control the light emitting element 20 to emit light. Since the light emitting element 20 in the organic light emitting diode display panel can generally be an organic light emitting diode, which is a current driven element, a corresponding pixel circuit 10 needs to be provided to provide a driving current for the light emitting element 20 so that the light emitting element 20 can emit light.

[0038] The pixel circuit in the prior art generally includes devices such as transistors and capacitors; wherein the transistor of the pixel circuit may include a driving transistor and a data writing transistor, and the data voltage signal provided by the data line is written to the gate of the driving transistor by the data writing transistor in the data writing stage, so that the driving transistor can generate a driving current for driving the light-emitting element according to the voltage of its gate and emit light in the light-emitting stage. However, due to the characteristics of the transistor itself, a small current (leakage current) will still pass through the transistor when it is turned off, so after the data writing stage is completed, the leakage current generated by the data writing transistor will still cause the gate voltage of the driving transistor to change, affecting the driving current generated by the driving transistor, thereby affecting the luminous brightness of the light-emitting element in the light-emitting stage, especially in the low-frequency driving mode. The leakage current will cause serious flickering problems. In the related art, the transistor connected to the gate of the driving transistor is generally set to have an active layer with an oxide semiconductor, and the low leakage characteristics of the metal oxide transistor are used to suppress the potential change of the gate of the driving transistor during the light-emitting process of the light-emitting element, and prevent the transistor connected to the gate of the driving transistor from leaking, which is conducive to reducing power consumption and realizing low-frequency display. However, in the structure of the pixel circuit including the metal oxide transistor, there is a problem of insufficient charging time in the high-frequency driving mode, that is, the display quality of the display panel in the prior art in the high-frequency driving mode is still not guaranteed.

[0039] In order to solve the above problem, in the present embodiment, the display panel 000 is provided, two data lines S are included between two adjacent sub-pixel columns PL, a plurality of sub-pixels P in the same sub-pixel column PL are connected to the two data lines S, and the two data lines S electrically connected to the sub-pixels P in the same sub-pixel column PL are named as the first data line S1 and the second data line S2 respectively. The pixel circuit 10 at least includes a driving transistor DT, a first data module 101 and a second data module 102, wherein a first end of the first data module 101 is connected to the first data line S1, and a second end of the first data module 101 is connected to a first electrode of the driving transistor DT; a first end of the second data module 102 is connected to the second data line S2, and a second end of the second data module 102 is connected to a first electrode of the driving transistor DT, and a second electrode of the driving transistor DT is connected to an anode of the light emitting element 20, that is, the first electrode of the driving transistor DT is connected to the first data line S1 and the second data line S2 through the first data module 101 and the second data module 102 respectively. When the display panel 000 is working, in the two data lines S corresponding to the same sub-pixel column PL, the first data module 101 can be used to write the data voltage signal provided by the first data line S1 into the gate of the driving transistor DT, so that the driving transistor DT can generate a driving current for driving the light-emitting element 20 to emit light according to the voltage of its gate during the light-emitting stage.

[0040] The second data module 102 of the present embodiment can be used to write the bias voltage signal provided by the second data line S2 to the first electrode of the driving transistor DT. In the prior art, in the driving cycle of the pixel circuit driving the light-emitting element to emit light, in the stage of driving the light-emitting element to emit light, the gate potential of the driving transistor is higher than the potential of the second electrode, and the driving transistor works in a forward bias state to provide a driving current to the light-emitting element. The forward bias state causes the driving transistor to produce a hysteresis effect. When working in a bias state for a long time, it will cause the ion polarization inside the driving transistor, and then form a built-in electric field inside the driving transistor, causing the threshold voltage of the driving transistor to increase continuously, the threshold voltage drifts, and the display brightness is unstable when the screen is switched, and the human eye can perceive the screen flickering. In addition, the threshold voltage drift caused by the hysteresis effect is at the nanosecond level, while the threshold compensation module in the conventional pixel circuit performs threshold compensation at the microsecond level or millisecond level. The threshold compensation module in the conventional pixel circuit cannot compensate for the threshold voltage drift caused by the hysteresis effect. Therefore, in this embodiment, the second data module 102 is set to write the bias voltage signal provided by the second data line S2 to the first electrode of the driving transistor DT. The second data module 102 is controlled to write the bias voltage signal to the first electrode of the driving transistor DT during part of the working phase of the pixel circuit 10 to adjust the bias state of the driving transistor DT, improve the threshold drift problem of the driving transistor DT, and enhance the display effect.

[0041] Furthermore, in the display panel 000 of the present embodiment, one sub-pixel column PL corresponds to two data lines S, and the pixel circuit 10 of one sub-pixel P includes a first data module 101 and a second data module 102. During the scanning and driving process of the same sub-pixel P, the data voltage signal can be written to the sub-pixel P of the current sub-image row PH via the first data line S1, and the bias state of the driving transistor DT of the sub-pixel P of the sub-image row PH is adjusted by the second data module 102 connected via the second data line S2, so that during the process of writing the data voltage signal to the sub-pixel P of the current sub-image row PH via the first data line S1, sufficient charging time is guaranteed, especially in the high-frequency driving mode with a high refresh frequency and a short scanning time for one row, sufficient charging time can be guaranteed for the data writing of the sub-pixel P, so that the data voltage signal can be written more fully, which is beneficial to improving the display quality of the display panel 000 in the high-frequency driving mode.

[0042] Optionally, in the display panel 000 of the present embodiment, one sub-pixel column PL corresponds to two data lines S, and the pixel circuit 10 of one sub-pixel P includes a first data module 101 and a second data module 102. For one scanning drive cycle of the display panel 000 (such as one frame time), the first data module 101 connected to the first data line S1 can be used to write data voltage signals to the sub-pixels P of the current sub-pixel row PH and adjust the bias state of the driving transistor DT of the sub-pixel P of the sub-pixel row PH. At the same time, the second data module 102 connected to the second data line S2 can be used to write data voltage signals to the sub-pixels P in the first few sub-pixel rows PH and adjust the bias state of the driving transistor DT of the sub-pixels P in the first few sub-pixel rows PH (at this time, since the first data module 101 in each pixel circuit 10 is 1 and the second data module 102 are both connected to the first electrode of the driving transistor DT, so they can play the role of writing data voltage signals and can also be reused to play the role of bias adjustment), so that in the process of writing data voltage signals to the sub-pixels P of the current sub-image row PH on the first data line S1 and adjusting the bias state of the driving transistor DT of the sub-pixels P of the sub-image row PH, it is ensured that the data voltage signals of the sub-pixels P of the sub-image row PH have been written in advance and the bias state of the driving transistor DT has been adjusted in advance, thereby ensuring that the sub-pixels P in the current sub-pixel row PH have sufficient charging time, especially in the high-frequency driving mode with a high refresh frequency, it can also ensure that the data writing of the sub-pixels P has sufficient charging time, thereby enabling the data voltage signals to be written more fully, which is beneficial to improving the display quality of the display panel 000 in the high-frequency driving mode.

[0043] It can be understood that the present embodiment does not limit the working timing of the first data module 101 and the second data module 102 included in the pixel circuit 10. It is only necessary to ensure sufficient writing time when writing the data voltage signal to the sub-pixel P through the two data lines S corresponding to a sub-pixel column PL, so as to achieve the display quality of the display panel 000 in the low-frequency driving display mode while improving the display effect of the display panel 000 in the high-frequency driving mode.

[0044] It can be understood that when the display panel 000 is an organic light emitting diode display panel, the signal line layout in the display panel 000 is relatively complex. At this time, a sub-pixel row PH may correspond to multiple scan lines G, and the area where the sub-pixel P is located can be the area defined by one of the scan lines G and the data line S. In specific implementation, the area of ​​the sub-pixel P in this embodiment can be understood based on actual conditions.

[0045] It should be noted that the display panel 000 provided in this embodiment can be an organic light emitting diode display panel. The figure of this embodiment only illustrates the structure of the display panel for example. In specific implementation, the structure of the display panel 000 includes but is not limited to this, and may also include other structures that can realize the display function. For details, please refer to the structure of the organic light emitting diode display panel in the relevant technology for understanding, and this embodiment will not be elaborated here.

[0046] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In this embodiment, the first data module 101 and the second data module 102 of the same pixel circuit 10 are not turned on at the same time.

[0047] This embodiment explains that when the same sub-pixel P in the display panel 000 is scan-driven, the first data module 101 and the second data module 102 of the same pixel circuit 10 are not turned on at the same time. Optionally, the first data module 101 can be turned on first, so that the first data module 101 connected to the first data line S1 completes the writing of the data voltage signal to the sub-pixel P of the current sub-image row PH, and then the second data module 102 is turned on, and the second data module 102 connected to the second data line S2 adjusts the bias state of the driving transistor DT of the sub-pixel P of the sub-image row PH, that is, by setting the first data module 101 and the second data module 102 of the same pixel circuit 10 to be turned on at different times, the bias state of the driving transistor DT of the pixel circuit 10 is adjusted after the writing of the data voltage signal is completed, so as to ensure that the data voltage signal is fully written into the driving transistor DT, and at the same time, the luminous display effect of the light-emitting element 20 connected to the pixel circuit 10 in the luminous stage can be improved by bias adjustment.

[0048] In some optional embodiments, please refer to Figure 3 and Figure 4 , Figure 3 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 4 yes Figure 3 Schematic diagram of electrical connection structure of a part of the sub-pixel column. In this embodiment, for the same sub-pixel column PL, the first data line S1 is connected to the first electrode of the first selection transistor T1, and the second data line S2 is connected to the first electrode of the second selection transistor T2;

[0049] The second electrode of the first selection transistor T1 is connected to the second electrode of the second selection transistor T2;

[0050] A gate of the first selection transistor T1 is connected to a first selection control signal CKH1 , and a gate of the second selection transistor T2 is connected to a second selection control signal CKH2 .

[0051] This embodiment explains that two data lines S corresponding to the same sub-pixel column PL in the display panel 000, namely the first data line S1 and the second data line S2, can be turned on at different times in a pixel circuit 10 by means of a selection transistor. Optionally, the display panel 000 may include a display area AA and a non-display area NA, and the non-display area NA is provided with a first selection transistor T1 and a second selection transistor T2 connected to the first data line S1. Among the two data lines S corresponding to the same sub-pixel column PL, the first data line S1 located in the display area AA is connected to the first electrode of the first selection transistor T1 located in the non-display area NA, the second data line S2 located in the display area AA is connected to the first electrode of the second selection transistor T2 located in the non-display area NA, and the second electrode of the first selection transistor T1 is connected to the second electrode of the second selection transistor T2. Optionally, the second electrode of the first selection transistor T1 and the second electrode of the second selection transistor T2 can be connected to the same binding pad (not shown in the figure) in the non-display area NA, and the required voltage signals are provided to the two data lines S corresponding to the same sub-pixel column PL in a time-sharing manner through the same binding pad. The gate of the first selection transistor T1 is connected to the first selection control signal CKH1, and the gate of the second selection transistor T2 is connected to the second selection control signal CKH2. The first selection control signal CKH1 is used to control whether the first selection transistor T1 is turned on or not. When the signal input by the first selection control signal CKH1 to the gate of the first selection transistor T1 is an enable signal so that the first selection transistor T1 is in a turned-on state, the second electrode of the first selection transistor T1 is connected to the first electrode of the first selection transistor T1, and the voltage signal input from the second electrode of the first selection transistor T1 can be transmitted to the first data line S1 through the first electrode of the first selection transistor T1, and then input to the pixel circuit 10 of the corresponding sub-pixel P when the first data module 101 is turned on. Similarly, the second selection control signal CKH2 is used to control whether the second selection transistor T2 is turned on or not. When the signal input to the gate of the second selection transistor T2 by the second selection control signal CKH2 is an enable signal so that the second selection transistor T2 is in the on state, the second electrode of the second selection transistor T2 is connected to the first electrode of the second selection transistor T2, and the voltage signal input from the second electrode of the second selection transistor T2 can be transmitted to the second data line S2 through the first electrode of the second selection transistor T2, and then input into the pixel circuit 10 of the corresponding sub-pixel P when the second data module 102 is turned on.

[0052] Optionally, the first selection control signal CKH1 and the second selection control signal CKH2 in the present embodiment can be respectively connected to the selection control signal lines (not shown in the figure) in the display panel 000, and the first selection control signal CKH1 and the second selection control signal CKH2 can control the first selection transistor T1 and the second selection transistor T2 to be turned on at different times, thereby achieving the first data module 101 and the second data module 102 of the same pixel circuit 10 to be turned on at different times. For example, after the first data module 101 completes writing of the data voltage signal to the pixel circuit 10, the second data module 102 adjusts the bias state of the driving transistor DT of the pixel circuit 10 to ensure that the data voltage signal is fully written into the driving transistor DT, and at the same time, the luminous display effect of the light-emitting element 20 connected to the pixel circuit 10 during the luminous stage can be improved through bias adjustment.

[0053] Optional, such as Figure 3 and Figure 4 As shown, in this embodiment, the first selection transistor T1 and the second selection transistor T2 are of the same type, such as the first selection transistor T1 and the second selection transistor T2 are both P-type transistors (such as Figure 4 As shown), or the first selection transistor T1 and the second selection transistor T2 are both N-type transistors (not shown in the figure), so that the first selection control signal CKH1 and the second selection control signal CKH2 can be set in the same time period with opposite polarities. When the first selection control signal CKH1 is an enable signal that can turn on the first selection transistor T1, the second selection control signal CKH2 is a non-enable signal that can turn off the second selection transistor T2. At this time, a path is formed between the second electrode of the first selection transistor T1 and the first data line S1. On the basis of the first data module 101 being turned on, the binding pad connected to the second electrode of the first selection transistor T1 provides a data voltage signal, and the data voltage signal can be written into the pixel circuit 10 through the first data line S1. When the first selection control signal CKH1 is a non-enable signal that can cut off the first selection transistor T1, and the second selection control signal CKH2 is an enable signal that can turn on the second selection transistor T2, a path is formed between the second electrode of the second selection transistor T2 and the second data line S2. On the basis of the second data module 102 being turned on, the binding pad connected to the second electrode of the second selection transistor T2 provides a bias voltage signal, and a bias voltage signal can be provided to the driving transistor DT of the pixel circuit 10 through the second data line S2 to adjust the bias state of the driving transistor DT.

[0054] It can be understood that when the first selection transistor T1 and the second selection transistor T2 are of the same type, the first selection control signal CKH1 and the second selection control signal CKH2 can be connected to different selection control signal lines in the display panel 000, that is, the first selection transistor T1 and the second selection transistor T2 can be individually controlled in on and off states through two different selection control signal lines, which is beneficial to ensure the time-sharing transmission signals of the two data lines S corresponding to the same sub-pixel column PL, thereby improving the stability of signal transmission.

[0055] Optional, such as Figure 3 and Figure 5 As shown, Figure 5 yes Figure 3 Another schematic diagram of an electrical connection structure of a part of a sub-pixel column, wherein the first selection transistor T1 and the second selection transistor T2 are of opposite types, such as the first selection transistor T1 is a P-type transistor and the second selection transistor T2 is an N-type transistor (such as Figure 5 As shown), or the first selection transistor T1 is an N-type transistor and the second selection transistor T2 is a P-type transistor (not shown in the figure), at this time, the gate of the first selection transistor T1 is connected to the gate of the second selection transistor T2, so that the first selection control signal CKH1 and the second selection control signal CKH2 can be set in the same time period with the same polarity. For example, when the first selection transistor T1 is a P-type transistor and the second selection transistor T2 is an N-type transistor (as shown in the figure), the gate of the first selection transistor T1 is connected to the gate of the second selection transistor T2. Figure 5 As shown in FIG. 1 ), when the first selection control signal CKH1 and the second selection control signal CKH2 are both negative voltage signals, the first selection transistor T1 is turned on and the second selection control signal CKH2 is turned off. At this time, a path is formed between the second electrode of the first selection transistor T1 and the first data line S1. On the basis of the first data module 101 being turned on, the binding pad connected to the second electrode of the first selection transistor T1 provides a data voltage signal, and the data voltage signal can be written into the pixel circuit 10 through the first data line S1. When the first selection transistor T1 is a P-type transistor and the second selection transistor T2 is an N-type transistor (as shown in FIG. 1 ), the first selection transistor T1 is turned on and the second selection control signal CKH2 is turned off. Figure 5 As shown), when the first selection control signal CKH1 and the second selection control signal CKH2 are both positive voltage signals, the first selection transistor T1 is turned off and the second selection control signal CKH2 is turned on. At this time, a path is formed between the second electrode of the second selection transistor T2 and the second data line S2. On the basis of the second data module 102 being turned on, the binding pad connected to the second electrode of the second selection transistor T2 provides a bias voltage signal, and the bias voltage signal can be provided to the driving transistor DT of the pixel circuit 10 through the second data line S2 to adjust the bias state of the driving transistor DT.

[0056] Further optionally, in the present embodiment, in the same time period, the first selection control signal CKH1 and the second selection control signal CKH2 have the same polarity, that is, the gate of the first selection transistor T1 and the gate of the second selection transistor T2 can be connected to the same selection control signal line, thereby reducing the number of selection control signal lines in the display panel, which is beneficial to reducing the border layout space of the non-display area NA of the display panel 000 and realizing a narrow border design.

[0057] In some optional embodiments, please refer to Figure 3 and Figure 6 , Figure 6 yes Figure 3 Another schematic diagram of the electrical connection structure of a part of the sub-pixel column, in this embodiment, the pixel circuit 10 further includes a first light emitting control module 103, a second light emitting control module 104, a first reset module 105, a second reset module 106, and a threshold compensation module 107;

[0058] A first end of the first light emitting control module 103 is electrically connected to the first power signal line PVDD, and a second end of the first light emitting control module 103 is electrically connected to the first electrode of the driving transistor DT;

[0059] A first end of the second light emitting control module 104 is electrically connected to the second electrode of the driving transistor DT, and a second end of the second light emitting control module 104 is electrically connected to the anode of the light emitting element 20;

[0060] A first end of the first reset module 105 is electrically connected to the first reset signal line REF1, and a second end of the first reset module 105 is electrically connected to the gate of the driving transistor DT;

[0061] A first end of the second reset module 106 is electrically connected to the second reset signal line REF2, and a second end of the second reset module 106 is electrically connected to the anode of the light emitting element 20;

[0062] A first end of the threshold compensation module 107 is electrically connected to the gate of the driving transistor DT, a second end of the threshold compensation module 107 is electrically connected to the second electrode of the driving transistor DT, and a cathode of the light emitting element 20 is connected to the second power signal line PVEE.

[0063] This embodiment explains the module connection structure of the pixel circuit 10 and the light-emitting element 20 of each sub-pixel P. Optionally, the pixel circuit 10 includes a first data module 101 and a second data module 102 connected to the first electrode of the driving transistor DT, and also includes a first light-emitting control module 103, a second light-emitting control module 104, a first reset module 105, a second reset module 106, and a threshold compensation module 107. When the pixel circuit 10 works in the light-emitting stage, the first light-emitting control module 103 and the second light-emitting control module 104 are turned on, a conduction circuit is formed between the first power signal line PVDD and the second power signal line PVEE, and the light-emitting element 20 emits light. The first light-emitting control module 103 and the second light-emitting control module 104 cooperate to provide a driving current to the light-emitting element 20, wherein the first light-emitting control module 103 is turned on, and the positive power signal provided by the first power signal line PVDD is provided to the first electrode of the driving transistor DT, and the driving transistor DT is turned on under the control of its gate voltage, and the voltage signal of the first electrode of the driving transistor DT is provided to the second electrode of the driving transistor DT; the second light-emitting control module 104 is turned on, and the voltage signal of the second electrode of the driving transistor DT is provided to the light-emitting element 20, so as to realize that the driving current flows through the light-emitting element 20 and controls the light-emitting element 20 to emit light. When the first data module 101 is turned on, the data voltage signal on the first data line S1 can be transmitted to the driving transistor DT. When the second data module 102 is turned on, the bias voltage signal on the second data line S2 can be transmitted to the driving transistor DT to adjust the bias state of the driving transistor DT. When the threshold compensation module 107 is turned on, the threshold compensation can be performed on the driving transistor DT.

[0064] When the first reset module 105 is turned on, the gate potential of the driving transistor DT is the first reset signal provided by the first reset signal line REF1, and the gate of the driving transistor DT is reset, so that the driving transistor DT can be turned on during threshold compensation. When the second reset module 106 is turned on, the anode potential of the light-emitting element 20 is the second reset signal provided by the second reset signal line REF2, and the anode of the light-emitting element 20 is reset, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and improving the display effect of the display panel 000. Optionally, the values ​​of the first reset signal provided by the first reset signal line REF1 and the second reset signal provided by the second reset signal line REF2 in this embodiment can be the same or different, and can be set according to actual needs during specific implementation.

[0065] Optional, such as Figure 3 , Figure 7 and Figure 8 As shown, Figure 7 yes Figure 3 Another schematic diagram of the electrical connection structure of a part of the neutron pixel column, Figure 8 yes Figure 7 In the driving timing diagram of the pixel circuit, in this embodiment, the first light emitting control module 103 includes a first transistor M1, the gate of the first transistor M1 is electrically connected to the first light emitting control signal line EM1, the source of the first transistor M1 is electrically connected to the first power signal line PVDD, and the drain of the first transistor M1 is electrically connected to the first electrode of the driving transistor DT;

[0066] The second light emitting control module 104 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second light emitting control signal line EM2, a source of the second transistor M2 is electrically connected to the second electrode of the driving transistor DT, and a drain of the second transistor M2 is electrically connected to the anode of the light emitting element 20;

[0067] The first data module 101 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the first scan signal line S1, a source of the third transistor M3 is electrically connected to the first data line S1, and a drain of the third transistor M3 is electrically connected to the first electrode of the driving transistor DT;

[0068] The second data module 102 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the second scan signal line S2, a source of the fourth transistor M4 is electrically connected to the second data line S2, and a drain of the fourth transistor M4 is electrically connected to the first electrode of the driving transistor DT;

[0069] The threshold compensation module 107 includes a fifth transistor M5, a gate of the fifth transistor M5 is electrically connected to the third scan signal line S3, a source of the fifth transistor M5 is electrically connected to the gate of the driving transistor DT, and a drain of the fifth transistor M5 is electrically connected to the second electrode of the driving transistor DT;

[0070] The first reset module 105 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the fourth scan signal line S4, a source of the sixth transistor M6 is electrically connected to the first reset signal line REF1, and a drain of the sixth transistor M6 is electrically connected to the gate of the driving transistor DT;

[0071] The second reset module 106 includes a seventh transistor M7 , a gate of the seventh transistor M7 is electrically connected to the fifth scan signal line S5 , a source of the seventh transistor M7 is electrically connected to the second reset signal line REF2 , and a drain of the seventh transistor M7 is electrically connected to the anode of the light emitting element 20 .

[0072] Further optionally, the pixel circuit 10 also includes a storage capacitor C, one end of the storage capacitor C is connected to the first power signal line PVDD, and the other end of the storage capacitor C is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which is beneficial for the driving transistor DT to remain turned on.

[0073] It can be understood that, in this embodiment, the fifth transistor M5 and the sixth transistor M6 connected to the gate of the driving transistor DT are N-type metal oxide transistors, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the driving transistor DT are all P-type low-temperature polysilicon transistors. The fifth transistor M5 and the sixth transistor M6 are N-type metal oxide transistors, the fifth transistor M5 is electrically connected to the gate of the driving transistor DT, and the sixth transistor M6 is also electrically connected to the gate of the driving transistor DT. The metal oxide transistor has a low leakage current in the off state, thereby reducing the influence of the leakage current on the gate potential of the driving transistor DT, thereby stabilizing the gate voltage of the driving transistor DT, improving the working stability of the driving transistor DT, and further ensuring the stability of the driving current, which is conducive to ensuring the uniformity of the light emitting brightness of the light emitting element 20 when the pixel circuit 10 of this embodiment is applied to the display panel 000. Especially when used in low-frequency drive display, the display time of a frame is long, so the potential of the driving transistor DT needs to be maintained for a long time. If the transistor connected to the gate of the driving transistor DT is a low-temperature polysilicon transistor, it is easy to cause obvious flickering by the leakage of the transistor connected to the gate of the driving transistor DT due to the large off-state leakage of the low-temperature polysilicon transistor. Therefore, this embodiment sets the fifth transistor M5 and the sixth transistor M6 as N-type metal oxide transistors, and uses their small off-state leakage characteristics to maintain the potential of the gate of the driving transistor DT for a long time during low-frequency drive display, thereby improving the flickering phenomenon during low-frequency drive and improving the display effect.

[0074] In the sub-pixel P provided in this embodiment, the working process of the pixel circuit 10 at least includes a first reset stage t1, an adjustment stage t2, a second reset stage t3, a threshold compensation stage t4, a data writing stage t5, a bias voltage adjustment stage t6, and a light emitting stage t7;

[0075] In the first reset stage t1, the fifth scan signal line S5 inputs a low-potential fifth scan signal to control the seventh transistor M7 of the second reset module 106 to turn on, the second light-emitting control signal line EM2 inputs a low-potential second light-emitting control signal to control the second transistor M2 of the second light-emitting control module 104 to turn on, the third scan signal line S3 inputs a high-potential third scan signal to control the fifth transistor M5 of the threshold compensation module 107 to turn on, the second reset signal line REF2 inputs a second reset signal to reset the gate of the driving transistor DT after passing through the seventh transistor M7, the second transistor M2, and the fifth transistor M5, and the driving transistor DT is turned on, the second reset signal line REF2 inputs a second reset signal to reset the anode of the light-emitting element 20 through the seventh transistor M7, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel 000.

[0076] In the adjustment stage t2, the second scan signal line S2 inputs a low potential second scan signal to control the fourth transistor M4 of the second data module 102 to turn on, and the third scan signal line S3 inputs a high potential third scan signal to control the fifth transistor M5 of the threshold compensation module 107 to turn on. The voltage signal input by the second data line S2 passes through the fourth transistor M4, the driving transistor DT, and the fifth transistor M5 to perform threshold compensation on the driving transistor DT. When the display screen of the display panel 00 switches from a black screen to a white screen, the hysteresis of the driving transistor DT causes the problem that the display brightness of the first frame is low when the display screen is just switched to the white screen. Therefore, in this embodiment, when the display panel 000 switches to the white screen, a first reset stage t1 and an adjustment stage t2 are performed. The first reset stage t1 is used to reset the driving transistor DT so that the driving transistor DT can be turned on in the adjustment stage t2 to prepare for the adjustment stage t2. The adjustment stage t2 can improve the hysteresis problem of the driving transistor DT and improve the display brightness of the first frame.

[0077] During the driving operation of the pixel circuit 10 of the present embodiment, after the problem of low brightness of the first frame when switching between black and white images is improved, the pixel circuit 10 may enter the second reset stage t3.

[0078] In the second reset stage t3, the fourth scan signal line S4 inputs a high potential fourth scan signal to control the sixth transistor M6 of the first reset module 105 to turn on, reset the gate of the driving transistor DT, and turn on the driving transistor DT to ensure the accuracy of the subsequent signal written to the gate of the driving transistor DT.

[0079] In the threshold compensation stage t4, the first scan signal line S1 inputs a low-potential first scan signal to control the third transistor M3 of the first data module 101 to turn on, and the third scan signal line S3 inputs a high-potential third scan signal to control the fifth transistor M5 of the threshold compensation module 107 to turn on, and the threshold compensation voltage provided by the first data line S1 is transmitted to the gate of the driving transistor DT through the third transistor M3, the driving transistor DT, and the fifth transistor, so as to perform threshold compensation on the driving transistor DT and self-compensate for the deviation of the threshold voltage of the driving transistor DT.

[0080] In the data writing phase t5, the second scan signal line S2 inputs a low potential second scan signal to control the fourth transistor M4 of the second data module 102 to turn on, and the data voltage signal provided by the second data line S2 is transmitted to the first electrode of the driving transistor DT through the fourth transistor M4.

[0081] In the bias voltage adjustment stage t6, the first scan signal line S1 inputs a low-potential first scan signal to control the third transistor M3 of the first data module 101 to turn on, and the bias voltage signal provided by the first data line S1 is transmitted to the driving transistor DT through the third transistor M3 to adjust the bias state of the driving transistor DT. Optionally, in the display panel 000 of this embodiment, in the holding frame in the low-frequency driving mode, the first scan signal line S1 can still input a low-potential first scan signal to control the third transistor M3 of the first data module 101 to turn on, and the bias voltage signal provided by the first data line S1 is continuously transmitted to the driving transistor DT through the third transistor M3 to adjust the bias state of the driving transistor DT in the low-frequency driving mode.

[0082] It can be understood that in some other optional embodiments, two bias voltage adjustment stages can be set in the working cycle of the pixel circuit. For example, before resetting the gate of the driving transistor DT, the first scanning signal line S1 can also be made to input a low-potential first scanning signal to control the third transistor M3 of the first data module 101 to be turned on, and the bias voltage signal provided by the first data line S1 is further transmitted to the driving transistor DT through the third transistor M3 to adjust the bias state of the driving transistor DT (not shown in the figure), so that the driving transistor DT is reverse biased, the first pole and the second pole of the driving transistor DT are reversed, the degree of ion polarization inside the driving transistor DT is weakened, and the threshold voltage of the driving transistor DT is reduced. The threshold voltage of the driving transistor DT is adjusted by biasing the driving transistor DT to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to the forward bias state of the driving transistor. Therefore, by adding a bias voltage adjustment stage in the driving working cycle of the pixel circuit 10, the time of the bias state of the driving transistor can be further adjusted to enhance the degree of improvement of the threshold voltage drift of the driving transistor due to the hysteresis effect.

[0083] In the light-emitting stage t7, the first light-emitting control signal line EM1 inputs a low-potential signal to control the first transistor M1 of the first light-emitting control module 103 to be turned on, and the second light-emitting control signal line EM2 inputs a low-potential signal to control the second transistor M2 of the second light-emitting control module 104 to be turned on. The driving transistor DT generates a driving current under the control of its gate voltage, and a conductive path is formed among the first power signal line PVDD, the first transistor M1, the driving transistor DT, the second transistor M2, the light-emitting element 20, and the second power signal line PVEE. The driving current is provided to the light-emitting element 20 to realize the driving current flowing through the light-emitting element 20 and control the light-emitting element 20 to emit light.

[0084] It can be understood that, in specific implementation, the connection structure of the pixel circuit 10 of this embodiment includes but is not limited to the above structure and driving sequence, and may also be other connection structures and driving methods, which are not limited in this embodiment.

[0085] The display panel 000 of the present embodiment corresponds two data lines S to one sub-pixel column PL, and can ensure sufficient charging time during the process of writing the data voltage signal to the sub-pixel P of the current sub-image row PH by the first data line S1. In particular, in the high-frequency driving mode with a high refresh frequency and a short row scanning time, it can also ensure that the data writing of the sub-pixel P has sufficient charging time, thereby allowing the data voltage signal to be written more fully, which is beneficial to improving the display quality of the display panel 000 in the high-frequency driving mode, and can also improve the hysteresis problem of the driving transistor DT when the black screen switches to the white screen in the low-frequency driving mode, thereby improving the display brightness of the first frame, which is beneficial to taking into account the display effects in both the low-frequency driving mode and the high-frequency driving mode.

[0086] In some other optional embodiments, the transistors included in the pixel circuit 10 in this embodiment may all be P-type transistors, such as P-type low-temperature polysilicon transistors. It can be understood that when the transistors in the pixel circuit 10 are all P-type transistors, this embodiment can not only utilize the high mobility and high driving speed characteristics of low-temperature polysilicon transistors, so that when the data module writes the data voltage signal, the response speed of the driving transistor DT is faster, and the data voltage signal can be written quickly to avoid the phenomenon of insufficient charging due to the long opening time of the driving transistor DT, but also can further ensure sufficient charging time by corresponding two data lines S through one sub-pixel column PL, especially in the high-frequency driving mode, the data voltage signal can be written more fully, which is beneficial to improve the display quality of the display panel 000 in the high-frequency driving mode. It should be noted that when the transistors in the pixel circuit 10 in this embodiment are all P-type transistors, the polarity of the driving signal corresponding to the third scan line S3 and the fourth scan line S4 needs to be changed, and only reference is needed. Figure 8The illustrated driving timing is to reverse the signal polarities of the third scanning line S3 connected to the gate of the fifth transistor M5 and the fourth scanning line S4 connected to the gate of the sixth transistor M6, so as to be suitable for the driving process of the fifth transistor M5 and the sixth transistor M6 being P-type transistors. In this embodiment, the driving timing when all the transistors in the pixel circuit 10 are P-type transistors is not specifically described.

[0087] In some optional embodiments, please refer to Figure 3 and Fig. 9 , Fig. 9 yes Figure 3 Another schematic diagram of the electrical connection structure of a partial area of ​​a sub-pixel column in the embodiment, the display panel 000 further includes a plurality of bias selection modules 30, one sub-pixel column PL is correspondingly connected to two bias selection modules 30, which are respectively a first bias selection module 301 and a second bias selection module 302;

[0088] The first data line S1 is connected to a first end of the first bias selection module 301, and the second data line S2 is connected to a first end of the second bias selection module 302;

[0089] The second end of the first bias selection module 301 and the second end of the second bias selection module 302 are both connected to the bias voltage signal VH.

[0090] This embodiment explains that a plurality of bias selection modules 30 may be provided in the display panel 000. Optionally, the bias selection module 30 may be provided within the non-display area NA of the display panel 000, thereby preventing the bias selection module 30 from occupying the display area AA of the display panel 000, which is beneficial to increasing the aperture ratio of the sub-pixel P. In the present embodiment, one sub-pixel column PL is connected to two bias selection modules 30, and the two bias selection modules 30 can be named as a first bias selection module 301 and a second bias selection module 302, respectively. Among the two data lines S corresponding to one sub-pixel column PL, one end of the first data line S1 located in the display area AA can be connected to the first end of the first bias selection module 301 in the non-display area NA, and the second data line S2 located in the display area AA is connected to the first end of the second bias selection module 302 in the non-display area NA. The second end of the first bias selection module 301 and the second end of the second bias selection module 302 are both connected to a bias voltage signal. Optionally, the second end of the first bias selection module 301 and the second end of the second bias selection module 302 can be connected to the same binding pad (not shown in the figure) in the non-display area NA, and the bias voltage signal VH is provided to the second end of the first bias selection module 301 and the second end of the second bias selection module 302 through the binding pad. In this embodiment, a bias selection module 30 is separately provided in the display panel 000. Through the control of the bias selection module 30, the bias voltage signal VH is selected to be transmitted to the pixel circuit 10 of the sub-pixel P through the first data line S1 or the second data line S2. Not only can one sub-pixel column PL correspond to two data lines S, but also sufficient charging time can be ensured during the process of writing the data voltage signal to the sub-pixel P of the current sub-image row PH through the first data line S1. In particular, in a high-frequency driving mode with a high refresh frequency and a short row scanning time, sufficient charging time can be ensured for data writing to the sub-pixel P, thereby making the data voltage signal more fully written, which is beneficial to improving the display quality of the display panel 000 in the high-frequency driving mode. At the same time, through the selection control of the two bias selection modules 30 corresponding to one sub-pixel column PL, it is possible to implement the adjustment of the bias state of the driving transistor DT in the pixel circuit 10 by multiplexing another data line S while writing the data voltage signal to the sub-pixel P through one data line S, which is beneficial to ensuring that the data voltage signal has sufficient writing time, and can also ensure the adjustment effect of the bias state of the driving transistor DT, thereby improving the display quality.

[0091] Optional, such as Figure 3 and Fig.10 As shown, Fig.10 yes Figure 3Another schematic diagram of the electrical connection structure of a partial area of ​​the neutron pixel column, in this embodiment, in this embodiment, the first bias selection module 301 includes a first bias selection transistor T3, the gate of the first bias selection transistor T3 is connected to the third selection control signal CKH3, the first electrode of the first bias selection transistor T3 is connected to the first data line S1, and the second electrode of the first bias selection transistor T3 is connected to the bias voltage signal VH;

[0092] The second bias selection module 302 includes a second bias selection transistor T4, a gate of which is connected to the fourth selection control signal CKH4, a first electrode of which is connected to the second data line S2, and a second electrode of which is connected to the bias voltage signal VH.

[0093] This embodiment explains that two data lines S corresponding to the same sub-pixel column PL in the display panel 000, namely the first data line S1 and the second data line S2, can be connected or not by selecting the first bias selection transistor T3 to control the connection between the first bias selection module 301 and the first data line S1, and connected or not by selecting the second bias selection transistor T4 to control the connection between the second bias selection module 302 and the second data line S2. Optionally, the first bias selection module 301 and the first data line S1, and the second bias selection module 302 and the second data line S2 are not turned on at the same time. Optionally, the display panel 000 may include a display area AA and a non-display area NA, wherein the non-display area NA is provided with a first bias selection transistor T3 of the first bias selection module 301 connected to the first data line S1 and a second bias selection transistor T4 of the second bias selection module 302, wherein among the two data lines S corresponding to the same sub-pixel column PL, the first data line S1 located in the display area AA is connected to the first electrode of the first bias selection transistor T3 located in the non-display area NA, the second data line S2 located in the display area AA is connected to the first electrode of the second bias selection transistor T4 located in the non-display area NA, and the second electrode of the first bias selection transistor T3 and the second electrode of the second bias selection transistor T4 are both connected to the bias voltage signal VH. The second electrode of the optional first bias selection transistor T3 and the second electrode of the second bias selection transistor T4 may be connected to the same binding pad (not shown in the figure) in the non-display area NA, and the required bias voltage signal VH is provided to the two data lines S corresponding to the same sub-pixel column PL in a time-sharing manner through the same binding pad.

[0094] The gate of the first bias selection transistor T3 is connected to the third selection control signal CKH3, and the gate of the second bias selection transistor T4 is connected to the fourth selection control signal CKH4. The third selection control signal CKH3 is used to control whether the first bias selection transistor T3 is turned on or not. When the signal input by the third selection control signal CKH3 to the gate of the first bias selection transistor T3 is an enable signal so that the first bias selection transistor T3 is in a turned-on state, the second electrode of the first bias selection transistor T3 is connected to the first electrode of the first bias selection transistor T3. The bias voltage signal VH input from the second electrode of the first bias selection transistor T3 can be transmitted to the first data line S1 through the first electrode of the first bias selection transistor T3, and then input to the pixel circuit 10 of the corresponding sub-pixel P when the first data module 101 is turned on.

[0095] Similarly, the fourth selection control signal CKH4 is used to control whether the second bias selection transistor T4 is turned on or not. When the signal input by the fourth selection control signal CKH4 to the gate of the second bias selection transistor T4 is an enable signal so that the second bias selection transistor T4 is in a turned-on state, the second electrode of the second bias selection transistor T4 is connected to the first electrode of the second bias selection transistor T4, and the bias voltage signal VH input from the second electrode of the second bias selection transistor T4 can be transmitted to the second data line S2 through the first electrode of the second bias selection transistor T4, and then input to the pixel circuit 10 of the corresponding sub-pixel P when the second data module 102 is turned on.

[0096] Optionally, the third selection control signal CKH3 and the fourth selection control signal CKH4 in the present embodiment can be respectively connected to the selection control signal lines (not shown in the figure) in the display panel 000. The third selection control signal CKH3 and the fourth selection control signal CKH4 are used to control the first bias selection transistor T3 and the fourth selection control signal CKH4 to be turned on at different times, thereby achieving the first data module 101 and the second data module 102 of the same pixel circuit 10 to be turned on at different times. While the data voltage signal is written to the sub-pixel P through one data line S, another data line S is reused to input the bias voltage signal VH to adjust the bias state of the driving transistor DT in the pixel circuit 10. This is beneficial to ensuring that the data voltage signal has sufficient writing time, and can also ensure the adjustment effect of the bias state of the driving transistor DT, thereby improving the display quality.

[0097] Further optionally, the first selection transistor T1 and the first bias selection transistor T3 in this embodiment are of the same type, for example, the first selection transistor T1 and the first bias selection transistor T3 are both P-type transistors (eg Fig.10As shown), or the first selection transistor T1 and the first bias selection transistor T3 are both N-type transistors (not shown in the figure), in the same time period, the polarity of the first selection control signal CKH1 and the third selection control signal CKH3 are opposite, so that the first selection transistor T1 and the first bias selection transistor T3 connected to the first data line S1 are not turned on at the same time, that is, the writing of the data voltage signal and the bias voltage signal DVH are transmitted to the first data line S1 in a time-sharing manner. Similarly, the second selection transistor T2 and the second bias selection transistor T4 in this embodiment are of the same type, such as the second selection transistor T2 and the second bias selection transistor T4 are both P-type transistors (such as Fig.10 As shown), or the second selection transistor T2 and the second bias selection transistor T4 are both N-type transistors (not shown in the figure), in the same time period, the polarity of the second selection control signal CKH2 and the fourth selection control signal CKH4 are opposite, so that the second selection transistor T2 and the second bias selection transistor T4 commonly connected to the second data line S2 can be turned on at different times, that is, the writing of the data voltage signal and the bias voltage signal DVH are transmitted to the second data line S2 in a time-sharing manner.

[0098] It can be understood that the bias voltage signal VH in this embodiment can be provided by a driver chip bound to the non-display area NA. Optionally, a data driver output module and a non-data driver output module can be integrated in the driver chip. The data driver output module is used to provide a data voltage signal for the data line S. The bias voltage signal VH can be input through the non-data driver output module, that is, the bias voltage signal and the data voltage signal can be separately input into the display panel 000 through the output module, and then the data driver output module can be turned off in the low-frequency driving mode, which is beneficial to saving the driving power consumption of the driver chip bound to the display panel 000.

[0099] Optional, such as Figure 3 , Fig.11 and Fig.12 As shown, Fig.11 yes Figure 3 Another schematic diagram of the electrical connection structure of a part of the neutron pixel column, Fig.12 yes Fig.11 In the driving timing diagram of the pixel circuit, in this embodiment, the first light emitting control module 103 includes a first transistor M1, the gate of the first transistor M1 is electrically connected to the first light emitting control signal line EM1, the source of the first transistor M1 is electrically connected to the first power signal line PVDD, and the drain of the first transistor M1 is electrically connected to the first electrode of the driving transistor DT;

[0100] The second light emitting control module 104 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second light emitting control signal line EM2, a source of the second transistor M2 is electrically connected to the second electrode of the driving transistor DT, and a drain of the second transistor M2 is electrically connected to the anode of the light emitting element 20;

[0101] The first data module 101 includes a third transistor M3, a source of the third transistor M3 is electrically connected to the first data line S1, and a drain of the third transistor M3 is electrically connected to the first electrode of the driving transistor DT;

[0102] The second data module 102 includes a fourth transistor M4, a source of the fourth transistor M4 is electrically connected to the second data line S2, and a drain of the fourth transistor M4 is electrically connected to the first electrode of the driving transistor DT;

[0103] The threshold compensation module 107 includes a fifth transistor M5, a source of the fifth transistor M5 is electrically connected to the gate of the driving transistor DT, and a drain of the fifth transistor M5 is electrically connected to the second electrode of the driving transistor DT;

[0104] The first reset module 105 includes a sixth transistor M6, a source of the sixth transistor M6 is electrically connected to the first reset signal line REF1, and a drain of the sixth transistor M6 is electrically connected to the gate of the driving transistor DT;

[0105] The second reset module 106 includes a seventh transistor M7 , a source of the seventh transistor M7 is electrically connected to the second reset signal line REF2 , and a drain of the seventh transistor M7 is electrically connected to the anode of the light emitting element 20 .

[0106] Further optionally, the pixel circuit 10 also includes a storage capacitor C, one end of the storage capacitor C is connected to the first power signal line PVDD, and the other end of the storage capacitor C is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which is beneficial for the driving transistor DT to remain turned on.

[0107] It can be understood that, in this embodiment, the fifth transistor M5 and the sixth transistor M6 connected to the gate of the driving transistor DT are N-type metal oxide transistors, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the driving transistor DT are all P-type low-temperature polysilicon transistors. The fifth transistor M5 and the sixth transistor M6 are N-type metal oxide transistors, and by utilizing their small off-state leakage current characteristics, the potential of the gate of the driving transistor DT can be maintained for a long time when the display is driven at a low frequency, thereby improving the flicker phenomenon during low-frequency driving and improving the display effect.

[0108] The working principle of a single pixel circuit 10 in this embodiment can be understood by referring to the description in the above embodiment. For example, the reset phase of the pixel circuit 10 in the sub-pixel P can be understood by referring to the description in the above embodiment. This embodiment will not be elaborated here. This embodiment describes the driving process of threshold compensation, data writing, and bias voltage adjustment of the pixel circuit 10 corresponding to multiple sub-pixels P in a sub-pixel column PL.

[0109] Optional, such as Fig.11 As shown, a sub-pixel column PL may include, from top to bottom, a first sub-pixel P1 located in a first sub-pixel row PH, a second sub-pixel P2 located in a second sub-pixel row PH, a third sub-pixel P3 located in a third sub-pixel row PH, a fourth sub-pixel P4 located in a fourth sub-pixel row PH, ...

[0110] In the first working stage J1: the low potential voltage signal of the first selection control signal CKH1 is input to the gate of the first selection transistor T1, the first selection transistor T1 is turned on, the data voltage signal is transmitted to the first data line S1, the gate of the third transistor M3 of the first data module 101 in the first sub-pixel P1 is input with a low potential scanning signal Scan1, the gate of the fifth transistor M5 of the threshold compensation module 107 in the first sub-pixel P1 is input with a high potential scanning signal S2N1, the fifth transistor M5 of the first sub-pixel P1 is turned on, and since the driving transistor DT is generally turned on when data is written, the data voltage signal on the first data line S1 is written to the gate of the driving transistor DT, thereby self-compensating for the deviation of the threshold voltage of the driving transistor DT of the first sub-pixel P1.

[0111] In the second working stage J2: the low potential voltage signal of the second selection control signal CKH2 is input to the gate of the second selection transistor T2, the second selection transistor T2 is turned on, the data voltage signal is transmitted to the second data line S2, the gate of the fourth transistor M4 of the second data module 102 in the second sub-pixel P2 is input with a low potential scanning signal Scan2, the gate of the fifth transistor M5 of the threshold compensation module 107 in the second sub-pixel P2 is input with a high potential scanning signal S2N2, the fifth transistor M5 of the second sub-pixel P2 is turned on, and since the driving transistor DT is generally turned on when data is written, the data voltage signal on the second data line S2 is written into the gate of the driving transistor DT of the second sub-pixel P2, thereby self-compensating for the deviation of the threshold voltage of the driving transistor DT of the second sub-pixel P2.

[0112] At this time, since the low-potential scan signal Scan1 is still being fed into the gate of the third transistor M3 of the first data module 101 in the first sub-pixel P1 in the first part of the time period before the second working stage J2, and the gate of the fifth transistor M5 of the threshold compensation module 107 in the first sub-pixel P1 is still the high-potential scan signal S2N1, the data voltage signal on the first data line S1 is still being written into the gate of the driving transistor DT, and the deviation compensation of the threshold voltage of the driving transistor DT of the first sub-pixel P1 is still being executed, which is equivalent to the data voltage signal provided on the second data line S2. During a part of the time period for compensating the threshold voltage of the second sub-pixel P2, the first data line S1 is still compensating the threshold voltage of the first sub-pixel P1 in the previous sub-pixel row PH, which is beneficial to make the compensation of the driving transistor DT in the first sub-pixel P1 more sufficient.

[0113] In the third working stage J3: the low potential voltage signal of the first selection control signal CKH1 is input to the gate of the first selection transistor T1, the first selection transistor T1 is turned on, the data voltage signal is transmitted to the first data line S1, the gate of the third transistor M3 of the first data module 101 in the third sub-pixel P3 is input with a low potential scanning signal Scan3, the gate of the fifth transistor M5 of the threshold compensation module 107 in the third sub-pixel P3 is input with a high potential scanning signal S2N3, the fifth transistor M5 of the third sub-pixel P3 is turned on, and since the driving transistor DT is generally turned on when data is written, the data voltage signal on the first data line S1 is written into the gate of the driving transistor DT of the third sub-pixel P3, thereby self-compensating for the deviation of the threshold voltage of the driving transistor DT of the third sub-pixel P3.

[0114] At this time, in the latter part of the third working stage J3, the low potential signal of the fourth selection control signal CKH4 is input to the gate of the second bias selection transistor T4, the second bias selection transistor T4 is turned on, and the bias voltage signal VH is written to the second data line S2. At the same time, the gate of the fourth transistor M4 of the second data module 102 of the first sub-pixel P1 is input with a low potential scanning signal SP1, the fourth transistor M4 of the first sub-pixel P1 is turned on, and the bias voltage signal VH on the second data line S2 is written into the first electrode of the driving transistor DT of the first sub-pixel P1, so that the bias state of the driving transistor DT of the first sub-pixel P1 is adjusted.

[0115] In the fourth working stage J4: the low potential voltage signal of the second selection control signal CKH2 is input to the gate of the second selection transistor T2, the second selection transistor T2 is turned on, the data voltage signal is transmitted to the second data line S2, the gate of the fourth transistor M4 of the second data module 102 in the fourth sub-pixel P4 is input with a low potential scanning signal Scan4, the gate of the fifth transistor M5 of the threshold compensation module 107 in the fourth sub-pixel P4 is input with a high potential scanning signal S2N4, the fifth transistor M5 of the fourth sub-pixel P4 is turned on, and since the driving transistor DT is generally turned on when data is written, the data voltage signal on the second data line S2 is written into the gate of the driving transistor DT of the fourth sub-pixel P4, thereby self-compensating for the deviation of the threshold voltage of the driving transistor DT of the fourth sub-pixel P4.

[0116] At this time, in the latter part of the fourth working stage J4, the low potential signal of the third selection control signal CKH3 is input to the gate of the first bias selection transistor T3, the first bias selection transistor T3 is turned on, and the bias voltage signal VH is written to the first data line S1. At the same time, the gate of the third transistor M3 of the first data module 101 of the second sub-pixel P2 is input with a low potential scanning signal SP2, the third transistor M3 of the second sub-pixel P2 is turned on, and the bias voltage signal VH on the first data line S1 is written to the first electrode of the driving transistor DT of the second sub-pixel P2, so that the bias state of the driving transistor DT of the second sub-pixel P2 is adjusted.

[0117] By analogy, it is possible to perform threshold compensation on the sub-pixel P in the current row through one data line S, while adjusting the bias state of the driving transistor DT in the sub-pixel P in the previous row through another data line S, and then reuse the two data lines S corresponding to a sub-pixel column PL to perform threshold compensation and bias adjustment on sub-pixels in different rows at different times, which is beneficial to ensure that the sub-pixels P in each row can get sufficient signal writing time, ensure the driving effect in the high-frequency driving mode, and improve the display quality.

[0118] It can be understood that, in specific implementation, the connection structure of the pixel circuit 10 of this embodiment includes but is not limited to the above structure and driving sequence, and may also be other connection structures and driving methods, which are not limited in this embodiment.

[0119] In some alternative embodiments, please refer to Fig.13 , Fig.13 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Fig.13The embodiment only takes a mobile phone as an example to illustrate the display device 111. It can be understood that the display device 111 provided in the embodiment of the present invention can be a computer, a television, a car display device or other display device 111 with a display function, and the present invention does not specifically limit this. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0120] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0121] The display panel of the present invention includes a plurality of sub-pixels, and the sub-pixels may include an electrically connected pixel circuit and a light-emitting element, and the pixel circuit is used to control the light-emitting element to emit light. In the display panel of the present invention, two data lines are included between two adjacent sub-pixel columns, and a plurality of sub-pixels in the same sub-pixel column are connected to the two data lines, and the two data lines electrically connected to the sub-pixels in the same sub-pixel column are named as the first data line and the second data line, respectively. The pixel circuit includes at least a driving transistor, a first data module and a second data module, and the first electrode of the driving transistor is connected to the first data line and the second data line through the first data module and the second data module, respectively. When the display panel is working, in the two data lines corresponding to the same sub-pixel column, the first data module can be used to write the data voltage signal provided by the first data line to the gate of the driving transistor, so that the driving transistor can generate a driving current for driving the light-emitting element according to the voltage of its gate and emit light in the light-emitting stage. The second data module writes the bias voltage signal provided by the second data line to the first electrode of the driving transistor, and controls the second data module to write the bias voltage signal to the first electrode of the driving transistor in the partial working stage of the pixel circuit to adjust the bias state of the driving transistor, improve the threshold drift problem of the driving transistor, and enhance the display effect. Furthermore, during the scanning drive process of the same sub-pixel, a data voltage signal can be written to the sub-pixel of the current sub-image row through the first data line, and the bias state of the driving transistor of the sub-pixel of the sub-image row can be adjusted through the second data module connected to the second data line, so that during the process of writing the data voltage signal to the sub-pixel of the current sub-image row through the first data line, sufficient charging time can be guaranteed, especially in the high-frequency driving mode with a high refresh frequency and a short row scanning time, the data writing of the sub-pixel can be guaranteed to have sufficient charging time, thereby enabling the data voltage signal to be written more fully, which is beneficial to improving the display quality of the display panel in the high-frequency driving mode.

[0122] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of sub-pixels, a plurality of scan lines and a plurality of data lines, wherein the scan lines and the data lines are cross-insulated and define an area where the sub-pixels are located; A plurality of the sub-pixels are arranged along a first direction to form a sub-pixel row, and a plurality of the sub-pixel rows are arranged along a second direction; a plurality of the sub-pixels are arranged along the second direction to form a sub-pixel column, and a plurality of the sub-pixel columns are arranged along the first direction; wherein the first direction and the second direction intersect; Two data lines are included between two adjacent sub-pixel columns, and a plurality of sub-pixels in the same sub-pixel column are connected to two data lines, which are respectively a first data line and a second data line; The sub-pixel includes a pixel circuit and a light-emitting element that are electrically connected; The pixel circuit at least includes a driving transistor, a first data module and a second data module; a first end of the first data module is connected to the first data line, and a second end of the first data module is connected to a first electrode of the driving transistor; a first end of the second data module is connected to the second data line, and a second end of the second data module is connected to the first electrode of the driving transistor; For the same sub-pixel column, the first data line is connected to the first electrode of the first selection transistor, and the second data line is connected to the first electrode of the second selection transistor; The second electrode of the first selection transistor is connected to the second electrode of the second selection transistor; The gate of the first selection transistor is connected to a first selection control signal, and the gate of the second selection transistor is connected to a second selection control signal; The second electrode of the driving transistor is connected to the anode of the light emitting element; The display panel further includes a plurality of bias selection modules, and one sub-pixel column is correspondingly connected to two bias selection modules, which are respectively a first bias selection module and a second bias selection module; The first data line is connected to a first end of the first bias selection module, and the second data line is connected to a first end of the second bias selection module; The second end of the first bias selection module and the second end of the second bias selection module are both connected to a bias voltage signal; The first bias selection module comprises a first bias selection transistor, a gate of the first bias selection transistor is connected to a third selection control signal, a first electrode of the first bias selection transistor is connected to the first data line, and a second electrode of the first bias selection transistor is connected to the bias voltage signal; The second bias selection module includes a second bias selection transistor, a gate of the second bias selection transistor is connected to a fourth selection control signal, a first electrode of the second bias selection transistor is connected to the second data line, and a second electrode of the second bias selection transistor is connected to the bias voltage signal.

2. The display panel according to claim 1, characterized in that: The first data module and the second data module of the same pixel circuit are not turned on at the same time.

3. The display panel according to claim 1, characterized in that: The first selection transistor and the second selection transistor are of the same type, and in the same time period, the first selection control signal and the second selection control signal have opposite polarities.

4. The display panel according to claim 1, characterized in that: The first selection transistor is of an opposite type to the second selection transistor, and a gate of the first selection transistor is connected to a gate of the second selection transistor.

5. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first light emitting control module, a second light emitting control module, a first reset module, a second reset module, and a threshold compensation module; A first end of the first light emitting control module is electrically connected to a first power signal line, and a second end of the first light emitting control module is electrically connected to a first electrode of the driving transistor; The first end of the second light emitting control module is electrically connected to the second electrode of the driving transistor, and the second end of the second light emitting control module is electrically connected to the anode of the light emitting element; A first end of the first reset module is electrically connected to a first reset signal line, and a second end of the first reset module is electrically connected to a gate of the driving transistor; A first end of the second reset module is electrically connected to a second reset signal line, and a second end of the second reset module is electrically connected to an anode of the light emitting element; A first end of the threshold compensation module is electrically connected to the gate electrode of the driving transistor, and a second end of the threshold compensation module is electrically connected to the second electrode of the driving transistor.

6. The display panel according to claim 5, characterized in that: The first light emitting control module comprises a first transistor, a gate of the first transistor is electrically connected to a first light emitting control signal line, a source of the first transistor is electrically connected to the first power supply signal line, and a drain of the first transistor is electrically connected to a first electrode of the driving transistor; The second light emitting control module comprises a second transistor, a gate of the second transistor is electrically connected to a second light emitting control signal line, a source of the second transistor is electrically connected to a second electrode of the driving transistor, and a drain of the second transistor is electrically connected to an anode of the light emitting element; The first data module comprises a third transistor, a gate of the third transistor is electrically connected to the first scan signal line, a source of the third transistor is electrically connected to the first data line, and a drain of the third transistor is electrically connected to the first electrode of the driving transistor; The second data module includes a fourth transistor, a gate of the fourth transistor is electrically connected to the second scan signal line, a source of the fourth transistor is electrically connected to the second data line, and a drain of the fourth transistor is electrically connected to the first electrode of the driving transistor; The threshold compensation module includes a fifth transistor, a gate of the fifth transistor is electrically connected to the third scan signal line, a source of the fifth transistor is electrically connected to the gate of the driving transistor, and a drain of the fifth transistor is electrically connected to the second electrode of the driving transistor; The first reset module includes a sixth transistor, a gate of the sixth transistor is electrically connected to the fourth scan signal line, a source of the sixth transistor is electrically connected to the first reset signal line, and a drain of the sixth transistor is electrically connected to the gate of the driving transistor; The second reset module includes a seventh transistor, a gate of the seventh transistor is electrically connected to the fifth scan signal line, a source of the seventh transistor is electrically connected to the second reset signal line, and a drain of the seventh transistor is electrically connected to the anode of the light emitting element.

7. The display panel according to claim 6, characterized in that: The fifth transistor and the sixth transistor are N-type metal oxide transistors, and the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the driving transistor are all P-type low-temperature polysilicon transistors.

8. The display panel according to claim 1, characterized in that: The first selection transistor and the first bias selection transistor are of the same type, and in the same time period, the polarities of the first selection control signal and the third selection control signal are opposite; The second selection transistor and the second bias selection transistor are of the same type, and in the same time period, the second selection control signal and the fourth selection control signal have opposite polarities.

9. A display device, characterized in that: A display panel comprising any one of claims 1 to 8.

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