Semiconductor Structure and Method for Forming the Same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. The method includes: sequentially forming first to third sacrificial layers on a substrate. The substrate includes a memory cell region and a peripheral region. The peripheral region includes a word line region. Remove the second and third sacrificial layers in the word line region to expose the top surface of the first sacrificial layer located in the word line region. Remove the first sacrificial layer in the word line region and the third sacrificial layer in the memory cell region. Form a word line dielectric layer on the substrate in the word line region. Form a first conductive layer on the word line dielectric layer. Remove the first and second sacrificial layers in the memory cell region. Form a tunneling dielectric layer on the substrate in the memory cell region. The thickness of the tunneling dielectric layer is less than the thickness of the word line dielectric layer. Form a floating gate layer on the tunneling dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure with a small peripheral region size and a method for forming the same. Background Art

[0002] Generally, electronic memories can be classified into volatile memories and non-volatile memories. Among non-volatile memories, flash memory has attracted wide attention due to its advantages such as low power consumption, low cost, and high reliability.

[0003] Generally, a flash chip can be divided into a memory cell area and a peripheral area. Currently, it is difficult to reduce the size of the peripheral area, and thus it is impossible to reduce the size of the flash chip. One of the reasons for the difficulty in reducing the peripheral area is that a charge pump for providing a voltage for flash memory cells needs to be provided in the peripheral area. Therefore, in the case where it is difficult to effectively reduce the size of the charge pump, it is also difficult to reduce the size of the peripheral area. Summary of the Invention

[0004] In view of the above problems, the present invention improves the voltage resistance of the word line structure unit in the word line area by providing a dielectric stack having an ONO (oxide-nitride-oxide) structure and arranging dielectric layers having a specific thickness relationship with each other in different regions. In the case where the overall flash chip needs to reach a specific voltage value, the word line structure unit disclosed by the present invention can withstand a larger voltage, so that the number of word line structure units can be reduced, that is, the area of the peripheral area occupied by the word line structure can be reduced, and further the size of the peripheral area can be reduced, thereby having better semiconductor structure characteristics.

[0005] According to some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes: forming a first sacrificial layer on a substrate. The substrate includes a memory cell region and a peripheral region. The peripheral region includes a word line region. Forming a second sacrificial layer on the first sacrificial layer. Forming a third sacrificial layer on the second sacrificial layer. Removing the third sacrificial layer and the second sacrificial layer in the word line region to expose the top surface of the first sacrificial layer located in the word line region. Removing the first sacrificial layer in the word line region and the third sacrificial layer in the memory cell region. Forming a word line dielectric layer on the substrate in the word line region. Forming a first conductive layer on the word line dielectric layer. Removing the second sacrificial layer in the memory cell region. Removing the first sacrificial layer in the memory cell region. Forming a tunneling dielectric layer on the substrate in the memory cell region. The thickness of the tunneling dielectric layer is less than the thickness of the word line dielectric layer. Forming a floating gate layer on the tunneling dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0007] Figures 1 to 19 FIG. is a cross-sectional schematic diagram showing the formation of a semiconductor structure at various stages according to some embodiments of the present invention.

[0008] Reference Numerals:

[0009] 1: Semiconductor structure

[0010] 100: Substrate

[0011] 110: First sacrificial layer

[0012] 120: Second sacrificial layer

[0013] 121: First hard mask layer

[0014] 122: Third sacrificial layer

[0015] 130: Isolation structure

[0016] 200: Word line dielectric layer

[0017] 300, 500: Conductive material

[0018] 310: First conductive layer

[0019] 400: Tunneling dielectric layer

[0020] 510: Floating gate layer

[0021] 511: Second hard mask layer

[0022] 600: Gate dielectric layer

[0023] 710: Gate layer

[0024] 800: Dielectric stack

[0025] 810: First sub-dielectric layer

[0026] 820: Second sub-dielectric layer

[0027] 830: Third sub-dielectric layer

[0028] 910: Control gate layer

[0029] 911: Second conductive layer

[0030] 920: Capping layer

[0031] BLA: Bit line area

[0032] CA: Memory cell area

[0033] DA: Device area

[0034] PA: Peripheral area

[0035] WLA: Word line area DETAILED DESCRIPTION

[0036] Figures 1 to 19 is a cross-sectional schematic diagram showing various stages of forming a semiconductor structure 1 according to some embodiments of the present invention.

[0037] Referring to Figure 1 , in some embodiments, a substrate 100 is provided. In some embodiments, the substrate 100 includes a memory cell area (CA) and a peripheral area (PA). In some embodiments, the peripheral area PA includes a device area (DA) of an electronic device, a word line area (WLA) of a word line, and a bit line area (BLA) of a bit line. In some embodiments, the device area DA is disposed between the word line area WLA and the memory cell area CA. In some embodiments, the word line area WLA is disposed between the device area DA and the bit line area BLA. However, the present invention is not limited thereto.

[0038] For ease of explanation, in the drawings of the present invention, each area is illustrated in a unit (cell) structure. For example, the structure in the word line area WLA can be referred to as a word line structure unit, and the structure in the bit line area BLA can be referred to as a bit line structure unit.

[0039] Reference Figure 2 A first sacrificial layer 110 is formed on a substrate 100, and a second sacrificial layer 120 is formed on the first sacrificial layer 110. In some embodiments, the first sacrificial layer 110 and / or the second sacrificial layer 120 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable materials, but the present invention is not limited thereto. The first sacrificial layer 110 and / or the second sacrificial layer 120 may be formed by a deposition process.

[0040] As Figure 2 shown, in some embodiments, a first hard mask layer 121 may be further formed on the second sacrificial layer 120 to perform subsequent etching processes using the first hard mask layer 121 as an etching mask. In some embodiments, the first hard mask layer 121 may be obtained by CVD deposition or other suitable processes. In some embodiments, the first hard mask layer 121 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof.

[0041] In some embodiments, after forming the first hard mask layer 121 on the second sacrificial layer 120, a photoresist layer may be formed on the first hard mask layer 121 and exposed according to requirements to obtain a patterned photoresist layer. Then, using the aforementioned patterned photoresist layer as an etching mask, the first hard mask layer 121 is etched to form a patterned first hard mask layer 121.

[0042] Reference Figure 3 As shown, in some embodiments, then using the aforementioned patterned first hard mask layer 121 as an etching mask, the second sacrificial layer 120, the first sacrificial layer 110, and the substrate 100 are etched to form trenches in the substrate 100, the first sacrificial layer 110, and the second sacrificial layer 120, and the active area in the semiconductor structure of the present invention is defined through the aforementioned steps. In some embodiments, the etched first sacrificial layer 110 and the second sacrificial layer 120 are penetrated, while the substrate 100 is not penetrated. It can be understood that the depth of etching the substrate 100 can be adjusted according to requirements. In some embodiments, based on different etching parameters, the trenches in the memory cell region CA may be U-shaped trenches, while the trenches in the peripheral region PA may be concave trenches. In some embodiments, the spacing between the trenches in the memory cell region CA may be smaller than the spacing between the trenches in the peripheral region PA. Therefore, the relative dimensions of the trenches as shown Figure 3 are only illustrative and not restrictive.

[0043] Reference Figure 4, before forming a third sacrificial layer on the second sacrificial layer 120 subsequently, an isolation structure 130 is formed on the substrate 100 and in the aforementioned trenches, so that the isolation structure 130 is located in the substrate 100, the first sacrificial layer 110, and the second sacrificial layer 120.

[0044] In some embodiments, the step of forming the isolation structure 130 on the substrate 100 may further include: filling the aforementioned trenches with an isolation material layer; and performing a planarization process to make the top surface of the isolation material layer substantially coplanar with the top surface of the second sacrificial layer 120, thereby forming the isolation structure 130 on the substrate 100. In some embodiments, the isolation structure 130 may be a shallow trench isolation structure. In some embodiments, the isolation structure 130 may include different isolation materials to fill trenches with different aspect ratios respectively.

[0045] Refer to Figure 5 , a third sacrificial layer 122 is formed on the second sacrificial layer 120. Specifically, the third sacrificial layer 122 is formed on the second sacrificial layer 120 and the isolation structure 130. In some embodiments, the third sacrificial layer 122 and the first sacrificial layer 120 may include the same or different materials. In some embodiments, the third sacrificial layer 122 may include an oxide formed using tetraethoxysilane (TEOS) as a precursor. In some embodiments, the thicknesses of the third sacrificial layer 122 and the first sacrificial layer 120 may be substantially the same.

[0046] Refer to Figure 6 , the second sacrificial layer 120 and the third sacrificial layer 122 in the word line area WLA are removed to expose the upper surface of the first sacrificial layer 110 in the word line area WLA. In some embodiments, the second sacrificial layer 120 and the third sacrificial layer 122 in the word line area WLA are removed by photolithography and etching processes. For example, in some embodiments, a patterned photoresist layer may be formed first to cover the memory cell area CA, the device area DA, and the bit line area BLA and expose the word line area WLA. Then, the third sacrificial layer 122 in the word line area WLA is removed by wet etching. Similarly, a patterned photoresist layer may be formed again to cover the memory cell area CA, the device area DA, the bit line area BLA, and the isolation structure 130 in the word line area WLA and expose the second sacrificial layer 120 in the word line area WLA. Then, the second sacrificial layer 120 in the word line area WLA is removed.

[0047] Refer to Figure 7, the first sacrificial layer 110 in the word line region WLA and the third sacrificial layer 122 in the memory cell region CA, device region DA, and bit line region BLA are removed. In some embodiments, since the thicknesses of the first sacrificial layer 110 and the third sacrificial layer 122 can be substantially the same, the step of removing the first sacrificial layer 110 in the word line region WLA and the step of removing the third sacrificial layer 122 in the memory cell region CA, device region DA, and bit line region BLA can be performed in the same process, thereby simultaneously exposing the top surface of the substrate 100 in the word line region WLA and the top surfaces of the isolation structure 130 and the second sacrificial layer 120 in the regions other than the word line region WLA, so that the process cost can be saved.

[0048] Refer to Figure 8 , a word line dielectric layer 200 is formed on the substrate 100 in the word line region WLA. In some embodiments, the word line dielectric layer 200 can be formed by a thermal oxidation process. In some embodiments, the thickness of the word line dielectric layer 200 is determined based on the expected breakdown voltage of the word line region WLA. For example, if the expected breakdown voltage of the word line region WLA is higher, the thickness of the word line dielectric layer 200 is thicker. In some embodiments, the thickness of the word line dielectric layer 200 can be 10 nm to 20 nm. In some embodiments, the word line dielectric layer 200 is formed on the substrate 100 in the word line region WLA by APCVD. In some embodiments, the word line dielectric layer 200 can be or can include an oxide, a nitride, a nitrogen oxide, a combination thereof, or any other suitable dielectric material, but the present invention is not limited thereto. In some embodiments, the thickness of the word line dielectric layer 200 can be greater than the thickness of the first sacrificial layer 110.

[0049] Refer to Figure 9 , a conductive material 300 is formed on the substrate 100. Specifically, the conductive material 300 is formed on the isolation structure 130, the second sacrificial layer 120, and the word line dielectric layer 200. In some embodiments, in the word line region WLA, since the top surface of the isolation structure 130 is higher than the top surface of the word line dielectric layer 200, that is, the top surface of the isolation structure 130 is farther from the substrate 100 compared to the top surface of the word line dielectric layer 200, a trench is formed. When the conductive material 300 is formed in the aforementioned trench, a recess may be generated. Therefore, in order to increase the reliability of the semiconductor structure of the present invention, it is necessary to ensure that the bottom surface of the recess is higher than the top surface of the isolation structure 130 to form a conductive layer with good electrical properties. In some embodiments, the conductive material 300 can include polycrystalline silicon, amorphous silicon, a metal, a metal nitride, a conductive metal oxide, a combination thereof, or other suitable materials, but the present invention is not limited thereto.

[0050] Referring to Figure 10 , a planarization process is performed to remove the first conductive material located on the memory cell region CA, the device region DA, and the bit line region BLA, and to make the top surface of the first conductive material in the word line region WLA substantially coplanar with the top surface of the isolation structure 130, and a first conductive layer 310 is formed on the word line dielectric layer 200 in the word line region WLA.

[0051] Referring to Figure 11 , the second sacrificial layer 120 located in the memory cell region CA is removed to expose the first sacrificial layer 110 located in the memory cell region CA. In some embodiments, the second sacrificial layer 120 located in the device region DA and the bit line region BLA may be further removed in the step of removing the second sacrificial layer 120 located in the memory cell region CA. In other words, the step of removing the second sacrificial layer 120 located in the memory cell region CA and the step of removing the second sacrificial layer 120 located in the device region DA and the bit line region BLA may be performed in the same process. In some embodiments, the removal may be performed by an etching process. In some embodiments, the process of removing the second sacrificial layer 120 located in the memory cell region CA may be the same as or different from the process of removing the second sacrificial layer 120 located in the word line region WLA. In some embodiments, specifically, a patterned photoresist layer may be formed to cover the word line region WLA and expose the memory cell region CA, the device region DA, and the bit line region BLA. Then, the second sacrificial layer 120 located in the memory cell region CA, the device region DA, and the bit line region BLA is removed to expose the first sacrificial layer 110 located in the memory cell region CA, the device region DA, and the bit line region BLA.

[0052] Referring to Figure 12 , the first sacrificial layer 110 located in the memory cell region CA is removed to expose the top surface of the substrate 100 located in the memory cell region CA. In some embodiments, the first sacrificial layer 110 located in the bit line region BLA may be further removed in the step of removing the first sacrificial layer 110 located in the memory cell region CA. In other words, the step of removing the first sacrificial layer 110 located in the memory cell region CA and the step of removing the first sacrificial layer 110 located in the bit line region BLA may be performed in the same process. In some embodiments, specifically, a patterned photoresist layer may be formed to cover the word line region WLA and the device region DA and expose the memory cell region CA and the bit line region BLA. Then, the first sacrificial layer 110 located in the memory cell region CA and the bit line region BLA is removed to expose the substrate 100 located in the memory cell region CA and the bit line region BLA.

[0053] Referring to Figure 13 , a tunneling dielectric layer 400 is formed on a substrate 100 in a memory cell region CA. In some embodiments, the tunneling dielectric layer 400 may be formed on the substrate 100 in the memory cell region CA and a peripheral region PA. Specifically, the tunneling dielectric layer 400 may be formed on the substrate 100 in the memory cell region CA, on a first sacrificial layer 110 in a device region DA, on an isolation structure 130 and a first conductive layer 310 in a word line region WLA, and on the substrate 100 in a bit line region BLA. That is, the tunneling dielectric layer 400 may extend into the bit line region BLA. In some embodiments, the tunneling dielectric layer 400 may be formed by a thermal oxidation process. In some embodiments, the thickness of the tunneling dielectric layer 400 is less than the thickness of the word line dielectric layer 200. In some embodiments, the thickness of the tunneling dielectric layer 400 may be 8 nm to 12 nm. In some embodiments, the thickness ratio of the word line dielectric layer 200 to the tunneling dielectric layer 400 is 1.25 to 1.67. In some embodiments, through the above process, the dielectric layer thicknesses in different regions of the semiconductor structure of the present invention may be different. For example, the tunneling dielectric layer 400 in the memory cell region CA has a relatively thin thickness capable of rapid response, and the word line dielectric layer 200 in the word line region WLA has a relatively thick thickness capable of withstanding high voltage.

[0054] Next, in some embodiments, a conductive material 500 is formed on the substrate 100. Specifically, the conductive material 500 is formed on the isolation structure 130 and the tunneling dielectric layer 400 in the memory cell region CA and the peripheral region PA. In some embodiments, in the memory cell region CA, since the top surface of the isolation structure 130 is higher than the top surface of the tunneling dielectric layer 400, that is, the top surface of the isolation structure 130 is farther from the substrate 100 than the top surface of the tunneling dielectric layer 400, a trench is formed. When forming the conductive material 500 in the foregoing trench, recesses may be generated. Therefore, in order to increase the reliability of the semiconductor structure of the present invention, it is necessary to ensure that the bottom surface of the recess is higher than the top surface of the isolation structure 130 to form a conductive layer with good electrical properties. In some embodiments, the reliability of the conductive layer in the device region DA and the bit line region BLA is similarly ensured. In some embodiments, the conductive material 500 may be the same as or different from the first conductive material. The conductive material 500 may be or may include polysilicon, amorphous silicon, metal, metal nitride, conductive metal oxide, a combination thereof, or other suitable materials, but the present invention is not limited thereto.

[0055] Referring to Figure 14, a planarization process is performed such that the top surface of the second conductive material in the memory cell region CA is substantially coplanar with the top surface of the isolation structure 130, and a floating gate layer 510 is formed on the tunneling dielectric layer 400 in the memory cell region CA. In some embodiments, performing the foregoing planarization process further includes removing the second conductive material and the tunneling dielectric layer 400 located in the word line region WLA to expose the top surface of the first conductive layer 310 in the word line region WLA.

[0056] Referring to Figure 15 , a second hard mask layer 511 is formed in the memory cell region CA, the word line region WLA, and the bit line region BLA. Specifically, the second hard mask layer 511 is formed on the floating gate layer 510 in the memory cell region CA, on the first conductive layer 310 in the word line region WLA, and on the floating gate layer 510 in the bit line region BLA to expose the device region DA. In some embodiments, the second hard mask layer 511 and the first hard mask layer 121 may be the same or different. In some embodiments, the second hard mask layer 511 may include an oxide, a nitride, a oxynitride, a carbide, or a combination thereof. In some embodiments, the second hard mask layer 511 may include an oxide formed using tetraethyl orthosilicate as a precursor and silicon nitride, and the oxide formed using tetraethyl orthosilicate as a precursor is closer to the substrate 100 than the silicon nitride.

[0057] Next, using the second hard mask 511 as an etching mask, the floating gate layer 510 in the device region DA is removed, and a part of the isolation structure 130 in the device region is removed. In some embodiments, the top surface of the removed isolation structure 130 in the device region DA is higher than the top surface of the tunneling dielectric layer 400.

[0058] Referring to Figure 16 , continuing from the above, using the second hard mask 511 as an etching mask, the tunneling dielectric layer 400 and the first sacrificial layer 110 in the device region DA are removed to expose the substrate 100 in the device region.

[0059] Referring to Figure 17, a gate dielectric layer 600 is formed on a substrate 100 in a device region DA, and a gate layer 710 is formed on the gate dielectric layer 600 through a conductive material. In some embodiments, the gate dielectric layer 600 may include an oxide, a nitride, a nitroxide, a high-k material, a combination thereof, or any other suitable dielectric material, but the present invention is not limited thereto. In some embodiments, the process of forming the gate dielectric layer 600 is similar to the aforementioned process of forming the floating gate layer 510. In one embodiment, a further process may be performed to make the structure in the device region DA serve as a transistor disposed within the device region DA. In some embodiments, the thickness of the gate dielectric layer 600 is determined based on the operating requirements of the transistors to be formed subsequently. In some embodiments, the thickness of the gate dielectric layer 600 may be 12 nm to 20 nm. In some embodiments, the thickness of the gate dielectric layer 600 is different from the thicknesses of the word line dielectric layer 200 and the tunneling dielectric layer 400.

[0060] Referring to Figure 18 , the second hard mask 511 is removed, and a portion of the isolation structure 130 in the memory cell region CA, the word line region WLA, and the bit line region BLA is removed. In some embodiments, a portion of the isolation structure 130 is removed such that the top surface of the isolation structure 130 in the memory cell region CA is between the top surface of the tunneling dielectric layer 400 and the top surface of the floating gate layer 510; such that the top surface of the isolation structure 130 in the word line region WLA is between the top surface of the word line dielectric layer 200 and the top surface of the first conductive layer 310; and such that the top surface of the isolation structure 130 in the bit line region BLA is between the top surface of the tunneling dielectric layer 400 and the top surface of the floating gate layer 510. Then, a dielectric stack 800 is conformally formed on the substrate 100. Specifically, the dielectric stack 800 is formed on the isolation structure 130 and the floating gate layer 510 in the memory cell region CA; the dielectric stack 800 is formed on the gate layer 710 in the device region DA; the dielectric stack 800 is formed on the isolation structure 130 and the word line dielectric layer 200 in the word line region WLA; and the dielectric stack 800 is formed on the isolation structure 130 and the floating gate layer 510 in the bit line region BLA.

[0061] In some embodiments, the dielectric stack 800 in the memory cell region CA, the word line region WLA, and the bit line region BLA includes a convex structure protruding away from the substrate. Therefore, compared with the dielectric stack 800 disposed on the isolation structure 130, the dielectric stack 800 disposed on the floating gate layer 510 in the memory cell region CA and the bit line region BLA, and the dielectric stack 800 disposed on the first conductive layer 310 in the word line region WLA are further away from the substrate 100.

[0062] AsFigure 18 As shown, the dielectric stack 800 includes a first sub-dielectric layer 810, a second sub-dielectric layer 820, and a third sub-dielectric layer 830. In some embodiments, the step of forming the dielectric stack 800 may further include forming the first sub-dielectric layer 810 on the isolation structure 130, the first conductive layer 310, the floating gate layer 510, and the gate layer 710; forming the second sub-dielectric layer 820 on the first sub-dielectric layer 810; and forming the third sub-dielectric layer 830 on the second sub-dielectric layer 820. In some embodiments, the dielectric stack 800 may include layers of different materials. In some embodiments, the dielectric layer stack 800 may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable materials, but the present invention is not limited thereto. In some embodiments, the first sub-dielectric layer 810 and the third sub-dielectric layer 830 include oxides, and the second sub-dielectric layer 820 includes nitrides, so the semiconductor structure of the present invention may have an oxide-nitride-oxide ONO structure.

[0063] Referring to Figure 19 , the dielectric stack 800 located in the device region DA is removed, and a control gate layer 910 is formed on the dielectric stack 800 in the memory cell region CA. In some embodiments, the control gate layer 910 may include or be polysilicon, amorphous silicon, metal, metal nitride, conductive metal oxide, combinations thereof, or other suitable materials.

[0064] In some embodiments, a second conductive layer 911 is further formed on the dielectric stack 800 in the word line region WLA. The material of the control gate layer 910 may be the same as or different from that of the second conductive layer 911. In some embodiments, the step of forming the control gate layer 910 and the step of forming the second conductive layer 911 may be performed in the same process. In other words, the material of the control gate layer 910 may be the same as the material of the second conductive layer 911. In some embodiments, a capping layer 920 is further formed on the control gate layer 910 in the memory cell region CA and the bit line region BLA, on the gate layer 710 in the device region DA, and on the second conductive layer 911 in the word line region WLA, to protect all components disposed under the capping layer 920, so as to obtain the semiconductor structure 1 of the present invention. In some embodiments, the capping layer 920 may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable materials.

[0065] It should be particularly noted that, in some embodiments, the first conductive layer 310 and the second conductive layer 911 located in the word line region WLA, and the floating gate layer 510 and the control gate layer 910 located in the bit line region BLA may be used as wirings of the memory chip to provide electrical connections between various components.

[0066] In summary, the semiconductor structure of the present invention includes a dielectric layer stack that is an ONO structure, and the ONO structure further includes a convex structure protruding away from the substrate, so that the breakdown voltage can be effectively improved. Furthermore, the semiconductor structure of the present invention includes dielectric layers disposed in different regions and having a specific thickness relationship with each other, so that the electrical characteristics of different regions can be adjusted.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: forming a first sacrificial layer on a substrate, wherein the substrate includes a memory cell region and a peripheral region, and the peripheral region includes a word line region; forming a second sacrificial layer on the first sacrificial layer; forming a third sacrificial layer on the second sacrificial layer; removing the third sacrificial layer and the second sacrificial layer in the word line region to expose the top surface of the first sacrificial layer in the word line region; removing the first sacrificial layer in the word line region and the third sacrificial layer in the memory cell region; forming a word line dielectric layer on the substrate in the word line region; forming a first conductive layer on the word line dielectric layer; removing the second sacrificial layer in the memory cell region; removing the first sacrificial layer in the memory cell region; forming a tunneling dielectric layer on the substrate in the memory cell region, wherein the thickness of the tunneling dielectric layer is less than the thickness of the word line dielectric layer; and forming a floating gate layer on the tunneling dielectric layer.

2. The forming method according to claim 1, characterized in that: the step of forming the tunneling dielectric layer on the substrate in the memory cell region further includes: forming the tunneling dielectric layer on the first conductive layer in the word line region; the step of forming the floating gate layer on the tunneling dielectric layer further includes: forming the floating gate layer on the tunneling dielectric layer in the word line region; and the forming method includes: removing the floating gate layer and the tunneling dielectric layer in the word line region to expose the top surface of the first conductive layer.

3. The forming method according to claim 1, characterized in that, before forming the third sacrificial layer on the second sacrificial layer, forming an isolation structure on the substrate, and the isolation structure is located in the substrate, the first sacrificial layer and the second sacrificial layer, and the third sacrificial layer is formed on the second sacrificial layer and the isolation structure, and the forming method further includes: removing a part of the isolation structure; forming a dielectric stack on the isolation structure, the first conductive layer and the floating gate layer, so that the dielectric stack disposed on the first conductive layer and the floating gate layer is farther from the substrate than the dielectric stack disposed on the isolation structure; forming a control gate layer on the dielectric stack in the memory cell region; and forming a second conductive layer on the dielectric stack in the word line region.

4. The forming method according to claim 3, characterized in that: the peripheral region further includes a device region, and the device region is between the word line region and the memory cell region; the step of removing the second sacrificial layer in the memory cell region further includes: removing the second sacrificial layer in the device region; and The step of forming the tunneling dielectric layer on the substrate in the memory cell region further includes: forming the tunneling dielectric layer on the first sacrificial layer in the device region.

5. The forming method according to claim 4, wherein, it further includes: removing a part of the floating gate layer and the isolation structure in the device region; removing the tunneling dielectric layer and the first sacrificial layer in the device region; forming a gate dielectric layer on the substrate in the device region; forming a gate layer on the gate dielectric layer.

6. The forming method according to claim 5, wherein, the thickness of the gate dielectric layer is different from the thickness of the word line dielectric layer and the tunneling dielectric layer.

7. The forming method according to claim 3, wherein, in the step of removing the part of the isolation structure, the top surface of the isolation structure in the word line region is between the top surface of the word line dielectric layer and the top surface of the first conductive layer, and the top surface of the isolation structure in the memory cell region is between the top surface of the tunneling dielectric layer and the top surface of the floating gate layer.

8. A semiconductor structure, wherein, it includes: a substrate, the substrate includes a memory cell region and a peripheral region, and the peripheral region includes a word line region; a word line dielectric layer disposed on the substrate in the word line region; a tunneling dielectric layer disposed on the substrate in the memory cell region, wherein the thickness of the tunneling dielectric layer is less than the thickness of the word line dielectric layer; an isolation structure disposed on the substrate, and the top surface of the isolation structure is higher than the top surfaces of the word line dielectric layer and the tunneling dielectric layer; a first conductive layer disposed on the word line dielectric layer; and a floating gate layer disposed on the tunneling dielectric layer, wherein, the peripheral region further includes a bit line region, and the tunneling dielectric layer extends to the bit line region.

9. The semiconductor structure according to claim 8, wherein, the top surface of the isolation structure in the word line region is lower than the top surface of the first conductive layer, and the top surface of the isolation structure in the memory cell region is lower than the top surface of the floating gate layer.

10. The semiconductor structure according to claim 8, wherein, it further includes: a dielectric stack disposed on the isolation structure, the first conductive layer and the floating gate layer, and the dielectric stack disposed on the first conductive layer and the floating gate layer is farther from the substrate than the dielectric stack disposed on the isolation structure; a control gate layer disposed on the dielectric stack in the memory cell region; and a second conductive layer disposed on the dielectric stack in the word line region.

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