Image sensor using an avalanche diode

Abstract

An image sensor using an avalanche diode, comprising a plurality of pixel circuits arranged in an array, a plurality of pull-back circuits, and a global current source circuit. Each of the plurality of pixel circuits includes a single-photon avalanche diode and four P-type or N-type transistors. Each of the plurality of pull-back circuits is configured corresponding to one column of pixel circuits. The global current source circuit is used to form a current mirror with each of the plurality of pull-back circuits.

Description

[0001] This application is a divisional application of a Chinese invention patent application with the application number 201911023484.6, the application date of October 25, 2019, and the title of "Image Sensor Using Avalanche Diode". Technical Field

[0002] The present invention relates to a photon detection technology, and more particularly to an image sensor using a single photon avalanche diode in a pixel circuit, and the quenching and reading circuits of the single photon avalanche diode have a low minimum pixel unit limit and a high fill factor. Background Art

[0003] Single photon detection is a good choice when dealing with low light environments and high frequency optical signals.

[0004] For example, a single photon avalanche diode (SPAD) can be used as a weak light detector, which has the advantages of high avalanche gain, fast response speed, and low power consumption. When each photon is received by the SPAD, an avalanche current is activated to indicate that a photon has been detected. The pulse caused by the avalanche current can be regarded as an event.

[0005] However, the single photon avalanche diode cannot complete quenching spontaneously, so it needs to be paired with a quenching circuit in its operation to quickly pull the bias voltage of the single photon avalanche diode below the breakdown voltage to quench the avalanche after the avalanche occurs, and then quickly pull it back above the breakdown voltage to restore the single photon avalanche diode to the state of waiting for photons to be detected.

[0006] One of the basic requirements of the quenching circuit is not to reduce the fill factor.

[0007] A known method is to independently form a three-dimensional stacked quenching circuit outside the pixel circuit. Since the pixel circuit and the quenching circuit are configured on different chips, the influence on the fill factor can be reduced.

[0008] Another known method is to use a logic circuit composed of P-type and N-type transistors to implement the quenching circuit. However, when using such a quenching circuit, two negative well regions (NWELL) with different potentials need to be fabricated within a single pixel unit. Based on design rules checking, there should be a minimum distance between the negative well regions with different potentials, which thus results in a limitation of the minimum pixel size.

[0009] In view of this, a quenching circuit for a single photon avalanche diode with a low minimum pixel unit limit and a high fill factor is indeed required. Summary of the Invention

[0010] The present invention provides an image sensor using a single photon avalanche diode in each pixel circuit, and the single photon avalanche diode has a low pixel size limit and a high fill factor.

[0011] The present invention provides an image sensor using a single photon avalanche diode, which includes a pixel array and a plurality of pull-back circuits. The pixel array includes a plurality of pixel circuits arranged in an array. Each of the plurality of pixel circuits includes an avalanche diode, a resistive transistor, a first switching transistor, a pull-down transistor, and a second switching transistor. The avalanche diode has an anode and a cathode, and the cathode is connected to a positive bias source. The drain of the resistive transistor is connected to the anode of the avalanche diode, and the gate of the resistive transistor is used to receive a fixed voltage signal. The drain of the first switching transistor is connected to the source of the resistive transistor, the gate of the first switching transistor receives an exposure signal, and the source of the first switching transistor is connected to a ground voltage. The gate of the pull-down transistor is connected to the anode of the avalanche diode, and the source of the pull-down transistor is connected to the ground voltage. The gate of the second switching transistor receives the exposure signal, the source of the second switching transistor is connected to the drain of the pull-down transistor, and the drain of the second switching transistor is used to generate an output voltage. Each of the plurality of pull-back circuits is arranged corresponding to a column of pixel circuits and includes a P-type transistor. The drain of the P-type transistor is used to read out the output voltage by connecting to the drain of the second switching transistor of each of the pixel circuits in the column through a read line. The source of the P-type transistor is connected to a system voltage, the gate of the P-type transistor receives a control signal, and the P-type transistor raises the output voltage after a photon event of reading out the output voltage. Wherein, the resistive transistor, the first switching transistor, the pull-down transistor, and the second switching transistor are N-type transistors.

[0012] The present invention also provides an operating method for an image sensor using a single photon avalanche diode. The operating method includes the following steps: turning on the resistive transistor with the fixed voltage signal at a first time; turning on the first switching transistor and the second switching transistor with the exposure signal at a second time to make the avalanche diode enter a state to be detected; and when the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-down transistor to generate a negative spike at the drain of the second switching transistor as a photon event of the output voltage.

[0013] The present invention also provides an image sensor using a single-photon avalanche diode, which image sensor includes a pixel array and a plurality of pull-back circuits. The pixel array includes a plurality of pixel circuits arranged in an array. Each of the plurality of pixel circuits includes an avalanche diode, a resistance transistor, a first switching transistor, a pull-up transistor, and a second switching transistor. The avalanche diode includes an anode and a cathode, and the anode is connected to a negative bias voltage source. The drain of the resistance transistor is connected to the cathode of the avalanche diode, and the gate of the resistance transistor is used to receive a fixed voltage signal. The drain of the first switching transistor is connected to the source of the resistance transistor, the gate of the first switching transistor receives an exposure signal, and the source of the first switching transistor is connected to a system voltage. The gate of the pull-up transistor is connected to the cathode of the avalanche diode, and the source of the pull-up transistor is connected to the system voltage. The gate of the second switching transistor receives the exposure signal, the source of the second switching transistor is connected to the drain of the pull-up transistor, and the drain of the second switching transistor is used to generate an output voltage. Each of the plurality of pull-back circuits is disposed corresponding to a column of pixel circuits and includes an N-type transistor. The drain of the N-type transistor is used to connect to the drain of the second switching transistor of each of the pixel circuits in the corresponding column through a read line to read out the output voltage. The source of the N-type transistor is connected to a ground voltage, the gate of the N-type transistor receives a control signal, and the N-type transistor pulls down the output voltage after a photon event of reading out the output voltage. Wherein, the resistance transistor, the first switching transistor, the pull-up transistor, and the second switching transistor are P-type transistors.

[0014] The present invention also provides an operating method for an image sensor using a single-photon avalanche diode, which operating method includes the following steps: turning on the resistance transistor with the fixed voltage signal at a first time; turning on the first switching transistor and the second switching transistor with the exposure signal at a second time to make the avalanche diode enter a state to be detected; and when the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-up transistor, so as to generate a positive spike at the drain of the second switching transistor as a photon event of the output voltage.

[0015] The present invention also provides an image sensor including a pixel array and a plurality of pull-back circuits. The pixel array includes a plurality of pixel circuits arranged in an array. Each of the plurality of pixel circuits includes an avalanche diode, a first transistor, and a second transistor, wherein the avalanche diode is connected to the gate of the first transistor, and the second transistor is connected between the drain of the first transistor and the read line. Each of the plurality of pull-back circuits is disposed corresponding to a column of pixel circuits and includes a P-type transistor. The drain of the P-type transistor is used to couple to the drain of the second transistor of each of the pixel circuits in the column through the read line to read out an output voltage. The source of the P-type transistor is connected to a system voltage, the gate of the P-type transistor receives a control signal, and the P-type transistor raises or lowers the output voltage after a photon event of reading out the output voltage, wherein the first transistor and the second transistor are N-type transistors.

[0016] In the quenching and reading circuit of the single-photon avalanche diode according to the embodiment of the present invention, only N-type or P-type transistors are used in each pixel, so there is only a single negative well region in each pixel.

[0017] In the image sensor according to the embodiment of the present invention, since the pull-back circuit is disposed outside each pixel circuit, it does not cause a limitation on the minimum pixel unit and does not affect the fill factor.

[0018] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following will be described in detail in conjunction with the accompanying drawings. In addition, in the description of the present invention, the same components are denoted by the same reference numerals, which are stated herein in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of an image sensor according to a first embodiment of the present invention;

[0020] Figure 2 is an operation timing diagram of the image sensor according to the first embodiment of the present invention;

[0021] Figure 3 is an operation flowchart of the image sensor according to the first embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of an image sensor according to a second embodiment of the present invention;

[0023] Figure 5 is an operation timing diagram of the image sensor according to the second embodiment of the present invention;

[0024] Figure 6 is an operation flowchart of the image sensor according to the second embodiment of the present invention;

[0025] Figure 7Schematic diagram of the image sensor according to the third embodiment of the present invention;

[0026] Figure 8 is the operation timing diagram of the image sensor according to the third embodiment of the present invention.

[0027] Description of reference numerals

[0028] 100 Image sensor

[0029] 11 Pixel array

[0030] 111 Pixel circuit

[0031] 12 Pull-back circuit

[0032] 13 Counter

[0033] 14 Row decoder

[0034] 15 Column decoder

[0035] 16 Global current source circuit Detailed implementation manners

[0036] Please refer to Figure 1 as shown, which is a schematic diagram of the image sensor 100 according to the first embodiment of the present invention. The image sensor 100 is used to detect extremely weak light and high-frequency signals, so single-photon avalanche diodes are used to detect photon events. By counting the photon events of each pixel, the processor can generate an image frame for object tracking, gesture recognition, three-dimensional image construction, physiological feature detection and recognition, etc.

[0037] The image sensor 100 includes a pixel array 11, a plurality of pull-back circuits 12, a plurality of counters 13, a row decoder 14, a column decoder 15, and a global current source circuit 16; wherein, the row decoder 14 and the column decoder 15 are used to determine the pixel positions in the pixel array 11 for exposure and output detection signals (such as the surges described later). The operation modes of the row decoder 14 and the column decoder 15 are already known and are not the main inventive objectives of the present invention, so they will not be described in detail here.

[0038] The pixel array 11 includes a plurality of pixel circuits 111 ( Figure 1 illustrated by taking 16×16 pixels as an example) arranged in an array. Each of the plurality of pixel circuits 111 includes an avalanche diode SPAD and four N-type transistors, namely a resistor transistor NM1, a first switching transistor NM0, a pull-down transistor NM3, and a second switching transistor NM2.

[0039] An avalanche diode SPAD is a single photon avalanche diode, which has an anode and a cathode. The cathode is connected to a positive bias voltage source VA, taking +15V as an example here, but not limited thereto. The anode is connected to node SN. When the potential difference (or bias voltage) between the cathode and the anode exceeds the breakdown voltage of the avalanche diode SPAD, a breakdown current Ia can be generated. In the first embodiment, the resistance transistor NM1 and the first switching transistor NM0 of the pixel circuit 111 are used to form a quenching circuit, so that when the avalanche diode SPAD generates the breakdown current Ia, the potential difference between the cathode and the anode is lower than the breakdown voltage for quenching; the pull-down transistor NM3 and the second switching transistor NM2 of the pixel circuit 111 are used to form a reading circuit to read the output voltage of the pixel circuit 111 to the corresponding column counter 13.

[0040] The drain of the resistance transistor NM1 is connected to node SN to connect the anode of the avalanche diode SPAD. The gate of the resistance transistor NM1 is used to receive a fixed voltage signal VQ to be turned on or off by it. In the first embodiment, the resistance transistor NM1 is used to form a controllable resistance, and its resistance value is determined according to the voltage value of the fixed voltage signal VQ. When the avalanche diode SPAD receives photons in the state to be detected and the first switching transistor NM0 is turned on, a voltage drop is generated on the resistance transistor NM1, so that the potential difference between the anode and the cathode of the avalanche diode SPAD is less than the breakdown voltage for quenching.

[0041] The drain of the first switching transistor NM0 is connected to the source of the resistance transistor NM1. The gate of the first switching transistor NM0 receives an exposure signal RS, which is, for example, a row selection signal, which is, for example, generated by a row decoder 14. The source of the first switching transistor NM0 is connected to the ground voltage.

[0042] The gate of the pull-down transistor NM3 is connected to node SN to connect the anode of the avalanche diode SPAD. The source of the pull-down transistor NM3 is connected to the ground voltage. The pull-down transistor NM3 is used as a discharge path for the voltage on node SN, and its discharge rate is determined according to the resistance value of the resistance transistor NM1 and the stray capacitance of the circuit. The resistance value and the stray capacitance are values that can be determined during circuit fabrication.

[0043] The gate of the second switching transistor NM2 also receives the exposure signal RS to be controlled by it and open and close simultaneously with the first switching transistor NM0. The source of the second switching transistor NM2 is connected to the drain of the pull-down transistor NM3. The drain of the second switching transistor NM2 is used to generate the output voltage of the relevant pixel circuit 111.

[0044] Each of the plurality of pull-back circuits 12 is used to read out the output voltage by connecting to the drain of the second switching transistor NM2 of each of the pixel circuits 111 in a column through the read line Rd. The image sensor 100 also includes, for example, a multiplexer (MUX) or a plurality of switching elements for connecting the pull-back circuits 12 corresponding to each column of pixel circuits to different pixel circuits 111 through the multiplexer or different switching elements respectively. In the first embodiment, each of the pull-back circuits 12 includes a P-type transistor PM0 for pulling up the output voltage after a spike in the read-out output voltage (illustrated later). The drain of the P-type transistor PM0 is connected to the drain of the second switching transistor NM2. The source of the P-type transistor PM0 is connected to the system voltage VDD, which may be the same as or different from the positive bias source VA. The gate of the P-type transistor PM0 receives the control signal VB.

[0045] The global current source circuit 16 is used to form a current mirror with each of the plurality of pull-back circuits 12. Only one global current source circuit 16 is provided in the image sensor 100. For example, the image sensor 100 also includes a multiplexer or a plurality of switching elements for connecting the global current source circuit 16 to different pull-back circuits 12 through the multiplexer or different switching elements. The global current source circuit 16 includes a P-type transistor, the drain and gate of which are connected and connected to the global current source, and the source of which is connected to the system voltage VDD.

[0046] Each of the plurality of counters 13 is coupled to a column of pixel circuits for counting the photon events of the output voltage of each pixel circuit 111 in the coupled column of pixel circuits.

[0047] Please refer to Figure 2 and Figure 3 as shown, Figure 2 which is the operation timing diagram of the image sensor 100 according to the first embodiment of the present invention, Figure 3 and is the operation flowchart of the image sensor 100 according to the first embodiment of the present invention. The operation method of the image sensor 100 includes the following steps: turning on the resistance transistor with a fixed voltage signal at a first time (step S31); turning on the first switching transistor and the second switching transistor with an exposure signal at a second time to make the avalanche diode enter the state to be detected (step S33); and when the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-down transistor, so as to generate a negative spike at the drain of the second switching transistor as a photon event of the output voltage (step S35).

[0048] Please also refer to Figures 1 to 3 , and then the detailed content of this operation method will be described. This operation method illustrates the operation mode of one pixel circuit 111, but it can be understood that the operations of the pixel circuits 111 in the same column of pixel circuits are only different in time sequence according to the row selection signal, and the rest are the same as Figure 2and Figure 3 are the same.

[0049] Step S31: At the first time t1, the constant voltage signal VQ is converted to a high level to turn on the resistive transistor NM1 of the pixel circuit 111. At this time, since the first switching transistor NM0 has not been turned on, there is no voltage drop across the resistive transistor NM1. At the first time t1, the control signal VB is converted to a low level to turn on the P-type transistor of the pull-back circuit 12 (at this time, the pull-back circuit 12 is connected to the corresponding pixel circuit 111 through a switching element or a multiplexer).

[0050] Step S33: At the second time t2, the exposure signal RS is converted to a high level to simultaneously turn on the first switching transistor NM0 and the second switching transistor NM2. In the first embodiment, the period during which the exposure signal RS is at a high level is called the exposure period, and each photon event during this exposure period is counted by the column counter 13. When the first switching transistor NM0 is turned on, since the resistive transistor NM1 was turned on at the first time t1, the voltage on the node SN is pulled down to a low level. In the first embodiment, the predetermined time when the first time t1 is earlier than the second time t2 is used as the setting time of the resistive transistor NM1. In addition, during the period from the second time t2 to the time t3, although the second switching transistor NM2 is turned on, since the pull-down transistor NM3 has not been turned on, the output voltage remains at a high level.

[0051] Step S35: During the exposure period, when the avalanche diode SPAD does not receive photons, the avalanche diode SPAD is in a state to be detected (for example Figure 2 during the period from t2 to t3), where the voltage of the node SN and the output voltage are maintained at a low level and a high level respectively. When the avalanche diode SPAD receives photons (for example Figure 2 at the time t3), the avalanche diode SPAD generates a breakdown current Ia flowing through the resistive transistor NM1 to form a potential difference thereon, causing the voltage of the node SN to be converted to a high level to turn on the pull-down transistor NM3. At this time, the drain of the second switching transistor NM2 is grounded through the second switching transistor NM2 and the pull-down transistor NM3, causing a negative spike in the output voltage as a photon event of the output voltage. At the same time, since the voltage of the node SN is converted to a high level, the potential difference between the anode and cathode of the avalanche diode SPAD is less than the breakdown voltage, and quenching occurs.

[0052] Then, the voltage on the node SN starts to discharge through the pull-down transistor NM3 at the time t4, and after the discharge time, the pull-down transistor NM3 automatically turns off (for example Figure 2It is turned off at time t5, and the avalanche diode SPAD returns to the state to be detected. Among them, the discharge time is determined by the resistance value of the resistive transistor NM1 and the stray capacitance of the circuit. As described above, the resistance value of the resistive transistor NM1 and the stray capacitance can be determined during circuit design, so the time for the avalanche diode SPAD to return to the state to be detected can be determined accordingly.

[0053] Finally, after the pull-down transistor NM3 is automatically turned off, the pull-back circuit 12 pulls up the output voltage back to the high level, for example, back to the original level at time t6. In this way, one quenching and reading are completed.

[0054] During the exposure period, for each incident photon, the operation of the pixel circuit 111 is repeated Figure 2 from the first time t1 to time t6. For example, the counter 13 can count Figure 2 4 negative spikes during the exposure period as the detection result.

[0055] Please refer to Figure 4 as shown, which is a schematic diagram of the image sensor 400 according to the second embodiment of the present invention. The image sensor 400 is also used to detect extremely weak light and high-frequency signals, and a single-photon avalanche diode is used to detect photon events. The processor can generate an image frame by counting the photon events of each pixel, so as to perform object tracking, gesture recognition, three-dimensional image construction, physiological feature detection and recognition, etc.

[0056] The image sensor 400 includes a pixel array 41, a plurality of pull-back circuits 42, a plurality of counters 43, a row decoder 44, a column decoder 45, and a global current source circuit 46. Among them, the row decoder 44 and the column decoder 45 are also used to determine the pixel positions in the pixel array 41 for exposure and output detection signals (such as the spikes described later).

[0057] The pixel array 41 includes a plurality of pixel circuits 411 ( Figure 4 For example, taking 16×16 pixels as an example for illustration) arranged in an array. Each of the plurality of pixel circuits 411 includes an avalanche diode SPAD and four P-type transistors, namely a resistive transistor PM1, a first switching transistor PM0, a pull-up transistor PM3, and a second switching transistor PM2.

[0058] The avalanche diode SPAD is a single-photon avalanche diode, which has an anode and a cathode. The anode is connected to a negative bias voltage source VA, taking -15V as an example here, but not limited thereto. The cathode is connected to the node SN. When the potential difference (or bias voltage) between the cathode and the anode exceeds the breakdown voltage of the avalanche diode SPAD, a breakdown current Ia can be generated. In the second embodiment, the resistance transistor PM1 and the first switching transistor PM0 of the pixel circuit 411 are used to form a quenching circuit, which is used to make the potential difference between the cathode and the anode lower than the breakdown voltage for quenching when the avalanche diode SPAD generates the breakdown current Ia; the pull-up transistor PM3 and the second switching transistor PM2 of the pixel circuit 411 are used to form a reading circuit to read the output voltage of the pixel circuit 411 to the corresponding column counter 43.

[0059] The drain of the resistance transistor PM1 is connected to the node SN to connect the cathode of the avalanche diode SPAD. The gate of the resistance transistor PM1 is used to receive a fixed voltage signal VQ to be turned on or off by it. In the second embodiment, the resistance transistor PM1 is used to form a controllable resistor, and its resistance value is determined according to the value of the fixed voltage signal VQ. When the avalanche diode SPAD receives photons in the state to be detected and the first switching transistor PM0 is turned on, a voltage drop is generated on the resistance transistor PM1, so that the potential difference between the anode and the cathode of the avalanche diode SPAD is less than the breakdown voltage for quenching.

[0060] The drain of the first switching transistor PM0 is connected to the source of the resistance transistor PM1. The gate of the first switching transistor PM0 receives an exposure signal RS, which is, for example, a row selection signal, which is, for example, generated by a row decoder 44. The source of the first switching transistor PM0 is connected to the system voltage VDD.

[0061] The gate of the pull-up transistor PM3 is connected to the node SN to connect the cathode of the avalanche diode SPAD. The source of the pull-up transistor PM3 is connected to the system voltage VDD. The pull-up transistor PM3 is used as a charging path for the voltage on the node SN, and its charging rate is determined according to the resistance value of the resistance transistor PM1 and the stray capacitance of the circuit. The resistance value and the stray capacitance are values that can be determined during circuit fabrication.

[0062] The gate of the second switching transistor PM2 also receives the exposure signal RS to be controlled by it and open and close simultaneously with the first switching transistor PM0. The source of the second switching transistor PM2 is connected to the drain of the pull-up transistor PM3. The drain of the second switching transistor PM2 is used to generate the output voltage of the relevant pixel circuit 411.

[0063] Each of the plurality of pull-back circuits 42 is used to read out the output voltage by connecting to the drain of the second switching transistor PM2 of each of a column of pixel circuits 411 through the read line Rd. The image sensor 400 also includes, for example, a multiplexer or a plurality of switching elements for connecting the pull-back circuits 42 corresponding to each column of pixel circuits to different pixel circuits 411 through the multiplexer or different switching elements respectively. In the second embodiment, each of the pull-back circuits 42 includes an N-type transistor NM0 for pulling down the output voltage after a surge in the read-out output voltage (illustrated later). The drain of the N-type transistor NM0 is connected to the drain of the second switching transistor PM2. The source of the N-type transistor NM0 is connected to the ground voltage. The gate of the N-type transistor NM0 receives a control signal VB.

[0064] The global current source circuit 46 is used to form a current mirror with each of the plurality of pull-back circuits 42. Only one global current source circuit 46 is provided in the image sensor 400. For example, the image sensor 400 also includes a multiplexer or a plurality of switching elements for connecting the global current source circuit 46 to different pull-back circuits 42 through the multiplexer or different switching elements. The global current source circuit 46 includes an N-type transistor whose drain and gate are connected and connected to the global current source, and whose source is connected to the ground voltage.

[0065] Each of the plurality of counters 43 is coupled to a column of pixel circuits for counting photon events of the output voltage of each pixel circuit 411 in the coupled column of pixel circuits.

[0066] Please refer to Figure 5 and Figure 6 shown in Figure 5 which is the operation timing diagram of the image sensor 400 according to the second embodiment of the present invention, Figure 6 and the operation flowchart of the image sensor 400 according to the second embodiment of the present invention. The operation method of the image sensor 400 includes the following steps: turning on the resistance transistor with a fixed voltage signal at a first time (step S61); turning on the first switching transistor and the second switching transistor with an exposure signal at a second time to make the avalanche diode enter the state to be detected (step S63); and when the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-up transistor, so as to generate a positive surge at the drain of the second switching transistor as a photon event of the output voltage (step S65).

[0067] Please also refer to Figures 4 to 6 , and then describe the details of this operation method. This operation method describes the operation mode of one pixel circuit 411, but it can be understood that the operations of the respective pixel circuits 411 in the same column of pixel circuits are only different in time sequence according to the row selection signal, and the rest are the same as Figure 5 and Figure 6 .

[0068] Step S61: At the first time t1, the constant voltage signal VQ is converted to a low level to turn on the resistance transistor PM1 of the pixel circuit 411. At this time, since the first switching transistor PM0 has not been turned on, there is no voltage drop across the resistance transistor PM1. At the first time t1, the control signal VB is converted to a high level to turn on the N-type transistor of the pull-back circuit 42 (at this time, the pull-back circuit 42 has been connected to the corresponding pixel circuit 411 through a switching element or a multiplexer).

[0069] Step S63: At the second time t2, the exposure signal RS is converted to a low level while turning on the first switching transistor PM0 and the second switching transistor PM2 simultaneously. In the second embodiment, the period during which the exposure signal RS is at a low level is called the exposure period, and each photon event during this exposure period is counted by the column counter 43. When the first switching transistor PM0 is turned on, since the resistance transistor PM1 was turned on at the first time t1, the voltage on the node SN is pulled up to a high level. In the second embodiment, the predetermined time that the first time t1 is earlier than the second time t2 is used as the setting time of the resistance transistor PM1. In addition, during the period from the second time t2 to the time t3, although the second switching transistor PM2 is turned on, since the pull-up transistor PM3 has not been turned on, the output voltage still remains at a low level.

[0070] Step S65: During the exposure period, when the avalanche diode SPAD does not receive photons, the avalanche diode SPAD is in a state to be detected (for example Figure 5 during the period from t2 to t3), where the voltage on the node SN and the output voltage are maintained at a high level and a low level respectively. When the avalanche diode SPAD receives photons (for example Figure 5 at the time t3), the avalanche diode SPAD generates a breakdown current Ia flowing through the resistance transistor PM1 to form a potential difference thereon, causing the voltage on the node SN to be converted to a low level to turn on the pull-up transistor PM3. At this time, the drain of the second switching transistor PM2 is connected to the system voltage VDD through the second switching transistor PM2 and the pull-up transistor PM3, causing a positive spike in the output voltage as a photon event of the output voltage. At the same time, since the voltage on the node SN is converted to a low level, the potential difference between the anode and cathode of the avalanche diode SPAD is less than the breakdown voltage, and quenching occurs.

[0071] Next, the voltage on the node SN starts to be charged by the pull-up transistor PM3 at the time t4, and after the charging time, the pull-up transistor PM3 automatically turns off (for example Figure 5is turned off at time t5), and the avalanche diode SPAD returns to the state to be detected; wherein, the charging time is determined by the resistance value of the resistive transistor PM1 and the stray capacitance of the circuit. As described above, the resistance value of the resistive transistor PM1 and the stray capacitance can be determined during the circuit design, so the time for the avalanche diode SPAD to return to the state to be detected can be determined accordingly.

[0072] Finally, after the pull-up transistor PM3 is automatically turned off, the pull-back circuit 42 pulls down the output voltage back to the low level, for example, back to the original level at time t6. Thus, one quenching and reading are completed.

[0073] During the exposure period, for each incident photon, the operation of the pixel circuit 411 is repeated Figure 5 from the first time t1 to time t6. For example, the counter 43 can Figure 5 count 4 positive surges during the exposure period as the detection result.

[0074] Although the above first embodiment and second embodiment are described by taking each pixel circuit having 4 transistors as an example, the present invention is not limited thereto. Please refer to Figure 7 and Figure 8 , Figure 7 is a schematic diagram of an image sensor 100 according to a third embodiment of the present invention; Figure 8 is an operation timing diagram of the image sensor 100 according to a third embodiment of the present invention.

[0075] In the third embodiment, the image sensor 100 also includes a pixel array 11, a plurality of pull-back circuits 12, a plurality of counters 13, a row decoder 14, a column decoder 15, and a global current source circuit 16. The pixel array 11 also includes a plurality of pixel circuits 111.

[0076] Each pixel circuit 111 includes an avalanche diode SPAD and at least one transistor NM3. The cathode of the avalanche diode SPAD is connected to a positive bias source VA, such as +15 volts, but not limited thereto. The anode of the avalanche diode SPAD is connected to a node SN, and this node SN is connected to the gate of the transistor NM3. Each of the plurality of pull-back circuits 12 is used to couple to the drain of the transistor NM3 of each pixel circuit 111 in a column of pixel circuits through a read line Rd.

[0077] In addition, in order to control the pixel circuits 111 in a column of pixel circuits to sequentially detect photon events, each pixel circuit 111 further includes another transistor NM2 connected between the transistor NM3 and the read line Rd. The operation of the image sensor 100 is shown in Figure 8, which is similar to the first embodiment, only without the transistors NM1 and NM0, so its details will not be elaborated here. The functions of the plurality of pull-back circuits 12, the plurality of counters 13, the row decoder 14, the column decoder 15, and the global current source circuit 16 are the same as those in the first embodiment.

[0078] It can be understood that the numerical values in the above embodiments, such as the number of pixels and the number of surges, are only examples and are not used to limit the present invention.

[0079] In addition, the high and low levels in the above embodiments can be appropriately selected as long as each component can operate, without specific limitations. At the same time, the fixed voltage signal VQ means that the voltage value during exposure is fixed.

[0080] In summary, although a single-photon avalanche diode can be used to detect extremely weak light and high-frequency signals, it still needs to cooperate with a quenching circuit operation, and a poor circuit design will affect the minimum pixel size and fill factor. Therefore, the present invention further provides an image sensor and its quenching and reading circuit ( Figure 1 , 4 ) and its operation method ( Figures 2 - 3 , 5-6), which has a simple circuit architecture, low pixel size limitation, and high fill factor.

[0081] Although the present invention has been disclosed through the foregoing examples, it is not used to limit the present invention. Any person with ordinary knowledge and skills in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. An image sensor, the image sensor comprising: A pixel array, the pixel array comprising a plurality of pixel circuits arranged in an array, each of the plurality of pixel circuits comprising: An avalanche diode, the avalanche diode having an anode and a cathode, the cathode being connected to a positive bias source; A resistive transistor, the drain of the resistive transistor being connected to the anode of the avalanche diode, the gate of the resistive transistor being configured to receive a fixed voltage signal; A first switching transistor, the drain of the first switching transistor being connected to the source of the resistive transistor, the gate of the first switching transistor receiving an exposure signal, the source of the first switching transistor being connected to a ground voltage; A pull-down transistor, the gate of the pull-down transistor being connected to the anode of the avalanche diode, the source of the pull-down transistor being connected to the ground voltage; And A second switching transistor, the gate of the second switching transistor receiving the exposure signal, the source of the second switching transistor being connected to the drain of the pull-down transistor, the drain of the second switching transistor being configured to generate an output voltage; A row decoder, the row decoder being configured to generate the exposure signal; And A plurality of pull-back circuits, each of the plurality of pull-back circuits being disposed corresponding to a column of pixel circuits and comprising a P-type transistor, the drain of the P-type transistor being configured to be connected to the drain of the second switching transistor of each of the pixel circuits in the column through a read line to read out the output voltage, the source of the P-type transistor being connected to a system voltage, the gate of the P-type transistor receiving a control signal, the P-type transistor pulling up the output voltage after a photon event of reading out the output voltage, Wherein, the resistive transistor, the first switching transistor, the pull-down transistor and the second switching transistor are N-type transistors.

2. The image sensor according to claim 1, further comprising a global current source circuit for forming a current mirror with each of the plurality of pull-back circuits.

3. The image sensor according to claim 1, further comprising a plurality of counters, each of the plurality of counters being coupled to the column of pixel circuits for counting photon events of the output voltage.

4. The image sensor according to claim 1, wherein, The exposure signal is a row selection signal; and The fixed voltage signal is used to determine the resistance value of the resistive transistor.

5. An image sensor, the image sensor comprising: A pixel array, the pixel array comprising a plurality of pixel circuits arranged in an array, each of the plurality of pixel circuits comprising: An avalanche diode, the avalanche diode comprising an anode and a cathode, the anode being connected to a negative bias source; A resistive transistor, the drain of the resistive transistor being connected to the cathode of the avalanche diode, the gate of the resistive transistor being configured to receive a fixed voltage signal; A first switching transistor, the drain of the first switching transistor being connected to the source of the resistive transistor, the gate of the first switching transistor receiving an exposure signal, the source of the first switching transistor being connected to a system voltage; A pull-up transistor, the gate of the pull-up transistor being connected to the cathode of the avalanche diode, the source of the pull-up transistor being connected to the system voltage; And A second switching transistor, whose gate receives the exposure signal, whose source is connected to the drain of the pull-up transistor, and whose drain is used to generate an output voltage; A row decoder, which is used to generate the exposure signal; And A plurality of pull-back circuits, each of which is arranged corresponding to a column of pixel circuits and includes an N-type transistor. The drain of the N-type transistor is used to read the output voltage by connecting the drain of the second switching transistor of each of the column of pixel circuits through a read line. The source of the N-type transistor is connected to the ground voltage. The gate of the N-type transistor receives a control signal. The N-type transistor pulls down the output voltage after a photon event of reading the output voltage. Wherein, the resistive transistor, the first switching transistor, the pull-up transistor and the second switching transistor are P-type transistors.

6. The image sensor according to claim 5, further comprising a global current source circuit for forming a current mirror with each of the plurality of pull-back circuits.

7. The image sensor according to claim 5, further comprising a plurality of counters, each of which is coupled to the column of pixel circuits for counting photon events of the output voltage.

8. The image sensor according to claim 5, wherein The exposure signal is a row selection signal; and The fixed voltage signal is used to determine the resistance value of the resistive transistor.

9. An operating method of the image sensor according to claim 1, the operating method comprising: Turning on the resistive transistor with the fixed voltage signal at a first time; Turning on the first switching transistor and the second switching transistor with the exposure signal at a second time to make the avalanche diode enter a state to be detected; and When the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-down transistor, so as to generate a negative spike at the drain of the second switching transistor as a photon event of the output voltage.

10. The operating method according to claim 9, wherein, The pull-down transistor automatically turns off after a discharge time, and the discharge time is determined by the resistance value of the resistive transistor and the stray capacitance of the circuit.

11. The operating method according to claim 10, further comprising: After the pull-down transistor automatically turns off, pulling up the output voltage with the pull-back circuit.

12. The operating method according to claim 9, wherein the first time is earlier than the second time by a predetermined time, and the predetermined time is used as the setting time of the resistive transistor.

13. An operating method of the image sensor according to claim 5, the operating method comprising: Turning on the resistive transistor with the fixed voltage signal at a first time; Turning on the first switching transistor and the second switching transistor with the exposure signal at a second time to make the avalanche diode enter a state to be detected; and When the avalanche diode receives photons, the avalanche diode generates a breakdown current to turn on the pull-up transistor, so as to generate a positive spike at the drain of the second switching transistor as a photon event of the output voltage.

14. The operating method according to claim 13, wherein, The pull-up transistor automatically turns off after a charging time after being turned on, and the charging time is determined by the resistance value of the resistive transistor and the stray capacitance of the circuit.

15. The operating method according to claim 14, further comprising: After the pull-up transistor automatically turns off, pulling down the output voltage with the pull-back circuit.

16. The operating method according to claim 13, wherein the first time is earlier than the second time by a predetermined time, and the predetermined time is used as the setting time of the resistive transistor.

17. An image sensor, comprising: A pixel array including a plurality of pixel circuits arranged in an array, each of the plurality of pixel circuits including an avalanche diode, a first transistor, and a second transistor, wherein the avalanche diode is connected to the gate of the first transistor, and the second transistor is connected between the drain of the first transistor and the read line; and A plurality of pull-back circuits, each of the plurality of pull-back circuits being disposed corresponding to a column of pixel circuits and including a P-type transistor, the drain of the P-type transistor being used to couple to the drain of the second transistor of each of the pixel circuits in the column through the read line to read an output voltage, the source of the P-type transistor being connected to a system voltage, the gate of the P-type transistor receiving a control signal, and the P-type transistor pulling up or pulling down the output voltage after a photon event of reading the output voltage, Among them, The first transistor and the second transistor are N-type transistors.

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