Chip testing system and testing method based on uIP

Abstract

The invention discloses a chip test system and test method based on uIP, and belongs to the field of chip test technology. The invention customizes a uIP module in a programmable device that can meet the interface signal type and timing requirements of different interface modules in a DUT chip under test, and matches each interface module in the DUT chip under test with test resources that meet its requirements through a three-step method of simple configuration of uIP and corresponding interface modules, loading a data source and sending data by the uIP module, and returning test feedback data of the interface module, greatly simplifies the process of chip testing, solves the technical problems that ALPG needs to master complex syntax to generate pattern test vectors, and SQPG and SCPG need to use tools to analyze and debug waveform signals because of the large amount of raw data generated by the Pattern files, and the low test efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing system and a testing method based on uIP. Background Art

[0002] To implement chip testing, it is generally necessary to implement DC testing capabilities and Function testing capabilities. DC testing, that is, testing of DC characteristics using Ohm's law, such as FVMV (constant voltage measurement) testing, FVMI (constant voltage measurement) testing, MVM (voltage measurement only) testing) capabilities. Function testing, that is, testing the various functions of the chip, is an abstract concept in the field of chip testing. Usually different chips have different functions, and there will be different testing methods. For example, the Function test of EEPROM storage chips includes read and write tests, and the Function test of FLASH storage chips includes read, write, and erase tests. In the field of chip testing technology, the capability requirements for ATE (Automatic Test Equipment) testers are usually as shown in Table a below:

[0003] Ability level 1 Ability Level 2 ATE Resources illustrate DC Test FVV PE, DPS Drive voltage Test voltage FIMI PE, DPS Drive current and measure current FIMV DPS Drive current and measure voltage MVM PE, DPS Voltage measurement only Function test Try ALPG FPGA Logical Pattern Generation SQPG FPGA Sequential Pattern Generation SCPG FPGA Scan Pattern generation, based on JTAG

[0004] Table a

[0005] In Table a, ALPG (Algorithmic Pattern Generator) represents algorithmic pattern generator;

[0006] SQPG (Sequence Pattern Generator) stands for Sequence Pattern Generator;

[0007] SCPG (Scan Pattern Generator) stands for Scan Pattern Generator;

[0008] PE (Pin Electronic) indicates pin circuit;

[0009] DPS (Device Power Supply) means device power supply unit;

[0010] FPGA (Field Programmable Gate Array) stands for Field Programmable Gate Array;

[0011] Pattern represents a test vector;

[0012] Scan Pattern indicates the data source that SCPG relies on;

[0013] JTAG (Joint Test Action Group) stands for Joint Test Action Group, which implements boundary scanning through access ports;

[0014] The application development of common automated chip testers (ATE) is basically based on the patterns (test vectors) of ALPG, SQPG, and SCPG to generate interactive signals with the chip. ALGP uses logical operations to generate patterns, which are generally used on memory chips whose access timing can be regularly controlled. Each ATE equipment manufacturer generally combines its own experience and technology to completely independently develop a set of programming languages. This language is close to assembly language, with relatively awkward syntax and high learning cost.

[0015] The source data of SQPG / SCPG is a two-dimensional matrix data based on pins and time, which is used to describe the pattern for the target DUT (Device Under Test) and its format is similar to the STIL (Standard Test Interface Language) standard. However, a pattern file usually contains tens of thousands or hundreds of thousands of lines or more of test vector data. The file is huge and requires tools to analyze and debug waveform signals, which is inefficient.

[0016] Attached Figure 1 The above chip testing method based on ALPG, SQPG and SCPG is demonstrated. The principle is: the site controller controls ALPG, SQPG and SCPG to interact with the chip under test DUT to complete the test purpose. However, there are several technical problems:

[0017] 1. ALPG pattern development requires mastering complex grammar, low language level, high learning cost, time-consuming and error-prone to use;

[0018] 2. The SQPG and SCPG files are large and raw data, which is not conducive to viewing and analysis;

[0019] 3. ALPG, SQPG, and SCPG are very complex in implementing chip testing functions at the FPGA level and require the development of a compiler, which results in a large amount of development work. Summary of the invention

[0020] The present invention aims to simplify the chip testing process, avoid the need to master complex syntax when ALPG generates pattern test vectors, and avoid the need to use tools to analyze and debug waveform signals due to the large size of pattern files generated by SQPG and SCPG due to the large amount of raw data. A chip testing system and testing method based on uIP are provided.

[0021] To achieve this object, the present invention adopts the following technical solutions:

[0022] A chip testing system based on uIP is provided, comprising at least one uIP module customized in a programmable device, each of the uIP modules being used to access an interface module with a corresponding interface type in a DUT chip under test during chip testing, so as to match the test resources required by the DUT chip under test, thereby satisfying the requirements of the accessed interface module for interface signal type and timing during chip testing.

[0023] Preferably, the programmable device is a FPGA field programmable gate array.

[0024] Preferably, the interface type of the interface module integrated in the DUT chip under test includes any one or more of I2C, SPI, parallel, SDHCI, ONFI, and NAND FLASH interfaces, and is not limited to the above types.

[0025] Preferably, the uIP module internally includes a data sending unit, a data receiving unit and a logic control unit. When the DUT chip under test is tested, after receiving a data sending instruction from the controller, the data sending unit loads the data source and sends it to the correspondingly connected interface module;

[0026] After the test is completed, the data receiving unit is used to receive the test feedback data of the interface module and transmit it back to the controller to analyze and judge the results;

[0027] The logic control unit is used to execute the chip test logic of the controller to test the DUT chip under test.

[0028] Preferably, the chip testing system further comprises a multiplexer, which is used to distribute and then distribute the IO pins of each uIP module customized in the same programmable device so as to match the uIP pin resources of the programmable device with the pins of the DUT chip under test.

[0029] Preferably, the chip testing system further comprises a PE circuit connected between the programmable device and the DUT chip under test for checking connectivity and short circuit between the chip testing system and the DUT chip under test.

[0030] Preferably, the chip testing system further comprises a PE bypass switch connected between the programmable device and the DUT chip under test for implementing switch control of chip testing.

[0031] Preferably, the PE bypass switch is connected between the signal output end of each of the uIP modules having a configuration relationship and the signal input end of the corresponding interface module in the DUT chip under test.

[0032] Preferably, the chip testing system further comprises a controller which is communicatively connected to the programmable device, the PE circuit, the PE bypass switch and the DUT chip under test respectively and is used to control the communication object to perform chip testing on the DUT chip under test according to a predetermined test logic.

[0033] The present invention also provides a chip testing method based on uIP, comprising the steps of:

[0034] S1, customize several uIP modules in the programmable device;

[0035] S2, configure a uIP module that can meet the interface signal type and timing requirements for each interface module in the DUT chip under test;

[0036] S3, driving each of the uIP modules to load the corresponding test data source and send it to the corresponding interface module having a configuration relationship therewith;

[0037] S4, each of the uIP modules receives the test feedback data sent by the corresponding interface module and transmits it back to the test data analysis platform;

[0038] S5, repeating steps S2-S4 until the chip test of the DUT chip under test is completed.

[0039] The present invention customizes a uIP module in a programmable device that can meet the interface signal type and timing requirements of different interface modules in a DUT chip under test, and matches each interface module in the DUT chip under test with test resources that meet its requirements through a three-step method of simple configuration of the uIP and the corresponding interface module, loading a data source and sending data by the uIP module, and returning test feedback data of the interface module and performing result analysis and judgment, thereby greatly simplifying the chip test process and solving the technical problems that ALPG needs to master complex syntax to generate Pattern test vectors, and SQPG and SCPG need to use tools to analyze and debug waveform signals because the Pattern files generated by a large amount of raw data are huge, and the test efficiency is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a logic diagram for DUT chip testing using ALPG, SQPG, and SCPG;

[0042] Figure 2 It is a schematic diagram of the test signal interaction between the DUT chip under test with different interface modules inside and the ATE test equipment;

[0043] Figure 3 It is a schematic diagram of the connection between uIP and the DUT chip under test;

[0044] Figure 4 It is a schematic diagram of the overall structure of a chip testing system based on uIP provided by an embodiment of the present invention;

[0045] Figure 5 This is a diagram of uIP channel resource selection Figure 1 ;

[0046] Figure 6 This is a diagram of uIP channel resource selection Figure 2 ;

[0047] Figure 7 It is a flow chart of a chip testing method based on uIP provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0048] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0049] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on this patent; in order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0050] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0051] In the description of the present invention, unless otherwise clearly specified and limited, if the term "connection" or the like appears to indicate the connection relationship between components, the term should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] Each interface module with different interface types in the same DUT chip under test, such as I2C, SPI, SDHCI, ONFI and other interface types, usually has different requirements for the type and timing of the interface signal during the chip testing process. In the prior art, using ALPG to generate pattern test vectors that meet the different requirements of different interface modules for the type and timing of interface signals requires mastering complex syntax, while using SQPG and SCPG to generate pattern files that are too large due to the large amount of raw data, and tools are required to analyze and debug waveform signals, and the test efficiency is very low. In order to solve this problem, the chip testing system based on uIP provided in the embodiment of the present invention customizes uIP (User Defined Programming Interface) in a programmable device (preferably FPGA). IP, user-defined soft core) module, and configures several uIP modules that can meet the interface module's requirements for interface signal type and timing for each interface module with different interface types in the same DUT chip under test. When testing the chip, the controller controls the corresponding uIP module to load the test data source and send it to the interface module with a configuration relationship with the uIP module. After receiving the test feedback data of the interface module, the uIP returns it to the data analysis platform for further data analysis and processing. Through such a three-step method of simple configuration of the uIP and the corresponding interface module, the uIP module loads the data source and sends the test data, and returns the test feedback data and performs result analysis and judgment, the chip testing process is greatly simplified, and the technical problems of ALPG generating Pattern test vectors requiring complex syntax and SQPG and SCPG generating Pattern files that are huge due to the large use of raw data and must rely on tools to analyze and debug waveform signals, as well as low testing efficiency are solved.

[0053] The principle of solving the technical problem by the chip testing system based on uIP provided in this embodiment is further explained below:

[0054] Each interface module in the DUT chip under test needs to be connected to the outside through IO. The chip test needs to access each interface module in the DUT through each IO. The access needs to comply with the interface module's requirements for interface signal type and timing. On the market, the types of chip access buses are limited, mainly I2C, SPI, parallel bus, SDHCI, ONFI and other types of buses. DUT chips under test are usually classified into simple interface chips and chips with complex functions according to the number of interfaces and functional complexity. Simple chips include EEPROM storage chips and temperature sensor chips with I2C interfaces, SPI NOR FLASH chips with SPI interfaces; complex chips include Figure 2 The chip shown has I2C, SPI, SDHCI, NAND FLASH and other interface modules. The embodiment of the present invention customizes a uIP module for each interface module in a programmable device, and matches the test resources required for chip testing for the corresponding interface module through the uIP module, so as to meet the requirements of the interface signal type and timing of the accessed interface module in the chip test. Since the bus types accessed by the chip are limited, after the uIP modules corresponding to each interface module of different interface types are developed by the ATE equipment manufacturer, there is no need to repeat the development, and it is also very convenient to use.

[0055] It should be emphasized that, in this embodiment, each interface module in the same DUT chip under test has a corresponding relationship with each uIP module customized in the same programmable device, that is, each interface module with different interface types is correspondingly configured with at least one uIP module that can meet the interface module's requirements for interface signal type and timing, and the corresponding relationship is as follows: Figure 3 As shown, for example Figure 3 In the example, a uIP module marked as uIPx is configured for the interface module x in the DUT chip under test, and a uIP module marked as uIPy is configured for the interface module y.

[0056] Each uIP module includes a data sending unit, a data receiving unit and a logic control unit. When testing the DUT chip under test, after receiving the data sending instruction from the controller, the data sending unit loads the test data source and sends it to the corresponding connected interface module; after the test is completed, the data receiving unit is used to receive the test feedback data of the interface module and send it back to the data analysis platform for result analysis and judgment; the logic control unit is used to execute the chip test logic of the controller to test the DUT chip under test.

[0057] To facilitate the selection of test channels, preferably, Figure 5 and Figure 6 As shown, the uIP-based chip testing system provided in this embodiment also includes a multiplexer ( Figure 5 , Figure 6 The multiplexer is used to distribute the IO pins of each uIP module customized in the same programmable device out and then distribute them in (the method of distributing out and distributing in Figure 5 , Figure 6 The controller selects the test channel using the existing method, and the selection process is not within the scope of the present invention, so it will not be described in detail.

[0058] To ensure the security of the connection between the chip test system provided in this embodiment and the DUT chip under test, Figure 4 As shown, the chip test system based on uIP provided in this embodiment preferably includes a PE circuit 10 connected between the programmable device and the DUT chip under test for checking the connectivity and short circuit between the chip test system and the DUT chip under test. It should be noted that there are many existing PE circuits that can check the connectivity and short circuit between the ATE device and the DUT, so the specific circuit structure of the PE circuit used in this embodiment will not be explained here.

[0059] In order to facilitate the switch control of chip testing, such as Figure 4 As shown, the uIP-based chip test system provided in this embodiment preferably also includes a PE bypass switch 20 connected between the programmable device and the DUT chip under test for realizing switch control of the chip test. The PE bypass switch is preferably connected to the controller in communication, and the controller can automatically control the on and off of the PE bypass switch during the test according to a preset program, thereby realizing switch control of the chip test process.

[0060] In order to facilitate the switch control of each uIP module accessing the corresponding interface module with a configuration relationship in the DUT chip under test, more preferably, a PE bypass switch is connected between the signal output end of each uIP module 40 with a configuration relationship and the signal input end of the corresponding interface module in the DUT chip under test. Similarly, the controller can automatically control the on and off of each bypass switch during the test according to a preset program, thereby realizing the switch control of the uIP module accessing the corresponding interface module.

[0061] The uIP-based chip test system provided in this embodiment also preferably includes a controller 30 that is respectively connected to the programmable device, the PE circuit, the PE bypass switch, and the DUT chip under test and is used to control these communication objects to test the DUT chip under test according to a predetermined test logic. There are many types of controllers available, so the specific selection of the controller is not explained here.

[0062] The present invention also provides a chip testing method based on uIP, such as Figure 7 As shown, the steps include:

[0063] S1, customize several uIP modules in the programmable device;

[0064] S2, configure a uIP module that can meet the interface signal type and timing requirements for each interface module in the DUT chip under test;

[0065] S3, driving each uIP module to load the corresponding test data source and send it to the corresponding interface module with which it has a configuration relationship;

[0066] S4, each uIP module receives the test feedback data sent by the corresponding interface module and sends it back to the test data analysis platform for analysis and judgment;

[0067] S5, repeat steps S2-S4 until the chip test of the DUT chip is completed.

[0068] In summary, the present invention customizes a uIP module in a programmable device that can meet the interface signal type and timing requirements of different interface modules in the DUT chip under test, and uses a three-step method of simple configuration of the uIP and the corresponding interface module, loading the data source and sending data by the uIP module, and returning the test feedback data of the interface module and performing result analysis and judgment. This matches the test resources that meet the requirements for each interface module in the DUT chip under test, greatly simplifies the chip testing process, and solves the technical problems of ALPG needing to master complex syntax to generate Pattern test vectors, and SQPG and SCPG using a large amount of raw data to generate Pattern files that are huge and require the use of tools to analyze and debug waveform signals, resulting in low testing efficiency.

[0069] It should be noted that the above specific implementations are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art should understand that various modifications, equivalent substitutions, changes, etc. can be made to the present invention. However, as long as these changes do not deviate from the spirit of the present invention, they should be within the scope of protection of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.

Claims

1. A chip testing system based on uIP, characterized in that: It includes at least one uIP module customized in a programmable device, each of which is used to access an interface module with a corresponding interface type in a DUT chip under test during chip testing to match the test resources required by the DUT chip under test, thereby satisfying the requirements of the accessed interface module for interface signal type and timing in chip testing; The uIP-based chip test system further includes a multiplexer, which is used to distribute the IO pins of each uIP module customized in the same programmable device and then distribute them in again, so as to match the uIP pin resources of the programmable device with the pins of the DUT chip under test; The uIP-based chip testing system further comprises a PE circuit connected between the programmable device and the DUT chip under test for checking the connectivity between the chip testing system and the DUT chip under test and whether there is a short circuit; The uIP-based chip testing system further includes a PE bypass switch connected between the programmable device and the DUT chip under test for implementing switch control of chip testing; The PE bypass switch is connected between the signal output end of each of the uIP modules having a configuration relationship and the signal input end of the corresponding interface module in the DUT chip under test; The uIP-based chip testing system also includes a controller that is communicatively connected to the programmable device, the PE circuit, the PE bypass switch, and the DUT chip under test, and is used to control the communication object to perform chip testing on the DUT chip under test according to a predetermined test logic.

2. The uIP-based chip testing system according to claim 1, characterized in that: The programmable device is a FPGA field programmable gate array.

3. The chip testing system based on uIP according to claim 1, characterized in that: The interface type of the interface module integrated in the DUT chip under test includes any one or more of I2C, SPI, parallel, SDHCI, ONFI, and NAND FLASH interfaces.

4. The uIP-based chip testing system according to claim 1, characterized in that: The uIP module includes a data sending unit, a data receiving unit and a logic control unit. When the DUT chip is tested, after receiving a data sending instruction from the controller, the data sending unit loads the data source and sends it to the corresponding interface module. After the test is completed, the data receiving unit is used to receive the test feedback data of the interface module and transmit it back to the controller; The logic control unit is used to execute the chip test logic of the controller to test the DUT chip under test.

5. A chip testing method based on uIP, implemented by the chip testing system based on uIP as claimed in any one of claims 1 to 4, characterized in that: Includes steps: S1, customize several uIP modules in the programmable device; S2, configure a uIP module that can meet the interface signal type and timing requirements for each interface module in the DUT chip under test; S3, driving each of the uIP modules to load the corresponding test data source and send it to the corresponding interface module having a configuration relationship therewith; S4, each of the uIP modules receives the test feedback data sent by the corresponding interface module and transmits it back to the test data analysis platform; S5, repeating steps S2-S4 until the chip test of the DUT chip under test is completed.

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