An FPGA-based on-board AIS signal receiver

Abstract

The present application discloses a spaceborne AIS signal receiver based on FPGA, including: the first shift register and the second shift register are used to receive and store in real time the data of the preprocessed real-time signal; the decision maker is coupled with the first shift register and the second shift register, and is used to make a decision on the data currently stored in the first shift register and the second shift register every time one bit of data is output by the first shift register and the second shift register, and when it is determined that the currently stored data is the AIS signal frame header, send the decision result to the one or more path selection circuits; one or more path selection circuits are used to receive and cache the AIS signal corresponding to the currently stored data based on the decision result. The present application solves the technical problems of insufficient capture granularity of AIS signals and large consumption of storage resources in the prior art.

Description

Technical Field

[0001] This application relates to the field of satellite communication technology, and particularly to an on-board AIS signal receiver based on FPGA. Background Art

[0002] The Automatic Identification System (AIS) of ships is an aids-to-navigation system that integrates functions of ship identification, safety monitoring, and communication navigation. The relevant technical protocols of AIS stipulate that the AIS system uses time division multiple access technology for communication. And within the communication range of the AIS system sub-network (such as 20 nautical miles), ship AIS devices transmit AIS signals according to time slots (such as 26.67 ms), and shore station AIS devices receive AIS signals. For example, in the case of full transmission, at most 37.5 packets can be received in 1 s.

[0003] As a device for receiving AIS signals transmitted by ship AIS devices, the antenna of the on-board AIS signal receiver covers multiple AIS sub-networks. Therefore, it is quite common for the on-board AIS signal receiver to receive AIS signals sent by different ship AIS devices simultaneously within one time slot, and there will be collision interference between receiving AIS signals sent by multiple different ship AIS devices simultaneously. Due to the existence of collision interference, higher challenges are posed to the on-board AIS signal receiver.

[0004] In the invention patent with the application number 201611010321.5 and the invention name "A Method and Device for Receiving and Processing On-board AIS Signals Based on Correlation", a scheme for receiving and processing AIS signals by an on-board AIS signal receiver is proposed. In this invention patent, strategies for on-orbit capture and storage of AIS signals are proposed. Specifically, in this invention patent, the AIS signals received throughout the time slot are searched once within each time slot, that is, the capture density is one time slot (capturing by searching the entire time slot once within one time slot). And it is quite common for the on-board AIS signal receiver to receive AIS signals sent by different ship AIS devices simultaneously within one time slot. Conducting a search once within one time slot may cause some received AIS signals not to be searched, resulting in missed capture of some AIS signals. In addition, the patent designs a first storage area, a second storage area, and a third storage area for the AIS signal cache, causing a relatively large overhead of resources such as FPGA RAM (the main internal resources of FPGA include look-up table LUT, register FF, memory RAM, and arithmetic unit DSP48). Summary of the Invention

[0005] The technical problem solved by this application is: in the prior art, the capture granularity of AIS signals is insufficient and the storage resource consumption is relatively large. This application provides a spaceborne AIS signal receiver based on FPGA. In the solution provided by the embodiments of this application, a capture is performed for each received real-time signal sampling point, rather than once in a time slot, thereby providing the capture granularity and avoiding missing the capture of some AIS signals. In addition, when the signal is captured in the embodiments of this application, each selection circuit targets one AIS signal, thereby reducing the overhead of storage resources.

[0006] In a first aspect, an embodiment of this application provides a spaceborne AIS signal receiver based on FPGA. The receiver includes: a first shift register, a second shift register, a decision maker, and one or more selection circuits; wherein, the first shift register and the second shift register are used to receive and store in real time the data of the preprocessed real-time signal.

[0007] The decision maker is coupled to the first shift register and the second shift register, and is used to make a decision on the data currently stored in the first shift register and the second shift register every time one bit of data is output by the first shift register and the second shift register, and when it is determined that the currently stored data is the AIS signal frame header, send the decision result to the one or more selection circuits.

[0008] One or more selection circuits are used to receive and cache the AIS signal corresponding to the currently stored data based on the decision result.

[0009] Optionally, the decision maker includes: a first decision maker, a second decision maker, and a third decision maker, wherein

[0010] The first decision maker is coupled to the first shift register, and is used to calculate the signal power parameter according to the currently stored data when one bit of data is output by the first shift register and the second shift register, and make a first decision based on the power parameter to obtain a first decision result.

[0011] The second decision maker is coupled to the first decision maker, the first shift register, and the second shift register, and is used to, if the first decision result is successful, calculate the first correlation signal energy value at a 4T symbol interval according to the currently stored data, and make a second decision based on the first correlation signal energy value to obtain a second decision result.

[0012] The third decision maker is coupled to the second decision maker, the first shift register, and the second shift register, and is configured to, if the second decision result is successful, calculate a second correlation signal energy value at a 2T symbol interval based on the currently stored data, and perform a third decision based on the second correlation signal energy value to obtain a third decision result; wherein, if the third decision result is successful, determine that the currently stored data is the AIS signal frame header, and send the third decision result to the one or more selection circuits.

[0013] Optionally, if there are multiple selection circuits, the multiple selection circuits receive and cache multiple successfully decided AIS signals in parallel.

[0014] Optionally, the multiple selection circuits include a first selection circuit and a second selection circuit;

[0015] If the first shift register and the second shift register receive and store the data of the preprocessed first real-time signal, and the decision maker decides that the data of the first real-time signal stored in the first shift register and the second shift register is the AIS signal frame header, the first selection circuit receives and caches the first AIS signal corresponding to the first real-time signal based on the decision result.

[0016] If, during the reception and caching of the first AIS signal by the first selection circuit, the first shift register and the second shift register also receive and store the data of the preprocessed second real-time signal;

[0017] The decision result obtained by the decision maker's decision on the data of the second real-time signal is that the data of the second real-time signal is the AIS signal frame header;

[0018] The second selection circuit is configured to receive and cache the second AIS signal corresponding to the second real-time signal based on the decision result.

[0019] Optionally, if the one or multiple selection circuits are all in the working state and receive the decision result sent by the decision maker, the decision result is ignored.

[0020] Optionally, each selection circuit includes a third shift register, a selector, a logic unit, and a memory; wherein,

[0021] The third shift register is configured to receive and store the data of the preprocessed real-time signal;

[0022] The selector is coupled to the third shift register, the decision maker, and the logic unit, and is configured to select communication when the decision result is successful, and send the data of the preprocessed real-time signal stored in the third shift register to the logic unit;

[0023] The logic unit receives the data of the preprocessed real-time signal and the preprocessed real-time signal, and transfers the received data to the memory;

[0024] The memory is coupled to the logic unit and is configured to store the data of the preprocessed real-time signal and the preprocessed real-time signal.

[0025] Optionally, the memory is a first-in-first-out queue, wherein the size of the first-in-first-out queue is equal to the length of the synchronization sequence of the signals sampled in one time slot.

[0026] Optionally, when capturing AIS signals of different channels, after an AIS signal of the same channel is successfully captured, then an AIS signal of another channel is captured, and the time interval between two captures is not less than the length of a frame header synchronization sequence.

[0027] Optionally, the interval between two captures of the same AIS signal is not less than the length of a frame header synchronization sequence.

[0028] Optionally, it further includes: an output unit; the output unit is coupled to one or more selection circuits and is configured to output the buffered AIS signals.

[0029] Compared with the prior art, the solution provided by the embodiments of the present application has at least the following beneficial effects:

[0030] 1. In the solution provided by the embodiments of the present application, one capture is performed for each received real-time signal sampling point, instead of one capture in one time slot, thereby providing the granularity of capture and avoiding missing the capture of some AIS signals.

[0031] 2. In the solution provided by the embodiments of the present application, when capturing signals, each selection circuit targets one AIS signal, thereby reducing the overhead of storage resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic structural diagram of a spaceborne AIS signal receiver based on FPGA provided by an embodiment of the present application;

[0033] Figure 2 It is a schematic structural diagram of a selection circuit provided by an embodiment of the present application;

[0034] Figure 3This is a schematic structural diagram of another spaceborne AIS signal receiver based on FPGA provided by the embodiments of the present application. Detailed implementation manners

[0035] In the solution provided by the embodiments of the present application, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

[0036] To better understand the above technical solution, the technical solution of the present application will be described in detail below through the drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. Without conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0037] Figure 1 This shows a schematic structural diagram of a spaceborne AIS signal receiver based on FPGA provided by the embodiments of the present application.

[0038] As an example, in Figure 1In this case, the receiver includes a shift register 101, a shift register 102, a decision maker 103, and one or more path selection circuits 104. Among them, the shift register 101 and the shift register 102 are used to receive and store the data of the preprocessed real-time signal (such as the signal frame header). For example, both the shift register 101 and the shift register 102 are built by a Dynamic Random Access Memory (DRAM), which can perform shift register operations on the captured input data and can also control the output through the address line like a Random Access Memory (RAM). In addition, the storage depths of the shift register 101 and the shift register 102 are determined, which are related to the length of the frame header synchronization sequence of the AIS signal and the sampling rate. For example, the length of the frame header synchronization sequence of the AIS signal is 24 bits. If the single sampling rate is adopted, the storage depths of the shift register 101 and the shift register 102 are 24 bits; if the 4-fold sampling rate is adopted, the storage depths of the shift register 101 and the shift register 102 are 96 bits. The specific sampling rate adopted can be set according to the actual situation and is not limited here. In addition, due to the existence of collision interference between signals, the signals directly received by the spaceborne AIS signal receiver may be noise signals, AIS signals or other signals. That is to say, the data stored in the shift register 101 and the shift register 102 can be the data of noise signals, the data of AIS signals or the data of other signals. For the sake of easy understanding, the signals corresponding to the data stored in the shift register 101 and the shift register 102 are collectively referred to as real-time signals herein. Further, in the solution provided in the embodiments of the present application, the shift register 101 and the shift register 102 do not directly store the data of the original real-time signal, but store the data of the preprocessed real-time signal. For example, the preprocessing includes mixing, filtering and other processes. The preprocessed real-time signal is the real-time signal after mixing and filtering.

[0039] Further, in order to improve the granularity of AIS signal capture, in the solution provided in the embodiments of the present application, when the shift register 101 and the shift register 102 output one bit of data each, it is necessary to make a decision (or capture) on the data currently stored in the shift register 101 and the shift register 102; it should be understood that, as can be seen from the above, before storing the data of the real-time signal into the shift register 101 and the shift register 102, preprocessing (such as sampling processing) is performed on the real-time signal, that is, the data stored in the shift register 101 and the shift register 102 is actually the sampled point data of the real-time signal after sampling, and each output of one bit of data actually means each output of one sampled point data of the real-time signal. It can be seen from this that in the solution provided in the embodiments of the present application, the granularity of capture is to perform one capture for each output of one sampled point of the real-time signal by the shift register 101 and the shift register 102.

[0040] Since the storage depths of the shift register 101 and the shift register 102 are determined, it is not certain which fields or which part of the data of the real-time signal they store. For example, the data they can store can be the real-time signal frame header field, or they can store the data field or store a part of the frame header field and a part of the data field. Therefore, in order to capture the AIS signal, it is necessary to make a decision (or capture) on the data stored in the shift register 101 and the shift register 102, determine whether the stored data is the AIS signal frame header, and cache the AIS signal when it is determined that the stored data is the AIS signal frame header.

[0041] Further, in Figure 1 this, the receiver further includes a decision maker 103, which is coupled to the shift register 101 and the shift register 102, and is used to make a decision on the data currently stored in the shift register 101 and the shift register 102 every time the shift register 101 and the shift register 102 output one bit of data, so as to determine whether the currently stored data is the AIS signal frame header.

[0042] As described above, the shift register 101 and the shift register 102 are controlled to output through the address line. For example, the shift register 101 is controlled by the address line to output data under a preset symbol length, and the shift register 102 is controlled by the address line to output data under a relevant step length. That is, in the solution provided in the embodiments of the present application, it is possible to determine whether the data currently stored in the shift register 101 and the shift register 102 is the AIS signal frame header based on the autocorrelation of the signal.

[0043] Again, as an example, in Figure 1Among them, the decision maker 103 includes: a decision maker 1031, a decision maker 1032, and a decision maker 1033; among them, the decision maker 1031 is coupled to the shift register 101, and is used to calculate the signal power parameter according to the currently stored data when the shift register 101 and the shift register 102 each output one bit of data, and perform the first decision based on the power parameter to obtain the first decision result. For example, the power parameter includes calculating the signal power sum of L symbols and the maximum power value. Another example is that the process of performing the first decision based on the power parameter to obtain the first decision result is as follows:

[0044] First, the shift register 101 controls the output through the address line to be the data under the preset symbol length. T is the symbol period, and the signal power S of L symbols and the maximum power value val are calculated:

[0045] ⑴

[0046] ⑵

[0047] Among them, represents the real part of the signal; x Q (nT) represents the imaginary part of the signal.

[0048] Then, the first decision is made: judge whether holds, where a is a preset threshold; if it does not hold, the real-time signal is discarded; if it holds, the first decision is successfully made and the second decision is performed.

[0049] Furthermore, the decision maker 1032 is coupled to the decision maker 1032, the shift register 101, and the shift register 102, and is used to calculate the first correlation signal energy value at the 4T symbol interval according to the data currently stored in the shift register 101 and the shift register 102 if the first decision result is successful, and perform the second decision based on the first correlation signal energy value to obtain the second decision result. Another example is that the process of performing the second decision based on the first correlation signal energy value to obtain the second decision result is as follows:

[0050] The shift register 102 controls the output through the address line to be the data under the preset symbol length , where m represents the correlation step length. The first correlation signal energy value is calculated as follows:

[0051] ⑶

[0052] ⑷

[0053] When m = 4, calculate and the value, and make a second decision based on this value: determine whether h > bS 2 holds, where b is a preset threshold; if it holds, it indicates that the second decision is successful, and a third decision is made; if it does not hold, the real-time signal is discarded.

[0054] Further, the decision maker 1033 is coupled to the decision maker 1032, the shift register 101, and the shift register 102, and is used to, if the result of the second decision is successful, calculate the second correlation signal energy value at the 2T symbol interval based on the data stored in the current shift register 101 and the shift register 102, and make a third decision based on the second correlation signal energy value to obtain the result of the third decision. For another example, the process of making a third decision based on the second correlation signal energy value to obtain the result of the third decision is as follows:

[0055] For the above formulas (3) and (4), assume that when m = 2, the calculated and values are obtained, and a third decision is made based on this value: determine whether h < c·S 2 holds, where c is a preset threshold; if it holds, it indicates that the third decision is successful; if it does not hold, the real-time signal is discarded.

[0056] Jump to Figure 1 , when the decision result of the decision maker 103 is successful, for example, the success of the decision result means that the results of the first decision, the second decision, and the third decision are all successful, that is, the decision maker 103 makes a successful decision, and the decision result is sent to one or more path selection circuits 104. Among them, one or more path selection circuits 104 are used to receive and cache the AIS signal corresponding to the currently stored data based on the decision result.

[0057] Figure 2 shows the schematic structural diagram of the selection circuit provided by the embodiment of the present application.

[0058] As an example, in Figure 2 , each path selection circuit includes a shift register 1041, a selector 1042, a logic unit 1043, and a memory 1044; among them, the shift register 1041 is used to receive and store the frame header of the preprocessed real-time signal; the selector 1042 is coupled to the shift register 1041, the decision maker 103, and the logic unit 1043, and is used to select and connect when the decision result is successful, and send the frame header of the preprocessed real-time signal stored in the shift register 1041 to the logic unit 1043; the logic unit 1043 receives the frame header of the preprocessed real-time signal and the preprocessed real-time signal, and transfers the data it receives to the memory 1044; the memory 1044 is coupled to the logic unit 1043, and is used to store the frame header of the preprocessed real-time signal and the preprocessed real-time signal.

[0059] Furthermore, in the solution provided by the embodiments of the present application, since the spaceborne AIS signal receiver captures and caches the real-time signals received in real time, it may take multiple clock cycles for one AIS signal to be captured and cached. When the spaceborne AIS signal receiver receives multiple real-time signals, it may cause signal processing blockage. To improve the processing efficiency and avoid signal processing blockage. In Figure 1 the shown spaceborne AIS signal receiver includes multiple path selection circuits, and the multiple path selection circuits can receive and cache multiple AIS signals with successful decisions in parallel.

[0060] As an example, the multiple path selection circuit includes a first selection circuit and a second selection circuit; if the first shift register and the second shift register receive and store the data of the preprocessed first real-time signal, and the decision maker decides that the data of the first real-time signal stored in the first shift register and the second shift register is the AIS signal header, then the first selection circuit receives and caches the first AIS signal corresponding to the first real-time signal based on the decision result; if during the period when the first selection circuit receives and caches the first AIS signal, the first shift register and the second shift register also receive and store the data of the preprocessed second real-time signal; the decision maker makes a decision on the data of the second real-time signal and the decision result is that the data of the second real-time signal is the AIS signal header; the second selection circuit is used to receive and cache the second AIS signal corresponding to the second real-time signal based on the decision result.

[0061] Also as an example, as Figure 2 shown, the memory 1044 is a first-in first-out queue FIFO. The size of the first-in first-out queue is equal to the length of the synchronization sequence of the signals sampled in one time slot. For example, if the real-time signal is preprocessed at a 4-fold sampling rate, the size of the first-in first-out queue is 1024 bits.

[0062] Also as an example, the frame header of the same real-time signal may be captured multiple times. Therefore, to avoid this situation, the interval between two captures of the same AIS signal is not less than the length of one frame header synchronization sequence. For example, if the real-time signal is preprocessed at a 4-fold sampling rate, the interval between two captures is not less than 96 sampling points.

[0063] Also as an example, when capturing AIS signals of different channels, after one AIS signal of the same channel is successfully captured, then the AIS signal of another channel can be captured, and the time interval between two captures is not less than the length of one frame header synchronization sequence.

[0064] Also as an example, in Figure 1Among them, the spaceborne AIS signal receiver further includes: an output unit 105; the output unit 105 is coupled to one or more multiplexing circuits 104, and is configured to output the captured AIS signal. For example, the output unit 105 is coupled to the memory in each multiplexing circuit 104. When the memory is full of stored data, the output unit 105 outputs the captured AIS signal in the memory.

[0065] Furthermore, in the solution provided by the embodiments of the present application, if all of the one or more multiplexing circuits 104 are in a working state and the decision result sent by the decision maker is received, the decision result is ignored. For example, when all the multiplexing circuits of the spaceborne AIS signal receiver provided by the embodiments of the present application are performing AIS signal capture and another AIS signal is received, since there is no idle multiplexing circuit to process this AIS signal at present, the spaceborne AIS signal receiver will temporarily ignore the capture of this AIS signal until there is an idle multiplexing circuit, or directly abandon the capture of this AIS signal.

[0066] For the sake of easy understanding, the working principle of the spaceborne AIS signal receiver provided by the embodiments of the present application will be briefly introduced by way of example below.

[0067] Figure 3 The structural schematic diagram of another spaceborne AIS signal receiver based on FPGA provided by the embodiments of the present application is shown.

[0068] As an example, in Figure 3 Among them, the spaceborne AIS receiver includes a shift register a001, a shift register b002, a shift register c003, a shift register d004, a shift register d005, a decision maker 100, a selector c013, a selector d014, a selector e015, a logic unit c023, a logic unit d024, a logic unit e025, a FIFO c033, a FIFO d034, a FIFO e035, and an output unit 036.

[0069] Among them, the shift registers a001, b002, c003, d004, and d005 are all built by DRAM (distributed RAM). On the one hand, they can shift-register the captured input data (that is, the storage depth of the shifter is fixed. For every 1 bit of data shifted in, 1 bit of data must be shifted out). On the other hand, like RAM, they can control the output address through the address line to output the data in the specified shift register storage space; the storage depths of the shift registers a001, b002, c003, d004, and d005 are all the length of the AIS frame header synchronization sequence. For example, the length of the AIS frame header synchronization sequence is 24 bits. In an embodiment of the present application, the capture input is 4 times sampling. Therefore, this value is actually 96 bits. The lengths described below are all based on 4 times sampling; specifically, the receiver input is a real-time signal after preprocessing such as mixing and filtering (it may be pure noise or an AIS signal before capture and an AIS signal after capture). The shift registers a001, b002, c003, d004, and d005 will synchronously cache this signal; the purpose of designing and using multiple such shift registers is to avoid address line conflicts of a single shift register, and the outputs of the shift registers a001, b002, c003, d004, and d005 act on different targets.

[0070] Further, the outputs of the shift registers a001 and b002 are connected to the decision maker 100. The output of the shift register a001 acts on the first decision, the second decision, and the third decision of the decision maker 100. Every time the shift registers a001 and b002 are updated by 1 bit, the decision maker 100 sequentially makes the first decision, the second decision, and the third decision. If all three decisions pass, it is considered that the signal is a real AIS signal and can be captured; at the same time, because the capture uses signal autocorrelation, under the capture architecture described in the embodiment of the present application, the same frame header (96 bits after 4 times sampling) may be captured multiple times. Therefore, to avoid this situation, the interval between two frame header captures should not be less than 96 bits. Therefore, the frame header capture interval is designed as a configurable parameter.

[0071] Furthermore, the outputs of shift register c003, shift register d004, and shift register d005 are respectively connected to selector c013, selector d014, and selector e015; selectors c013, d014, and e015 are the first-level control logic for controlling the external output of the capture module, and their other input ends are connected to the output of decision maker 100. When decision maker 100 issues a capture success signal, selectors c013, d014, and e015 forward the outputs of the corresponding shift registers c003, d004, and d005 to the inputs of logic units c023, d024, and e025; specifically, the priority for selectors c013, d014, and e015 to start forwarding is selector c013 > selector d014 > selector e015, and at most one selector is started to forward the output data of the shift register during one successful capture; when all of shift registers c003, d004, and d005 are in the output state, the capture success signal of decision maker 100 will be ignored to ensure the full utilization of the throughput and resources of the front and back stages.

[0072] The outputs of selectors c013, d014, and e015 are respectively connected to the inputs of logic units c023, d024, and e025; logic units c023, d024, and e025 are the first-level control logic for controlling the external output of the capture module, and their other input ends are connected to the real-time signal after preprocessing such as mixing and filtering; when decision maker 100 issues a capture success signal, after selectors c013, d014, and e015 forward the outputs of the corresponding shift registers c003, d004, and d005 to logic units c023, d024, and e025, the logic units first control the output of the frame header (96bit) stored in the corresponding shift registers c003, d004, and d005, and then output the real-time signal after preprocessing such as mixing and filtering until the number of bits of the output reaches the set value (in an embodiment of the present invention, for AIS backup frequency points with a large number of AIS signals equal to or less than 1 time slot, this value is set to 4 times the sampling value of the number of bits of one time slot, that is, 1024bit. Also, because the continuous capture interval is 96bit, and when all of shift registers c003, d004, and d005 are in the output state, the capture success signal of decision maker 100 will be ignored, so at most 1024bit / 96bit captures can be completed in one time slot in this embodiment, and three capture outputs are performed).

[0073] The outputs of logic unit c023, logic unit d024, and logic unit e025 are respectively connected to the inputs of FIFO c033, FIFO d034, and FIFO e035; FIFO c033, FIFO d034, and FIFO e035 are all FIFOs. For example, in an embodiment of the present application, the FIFO depth is 1024 bits to adapt to one time slot length; FIFO c033, FIFO d034, and FIFO e035 buffer the data output by logic unit c023, logic unit d024, and logic unit e025, preventing timing conflicts when the captured data is output to the lower-level module.

[0074] The outputs of FIFO c033, FIFO d034, and FIFO e035 are respectively connected to the inputs of output unit 036; output unit 036 is the third-level control logic for controlling the external output of the capture module, and will control the output of FIFO c033, FIFO d034, and FIFO e035 according to the empty and full flags of FIFO c033, FIFO d034, and FIFO e035; the first FIFO to be full will be output first, and the output will stop until it is empty.

[0075] In the solution provided by the embodiment of the present application, when receiving other real-time signals and the shift registers 101 and 102 shift out data, the real-time signals corresponding to the frame headers stored in the shift registers 101 and 102 are judged and captured. That is, in the embodiment of the present application, a capture is performed for each received real-time signal sampling point, rather than capturing once in one time slot, thereby providing the granularity of capture and avoiding missing the capture of some AIS signals. In addition, when capturing signals in the embodiment of the present application, each selection circuit targets one AIS signal, thereby reducing the overhead of storage resources.

[0076] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. An on-board AIS signal receiver based on FPGA, characterized in that, Including: A first shift register, a second shift register, a decision maker, and one or more path selection circuits; wherein, The first shift register and the second shift register are used to receive and store in real time the data of the preprocessed real-time signal; The decision maker is coupled to the first shift register and the second shift register, and is used to make a decision on the data currently stored in the first shift register and the second shift register every time one bit of data is output by the first shift register and the second shift register, and when it is determined that the currently stored data is the AIS signal header, send the decision result to the one or more path selection circuits; One or more path selection circuits, which are used to receive and cache the AIS signal corresponding to the currently stored data based on the decision result; The decision maker includes: a first decision maker, a second decision maker, and a third decision maker, wherein, The first decision maker is coupled to the first shift register, and is used to calculate the signal power parameter according to the currently stored data when one bit of data is output by the first shift register and the second shift register, and make a first decision based on the power parameter to obtain a first decision result; The second decision maker is coupled to the first decision maker, the first shift register, and the second shift register, and is used to calculate the first correlation signal energy value at the 4T symbol interval according to the currently stored data if the first decision result is successful, and make a second decision based on the first correlation signal energy value to obtain a second decision result; The third decision maker is coupled to the second decision maker, the first shift register, and the second shift register, and is used to calculate the second correlation signal energy value at the 2T symbol interval according to the currently stored data if the second decision result is successful, and make a third decision based on the second correlation signal energy value to obtain a third decision result; wherein, if the third decision result is successful, it is determined that the currently stored data is the AIS signal header, and the third decision result is sent to the one or more path selection circuits.

2. The receiver according to claim 1, characterized in that, If there are multiple path selection circuits, the multiple path selection circuits receive and cache the multiple AIS signals with successful decisions in parallel.

3. The receiver according to claim 2, characterized in that, The multiple path selection circuits include a first selection circuit and a second selection circuit; If the first shift register and the second shift register receive and store the data of the first real-time signal after preprocessing, and the decision maker determines that the data of the first real-time signal stored in the first shift register and the second shift register is the AIS signal header, the first selection circuit receives and caches the first AIS signal corresponding to the first real-time signal based on the decision result; If during the period when the first selection circuit receives and caches the first AIS signal, the first shift register and the second shift register also receive and store the data of the second real-time signal after preprocessing; The decision result obtained by the decision maker making a decision on the data of the second real-time signal is that the data of the second real-time signal is the AIS signal header; The second selection circuit is configured to receive and cache the second AIS signal corresponding to the second real-time signal based on the judgment result.

4. The receiver according to claim 3, characterized in that If all of the one or more path selection circuits are in an operating state and the judgment result sent by the judge is received, the judgment result is ignored.

5. The receiver according to claim 4, characterized in that Each path selection circuit includes a third shift register, a selector, a logic unit, and a memory; wherein, The third shift register is configured to receive and store the data of the preprocessed real-time signal. The selector is coupled to the third shift register, the judge, and the logic unit, and is configured to select and connect when the judgment result is successful, and send the data of the preprocessed real-time signal stored in the third shift register to the logic unit. The logic unit receives the data of the preprocessed real-time signal and the preprocessed real-time signal, and transfers the received data to the memory. The memory is coupled to the logic unit and is configured to store the data of the preprocessed real-time signal and the preprocessed real-time signal.

6. The receiver according to claim 5, characterized in that, The memory is a first-in-first-out queue, wherein the size of the first-in-first-out queue is equal to the length of the synchronization sequence of the signals sampled in one time slot.

7. The receiver according to claim 6, wherein, When capturing AIS signals of different channels, after an AIS signal of the same channel is successfully captured, an AIS signal of another channel is captured, and the time interval between the two captures is not less than the length of a frame header synchronization sequence.

8. The receiver according to claim 7, wherein, Wherein, The interval between two captures of the same AIS signal is not less than the length of a frame header synchronization sequence.

9. The receiver according to claim 8, wherein Further included: An output unit; the output unit is coupled to one or more path selection circuits and is configured to output the cached AIS signal.

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