NVMe dual-host visible storage system, method, device and medium of VPX interface

Abstract

The application provides a VPX interface NVMe dual-host visual storage system, method, device and medium, which comprises a VPX connector and two NVMe storage modules; the VPX connector comprises P1 and P0, and the PCIE X8 signal is input into the NVMe storage module through the P1 in the VPX connector; wherein the NVMe storage module comprises an IPMI module, an NVMe host module, a NAND FLASH module, a DDR module, a power module, a DDR and NAND protection module. The application is improved in heat dissipation, reliability, rate, cost, expansibility and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular, to a VPX interface NVMe dual-host visual storage system, method, device and medium. BACKGROUND

[0002] With the increasing use of various software in servers, the amount of information data generated also increases dramatically, and the original 1T or 2T storage capacity of the server mainboard cannot meet the requirements, and larger and faster storage devices need to be loaded. Similar solutions to the present application include: by loading a board, expanding the storage interface on the board, and increasing the number of hard disks. Due to the increase in the number of interfaces, the reliability of the entire module decreases, and the transmission rate of each additional layer will have a certain delay.

[0003] Term explanation:

[0004] NVME: a logical device interface specification, similar to AHCI, based on device logical interface bus transmission protocol specification, Non-Volatile Memory express (NVMe). The PCIe device in the NVMe standard can be referred to as an NVMe storage device (or NVMe SSD), and the NVMe storage device has the characteristics of low power consumption and high performance.

[0005] VPX: VPX is a VITA organization based on VME bus, according to the increasing needs of the industry for bandwidth, a kind of embedded system bus standard realized by introducing high-speed serial bus technology.

[0006] IPMI: an intelligent platform management interface, which can cross different OS, Fireware and hardware platforms, and intelligently monitor the running information of the device voltage, current, temperature, etc. SUMMARY

[0007] In view of the defects in the prior art, the present application provides a VPX interface NVMe dual-host visual storage system, method, device and medium.

[0008] According to the VPX interface NVMe dual-host visual storage system, method, device and medium provided by the present application, the scheme is as follows:

[0009] In a first aspect, a VPX interface NVMe dual-host visual storage system is provided, which comprises a VPX connector and an NVMe storage module.

[0010] The NVMe storage module is provided in two ways; the VPX connector includes P1 and P0, and the PCIE X8 signal is input to the NVMe storage module through P1 in the VPX connector.

[0011] The NVMe storage module comprises an IPMI module, an NVMe host module, a NAND FLASH module, a DDR module, a power module, a DDR and NAND protection module.

[0012] The VPX connector P1 is electrically connected to the NVMe host module, the VPX connector P0 is electrically connected to the IPMI module, the NVMe host module is connected to the DDR module, the NAND FLASH module and the power module respectively, the IPMI module is connected to the NAND protection module and the power module respectively, and the NAND protection module is connected to the DDR module, the NAND FLASH module and the NVMe host module respectively.

[0013] Preferably, the system uses two-way NVMe host module circuits, and the two-way NVMe host module can be mounted separately or logically combined and mounted on the server CPU as a whole, and the capacity of the whole module reaches 16T.

[0014] Preferably, the NAND FLASH module uses 16 512G NAND Flash particles, the model is MT29E4T08CTHBBM5_3_1, and the nominal storage capacity is 8T.

[0015] Preferably, the core device of the NVMe host module is an IC-TAI-EN316801 controller, which complies with the NVMe 1.2.1 standard, supports PCIe Gen3 x8 / x4 8GT / s, and supports 16-way NAND channel.

[0016] Preferably, the DDR and NAND protection circuit module selects a TPS51200DRCR chip to build a memoryRegulator circuit.

[0017] Preferably, the core chip of the IPMI module selects an STC8F2K64S2-LQFP44 single-chip microcomputer, the temperature acquisition chip selects a MAX6625, and the current and voltage acquisition chip selects an LTC2991.

[0018] In a second aspect, an NVMe dual-host visual storage method of a VPX interface is provided, and the method comprises the following steps:

[0019] In step S1, direct current is input through P0 in the VPX connector, and DC 12V power is supplied to the power module, the DDR and NAND protection module after passing through the IMPI module.

[0020] Step S2: the power module converts the 12V voltage input by the IPMI module into different voltage grades for the NVMe host module; at the same time, the power module converts the 12V voltage input by the IPMI module into the voltage grade required by other modules, and the IPMI module supplies 3V3 auxiliary voltage to other modules.

[0021] Preferably, the step S2 specifically comprises: the power module converts 12V into 1.35V, 1.1V, 3.0V, 1.8V different voltage grades for the NVMe host module; wherein, 3.0V, 1.8V is supplied to the NAND FLASH module, and 1.35V is supplied to the DDR module; at the same time, the power module converts 12V into DC 3V3, and supplies auxiliary voltage to other modules via the IPMI module.

[0022] In a third aspect, a device is provided, the device comprising:

[0023] one or more processors;

[0024] a storage device for storing one or more programs,

[0025] When the one or more programs are executed by the one or more processors, the one or more processors implement the steps in the method.

[0026] In a fourth aspect, a computer-readable storage medium storing a computer program is provided, and the computer program is executed by a processor to implement the steps in the method.

[0027] Compared with the prior art, the present application has the following beneficial effects:

[0028] 1. The present application adopts a standard 6U size, has good universality and expansibility, adopts a VPX connector, has stronger mechanical properties, can stably operate in a harsh environment, and its transmission rate performance is not affected; meets the demand of server mass data storage, and has higher performance and lower power consumption than AHCI / SATA / SAS storage equipment;

[0029] 2. Compared with the previous scheme for increasing storage capacity by continuously expanding the storage interface to increase the number of hard disks, the present application has higher speed and heat dissipation effect, and can effectively and real-timely monitor the working condition. BRIEF DESCRIPTION OF DRAWINGS

[0030] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0031] Figure 1 It is a whole architecture diagram of the VPX storage module;

[0032] Figure 2 This is a schematic diagram of a single NVMe master control circuit for a VPX storage module;

[0033] Figure 3 This is a schematic diagram of the connection signal between the NVMe master control module and the power module;

[0034] Figure 4 This is a schematic diagram of the communication signal between the NVMe master module and the DDR module;

[0035] Figure 5 This is a schematic diagram of the communication signals between the NVMe master module and the NAND FLASH module;

[0036] Figure 6 Schematic diagram of the NAND protection circuit. DETAILED DESCRIPTION

[0037] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0038] The embodiment of the present invention provides an NVMe dual-master visual storage system with a VPX interface, which comprehensively considers heat dissipation, reliability, speed, cost, scalability and other aspects. Figure 1 Figure 2 shows the overall architecture of the VPX storage module. PCIE x8 signals are fed to the NVMe storage module via P1 in the VPX connector. A single NVMe storage module only requires PCIE x4 signals, so a dual-channel NVMe storage module was designed to increase storage capacity while effectively utilizing the 6U module space. The PCIE x8 signals are split into two PCIE x4 signals through the clock and reset buffers.

[0039] The schematic diagram of the NVMe storage module circuit principle of the module of the present invention is as follows Figure 2 As shown, the NVMe storage module is configured as two channels; the VPX connector includes P1 and P0, and the PCIE X8 signal is input to the NVMe storage module through P1 in the VPX connector, and each NVMe storage module receives the PCIE X4 signal; wherein, each NVMe storage module includes: IPMI module, NVMe master control module, NAND FLASH module, DDR module, power module (power module), DDR and NAND protection module.

[0040] The VPX connector P1 is electrically connected to the NVMe master control module, the VPX connector P0 is electrically connected to the IPMI module, the NVMe master control module is respectively connected to the DDR module, the NAND FLASH module and the power module; the IPMI module is respectively connected to the NAND protection module and the power module; the NAND protection module is respectively connected to the DDR module, the NAND FLASH module and the NVMe master control module.

[0041] Currently, servers are generally designed in a modular and structured manner. The chassis contains multiple 3U or 6U standard functional modules such as AC-DC conversion functions. The AC-DC module in the server converts 220V AC power into 12V DC power to power other modules in the server chassis. The server has a baseboard or backplane as a communication bridge between the modules. The present invention is based on such an application scenario.

[0042] Specific as Figure 2 As shown, in the present invention, direct current is input from P0 in the VPX connector, and supplies DC 12V to the power module (power module) and the protection module after passing through the IMPI module. The POWER module converts 12V into 1.35V, 1.1V, 3.0V, 1.8V and other gear voltages to power the NVMe master module, 3.0V and 1.8V to the NAND FLASH module, and 1.35V to the DDR module. At the same time, the POWER module converts 12V into DC 3V3 and supplies auxiliary voltages (address signals or I2C signal pull-ups, etc.) to other modules. The interactive signals between the NVMe master module and the power module are as follows: Figure 3 The interaction signals between the NVMe master module and the DDR module are shown in Figure 4 The interaction signals between the NVMe master module and the NAND FLASH module are shown in Figure 5 shown.

[0043] The core component of the NVMe master control module is the IC-TAI-EN316801 controller, which complies with the NVMe 1.2.1 standard and supports PCIe Gen3 x8 / x4 8GT / s. The IC-TAI-EN316801 controller supports the NVMe protocol and 16 NAND channels, allowing for increased storage capacity by mounting more NAND chips. It also comes with excellent after-sales technical support.

[0044] The NVMe master module supports 16-way NAND channel, and the maximum performance can achieve 5GB / s of sequential reading, 4GB / s of sequential writing, and 1M IOPS of 4KB random reading. In the design, 16 512G NAND Flash particles are used, the model is MT29E4T08CTHBBM5_3_1, and the nominal storage capacity is 8T. Because 2-way NVMe master module circuits are used, 2-way NAND FLASH modules can be mounted separately or logically combined and mounted on the server CPU as a whole. The capacity of the whole module is 16T.

[0045] The NVMe master module supports a dual-channel 40-bit DDR controller, supports DDR3L 1333MT / s, and has a maximum DRAM capacity of 16GB. The DDR module uses 10 MT41K1G8RKB-107_1 particles, and the cache capacity is 10GB. It provides reliable protection for high-speed data storage. The NAND particle is the smallest unit of storage, and the storage particle can be selected from different manufacturers and models. The DDR particle cache function is similar, and they are both essential parts of a computer.

[0046] The DDR and NAND protection circuit module selects the TPS51200DRCR chip of TI company to build a memory regulator circuit, as shown in Figure 6 The DDR protection circuit is the same as this.

[0047] The core chip of the IPMI module selects the STC8 series single-chip microcomputer of Macroblock Technology, the temperature acquisition chip selects MAX6625, and the current and voltage acquisition chip selects LTC2991. The real-time data collected is transmitted to the STC8 single-chip microcomputer through I2C. The STC8 single-chip microcomputer uploads the collected current, voltage, temperature and other information to the BMC module of the server through the I2C bus, so as to monitor the state of the module in real time.

[0048] The application also provides an NVMe double-master visual storage method of a VPX interface, which specifically comprises the following steps:

[0049] Step S1: DC power is input through P0 in the VPX connector, and DC 12V power is supplied to the power module and the NAND protection module after passing through the IMPI module.

[0050] Step S2: The POWER module converts 12V power into 1.35V, 1.1V, 3.0V, 1.8V and other voltage grades to supply power to the NVMe master module, supply 3.0V and 1.8V power to the NAND FLASH module, and supply 1.35V power to the DDR module; at the same time, the POWER module converts 12V power into DC 3V to supply auxiliary voltage to other modules.

[0051] The embodiment of the application provides a VPX interface NVMe dual-host visual storage system, method, device and medium, adopts a standard 6U size, has good universality and expansibility, adopts a VPX connector and has stronger mechanical properties, can stably operate in a harsh environment, and transmission rate performance is not affected; the demand of a server for mass data storage is met, and compared with AHCI / SATA / SAS storage equipment, higher performance and lower power consumption are obtained. Compared with the previous scheme of increasing the number of hard disks by continuously expanding the storage interface to increase the storage capacity, higher rate and heat dissipation effect are obtained, and the working condition can be effectively monitored in real time.

[0052] Those skilled in the art know that, in addition to implementing the system provided by the application and each device, module and unit thereof in a pure computer readable program code manner, the system provided by the application and each device, module and unit thereof can also be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming method steps to achieve the same function. Therefore, the system provided by the application and each device, module and unit thereof can be considered as a hardware component, and the devices, modules and units included therein for realizing various functions can also be considered as structures in the hardware component; the devices, modules and units for realizing various functions can also be considered as both software modules for realizing methods and structures in the hardware component.

[0053] The specific embodiments of the application are described above. It should be understood that the application is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the application. In the case of no conflict, the embodiments of the application and the features in the embodiments can be combined with each other at will.

Claims

1. A VPX interface NVMe dual-master visual storage system, characterized in that: include: VPX connectors and NVMe storage modules; The NVMe storage module is configured as two-way; the VPX connector includes P1 and P0, and the PCIE X8 signal is input to the NVMe storage module through P1 in the VPX connector; Among them, the NVMe storage module includes: IPMI module, NVMe master control module, NAND FLASH module, DDR module, power module, DDR and NAND protection module; The VPX connector P1 is electrically connected to the NVMe master control module, the VPX connector P0 is electrically connected to the IPMI module, the NVMe master control module is respectively connected to the DDR module, the NAND FLASH module and the power module; the IPMI module is respectively connected to the NAND protection module and the power module; the NAND protection module is respectively connected to the DDR module, the NAND FLASH module and the NVMe master control module; The system uses two NVMe master control module circuits. The two NVMe master control modules can be mounted separately or logically combined and mounted as a whole on the server CPU. The capacity of the entire module reaches 16T.

2. The NVMe dual-master visual storage system with VPX interface according to claim 1, characterized in that: The NANDFLASH module uses 16 512G NAND Flash particles, model MT29E4T08CTHBBM5_3_1, with a nominal storage capacity of 8T.

3. The NVMe dual-master visual storage system with VPX interface according to claim 1, characterized in that: The core component of the NVMe master control module is the IC-TAI-EN316801 controller, which complies with the NVMe1.2.1 standard, supports PCIe Gen3 x8 / x48GT / s, and supports 16 NAND channels.

4. The NVMe dual-master visual storage system with VPX interface according to claim 1, characterized in that: The DDR and NAND protection circuit module uses the TPS51200DRCR chip to construct the memory regulator circuit.

5. The NVMe dual-master visual storage system with VPX interface according to claim 1, characterized in that: The core chip of the IPMI module is the STC8F2K64S2-LQFP44 single-chip microcomputer, the temperature acquisition chip is the MAX6625, and the current and voltage acquisition chip is the LTC2991.

6. A VPX interface NVMe dual-master visual storage method, characterized in that: The NVMe dual-master visual storage system based on the VPX interface according to any one of claims 1 to 5 comprises: Step S1: DC power is input through P0 of the VPX connector and supplied to the power module, DDR and NAND protection module through the IMPI module. Step S2: The power module converts the 12V voltage input by the IPMI module into different voltage levels and distributes them to the NVMe master control module for power supply. At the same time, the power module converts the 12V voltage input by the IPMI module into the voltage level required by other modules. At the same time, the IPMI module supplies 3V3 auxiliary voltage to other modules.

7. The NVMe dual-master visual storage method of the VPX interface according to claim 6, characterized in that: The step S2 specifically includes: the power module converts 12V electricity into different voltage levels of 1.35V, 1.1V, 3.0V, and 1.8V and distributes them to the NVMe master control module; among them, 3.0V and 1.8V electricity are supplied to the NAND FLASH module, and 1.35V electricity is supplied to the DDR module; at the same time, the power module converts 12V electricity into DC 3V3 and supplies auxiliary voltage to other modules through the IPMI module.

8. A device, characterized in that The device comprises: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method according to any one of claims 6 to 7.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 6 to 7 are implemented.

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