An accumulator double buffering method and apparatus supporting work area and result area switching

Abstract

The application provides an accumulator double buffering method and device supporting work area and result area switching, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: taking one buffer in an idle state as a work area and taking another buffer in an unloading state as a result area when it is not determined that the two buffers are areas, and performing S2 when it is determined that the two buffers are areas; S2: controlling the work area to perform accumulation operation and store accumulation results and controlling the result area to unload data; S3: switching the work area to the result area when the accumulation results of the work area are stored, and switching the result area to the work area when the data of the result area is unloaded and cleared. The accumulation results of the application can be directly accumulated with the current buffer and written without waiting for the completion of the buffer data unloading, so that the delay of the accumulation result write-back can be hidden, and the performance of the systolic array is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-performance microprocessor design, in particular to an accumulator double buffering method and device supporting switching of working area and result area. BACKGROUND

[0002] Artificial intelligence technology is developing rapidly and has been widely used in many fields such as fingerprint recognition, voice processing, etc., and is also quietly changing people's lives. Neural networks are the basis of artificial intelligence technology. Common neural network models such as convolutional neural networks (CNN), recurrent neural networks (RNN), etc. are usually composed of multiple layers of networks, each layer containing a large number of convolution and matrix multiplication operations, which requires occupying more hardware resources. In order to accelerate the convolution and matrix multiplication operations in neural networks, the academic and industrial circles have proposed a systolic array structure. When the systolic array is working, the north-end data is transmitted from north to south, and the west-end data is transmitted from west to east, to drive the basic cells in the systolic array to complete matrix multiplication operations by data flow, and send the intermediate accumulation results to the south-side accumulator buffer for accumulation and caching. When receiving the unloading signal from the systolic array controller, the data in the accumulation buffer will be written back to the local data memory (LDM) outside the array.

[0003] The existing technology usually adopts a single accumulator buffer design, that is, there is only one accumulator buffer. The disadvantage of this design is that when the accumulation result is ready to be written back to the accumulator buffer at the end of the current calculation, it must be ensured that the current accumulator buffer is in an idle state and the entries are cleared to 0. If the accumulator buffer is unloading data at this time, it must wait until the accumulator buffer unloads and clears to 0. This will increase the delay of writing back the accumulation result. SUMMARY

[0004] In order to solve the above problems, the embodiments of the present application provide an accumulator double buffering method and device supporting switching of working area and result area.

[0005] In a first aspect, the embodiments of the present application provide an accumulator double buffering method supporting switching of working area and result area, comprising the following steps:

[0006] S1: when the two buffers are not determined as working area and result area, one buffer in an idle state is used as working area and the other buffer in an unloading state is used as result area, and S2 is executed when the two buffers are determined as working area and result area;

[0007] S2: controlling the working area to perform accumulation operation and store the accumulation result, and controlling the result area to unload data;

[0008] S3: switching the buffer as the result area when the accumulation result storage in the work area is completed, and switching the buffer as the work area when the data unloading in the result area is completed and cleared.

[0009] Preferably, the step S1 specifically comprises:

[0010] S11: acquiring the area information of the two buffers respectively;

[0011] S12: if the two buffers have determined area information respectively, executing S2, if the two buffers have no determined area information, executing downwardly;

[0012] S13: acquiring the state information of the two buffers respectively;

[0013] S14: taking one buffer in the idle state as the work area, and taking the other buffer in the unloading state as the result area.

[0014] Preferably, the step of controlling the work area to perform accumulation operation and store the accumulation result specifically comprises:

[0015] S21: sending the buffer address to the work area;

[0016] S22: controlling the work area to read the source operand in the first preset entry pointed by the buffer address;

[0017] S23: acquiring the intermediate result of the first preset row calculation in the systolic array, and performing accumulation operation on the intermediate result and the source operand;

[0018] S24: writing the accumulation result into the first preset entry.

[0019] Preferably, the step of controlling the result area to unload data specifically comprises:

[0020] S25: sending the unloading entry address to the result area;

[0021] S26: controlling the result area to read the unloading content in the second preset entry pointed by the unloading entry address;

[0022] S27: writing the unloading content in the second preset entry back to the local data storage.

[0023] In the second aspect, the embodiment of the present application provides an accumulator double-buffering device supporting work area and result area switching, comprising

[0024] a determining module, configured to take one buffer in the idle state as the work area and take the other buffer in the unloading state as the result area when it is not determined that the two buffers are respectively the work area and the result area;

[0025] The accumulator buffer control module is configured to control the working area to perform accumulation operation and store the accumulation result, and control the result area to unload data.

[0026] The switching module is configured to switch one buffer as the working area when the accumulation result of the working area is stored, and switch another buffer as the result area when the data of the result area is unloaded and cleared.

[0027] Preferably, the determining module comprises

[0028] The first information acquisition unit is configured to acquire the area attribute information of the two buffers respectively.

[0029] The second information acquisition unit is configured to acquire the state information of the two buffers respectively when the area attribute information of the two buffers is not determined.

[0030] The setting unit is configured to set one buffer in the idle state as the working area, and set another buffer in the unloading state as the result area.

[0031] Preferably, the accumulator buffer control module comprises

[0032] The first address sending unit is configured to send the buffer address to the working area.

[0033] The first control unit is configured to control the working area to read the source operand in the first preset entry pointed by the buffer address.

[0034] The first calculation unit is configured to acquire the intermediate result of the first preset row calculation in the systolic array, and perform accumulation operation on the intermediate result and the source operand.

[0035] The first storage unit is configured to write the accumulation result into the first preset entry.

[0036] Preferably, the accumulator buffer control module further comprises

[0037] The second address sending unit is configured to send the unloading entry address to the result area.

[0038] The second control unit is configured to control the result area to read the unloading content in the second preset entry pointed by the unloading entry address.

[0039] The second storage unit is configured to write the unloading content in the second preset entry back to the local data storage.

[0040] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor. When the processor executes the computer program, the steps of the method provided in the first aspect or any possible implementation manner of the first aspect are implemented.

[0041] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps of the method provided in the first aspect or any possible implementation manner of the first aspect.

[0042] The beneficial effects of the present application are as follows: if one of the two buffers which will be in an idle state when the other buffer is in a working area or a result area is determined as the working area and the other buffer which will be in an unloaded state is determined as the result area, if the two buffers are distributed as one of the working area and the result area are executed in S2, then the working area is controlled to perform accumulation operation, the accumulation result is stored, the result area is controlled to unload data, finally, when the accumulation result in the working area is stored, one of the buffers which is as the working area is switched to the result area, when the data in the result area is unloaded and cleared, the other buffer which is as the result area is switched to the working area, one of the buffers is in accumulation and cache mode, and the other buffer is in unloading mode, compared with the single buffer mode, the accumulation result can be directly accumulated with the current buffer and written without waiting for the completion of the buffer data unloading, thus the delay of the accumulation result write-back can be hidden, and the performance of the systolic array is improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0044] Figure 1 A flowchart of an accumulator double-buffering method supporting working area and result area switching provided by the embodiments of the present application;

[0045] Figure 2 A structural diagram of an accumulator double-buffering device provided by the embodiments of the present application;

[0046] Figure 3 A structural diagram of an electronic device provided by the embodiments of the present application;

[0047] Figure 4 A double-accumulator buffering diagram in the accumulator double-buffering method supporting working area and result area switching provided by the embodiments of the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application.

[0049] In the following description, the terms "first", "second", etc. are used only for the purpose of description, and should not be interpreted in a relative way, i.e. indicating or implying relative importance. The following description provides a number of examples of the present application, which can be replaced or combined between different examples, and thus the present application can be considered to include all possible combinations of the same and / or different examples described. Thus, if one example includes features A, B, C, and another example includes features B, D, the present application should be considered to include an example comprising one or more of all possible combinations of A, B, C, D, even if this example is not explicitly described in the following.

[0050] The following description provides examples, and is not intended to limit the scope, applicability or examples set forth in the claims. Changes can be made in the function and arrangement of elements described without departing from the scope of the application. Various examples can omit, substitute, or add various procedures or components as appropriate. For instance, the methods described can be performed in an order different than described, and various steps can be added, omitted, or combined. Also, features described with respect to some examples can be combined in other examples.

[0051] Reference will now be made to Figure 1 . Figure 1 is a flowchart of an accumulator double buffering method supporting switching between a work area and a result area provided by an embodiment of the present application. In the embodiment of the present application, the method comprises the following steps:

[0052] S1: when the two buffers are not determined to be work areas or result areas, one buffer in an idle state is used as a work area, and the other buffer in an unloaded state is used as a result area, and when the two buffers are determined to be work areas or result areas, S2 is performed;

[0053] S2: controlling the work area to perform accumulation operation and store the accumulation result, and controlling the result area to unload data;

[0054] S3: when the accumulation result of the work area is stored, the buffer is switched to a result area, and when the data of the result area is unloaded and cleared, the buffer is switched to a work area.

[0055] In the embodiment of the present application, the double-accumulator buffer design is proposed, and the two buffers are alternately used, that is, one buffer is used as a working area, and the other buffer is used as a result area, so as to hide the accumulation result write-back delay. When the accumulation result needs to be written to the accumulation buffer, it is necessary to ensure that the buffer is in an idle state. In the present application, two buffers are provided. At the beginning, if it cannot be determined which area the two buffers are distributed to, that is, it cannot be determined that the two buffers are distributed to one of the working area and the result area, it is necessary to first determine which area the two buffers are distributed to, and the buffer in the idle state is used as the working area, and the other buffer in the unloaded state is used as the result area. If the two buffers can be determined to be distributed to which area, S2 can be directly executed.

[0056] In an implementable manner, S1 specifically includes the following steps.

[0057] S11: respectively acquiring area attribute information of the two buffers;

[0058] S12: if the two buffers respectively have determined area attribute information, executing S2, and if the two buffers do not have determined area attribute information, executing downwardly;

[0059] S13: respectively acquiring state information of the two buffers;

[0060] S14: using one buffer in the idle state as the working area, and using the other buffer in the unloaded state as the result area.

[0061] In the embodiment of the present application, if the two buffers respectively have determined area attribute information, that is, if one buffer is the working area and the other buffer is the result area, the area attribute information of one buffer is the working area, and the area attribute information of the other buffer is the result area. If the two buffers do not have determined area attribute information, the state information corresponding to the two buffers is respectively acquired, the buffer is determined to be in which area according to the state information, one buffer in the idle state is used as the working area, and the other buffer in the unloaded state is used as the result area.

[0062] In an implementable manner, the control of the working area to perform the accumulation operation and store the accumulation result specifically includes the following steps.

[0063] S21: sending a buffer address to the working area;

[0064] S22: controlling the working area to read a source operand in a first preset entry pointed by the buffer address;

[0065] S23: acquiring an intermediate result calculated by a first preset row in the systolic array, and performing an accumulation operation on the intermediate result and the source operand;

[0066] S24: writing the accumulation result into the first preset entry.

[0067] In an implementation, the step of controlling the result area to unload data specifically includes:

[0068] S25: sending an unload entry address to the result area;

[0069] S26: controlling the result area to read the unload content in the second preset entry pointed by the unload entry address;

[0070] S27: writing the unload content in the second preset entry back to the local data memory.

[0071] In the embodiments of the present application, the double accumulator buffer is two buffers with the same bit width and depth. The buffer has two ports for reading and writing, and supports one buffer in the accumulation and caching mode (referred to as accumulation buffer, also referred to as working area), that is, according to the buffer address provided by the accumulator buffer control logic, the source operand of the corresponding entry is read, the intermediate result calculated by the southernmost row of the systolic array is accumulated, and the accumulation result is written into the original entry; the other buffer is in the data unloading and 0 clearing mode (referred to as unloading buffer, also referred to as result area), that is, according to the unload entry address generated by the accumulator buffer control logic, the content of the corresponding entry is written back to the LDM. When the two buffers complete the current task, that is, the data in the unloading buffer has been written back to the LDM and cleared to 0, the accumulation buffer completes the accumulation of all intermediate results and writes them into the accumulation buffer, and the accumulator buffer control logic switches the two buffers. The original accumulation buffer is switched to the unloading buffer, and the data is unloaded when the unloading signal from the accumulator buffer control logic is received; the original unloading buffer becomes the accumulation buffer, and the intermediate results are accumulated and cached after the systolic array completes the calculation.

[0072] Referring to Figure 4 , Figure 4Figure 1 is a schematic diagram of a double accumulator buffer in an accumulator double buffer method supporting switching between a work area and a result area provided by an embodiment of the present application. The two buffers have the same bit width and depth, and are switched back and forth between the work area and the result area. When initialized, both buffers are cleared to 0, and are in an idle mode. When a round of calculation is completed, the accumulator buffer control logic selects buffer 0 as the accumulation buffer, and the accumulated result is written into buffer 0. At this time, buffer 0 is the work area, and buffer 1 is in an idle state. When an unload signal is received, buffer 0 becomes the result area, and the content of buffer 0 is written into the LDM. Buffer 1 receives the intermediate result from the systolic array, and writes the accumulated result into buffer 1, which becomes the work area at this time. When the intermediate result accumulation is completed and written into buffer 1, buffer 1 becomes the result area, and is ready to unload data. When the content of buffer 0 is completely written back to the LDM and cleared to 0, buffer 0 becomes the work area, and is ready to accumulate results and cache. The accumulator buffer control logic switches the two buffers according to the rules. The double accumulator buffer supports one buffer in an accumulation and caching mode, and the other buffer in an unload mode. The two modes are switched by the control logic. Compared with the single buffer mode, the intermediate result can be directly accumulated with the current accumulation buffer and written without waiting for the completion of the buffer data unloading, so that the delay of the accumulation result write-back can be hidden, and the performance of the systolic array is improved.

[0073] The application will be described in greater detail with reference to the drawings, in which Figure 2 The accumulator double buffer device supporting switching between a work area and a result area provided by an embodiment of the present application will be described in detail. It should be noted that the Figure 2 The accumulator double buffer device supporting switching between a work area and a result area shown in the figure is used to execute the method of the embodiment shown in the figure. Figure 1 The method of the embodiment shown in the figure is described only with reference to the parts related to the embodiment of the present application, and the specific technical details not disclosed are described with reference to the embodiment shown in the figure. Figure 1 The embodiment shown in the figure.

[0074] Please refer to Figure 2 , Figure 2 Figure 1 is a structure schematic diagram of an accumulator double buffer device supporting switching between a work area and a result area provided by an embodiment of the present application. As shown in the figure, the device includes Figure 2 a determination module 201, used to determine one buffer in an idle state as a work area and the other buffer in an unload state as a result area when it is not determined which area the two buffers are in;

[0075] The determination module 201 is used to determine one buffer in an idle state as a work area and the other buffer in an unload state as a result area when it is not determined which area the two buffers are in.

[0076] The accumulator buffer control module 202 is used to control the work area to perform accumulation operation and store the accumulation result, and control the result area to unload data.

[0077] The switching module 203 is used to switch one buffer as the work area when the accumulation result of the work area is stored, and switch another buffer as the result area when the data of the result area is unloaded and cleared.

[0078] In an implementation, the determining module 201 comprises

[0079] The first information obtaining unit is used to obtain the area attribute information of the two buffers respectively.

[0080] The second information obtaining unit is used to obtain the state information of the two buffers respectively when the two buffers do not have the area attribute information.

[0081] The setting unit is used to set one buffer in the idle state as the work area, and set another buffer in the unloading state as the result area.

[0082] In an implementation, the accumulator buffer control module 202 comprises

[0083] The first address sending unit is used to send the buffer address to the work area.

[0084] The first control unit is used to control the work area to read the source operand in the first preset entry pointed by the buffer address.

[0085] The first calculation unit is used to obtain the intermediate result of the first preset row calculation in the systolic array, and perform accumulation operation on the intermediate result and the source operand.

[0086] The first storage unit is used to write the accumulation result into the first preset entry.

[0087] In an implementation, the accumulator buffer control module 202 further comprises

[0088] The second address sending unit is used to send the unloading entry address to the result area.

[0089] The second control unit is used to control the result area to read the unloading content in the second preset entry pointed by the unloading entry address.

[0090] The second storage unit is used to write the unloading content in the second preset entry back to the local data storage.

[0091] Those skilled in the art can clearly understand that the technical solutions of the embodiments of the present application can be implemented by means of software and / or hardware. The "unit" and "module" in the specification refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, and the hardware can be, for example, a Field-Programmable Gate Array (FPGA), an Integrated Circuit (IC), and the like.

[0092] The various processing units and / or modules of the embodiments of the present application can be implemented by analog circuits that implement the functions of the embodiments of the present application, or can be implemented by software that executes the functions of the embodiments of the present application.

[0093] Referring to Figure 3 , a structural schematic diagram of an electronic device related to the embodiments of the present application is shown, which can be used to implement the method in the embodiments shown in Figure 1 . As shown in Figure 3 , the electronic device 300 can include at least one central processor 301, at least one network interface 304, a user interface 303, a memory 305, and at least one communication bus 302.

[0094] The communication bus 302 is used to realize the connection and communication between the components.

[0095] The user interface 303 can include a display screen (Display) and a camera (Camera), and the optional user interface 303 can also include a standard wired interface and a wireless interface.

[0096] The network interface 304 can optionally include a standard wired interface and a wireless interface (such as a WI-FI interface).

[0097] The central processor 301 can include one or more processing cores. The central processor 301 connects various parts within the entire electronic device 300 by various interfaces and lines, and performs various functions of the terminal 300 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 305, and calling data stored in the memory 305. Alternatively, the central processor 301 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The central processor 301 can integrate one or a combination of a central central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes an operating system, a user interface, and an application program; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the central processor 301, but can be implemented by a separate chip.

[0098] The memory 305 can include a random access memory (RAM) and can also include a read-only memory (ROM). Alternatively, the memory 305 includes a non-transitory computer-readable storage medium. The memory 305 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 305 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store data involved in the above-mentioned various method embodiments, etc. The memory 305 can also be at least one storage device located away from the above-mentioned central processor 301. As shown, the memory 305 as a computer storage medium can include an operating system, a network communication module, a user interface module, and program instructions. Figure 3 As shown, the memory 305 as a computer storage medium can include an operating system, a network communication module, a user interface module, and program instructions.

[0099] In Figure 3The electronic device 300 shown, the user interface 303 is mainly used for providing the interface for the user to input, obtaining the data input by the user; and the central processing unit 301 can be used for calling the accumulator double-buffering application program stored in the memory 305 to support the switching of the work area and the result area, and specifically performing the following operations:

[0100] S1: when the two buffers are not determined to be work areas, one buffer in an idle state is used as a work area, and the other buffer in an unloaded state is used as a result area; when the two buffers are determined to be work areas, S2 is performed;

[0101] S2: controlling the work area to perform accumulation operation and store the accumulation result, and controlling the result area to unload data;

[0102] S3: when the accumulation result of the work area is stored, the buffer is switched to a result area; when the data in the result area is unloaded and cleared, the buffer is switched to a work area.

[0103] The application also provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the steps of the above method. The computer readable storage medium can include but is not limited to any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, micro-drives, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0104] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the action order described, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0105] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0106] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely illustrative, and the division of units can be different, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some intervening general purpose or special purpose hardware devices, or can be in electrical or other forms.

[0107] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0108] In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present alone, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0109] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0110] Those of ordinary skill in the art can understand that all or part of the steps of the various methods in the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer readable storage medium, which can include a flash disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, etc.

[0111] The above merely show example embodiments of the present disclosure, and cannot limit the scope of the present disclosure. That is, equivalent changes and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Those skilled in the art will readily conceive of other implementations of the present disclosure upon considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the art not described in the present disclosure. The specification and examples are merely considered as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. An accumulator double buffering method supporting work area and result area switching, characterized by, The method comprises the following steps: S1: taking one buffer in an idle state as a working area and the other buffer in an unloading state as a result area when the two buffers do not have determined zone attributes, and performing S2 when the two buffers have determined zone attributes; S2: controlling the working area to perform accumulation operation and store the accumulation result, and controlling the result area to unload data; S3: switching the buffer as the working area to the result area when the accumulation result of the working area is stored, and switching the buffer as the result area to the working area when the data of the result area is unloaded and cleared; controlling the working area to perform accumulation operation and store the accumulation result specifically comprises: S21: sending a buffer address to the working area; S22: controlling the working area to read a source operand in a first preset entry pointed by the buffer address; S23: obtaining an intermediate result calculated by a first preset row in the systolic array, and performing accumulation operation on the intermediate result and the source operand; S24: writing the accumulation result into the first preset entry; controlling the result area to unload data specifically comprises: S25: sending an unloading entry address to the result area; S26: controlling the result area to read unloading content in a second preset entry pointed by the unloading entry address; S27: writing the unloading content in the second preset entry back to the local data storage.

2. An accumulator double buffering method of supporting work area and result area switching according to claim 1, characterized in that, Step S1 specifically comprises: S11: obtaining zone attribute information of the two buffers respectively; S12: performing S2 if the two buffers have determined zone attribute information respectively, and executing the following steps if the two buffers do not have determined zone attribute information; S13: obtaining state information of the two buffers respectively; S14: taking one buffer in an idle state as a working area and the other buffer in an unloading state as a result area.

3. An accumulator double buffering device supporting work area and result area switching, characterized by: The method comprises a determining module for taking one buffer in an idle state as a working area and the other buffer in an unloading state as a result area when the two buffers do not have determined zone attributes; an accumulator buffer control module for controlling the working area to perform accumulation operation and store the accumulation result, and controlling the result area to unload data; a switching module for switching one buffer as the working area to the result area when the accumulation result of the working area is stored, and switching the other buffer as the result area to the working area when the data of the result area is unloaded and cleared; the accumulator buffer control module comprises a first address sending unit for sending a buffer address to the working area; a first control unit for controlling the working area to read a source operand in a first preset entry pointed by the buffer address; a first calculation unit for obtaining an intermediate result calculated by a first preset row in the systolic array, and performing accumulation operation on the intermediate result and the source operand; a first storage unit for writing the accumulation result into the first preset entry; the accumulator buffer control module further comprises a second address sending unit for sending an unloading entry address to the result area; a second control unit for controlling the result area to read unloading content in a second preset entry pointed by the unloading entry address; a second storage unit for writing the unloading content in the second preset entry back to the local data storage.

4. An accumulator double buffering device supporting work area and result area switching as recited in claim 3, characterized in that: the determining module comprises a first information obtaining unit for obtaining zone attribute information of the two buffers respectively; The second information acquisition unit is configured to acquire state information of the two buffers respectively when the two buffers do not have determined zone attribute information. The setting unit is configured to set one buffer in an idle state as a work area and set the other buffer in an unloading state as a result area.

5. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor, when executing the computer program, implements the steps of the method according to any one of claims 1-2.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the method according to any one of claims 1-2.

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