Package substrate, method of manufacturing the same, and chip package structure

Abstract

The present application provides a packaging substrate, a manufacturing method thereof and a chip packaging structure. The packaging substrate includes a first redistribution line structure layer, a plurality of conductive connecting members, a connecting structure layer, at least one reinforcing rib and a packaging adhesive. The conductive connecting members are disposed on a first surface of the first redistribution line structure layer and electrically connected with the first redistribution line structure layer. The connecting structure layer is disposed on a second surface of the first redistribution line structure layer and includes a base material and a plurality of contact pads. A top surface and a bottom surface of each contact pad are exposed to an upper surface and a lower surface of the base material, respectively. The contact pads are electrically connected with the first redistribution line structure layer. The reinforcing rib is disposed on the first surface of the first redistribution line structure layer and located between at least two of the conductive connecting members. The packaging adhesive is disposed on the first surface of the first redistribution line structure layer and covers the conductive connecting members and the reinforcing rib.

Description

TECHNICAL FIELD

[0001] The present application relates to a packaging substrate, a manufacturing method thereof, and a chip packaging structure using the same. BACKGROUND

[0002] In the prior art, two and a half dimension integrated circuit stacking (2.5D IC) stacking needs to use a silicon interposer, so that the packaging cost is high. In order to effectively reduce the packaging cost, the silicon interposer is replaced by an organic interposer. However, in the assembly process, the assembly surface is often warped due to heat, so that the surface co-planarity of the packaging substrate is poor, and thus the chip cannot be successfully assembled on the packaging substrate. SUMMARY

[0003] The present application relates to a packaging substrate, a manufacturing method thereof, and a chip packaging structure using the same.

[0004] The present application relates to a packaging substrate, a manufacturing method thereof, and a chip packaging structure using the same.

[0005] The present application relates to a packaging substrate, a manufacturing method thereof, and a chip packaging structure using the same.

[0006] According to an embodiment of the present application, the packaging substrate includes a first redistribution line structure layer, a plurality of conductive connecting members, a connecting structure layer, at least one reinforcing rib, and a packaging adhesive. The first redistribution line structure layer has a first surface and a second surface opposite to each other. The conductive connecting members are disposed on the first surface of the first redistribution line structure layer and electrically connected to the first redistribution line structure layer. The connecting structure layer is disposed on the second surface of the first redistribution line structure layer. The connecting structure layer includes a substrate and a plurality of contact pads. A top surface and a bottom surface of each contact pad are exposed to an upper surface and a lower surface of the substrate, respectively. The contact pads are electrically connected to the first redistribution line structure layer. The reinforcing rib is disposed on the first surface of the first redistribution line structure layer and located between at least two of the conductive connecting members. The packaging adhesive is disposed on the first surface of the first redistribution line structure layer and covers the conductive connecting members and the reinforcing rib.

[0007] According to an embodiment of the present application, a method for manufacturing a package substrate includes the following steps. A substrate and a plurality of conductive bars are provided. The conductive bars are embedded in the substrate, and one end of each of the conductive bars is exposed on one side of the substrate. A first redistribution line structure layer is formed on the side of the substrate. A plurality of conductive connectors and at least one reinforcing rib are formed on the first redistribution line structure layer, wherein the reinforcing rib is located between at least two of the conductive connectors. A package adhesive is formed on the first redistribution line structure layer to cover the conductive connectors and the reinforcing rib. After the package adhesive is formed, part of the substrate and part of the conductive bars are removed to form a connection structure layer. The connection structure layer includes a base material and a plurality of contact pads. A top surface and a bottom surface of each of the contact pads are exposed on an upper surface and a lower surface of the base material, respectively.

[0008] According to an embodiment of the present application, a chip package structure includes a package substrate and at least one chip. The package substrate includes a first redistribution line structure layer, a plurality of conductive connectors, a connection structure layer, at least one reinforcing rib, and a package adhesive. The first redistribution line structure layer has a first surface and a second surface opposite to each other. The conductive connectors are disposed on the first surface of the first redistribution line structure layer and electrically connected to the first redistribution line structure layer. The connection structure layer is disposed on the second surface of the first redistribution line structure layer. The connection structure layer includes a base material and a plurality of contact pads. A top surface and a bottom surface of each of the contact pads are exposed on an upper surface and a lower surface of the base material, respectively. The contact pads are electrically connected to the first redistribution line structure layer. The reinforcing rib is disposed on the first surface of the first redistribution line structure layer and located between at least two of the conductive connectors. The package adhesive is disposed on the first surface of the first redistribution line structure layer and covers the conductive connectors and the reinforcing rib. The chip is disposed on the package substrate and electrically connected to the contact pads of the connection structure layer.

[0009] Based on the above, in the design of the package substrate of the present application, the conductive connectors and the reinforcing rib are disposed on the same surface of the first redistribution line structure layer, and the package adhesive covers the conductive connectors and the reinforcing rib, thereby the warpage of the package substrate can be inhibited and reduced, and the package substrate of the present application has better flatness and structural reliability. Furthermore, in the manufacturing process of the package substrate of the present application, a temporary substrate is not needed, and a laser debond manufacturing process is not needed, so that the manufacturing cost can be effectively reduced. In addition, in the manufacturing process of the package substrate of the present application, the package adhesive covers the conductive connectors and the reinforcing rib, so that the back surface of the package substrate becomes flat, which is beneficial to the subsequent assembly of the chip on the front surface of the package substrate. In addition, since the package substrate of the present application has better flatness, the chip package structure using the package substrate of the present application can have better package yield. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1A-1E FIG. 1 is a cross-sectional schematic view of a method for manufacturing a package substrate according to an embodiment of the present application;

[0011] Figures 1F-1J is a cross-sectional schematic view of a manufacturing method of a chip package structure by disposing a chip on a package substrate of Figure 1E ;

[0012] Figures 2A-2D is a cross-sectional schematic view of a manufacturing method of a package substrate according to another embodiment of the present application;

[0013] Figures 2E-2I is a cross-sectional schematic view of a manufacturing method of a chip package structure by disposing a chip on a package substrate of Figure 2D ;

[0014] Figures 3A-3C is a cross-sectional schematic view of a manufacturing method of a package substrate according to another embodiment of the present application;

[0015] Figures 3D-3H is a cross-sectional schematic view of a manufacturing method of a chip package structure by disposing a chip on a package substrate of Figure 3C ;

[0016] Figure 4A is a cross-sectional schematic view of a chip package structure according to an embodiment of the present application;

[0017] Figure 4B is a cross-sectional schematic view of a chip package structure according to an embodiment of the present application;

[0018] Figures 5A-5D is a bottom view of various package substrates according to embodiments of the present application.

[0019] BRIEF DESCRIPTION OF DRAWINGS

[0020] 10a, 10b, 10c, 10d, 10e: chip package structure

[0021] 20: drive substrate

[0022] 22: connection pad

[0023] 30: solder ball

[0024] 100a, 100b, 100c, 100e, 100f, 100g, 100h, 100i: package substrate

[0025] 110: connection structure layer

[0026] 112: base material

[0027] 112a: base

[0028] 113: one side

[0029] 114: connection pad;

[0030] 114a: conductive strip;

[0031] 115: one end;

[0032] 120: first redistribution line structure layer;

[0033] 121, 123: dielectric layer;

[0034] 122, 124: redistribution line layer;

[0035] 125, 127: conductive via;

[0036] 126: connection pad;

[0037] 130, 130a, 130b, 130c, 130e: conductive connection;

[0038] 132a, 132b, 132c: first bottom surface;

[0039] 140a, 140b, 140c, 140f, 140g, 140h, 140i, 240: stiffener; 142a: second bottom surface;

[0040] 144i: first stiffener;

[0041] 146i: second stiffener;

[0042] 150: encapsulation;

[0043] 160, 170: second redistribution line structure layer;

[0044] 161, 163, 171, 173: dielectric layer;

[0045] 162, 172: redistribution line layer;

[0046] 164: connection pad;

[0047] 165, 167, 175, 177: conductive via;

[0048] 180: build-up structure layer;

[0049] 182: glass fiber substrate;

[0050] 183: first via;

[0051] 184: first patterned conductive layer;

[0052] 185: second via;

[0053] 186: second patterned conductive layer;

[0054] 187: third via hole;

[0055] 200, 250: chip;

[0056] 201: peripheral surface;

[0057] 203: back surface;

[0058] 210: microsolder joint;

[0059] 220: underfill;

[0060] 230: sealing material;

[0061] 231: surface;

[0062] H, H', H": length;

[0063] L: cutting line;

[0064] F1: first surface;

[0065] F2: second surface;

[0066] S1: top surface;

[0067] S2: bottom surface;

[0068] S3: upper surface;

[0069] S4: lower surface;

[0070] T: thickness. DETAILED DESCRIPTION

[0071] Reference will now be made to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0072] Figures 1A-1E is a cross-sectional schematic view of a method of manufacturing a package substrate according to an embodiment of the present application. Regarding the method of manufacturing a package substrate of the present embodiment, first, refer to Figure 1A , a substrate 112a and a plurality of conductive strips 114a are provided. The conductive strips 114a are embedded in the substrate 112a, and one end 115 of each of the conductive strips 114a is exposed on one side 113 of the substrate 112a. Here, the material of the substrate 112a is, for example, glass, silicon, or other dielectric material.

[0073] Next, refer to Figure 1BThe first redistribution structure layer 120 is formed on the side 113 of the substrate 112a. In detail, the first redistribution structure layer 120 includes a plurality of dielectric layers 121, 123, a plurality of redistribution layers 122, 124, a plurality of conductive vias 125, 127, and a plurality of connection pads 126. The redistribution layers 122, 124 and the dielectric layers 121, 123 are alternately stacked on the side 113 of the substrate 112a, and the connection pads 126 are on the dielectric layer 123. The redistribution layer 122 directly contacts and electrically connects one end 115 of each conductive strip 114a, and is electrically connected to the redistribution layer 124 through the conductive via 125. The redistribution layer 124 is electrically connected to the connection pad 126 through the conductive via 127.

[0074] Next, referring to Figure 1C a plurality of conductive connectors 130a and at least one reinforcing rib (a plurality of reinforcing ribs 140a are schematically shown) are formed on the first redistribution structure layer 120, wherein the reinforcing ribs 140a are located between the conductive connectors 130a. Further, the conductive connectors 130a of the present embodiment are, for example, solder balls, wherein the conductive connectors 130a are directly on the connection pads 126 of the first redistribution structure layer 120. The reinforcing ribs 140a are directly on the dielectric layer 123 and do not contact the connection pads 126, wherein the reinforcing ribs 140a are made of, for example, steel, aluminum, copper, silicon, or glass, but are not limited thereto. It should be noted that the present embodiment does not limit the order in which the conductive connectors 130a and the reinforcing ribs 140a are formed, and the order in which the conductive connectors 130a and the reinforcing ribs 140a are formed can be determined according to requirements.

[0075] Next, referring to Figure 1D a packaging gel 150 is formed on the first redistribution structure layer 120 to cover the conductive connectors 130a and the reinforcing ribs 140a. Here, the packaging gel 150 completely covers the conductive connectors 130a and the reinforcing ribs 140a. If necessary, a grinding process can be selectively added to grind the packaging gel 150 that is too thick.

[0076] Finally, referring to Figure 1D and Figure 1EAfter the encapsulation 150 is formed, a thinning process is performed to remove portions of the substrate 112a and portions of the conductive strips 114a to form a connection structure layer 110. The connection structure layer 110 includes a base material 112 and a plurality of pads 114, where the base material 112 is substantially a portion of the substrate 112a and the pads 114 are substantially portions of the conductive strips 114a. A top surface S1 and a bottom surface S2 of each pad 114 are exposed to an upper surface S3 and a lower surface S4 of the base material 112, respectively. In one embodiment, the top surface S1 and the bottom surface S2 of each pad 114 are trimmed to be flush with the upper surface S3 and the lower surface S4 of the base material 112, respectively. In addition, it is noted that the connection structure layer 110 can be optionally subjected to a surface treatment process according to the requirements of subsequent die bonding. For example, if the base material 112 is silicon, a dielectric material layer is added; if the base material 112 is glass, no dielectric material layer is added. In addition, the pads 114 are subjected to different surface treatment processes according to the bonding method (e.g., micro solder joint bonding or hybrid bonding) to be used subsequently. Thus, the fabrication of the package substrate 100a is completed.

[0077] Structurally, referring again to Figure 1E , the package substrate 100a includes a first redistribution line structure layer 120, conductive connections 130a, a connection structure layer 110, a reinforcement 140a, and an encapsulation 150. The first redistribution line structure layer 120 has a first surface F1 and a second surface F2 opposite to each other. The conductive connections 130a are disposed on the first surface F1 of the first redistribution line structure layer 120 and are electrically connected to the first redistribution line structure layer 120. The connection structure layer 110 is disposed on the second surface F2 of the first redistribution line structure layer 120. The connection structure layer 110 includes a base material 112 and pads 114. A top surface S1 and a bottom surface S2 of each pad 114 are exposed to an upper surface S3 and a lower surface S4 of the base material 112, respectively. The pads 114 are electrically connected to the first redistribution line structure layer 120. The reinforcement 140a is disposed on the first surface F1 of the first redistribution line structure layer 120 and is located between at least two of the conductive connections 130a. The encapsulation 150 is disposed on the first surface F1 of the first redistribution line structure layer 120 and covers the conductive connections 130a and the reinforcement 140.

[0078] In short, the packaging substrate 100a of this embodiment suppresses and reduces warpage by providing reinforcing ribs 140a. Furthermore, the packaging substrate 100a of this embodiment integrates a circuit board upslab fabrication process, namely, a first redistribution circuit structure layer 120. The conductive connectors 130a and reinforcing ribs 140a are disposed on the same surface of the first redistribution circuit structure layer 120, and the encapsulant 150 covers the conductive connectors 130a and reinforcing ribs 140a, thereby suppressing and reducing warpage of the packaging substrate 100a, resulting in better flatness and structural reliability for the packaging substrate 100a of this embodiment. In addition, during the fabrication of the packaging substrate 100a of this embodiment, a temporary substrate is not required, and therefore a laser debonding process is not necessary, effectively reducing manufacturing costs.

[0079] Figures 1F-1J The diagram illustrates the chip configuration. Figure 1E A cross-sectional schematic diagram of a method for fabricating a chip package structure on a packaging substrate.

[0080] Next, please refer to Figure 1F At least one chip (two chips 200 are schematically shown) is configured on the package substrate 100a, wherein the chip 200 is electrically connected to the pads 114 of the connection structure layer 110 via micro-bump bonding or hybrid bond bonding. Here, as Figure 1F Chip 200 is electrically connected to pad 114 via micro solder contacts 210, and then an underfill 220 is filled between the package substrate 100a and chip 200 to cover the micro solder contacts 210. In one embodiment, the contact pitch of chip 200 is 10 micrometers to 80 micrometers.

[0081] Next, please refer to Figure 1G A sealing material 230 is formed on the connection structure layer 110 of the packaging carrier 100a and covers the surrounding surface 201 of the chip 200 to increase structural strength and reliability. Optionally, the sealing material 230 can be polished so that the back side 203 of the chip 200 is exposed to the surface 231 of the sealing material 230, which can have a better heat dissipation effect.

[0082] Afterwards, please refer to the following: Figure 1G and Figure 1HA dry etching process is performed to remove a portion of the encapsulant 150, thereby exposing at least the first bottom surface 132a of each conductive connector 130a. Here, the encapsulant 150 also simultaneously exposes the second bottom surface 142a of each reinforcing rib 140a. The reinforcing rib 140a has a length H, while the encapsulant 150 has a thickness T, and the length H is equal to the thickness T. In another embodiment not shown, the length of the reinforcing rib may also be less than the thickness of the encapsulant, meaning the reinforcing rib may not be exposed outside the encapsulant.

[0083] Finally, please also refer to Figure 1I and Figure 1J The chip packaging structure 10a is fabricated by performing a monomerization process to cut the sealing material 230 and the packaging substrate 100a along the cutting line L.

[0084] Structurally, please refer to [the relevant documentation / reference]. Figure 1J The chip packaging structure 10a in this embodiment includes the above-described... Figure 1E The packaged structure 10a comprises a packaging substrate 100a and a chip 200, wherein the chip 200 is disposed on the packaging substrate 100a and electrically connected to the pads 114 of the connection structure layer 110. Further, the chip 200 can be electrically connected to the pads 114 of the connection structure layer 110 via micro-bump bonding or hybrid bond bonding. Furthermore, the chip packaged structure 10a of this embodiment also includes a sealing material 230 disposed on the connection structure layer 110 of the packaging substrate 100a, covering the surrounding surface 201 of the chip 200, with the back surface 203 of the chip 200 exposed to the surface 231 of the sealing material 230. Here, the edges of the sealing material 230 expose the edges of the packaging substrate 100a, and the encapsulating colloid 150 exposes the first bottom surface 132a of each conductive connector 130a and the second bottom surface 142a of the reinforcing rib 140a.

[0085] In applications, such as Figure 1J As shown, the chip package structure 10a is electrically connected to the pad 22 on the driver substrate 20 via the conductive connector 130a, and thus electrically connected to the driver substrate 20. Here, the driver substrate 20 may be, for example, a printed circuit board, but is not limited thereto.

[0086] In the manufacturing process of the package substrate 100a of the present embodiment, the package adhesive 150 covers the conductive connectors 130a and the reinforcing ribs 140a, so that the back surface of the package substrate 100a becomes flat. Therefore, when the chip package structure 10a is manufactured subsequently, the package substrate 100a has better flatness, which is beneficial for the chip 200 to be arranged on the front surface of the package substrate 100a, and the electrical connection between the chip 200 and the pads 114 can be achieved by micro bump bonding or hybrid bond bonding, so that better package yield can be obtained.

[0087] It should be noted that the following embodiments use the element numbers and some contents of the previous embodiments, in which the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiments, which will not be repeated hereinafter.

[0088] Figures 2A-2D is a cross-sectional view of a manufacturing method of a package substrate according to another embodiment of the present application. The manufacturing method of the package substrate of the present embodiment is similar to the manufacturing method of the package substrate described above, and the difference between them is that, after the step of Figure 1B , i.e. after the first redistribution line structure layer 120 is formed on the side 113 of the substrate 112a, please refer to Figure 2A , a second redistribution line structure layer 160 is formed on the first redistribution line structure layer 120. In detail, the second redistribution line structure layer 160 includes a plurality of dielectric layers 161, 163, a redistribution line layer 162, a plurality of conductive vias 165, 167 and a plurality of connection pads 164. The redistribution line layer 162 and the dielectric layers 161, 163 are alternately stacked on the first redistribution line structure layer 120, and the connection pads 164 are located on the dielectric layer 163. The redistribution line layer 162 is electrically connected to the first redistribution line structure layer 120 through the conductive vias 165. The connection pads 164 are electrically connected to the redistribution line layer 162 through the conductive vias 167. Here, the line width and the line spacing of the second redistribution line structure layer 160 are greater than those of the first redistribution line structure layer 120.

[0089] Next, please refer to Figure 2B, a plurality of conductive connectors 130b and at least one reinforcing rib (a plurality of reinforcing ribs 140b are schematically shown) are formed on the second redistribution structure layer 160, wherein the reinforcing ribs 140b are located between the conductive connectors 130b. Further, the conductive connectors 130b in the present embodiment are, for example, solder balls, wherein the conductive connectors 130b are directly located on the connection pads 164 of the second redistribution structure layer 160. The reinforcing ribs 140b are directly located on the dielectric layer 163 and do not contact the connection pads 164, wherein the reinforcing ribs 140b are made of, for example, steel, aluminum, copper, silicon or glass, but are not limited thereto. It is noted that the present embodiment does not limit the order of forming the conductive connectors 130b and the reinforcing ribs 140b, and the order of forming the conductive connectors 130b and the reinforcing ribs 140b can be determined according to requirements.

[0090] Then, referring to Figure 2C , the encapsulation 150 is formed on the second redistribution structure layer 160 to cover the conductive connectors 130b and the reinforcing ribs 140b. Here, the encapsulation 150 completely covers the conductive connectors 130b and the reinforcing ribs 140b. If necessary, a grinding process can be selectively added to grind the encapsulation 150 that is too thick.

[0091] Finally, referring to Figure 2C and Figure 2D , after the encapsulation 150 is formed, a thinning process is performed to remove part of the substrate 112a and part of the conductive strips 114a, thereby forming the connection structure layer 110. The connection structure layer 110 includes a base material 112 and a plurality of connection pads 114, wherein the base material 112 is substantially part of the substrate 112a, and the connection pads 114 are substantially part of the conductive strips 114a. The top surface S1 and the bottom surface S2 of each connection pad 114 are respectively exposed to the upper surface S3 and the lower surface S4 of the base material 112. In addition, it is noted that the connection structure layer 110 can be selectively subjected to a surface treatment process according to the requirements of subsequent chip bonding. For example, if the material of the base material 112 is silicon, a dielectric material layer needs to be added; if the material of the base material 112 is glass, no dielectric material layer needs to be added. In addition, according to the bonding method (such as micro solder joint bonding or hybrid bonding) to be used subsequently, the connection pads 114 need to be subjected to different surface treatment processes. Thus, the fabrication of the package substrate 100b is completed.

[0092] Figures 2E-2I A cross-sectional schematic view illustrating a method for fabricating a chip package structure by arranging a chip on the package substrate of Figure 2D .

[0093] Next, referring to Figure 2EAt least one chip (two chips 200 are schematically shown) is disposed on the package substrate 100b, wherein the chip 200 is electrically connected to the contact pad 114 of the connection structure layer 110 by micro bump bonding or hybrid bond bonding. Here, the chip 200 is electrically connected to the contact pad 114 by the micro bump 210, and then the underfill 220 is filled between the package substrate 100b and the chip 200 to cover the micro bump 210. In one embodiment, the pitch of the contact pads of the chip 200 is 10-80 microns. Figure 2E The chip 200 is electrically connected to the contact pad 114 by the micro bump 210, and then the underfill 220 is filled between the package substrate 100b and the chip 200 to cover the micro bump 210. In one embodiment, the pitch of the contact pads of the chip 200 is 10-80 microns.

[0094] Next, referring to Figure 2F , the encapsulation material 230 is formed on the connection structure layer 110 of the package substrate 100b and covers the peripheral surface 201 of the chip 200 to increase the structural strength and reliability. Optionally, the encapsulation material 230 is polished to expose the back surface 203 of the chip 200 to the surface 231 of the encapsulation material 230, which can have a better heat dissipation effect.

[0095] Next, referring to Figure 2F and Figure 2G , a dry etching process is performed to remove part of the encapsulation material 150 to expose at least the first bottom surface 132b of each conductive connection member 130b. Here, the reinforcing rib 140b has a length H' and the encapsulation material 150 has a thickness T, and the length H' is less than the thickness T.

[0096] Finally, referring to Figure 2H and Figure 2I , a singulation process is performed to cut the encapsulation material 230 and the package substrate 100b along the cutting line L to form the chip package structure 10b.

[0097] In application, as shown in Figure 2I , the chip package structure 10b can be electrically connected to the driving substrate 20 by the conductive connection member 130b and the contact pad 22 on the driving substrate 20. Here, the driving substrate 20 can be, for example, a printed circuit board, but is not limited thereto.

[0098] Figures 3A-3C is a cross-sectional schematic view of a manufacturing method of a package substrate according to another embodiment of the present application. The manufacturing method of the package substrate of the present embodiment is similar to the manufacturing method of the package substrate described above, and the difference between the two is that after the step of Figure 1B , i.e., after the first redistribution line structure layer 120 is formed on the side 113 of the substrate 112a, referring to Figure 3AThe second redistribution structure layer 170 is formed on the first redistribution structure layer 120. In detail, the second redistribution structure layer 170 includes a plurality of dielectric layers 171, 173, a redistribution layer 172, and a plurality of conductive vias 175, 177. The redistribution layer 172 and the dielectric layers 171, 173 are alternately stacked on the first redistribution structure layer 120. The redistribution layer 172 is electrically connected to the first redistribution structure layer 120 through the conductive vias 175. Here, the line width and the line space of the second redistribution structure layer 170 are greater than those of the first redistribution structure layer 120.

[0099] Next, referring to Figure 3A a plurality of conductive connectors 130c and at least one reinforcing rib (a plurality of reinforcing ribs 140c are schematically shown) are formed on the second redistribution structure layer 170. The reinforcing ribs 140c are located between the conductive connectors 130c. In this embodiment, the conductive connectors 130c are, for example, copper pillars. The conductive connectors 130c are directly located on the conductive vias 177 of the second redistribution structure layer 170. The reinforcing ribs 140c are directly located on the dielectric layers 173 and do not contact the conductive vias 177. The reinforcing ribs 140c are made of, for example, steel, aluminum, copper, silicon, or glass, but are not limited thereto. It should be noted that the order of forming the conductive connectors 130c and the reinforcing ribs 140c is not limited in this embodiment and can be determined according to requirements.

[0100] Next, referring to Figure 3B a packaging adhesive 150 is formed on the second redistribution structure layer 170 to cover the conductive connectors 130c and the reinforcing ribs 140c. Here, the packaging adhesive 150 completely covers the conductive connectors 130c and the reinforcing ribs 140c. If necessary, a grinding process can be selectively added to grind the packaging adhesive 150 that is too thick.

[0101] Finally, referring to Figure 3B and Figure 3CAfter forming the encapsulating colloid 150, a thinning process is performed to remove a portion of the substrate 112a and a portion of the conductive strip 114a, thereby forming a connection structure layer 110. The connection structure layer 110 includes a substrate 112 and a plurality of pads 114, wherein the substrate 112 is substantially part of the substrate 112a, and the pads 114 are substantially part of the conductive strips 114a. The top surface S1 and bottom surface S2 of each pad 114 are exposed to the upper surface S3 and lower surface S4 of the substrate 112, respectively. Furthermore, it should be noted that the surface treatment process of the connection structure layer 110 can be selectively applied according to the requirements of subsequent chip bonding. For example, if the substrate 112 is made of silicon, a dielectric material layer needs to be added; if the substrate 112 is made of glass, no dielectric material layer is required. In addition, depending on the subsequent bonding method (such as micro-soldering or hybrid bonding), different surface treatment processes are required for the pads 114. At this point, the production of the packaging substrate 100c has been completed.

[0102] Figures 3D-3H The diagram illustrates the chip configuration. Figure 3C A cross-sectional schematic diagram of a method for fabricating a chip package structure on a packaging substrate.

[0103] Next, please refer to Figure 3D At least one chip (two chips 200 are schematically shown) is configured on the package substrate 100c, wherein the chip 200 is electrically connected to the pads 114 of the connection structure layer 110 via micro-bump bonding or hybrid bond bonding. Here, as Figure 3D Chip 200 is electrically connected to pad 114 via micro solder contacts 210, and then an underfill 220 is filled between the package substrate 100c and chip 200 to cover the micro solder contacts 210. In one embodiment, the contact pitch of chip 200 is 10 micrometers to 80 micrometers.

[0104] Next, please refer to Figure 3E A sealing material 230 is formed on the connection structure layer 110 of the packaging carrier 100c and covers the surrounding surface 201 of the chip 200 to increase structural strength and reliability. Optionally, the sealing material 230 can be polished so that the back side 203 of the chip 200 is exposed to the surface 231 of the sealing material 230, which can have a better heat dissipation effect.

[0105] Afterwards, please refer to the following: Figure 3E and Figure 3FA dry etching procedure is performed to remove part of the encapsulation 150 to expose at least the first bottom surface 132c of each conductive connector 130c. Here, the stiffener 140c has a length H" and the encapsulation 150 has a thickness T, and the length H" is less than the thickness T.

[0106] Finally, referring to Figure 3G and Figure 3H , a singulation procedure is performed to singulate the encapsulation material 230 and the encapsulation carrier 100c along the singulation line L to form a chip package structure 10c.

[0107] In application, as shown in Figure 3H , the chip package structure 10c can be electrically connected to the drive substrate 20 through the conductive connectors 130c and the solder balls 30, and the solder balls 30 and the pads 22 on the drive substrate 20. Here, the drive substrate 20 can be, for example, a printed circuit board, but is not limited thereto.

[0108] Figure 4A is a cross-sectional view of a chip package structure according to an embodiment of the present application. Referring to Figure 1J and Figure 4A , the chip package structure 10d of the present embodiment is similar to the chip package structure 10a of Figure 1J , except that in the present embodiment, the chip package structure 10d includes a chip 200 and a chip 250, wherein the chip 200 has a different property from the chip 250, and the chip 200 has a different size from the chip 250. That is, the chip package structure 10d of the present embodiment heterogeneously integrates different chips 200, 250. In addition, the chip package structure 10d of the present embodiment further includes a stiffener 240, which is disposed between the chip 200 and the chip 250, and is directly on the base material 112 of the connection structure layer 110 without contacting the pads 114, thereby increasing the structural strength of the overall chip package structure 10d.

[0109] Figure 4B is a cross-sectional view of a chip package structure according to an embodiment of the present application. Referring to Figure 1J and Figure 4B , the chip package structure 10e of the present embodiment is similar to the chip package structure 10a of Figure 1JThe chip package structure 10a is similar to the chip package structure 10, and the difference between them is that in the present embodiment, the package substrate 100e further comprises a build-up structure layer 180 disposed on the first surface F1 of the first redistribution line structure layer 120 and between the conductive connectors 130e and the first redistribution line structure layer 120. In detail, the build-up structure layer 180 comprises a glass substrate 182, a first patterned conductive layer 184, a second patterned conductive layer 186, at least one first via (two first vias 183 are shown), at least one second via (two second vias 185 are shown), and at least one third via (three third vias 187 are shown). The first patterned conductive layer 184 and the second patterned conductive layer 186 are respectively disposed on opposite sides of the glass substrate 182. The third vias 187 penetrate the glass substrate 182 and electrically connect the first patterned conductive layer 184 and the second vias 185. The first patterned conductive layer 184 is electrically connected to the first redistribution line structure layer 120 through the first vias 183. The second patterned conductive layer 186 is electrically connected to the third vias 187 through the second vias 185. The conductive connectors 130e are connected to the second patterned conductive layer 186 and are electrically connected to the first redistribution line structure layer 120 through the build-up structure layer 180.

[0110] Figures 5A-5D are bottom views of various package substrates according to embodiments of the present application. Please refer to Figure 5A , Figure 5C and Figure 5D In the package substrates 100f, 100h, 100i, the stiffeners 140f, 140h, 140i are continuous structure layers, and through their material properties (i.e. rigidity), the structural strength of the overall package substrates 100f, 100h, 100i is increased, and the warpage of the package substrates 100f, 100h, 100i is inhibited and reduced. In detail, Figure 5A In the package substrate 100f, the stiffeners 140f are arranged in a grid shape to form a continuous structure layer, and the conductive connectors 130 (e.g. solder balls) are located within the grid shape; Figure 5C In the package substrate 100h, the stiffeners 140h are a single continuous structure layer, and surround the periphery of the conductive connectors 130; Figure 5D In the package substrate 100i, the stiffeners 140i comprise first stiffeners 144i and second stiffeners 146i, wherein the first stiffeners 144i are a single continuous structure layer, and surround the periphery where the conductive connectors 130 are distributed, and the second stiffeners 146i are dispersedly arranged and distributed between the conductive connectors 130. In addition, please refer to Figure 5BIn the package substrate 100g, since the package substrate 100g itself has a certain structural strength, the rigidity can be increased by the plurality of reinforcing ribs 140g arranged dispersedly from each other, thereby improving the structural strength of the package substrate 100g and further inhibiting and reducing the warpage of the package substrate 100g.

[0111] In summary, in the design of the package substrate of the present application, the conductive connecting members and the reinforcing ribs are arranged on the same surface of the first redistribution line structure layer, and the package adhesive covers the conductive connecting members and the reinforcing ribs, thereby inhibiting and reducing the warpage of the package substrate, and further making the package substrate of the present application have better flatness and structural reliability. Furthermore, in the manufacturing process of the package substrate of the present application, no temporary substrate is needed, and thus no laser debond manufacturing process is needed, thereby effectively reducing the manufacturing cost. In addition, in the manufacturing process of the package substrate of the present application, the package adhesive covers the conductive connecting members and the reinforcing ribs, and thus the back surface of the package substrate becomes flat, which is beneficial for the subsequent assembly of the chip on the front surface of the package substrate. In addition, since the package substrate of the present application has better flatness, the chip package structure using the package substrate of the present application can have better package yield.

[0112] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A package substrate, characterized by, Comprising: a first redistribution layer structure layer having a first surface and a second surface opposite to each other; a plurality of conductive connectors disposed on the first surface of the first redistribution layer structure layer and electrically connected with the first redistribution layer structure layer; a connection structure layer disposed on the second surface of the first redistribution layer structure layer, the connection structure layer comprising a substrate and a plurality of contact pads, each of the plurality of contact pads having a top surface and a bottom surface flush with an upper surface and a lower surface of the substrate respectively, and the plurality of contact pads being electrically connected with the first redistribution layer structure layer, the substrate of the connection structure layer comprising glass or silicon; at least one reinforcing rib disposed on the first surface of the first redistribution layer structure layer and located between at least two of the plurality of conductive connectors; and an encapsulation adhesive disposed on the first surface of the first redistribution layer structure layer and covering the plurality of conductive connectors and the at least one reinforcing rib, wherein the temporary substrate is not required in the manufacturing process of the packaging substrate. Each of the plurality of conductive connectors comprises a solder ball or a copper pillar.

2. The package board according to claim 1, wherein Further comprising:

3. The package board according to claim 1, wherein a second redistribution layer structure layer disposed on the first surface of the first redistribution layer structure layer and located between the plurality of conductive connectors and the first redistribution layer structure layer, wherein the plurality of conductive connectors are electrically connected with the first redistribution layer structure layer through the second redistribution layer structure layer. The line width and line spacing of the second redistribution layer structure layer are greater than the line width and line spacing of the first redistribution layer structure layer.

4. The package board according to claim 3, wherein Further comprising:

5. The package board according to claim 1, wherein a build-up structure layer disposed on the first surface of the first redistribution layer structure layer and located between the plurality of conductive connectors and the first redistribution layer structure layer, the build-up structure layer comprising a fiberglass substrate, a first patterned conductive layer, a second patterned conductive layer, at least one first via, at least one second via, and at least one third via, the first patterned conductive layer and the second patterned conductive layer being located on opposite sides of the fiberglass substrate respectively, the at least one third via penetrating through the fiberglass substrate and electrically connecting the first patterned conductive layer and the at least one second via, the first patterned conductive layer being electrically connected with the first redistribution layer structure layer through the at least one first via, the second patterned conductive layer being electrically connected with the at least one first via through the at least one second via, and the plurality of conductive connectors being connected with the second patterned conductive layer and electrically connected with the first redistribution layer structure layer through the build-up structure layer. The at least one reinforcing rib has a length, and the encapsulation adhesive has a thickness, the length being less than or equal to the thickness.

6. The package board according to claim 1, wherein The at least one reinforcing rib comprises steel, aluminum, copper, silicon, or glass.

7. The package board according to Claim 1, wherein The at least one reinforcing rib comprises a plurality of reinforcing ribs, and the plurality of reinforcing ribs are dispersedly arranged or arranged in a grid shape.

8. The package board according to Claim 1, wherein The at least one reinforcing rib is a continuous structure layer.

9. The package board according to Claim 1, wherein Comprising:

10. A method for manufacturing a package substrate, the method comprising: ​ A substrate and a plurality of conductive strips embedded in the substrate, and one end of each of the plurality of conductive strips is exposed to one side of the substrate are provided. A first redistribution line structure layer is formed on the side of the substrate. A plurality of conductive connectors and at least one reinforcing rib are formed on the first redistribution line structure layer, wherein the at least one reinforcing rib is located between the plurality of conductive connectors. An encapsulation adhesive is formed on the first redistribution line structure layer to cover the plurality of conductive connectors and the at least one reinforcing rib. And Part of the substrate and part of the plurality of conductive strips are removed to form a connection structure layer including a substrate and a plurality of pads, and the top surface and the bottom surface of each of the plurality of pads are respectively exposed to the upper surface and the lower surface of the substrate, and the material of the substrate of the connection structure layer includes glass or silicon. In the process of manufacturing the packaging substrate, a temporary substrate is not required.

11. The method of claim 10, wherein Further comprising: Before forming the plurality of conductive connectors and the at least one reinforcing rib on the first redistribution line structure layer, a second redistribution line structure layer is formed on the first redistribution line structure layer, wherein the line width and the line spacing of the second redistribution line structure layer are greater than the line width and the line spacing of the first redistribution line structure layer.

12. The method of claim 10, wherein Each of the plurality of conductive connectors includes a solder ball or a copper pillar.

13. The method of claim 10, wherein The material of the at least one reinforcing rib includes steel, aluminum, copper, silicon, or glass.

14. The method of claim 10, wherein The at least one reinforcing rib has a length, and the encapsulation adhesive has a thickness, and the length is less than or equal to the thickness.

15. A chip package structure, comprising: Comprising: A packaging substrate comprising: A first redistribution line structure layer having a first surface and a second surface opposite to each other; A plurality of conductive connectors disposed on the first surface of the first redistribution line structure layer and electrically connected to the first redistribution line structure layer; A connection structure layer disposed on the second surface of the first redistribution line structure layer and including a substrate and a plurality of pads, the top surface and the bottom surface of each of the plurality of pads are respectively flush with the upper surface and the lower surface of the substrate, and the plurality of pads and the first redistribution line structure layer are electrically connected; At least one reinforcing rib disposed on the first surface of the first redistribution line structure layer and located between the plurality of conductive connectors; and An encapsulation adhesive disposed on the first surface of the first redistribution line structure layer and covering the plurality of conductive connectors and the at least one reinforcing rib; and At least one chip disposed on the packaging substrate and directly electrically connected to the plurality of pads of the connection structure layer, In the process of manufacturing the packaging substrate, a temporary substrate is not required.

16. The chip package structure of claim 15, wherein, Further comprising: A sealing material disposed on the connection structure layer of the packaging substrate and covering the peripheral surface of at least one chip, wherein the back surface of the at least one chip is exposed to the surface of the sealing material.

17. The chip package structure of claim 15, wherein, The at least one chip is electrically connected to the plurality of pads by micro solder joint bonding or hybrid bonding.

18. The chip package structure of claim 15, wherein, The encapsulation adhesive exposes at least a first bottom surface of each of the plurality of conductive connectors.

19. The chip package structure of claim 18, wherein, The encapsulation gel also exposes a second bottom surface of the reinforcing rib.

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