A stepped LDMOS device and its fabrication method

Abstract

This application belongs to the field of semiconductor technology and provides a stepped LDMOS device and its fabrication method. The stepped LDMOS device includes: a semiconductor substrate, a buried oxide region, a drift region, a drain region, a P-type well region, a source region, a P-type base region, a passivation layer, a gate region, a gate extension region, a source electrode, a drain electrode, and a gate electrode. By setting the buried oxide region to be stepped, an electric field peak is generated corresponding to each step structure, thereby forming multiple holes at the corners of the step structure. According to the dielectric field enhancement principle and electric field modulation effect, the electric field of the buried oxide region is increased, thereby effectively increasing the breakdown voltage of the LDMOS device. By setting the gate extension region, a low-resistance electron channel can be formed above the drift region, thereby reducing the on-resistance of the LDMOS device, achieving the purpose of reducing the on-resistance of the device while increasing the breakdown voltage.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a stepped LDMOS device and its fabrication method. Background Technology

[0002] With the increasing integration of integrated circuits, laterally diffused metal-oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially widely used in high-voltage power amplifier applications, such as LED drivers, switching converters, audio amplifiers, and power management products.

[0003] For high-performance power devices, in addition to high breakdown voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between breakdown voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between breakdown voltage and on-resistance, minimizing on-resistance while maintaining a certain breakdown voltage to obtain the maximum possible output power. Some literature has studied the on-resistance of conventionally doped LDMOS and yielded many results, but it has not fundamentally resolved the contradiction between on-resistance and breakdown voltage. The demand for high-performance devices has made the research focus of LDMOS to simultaneously achieve high breakdown voltage and low on-resistance. The breakdown voltage in the off-state and the on-state on-resistance of LDMOS are both inversely proportional to the drift region concentration. Early LDMOS devices had low breakdown voltages due to excessively high drift region concentration. Subsequent RESURF LDMOS devices improved the breakdown voltage by reducing the drift region concentration, but this significantly increased the on-resistance.

[0004] This shows that traditional LDMOS devices have difficulty achieving a balance between increasing breakdown voltage and reducing on-resistance. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a stepped LDMOS device and its fabrication method, which can solve the problem that existing LDMOS devices cannot achieve a balance between increasing breakdown voltage and reducing on-resistance.

[0006] A first aspect of this application provides a stepped LDMOS device, the stepped LDMOS device comprising:

[0007] Semiconductor substrate;

[0008] A buried oxide region is disposed on the semiconductor substrate; wherein the buried oxide region is stepped.

[0009] A drift zone is located on the stepped structure of the buried oxygen zone;

[0010] The drain region is located on the drift region;

[0011] A P-type trap region is disposed on the buried oxygen region and in contact with the drift region; wherein the P-type trap region is L-shaped.

[0012] The source region is located on the horizontal portion of the P-type well region;

[0013] A P-type base region is disposed on the buried oxide region and is in contact with the P-type well region and the source region, respectively.

[0014] A passivation layer is disposed on the source region, the P-type well region, and the drift region; wherein the passivation layer is L-shaped.

[0015] The gate region is disposed on the horizontal portion of the passivation layer and is in contact with the vertical portion of the passivation layer;

[0016] A gate extension region is disposed on the horizontal portion of the passivation layer and is in contact with the gate region;

[0017] The source electrode is in contact with the source region;

[0018] The drain electrode is in contact with the drain region;

[0019] The gate electrode is in contact with the gate region.

[0020] In one embodiment, the gate extension region includes:

[0021] A first P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the gate region;

[0022] The second P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the first P-type doped region;

[0023] The first N-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the second P-type doped region;

[0024] The third P-type doped region is located on the horizontal portion of the passivation layer and is in contact with the first N-type doped region.

[0025] In one embodiment, the buried oxide region includes multiple stepped structures; wherein the height difference of the stepped structures is proportional to the distance between the source regions.

[0026] In one embodiment, the buried oxide region includes a plurality of stepped structures; wherein the width of each stepped structure is inversely proportional to the distance between the source regions.

[0027] In one embodiment, the thickness of the drift region is greater than the thickness of the buried oxygen region.

[0028] In one embodiment, the width of the drain region is smaller than the width of the step in the stepped structure that contacts the semiconductor substrate.

[0029] In one embodiment, the thickness of the P-type base region is the sum of the thicknesses of the source region and the horizontal portion of the P-type well region.

[0030] In one embodiment, the width of the first P-type doped region is smaller than the width of the second P-type doped region.

[0031] In one embodiment, the stepped LDMOS device further includes:

[0032] Multiple isolation regions are located within the second P-type doped region.

[0033] The second aspect of this application provides a method for fabricating a stepped LDMOS device, comprising:

[0034] A buried oxide region is formed on a semiconductor substrate; wherein the buried oxide region has a groove structure and the groove sidewalls of the buried oxide region are stepped;

[0035] A drift zone is formed within the groove of the buried oxygen zone;

[0036] A P-type well region and a P-type base region are formed on the buried oxygen region, and the P-type well region is in contact with the drift region; wherein the P-type well region is L-shaped.

[0037] A source region is formed on the horizontal portion of the P-type well region; wherein the source region is in contact with the P-type base region;

[0038] A drain region is formed in the drift region;

[0039] A passivation layer is formed on the source region, the P-type well region, the drain region, and the drift region; wherein the passivation layer is L-shaped.

[0040] A gate region and a gate extension region are sequentially formed on the horizontal portion of the passivation layer; wherein the gate region is located between the vertical portion of the passivation layer and the gate extension region;

[0041] A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region.

[0042] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting the buried oxide region in a stepped shape, each stepped structure generates an electric field peak, thereby forming multiple holes at the corners of the stepped structure. Based on the dielectric field enhancement principle and electric field modulation effect, the electric field of the buried oxide region is increased, thereby effectively increasing the breakdown voltage of the LDMOS device. By setting the gate extension region, a low-resistance electron channel can be formed above the drift region, thereby reducing the on-resistance of the LDMOS device. This achieves the goal of reducing the on-resistance of the device while increasing the breakdown voltage. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the stepped LDMOS device provided in the embodiments of this application. Figure 1 ;

[0044] Figure 2 This is a schematic diagram of the structure of the stepped LDMOS device provided in the embodiments of this application. Figure 2 ;

[0045] Figure 3 This is a schematic diagram of the structure of the stepped LDMOS device provided in the embodiments of this application. Figure 3 ;

[0046] Figure 4 This is a schematic diagram of the structure of the stepped LDMOS device provided in the embodiments of this application. Figure 4 ;

[0047] Figure 5 This is a schematic diagram of the fabrication steps of a stepped LDMOS device according to an embodiment of this application;

[0048] Figure 6 This is a schematic diagram illustrating the specific steps involved in forming the buried oxide zone and the drift zone according to an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of the formation of the buried oxide zone and the drift zone according to an embodiment of this application;

[0050] Figure 8 This is a schematic diagram of the formation of a P-type well region, a P-type base region, a source region, and a drain region according to an embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the passivation layer region after formation according to an embodiment of this application;

[0052] Figure 10 This is a schematic diagram of the formation of the gate region and the gate extension region provided in one embodiment of this application;

[0053] Figure 11This is a schematic diagram of the structure after forming the source electrode, drain electrode, and gate electrode according to an embodiment of this application;

[0054] Figure 12 This is a schematic diagram of a shearing process for forming an LDMOS device according to an embodiment of this application. Detailed Implementation

[0055] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0056] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0057] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0059] With the increasing integration of integrated circuits, laterally diffused metal-oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially widely used in high-voltage power amplifier applications, such as LED drivers, switching converters, audio amplifiers, and power management products.

[0060] In practical applications, since MOSFETs are unipolar devices, increasing their breakdown voltage is accompanied by increasing the length of the drift region and decreasing its concentration. Furthermore, for traditional high-voltage power MOSFETs, their on-resistance is primarily determined by the resistance of their drift region. For conventional SOILDMOS, the thickness and size of the drift region must satisfy the RESURF principle to achieve complete depletion in the blocking state, thus reaching the device's maximum breakdown voltage. If the drift region is thick, the doping concentration is relatively low, resulting in a higher specific on-resistance and a weaker RESURF effect, leading to insignificant electric field modulation of the drift region and thus limited improvement in the device's breakdown voltage.

[0061] This shows that traditional LDMOS devices have difficulty achieving a balance between increasing breakdown voltage and reducing on-resistance.

[0062] To address the aforementioned technical problems, this application provides a stepped LDMOS device, as shown in the reference. Figure 1 As shown, the stepped LDMOS device includes: a semiconductor substrate 10, a buried oxide region 20, a drift region 30, a drain region 40, a P-type well region 50, a source region 60, a P-type base region 70, a passivation layer 80, a gate region 100, a gate extension region 90, a source electrode S, a drain electrode D, and a gate electrode G.

[0063] Specifically, a buried oxide region 20 is disposed on a semiconductor substrate 10; wherein the buried oxide region 20 is stepped; a drift region 30 is disposed on the stepped structure of the buried oxide region 20; a drain region 40 is disposed on the drift region 30; a P-type well region 50 is disposed on the buried oxide region 20, and the P-type well region 50 is in contact with the drift region 30; wherein the P-type well region 50 is L-shaped; a source region 60 is disposed on the horizontal portion of the P-type well region 50; a P-type base region 70 is disposed on the buried oxide region 20, and the P-type base region 70 is in contact with both the P-type well region 50 and the source region 60; a passivation layer... Passivation layer 80 is disposed on source region 60, P-type well region 50, drain region 40 and drift region 30; wherein, passivation layer 80 is L-shaped; gate region 100 is disposed on the horizontal portion of passivation layer 80 and is in contact with the vertical portion of passivation layer 80; gate extension region 90 is disposed on the horizontal portion of passivation layer 80 and is in contact with gate region 100; source electrode S is in contact with source region 60 and P-type base region 70 respectively; drain electrode D is in contact with drain region 40; gate electrode G is in contact with gate region 100.

[0064] In this embodiment, both the P-type well region 50 and the P-type base region 70 are disposed on the buried oxide region 20. The sum of the width of the P-type base region 70 and the maximum width of the P-type well region 50 is less than the width of the stepped structure near the source region 60 in the stepped structure of the buried oxide region 20 (i.e., less than the width of the horizontal portion of the uppermost stepped structure of the buried oxide region 20). The P-type well region 50 is L-shaped, including a horizontal portion and a vertical portion. The source region 60 is disposed on the horizontal portion of the P-type well region 50. The upper surface of the source region 60 is flush with the upper surface of the P-type well region 50, and the width of the source region 60 is equal to the width of the P-type well region 50. At this time, the source region 60 and the P-type well region 50 form a cuboid. In this embodiment, the drift region 30 is disposed between the P-type well region 50 and the drain region 40. The drain region 40, drift region 30, P-type well region 50, source region 60 and P-type base region 70 are at the same horizontal height. The passivation layer 80 is disposed on the source region 60, P-type well region 50 and drift region 30.

[0065] In this embodiment, the passivation layer 80 is L-shaped, which includes a horizontal portion and a vertical portion. The gate region 100 and the gate extension region 90 are both disposed on the horizontal portion of the passivation layer 80, and the gate region 100 is in contact with the vertical portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100. For example, the upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the passivation layer 80, and the widths of the gate region 100 and the gate extension region 90 are equal to the width of the horizontal portion of the passivation layer. In this case, the gate region 100, the gate extension region 90, and the passivation layer 80 together form a cuboid. In this embodiment, the gate electrode G is disposed on the gate region 100 and the gate extension region 90, and the gate electrode G is in contact with the gate region 100 and the gate extension region 90, respectively.

[0066] In this embodiment, the drift region 30 is disposed on the stepped structure of the buried oxide region 20. The drift region 30 can be divided into two parts: the first part is "L"-shaped and the second part is an inverted stepped structure. The drain region 40 is disposed on the horizontal part of the first part of the drift region 30. The inverted stepped structure of the second part of the drift region 30 is in contact with the stepped structure of the buried oxide region 20. This allows holes to accumulate at the corners of the stepped buried oxide region 20 (i.e., at the connection between the horizontal and vertical parts of each stepped structure) under the action of the horizontal and vertical electric fields when the LDMOS device is working. This increases the electric field of the buried oxide region 20. According to the dielectric field enhancement principle and electric field modulation effect, the breakdown voltage of the LDMOS device can be effectively increased.

[0067] In this embodiment, the buried oxide region 20 is stepped, comprising multiple stepped structures, each including a horizontal portion and a vertical portion. The horizontal and vertical portions of each stepped structure are connected sequentially, and the bottom of the buried oxide region 20 contacts the semiconductor substrate 10. In this embodiment, by setting the buried oxide region 20 to a stepped shape, when the LDMOS device is operating, under the influence of the horizontal and vertical electric fields, holes accumulate at the corners of the stepped buried oxide region 20 (i.e., at the connection points of the horizontal and vertical portions of each stepped structure), thereby increasing the electric field of the buried oxide region 20. Based on the dielectric field enhancement principle and electric field modulation effect, this effectively increases the breakdown voltage of the LDMOS device.

[0068] In this embodiment, the gate extension region 90 is disposed on the horizontal portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100. By providing the gate extension region 90, a low-resistance, high-concentration electron channel from the drain region 40 to the source region 60 can be formed above the drift region 30, thereby reducing the on-resistance of the LDMOS device.

[0069] In this embodiment, the breakdown voltage of the device can be increased by setting the buried oxide region 20 in a stepped shape, and the on-resistance of the device can be reduced by setting the gate extension region 90. In this way, the on-resistance of the device can be reduced while increasing the breakdown voltage, thus solving the problem that it is difficult to achieve a balance between increasing the breakdown voltage and reducing the on-resistance of LDMOS devices.

[0070] In one embodiment, for the material of the buried oxide region 20, silicon oxide is a commonly used material with mature technology. Alternatively, a low-K dielectric with a dielectric constant lower than that of silicon oxide can be used to improve the longitudinal withstand voltage and reduce the thickness of the buried oxide region 20.

[0071] In one embodiment, reference Figure 2 As shown, the gate extension region 90 includes: a first P-type doped region 91, a second P-type doped region 92, a first N-type doped region 93, and a third P-type doped region 94.

[0072] Specifically, a first P-type doped region 91 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the gate region 100; a second P-type doped region 92 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the first P-type doped region 91; a first N-type doped region 93 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the second P-type doped region 92; and a third P-type doped region 94 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the first N-type doped region 93.

[0073] In this embodiment, the first P-type doped region 91 and the second P-type doped region 92 are doped with P-type doping ions. Among them, the doping concentration of the first P-type doped region 91 is greater than that of the second P-type doped region 92. The first N-type doped region 93 can be doped with N-type doping ions. For example, the N-type doping ions can be nitrogen ions or phosphorus ions. The third P-type doped region 94 can be doped with P-type doping ions. For example, the P-type doping ions can be aluminum ions. By doping different elements, a PN junction is formed between the first N-type doped region 93 and the third P-type doped region 94, which can enhance the electric field above the passivation layer 80, thereby forming a low-resistance electron channel above the drift region 30 and reducing the on-resistance.

[0074] In one embodiment, the doping ions of the second P-type doped region 92 are the same as those of the first P-type doped region 91, but the doping concentrations are different, and they are different from the doping ions of the first N-type doped region 93, which can avoid the adverse effect on the longitudinal electric field intensity of the drift region 30 after the second P-type doped region 92 is depleted in the device off-state breakdown voltage state. Therefore, the breakdown voltage capability of the device can be improved. However, due to the different doping types of the first N-type doped region 93, the process requirements are more complex.

[0075] In one embodiment, refer to Figure 2 As shown, the buried oxide region 20 includes a plurality of stepped structures; among them, the step height difference of the stepped structures is proportional to the distance from the source region 60.

[0076] Specifically, among the plurality of stepped structures, the height difference of the stepped structure closer to the source region 60 is smaller, and the height difference of the stepped structure farther from the source region 60 is larger. For example, h1 < h2 < h3, and the magnitude of the height difference is the thickness of the vertical part in the stepped structure. For example, h1 is the thickness of the first step, h2 is the thickness of the second step, and h3 is the thickness of the third step. The plurality of stepped structures include a plurality of vertical parts. The thickness of the vertical part closer to the source region 60 (farther from the semiconductor substrate 10) is smaller, and the thickness of the vertical part farther from the source region 60 (closer to the semiconductor substrate 10) is larger. Because when the LDMOS device is working, the electric field intensity gradually decreases from the drain region 40 to the source region 60, that is, the electric field intensity of the drain region 40 is larger. By setting the thickness of the vertical part farther from the source region 60 (closer to the drain region 40) to be larger (that is, the step height difference is larger), a larger height difference can accumulate more holes, and multiple electric field spikes can be introduced. Then its ability to modulate the electric field near the drain region 40 is stronger, and the surface electric field of the LDMOS device can be better modulated, improving the lateral breakdown voltage of the device.

[0077] In one embodiment, refer to Figure 3 As shown, the buried oxide region 222 includes a plurality of stepped structures; among them, the width of each stepped structure is inversely proportional to the distance from the source region 60.

[0078] Specifically, among the multiple stepped structures, the width of the stepped structure closer to the source region 60 is larger, and the width of the stepped structure farther from the source region 60 is also larger. For example, w1>w2>w3. For example, w1 is the width of the second step, w2 is the width of the third step, and w3 is the width of the fourth step. The width of the stepped structure is the width of the horizontal part in the stepped structure. The multiple stepped structures include multiple horizontal parts. The width of the horizontal part closer to the source region 60 (farther from the semiconductor substrate 10) is larger, and the width of the horizontal part farther from the source region 60 (closer to the semiconductor substrate 10) is smaller. Because when the LDMOS device is working, the electric field intensity gradually decreases from the drain region 40 to the source region 60, that is, the electric field intensity in the drain region 40 is larger. The width of the horizontal part farther from the source region 60 (closer to the drain region 40) is smaller. Then, more stepped structures can be arranged in the part of the buried oxide region 20 close to the drain region 40. Because holes can be accumulated at the corner of the vertical part and the horizontal part of each structure, more stepped structures can accumulate more holes, and more electric field spikes can be introduced. Then, its ability to modulate the electric field near the drain region 40 is stronger, and the surface electric field of the LDMOS device can be better modulated, improving the lateral breakdown voltage of the device.

[0079] In one embodiment, the thickness of the drift region 30 is greater than the thickness of the buried oxide region 20. Here, the drift region 30 is made of silicon layer material. By setting the thickness of the drift region 30 to be greater than the thickness of the buried oxide region 20, it is more beneficial for the stepped structure of the buried oxide region 20 to accumulate holes, and the electric field near the drain region 40 can be better modulated, thereby improving the lateral breakdown voltage of the device.

[0080] In one embodiment, referring to Figure 3 As shown, the width of the drain region 40 is smaller than the width of the step in the stepped structure that contacts the semiconductor substrate 10.

[0081] In this embodiment, the width of the drain region 40 is smaller than the width of the horizontal part in the stepped structure of the buried oxide region 20 close to the semiconductor substrate 10. For example, w4<w3, where w4 is the width of the drain region 40. Thus, holes can better modulate the electric field near the drain region 40, and the surface electric field of the LDMOS device can be better modulated, improving the lateral breakdown voltage of the device.

[0082] In one embodiment, the thickness of the P-type base region 70 is the sum of the thicknesses of the source region 60 and the horizontal part of the P-type well region 50.

[0083] Specifically, the thickness of the P-type base region 70 is greater than the thickness of the source region 60 because the P-type base region 70 is the voltage access point of the LDMOS device. By setting the thickness of the P-type base region 70 to be the sum of the thicknesses of the source region 60 and the horizontal portion of the P-type well region 50, the voltage can be better accessed, maintaining the stability of the LDMOS device and improving its performance.

[0084] In one embodiment, the width of the first P-type doped region 91 is smaller than the width of the second P-type doped region 92.

[0085] In this embodiment, the doping concentration of the second P-type doped region 92 is less than that of the first P-type doped region 91. By setting the width of the first P-type doped region 91 to be less than the width of the second P-type doped region 92, more low-resistance electron channels can be formed above the drift region 30, reducing the on-resistance and thus lowering the on-resistance of the device.

[0086] In one embodiment, reference Figure 4 As shown, the stepped LDMOS device also includes multiple isolation regions 110.

[0087] Specifically, multiple isolation regions 110 are disposed within the second P-type doped region 92. The depth of the multiple isolation regions 110 gradually increases from the source region 60 to the drain region 40. Specifically, the depth of the isolation region 110 near the source region 60 is less than the depth of the isolation region 110 near the drain region 40. The multiple isolation regions 110 are formed by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, and then filling the trenches with deposited oxide. By setting multiple isolation regions 110 within the second P-type doped region 92, a high electric field can be formed at the multiple isolation regions 110, which can modulate the electric field distribution of the LDMOS device and improve the breakdown voltage of the LDMOS device.

[0088] In one embodiment, the passivation layer 80 is made of a high-k dielectric material. By using a high-k dielectric, the concentration of electron channels formed above the drift region 30 can be increased and the resistance can be reduced. In this way, the on-resistance of the LDMOS device can be reduced more effectively.

[0089] In one embodiment, the semiconductor substrate 10 may be a silicon-based substrate or a silicon carbide substrate.

[0090] In one embodiment, the buried oxide region 20 is silicon oxide.

[0091] In one embodiment, the drift region 30 is Si.

[0092] In one embodiment, the gate electrode G can be at least one of copper, gold, and silver.

[0093] In one embodiment, the drain electrode D can be at least one of copper, gold, and silver.

[0094] In one embodiment, the source electrode S can be at least one of copper, gold, and silver.

[0095] In one embodiment, the source region 60, drain region 40, and gate region 100 can serve as pad materials for the corresponding electrodes, such as gallium nitride, or as metal material layers.

[0096] This application also provides a method for fabricating a stepped LDMOS device, referencing... Figure 5 As shown, the fabrication method of the LDMOS device provided in this embodiment includes steps S10 to S50.

[0097] In step S10, a buried oxide region 20 and a drift region 30 are sequentially formed on the semiconductor substrate 10.

[0098] Specifically, the buried oxygen zone 20 has a groove structure, and the sidewalls of the groove of the buried oxygen zone 20 are stepped, with the drift zone 30 located within the groove of the buried oxygen zone 20.

[0099] In this embodiment, the semiconductor substrate 10 can be an N-type silicon substrate. In specific applications, a buried oxide region 20 can be formed on the semiconductor substrate 10 by depositing silicon dioxide material or by oxidizing the N-type silicon substrate. The thickness of the buried oxide region 20 can be set according to the application requirements of the device.

[0100] In one specific application, a layer of silicon dioxide is deposited on a semiconductor substrate 10 to form a buried oxide region 20. A first-thickness drift region 30 is then formed on the buried oxide region 20 by depositing semiconductor or metal material in a predetermined area using a mask. (See reference) Figure 6 (a)), and then the drift region 30 of the first thickness is sheared at a preset scale, referring to Figure 6 (b); and a buried oxide region 20 is formed by depositing semiconductor or metal materials on both sides of the sheared drift region 30 (see reference). Figure 6 (c)); A second-thickness drift region 30 is formed on the buried oxide region 20 by depositing semiconductor or metal materials in a predetermined area using a mask (see reference). Figure 6 (d)), and then the drift region 30 of the second thickness is sheared at a preset scale (refer to...). Figure 6 (e)) and a buried oxide region 20 is formed by depositing semiconductor or metal materials on both sides of the sheared drift region 30 (see reference). Figure 6 (f)), and so on, until a cycle is formed. Figure 7 The drift zone 30 and the oxygen-buried zone 20 are shown.

[0101] In this embodiment, the recessed sidewalls of the buried oxide region 20 are stepped. For example, the buried oxide region 20 includes multiple stepped structures, each of which includes a horizontal portion and a vertical portion. The horizontal and vertical portions of each stepped structure are connected sequentially, and the bottom of the buried oxide region 20 is in contact with the semiconductor substrate 10. In this embodiment, by setting the recessed sidewalls of the buried oxide region 20 to be stepped, when the LDMOS device is working, under the action of the horizontal and vertical electric fields, holes will accumulate at the corners of the stepped buried oxide region 20 (i.e., at the connection between the horizontal and vertical portions of each stepped structure), thereby increasing the electric field of the buried oxide region 20. According to the dielectric field enhancement principle and the electric field modulation effect, the breakdown voltage of the LDMOS device can be effectively increased.

[0102] In step S20, refer to Figure 8 As shown, a P-type well region 50, a P-type base region 70, a source region 60, and a drain region 40 are sequentially formed on the buried oxide region 20.

[0103] Specifically, the P-type well region 50 is in contact with the drift region 30. The P-type well region 50 is L-shaped, and the P-type base region 70 is in contact with both the P-type well region 50 and the source region 60. The source region 60 is located on the horizontal part of the P-type well region 50 and is in contact with the P-type base region 70. The drain region 40 is located on the drift region 30.

[0104] In a specific application, a P-type well region 50, a P-type base region 70, a source region 60, and a drain region 40 can be formed in a predetermined region on the buried oxide region 20 by depositing semiconductor or metal materials.

[0105] In a specific application, the P-type well region 50 and the P-type base region 70 are disposed on the buried oxide region 20. The sum of the width of the P-type base region 70 and the maximum width of the P-type well region 50 (i.e., the sum of the width of the horizontal portion and the width of the vertical portion of the P-type well region 50) is less than the width of the stepped structure near the source region 60 in the stepped structure of the buried oxide region 20 (i.e., less than the width of the horizontal portion of the uppermost stepped structure of the buried oxide region 20). The P-type well region 50 is L-shaped, and the source region 60 is disposed on the horizontal portion of the P-type well region 50. The upper surface of the source region 60 is flush with the upper surface of the P-type well region 50, and the width of the source region 60 is equal to the width of the P-type well region 50. At this time, the source region 60 and the P-type well region 50 form a cuboid. In this embodiment, the drift region 30 is disposed between the P-type well region 50 and the drain region 40. After filling, the drain region 40, drift region 30, P-type well region 50, source region 60 and P-type base region 70 are at the same horizontal height. The passivation layer 80 is disposed on the source region 60, P-type well region 50 and drift region 30.

[0106] In step S30, refer to Figure 9As shown, a passivation layer 80 is formed on the source region 60, the P-type well region 50, the drain region 40, and the drift region 30; wherein, the passivation layer 80 is L-shaped.

[0107] In step S40, refer to Figure 10 As shown, a gate region 100 and a gate extension region 90 are sequentially formed on the horizontal portion of the passivation layer 80.

[0108] Specifically, the gate region 100 is located between the vertical portion of the passivation layer 80 and the gate extension region 90.

[0109] In this embodiment, the passivation layer 80 is L-shaped. The gate region 100 and the gate extension region 90 are both disposed on the horizontal portion of the passivation layer 80, and the gate region 100 is in contact with the vertical portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100. The upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the vertical portion of the passivation layer 80, and the widths of the gate region 100 and the gate extension region 90 are equal to the width of the horizontal portion of the passivation layer 80. At this time, the gate region 100, the gate extension region 90, and the passivation layer 80 together form a cuboid.

[0110] In one specific application, by setting the gate extension region 90, the electric field above the passivation layer 80 can be enhanced, thereby forming a low-resistance electronic channel above the drift region 30, which in turn reduces the on-resistance of the LDMOS device.

[0111] In step S50, refer to Figure 11 As shown, a source electrode S is formed on the source region 60, a drain electrode D is formed on the drain region 40, and a gate electrode G is formed on the gate region 100.

[0112] In a specific application, a mask is used to determine the shape of the source electrode S, the gate electrode G, and the drain electrode D, and metal is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D.

[0113] In this embodiment, a mask is used to define the shapes of the source electrode S, the gate electrode G, and the drain electrode D, thereby depositing metal material on the mask to form the source electrode S, the gate electrode G, and the drain electrode D, and then removing the mask.

[0114] In one embodiment, reference Figure 12 As shown, the fabricated LDMOS device is cut from the middle to form two LDMOS devices.

[0115] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A stepped LDMOS device, characterized by, The stepped LDMOS device comprises: a semiconductor substrate; a buried oxide region disposed on the semiconductor substrate; wherein the buried oxide region is in a stepped structure; a drift region disposed on the stepped structure of the buried oxide region; a drain region disposed on the drift region; a P-type well region disposed on the buried oxide region and in contact with the drift region; wherein the P-type well region is in an "L" shape; a source region disposed on the horizontal part of the P-type well region; a P-type base region disposed on the buried oxide region and in contact with the P-type well region and the source region respectively; a passivation layer disposed on the source region, the P-type well region and the drift region; wherein the passivation layer is in an "L" shape; a gate region disposed on the horizontal part of the passivation layer and in contact with the vertical part of the passivation layer; a gate extension region disposed on the horizontal part of the passivation layer and in contact with the gate region; the gate extension region comprises: a first P-type doped region disposed on the horizontal part of the passivation layer and in contact with the gate region; a second P-type doped region disposed on the horizontal part of the passivation layer and in contact with the first P-type doped region; a first N-type doped region disposed on the horizontal part of the passivation layer and in contact with the second P-type doped region; a third P-type doped region disposed on the horizontal part of the passivation layer and in contact with the first N-type doped region; a plurality of isolation regions disposed in the second P-type doped region of the gate extension region; a source electrode in contact with the source region; a drain electrode in contact with the drain region; the gate extension region is located between the gate region and the drain electrode; a gate electrode in contact with the gate region.

2. The stepped LDMOS device of claim 1, wherein, The buried oxide region comprises a plurality of stepped structures; wherein the step height difference of the stepped structure is proportional to the distance between the stepped structure and the source region.

3. The stepped LDMOS device of claim 1, wherein, The buried oxide region comprises a plurality of stepped structures; wherein the width of each stepped structure is inversely proportional to the distance between the stepped structure and the source region.

4. The stepped LDMOS device of claim 1, wherein, The thickness of the drift region is greater than the thickness of the buried oxide region.

5. The stepped LDMOS device of claim 1, wherein, The width of the drain region is less than the width of the step of the stepped structure in contact with the semiconductor substrate.

6. The stepped LDMOS device of claim 1, wherein, The thickness of the P-type base region is the sum of the thickness of the source region and the horizontal part of the P-type well region.

7. The stepped LDMOS device of claim 1, wherein, The width of the first P-type doped region is less than the width of the second P-type doped region.

8. A method for fabricating a stepped LDMOS device, characterized in that, The method comprises: forming a buried oxide region on a semiconductor substrate; wherein the buried oxide region is in a groove structure, and the groove sidewall of the buried oxide region is in a stepped structure; forming a drift region in the groove of the buried oxide region; forming a P-type well region and a P-type base region on the buried oxide region, the P-type well region being in contact with the drift region; wherein the P-type well region is in an "L" shape; forming a source region on the horizontal part of the P-type well region; wherein the source region is in contact with the P-type base region; forming a drain region on the drift region; forming a passivation layer on the source region, the P-type well region, the drain region and the drift region; wherein the passivation layer is in an "L" shape; A gate region and a gate extension region are sequentially formed on the horizontal part of the passivation layer; the gate region is arranged between the vertical part of the passivation layer and the gate extension region; the gate extension region comprises: a first P-type doped region arranged on the horizontal part of the passivation layer and in contact with the gate region; a second P-type doped region arranged on the horizontal part of the passivation layer and in contact with the first P-type doped region; a first N-type doped region arranged on the horizontal part of the passivation layer and in contact with the second P-type doped region; and a third P-type doped region arranged on the horizontal part of the passivation layer and in contact with the first N-type doped region; A plurality of isolation regions are formed in the second P-type doped region of the gate extension region; A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region; the gate extension region is located between the gate region and the drain electrode.

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