Composite terminal structure and preparation method

Abstract

The invention relates to a terminal structure and a preparation method thereof, in particular to a composite terminal structure and a preparation method thereof. According to the technical scheme, the composite terminal structure comprises a semiconductor substrate of a first conductive type and a JTE transverse terminal expansion structure arranged in a terminal area of the semiconductor substrate, and the JTE transverse terminal expansion structure comprises a JTE transverse terminal expansion area of a second conductive type; at least one adjustment compensation unit for longitudinal electric field modulation and charge compensation is arranged in the JTE transverse terminal expansion region on the cross section of the terminal structure; when the terminal structure is in a reverse bias state, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE transverse terminal extension region where the adjustment compensation unit is located, so that the voltage resistance of the terminal structure is improved by utilizing the formed three-dimensional charge balance region. The voltage endurance capability of the terminal structure can be effectively improved, and the process adaptability is improved.

Description

Technical Field

[0001] This invention relates to a terminal structure and its preparation method, and more particularly to a composite terminal structure and its preparation method. Background Technology

[0002] Power semiconductors are the "heart" of modern power electronic devices, widely used in key areas such as motor controllers for new energy vehicles, traction converters for rail transit, industrial frequency converters, and smart grids. These applications often require power devices to operate stably for extended periods in harsh environments with high temperature, high humidity, and high vibration. Any unexpected failure caused by environmental stress can lead to system malfunctions, resulting in significant economic losses or even safety accidents.

[0003] To improve the reliability of power devices, their reliability boundaries should generally be verified through accelerated testing such as HV-H3TRB before they are marketed. With the maturity and widespread adoption of third-generation semiconductor technologies, represented by silicon carbide (SiC) and gallium nitride (GaN), power devices are evolving towards higher voltages, higher frequencies, and higher power densities. However, the increase in voltage levels (such as 2000V and 3300V devices) leads to a dramatic increase in electric field strength, posing unprecedented challenges to the device's termination protection and passivation layers. Traditional H3TRB testing (typically with a bias voltage ≤100V) is no longer effective in assessing the reliability of high-voltage devices under real-world operating conditions (withstanding 80% of the rated high voltage). Therefore, it is necessary to upgrade to the more stringent HV-H3TRB testing.

[0004] To increase the reliability of power devices, although the field limiting ring plus field plate termination structure can pass the H3TRB test smoothly, a small number of power devices still fail in the HV-H3TRB test. Moreover, the cause of the test failure is highly related to the withstand voltage of the power device termination structure. Therefore, how to effectively improve the withstand voltage capability of the termination structure is a technical problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a composite terminal structure and preparation method, which can effectively improve the pressure resistance of the terminal structure and improve the process adaptability.

[0006] According to the technical solution provided by the present invention, a composite terminal structure is provided, the terminal structure comprising a semiconductor substrate of a first conductivity type and a JTE lateral terminal extension structure disposed within the terminal region of the semiconductor substrate, wherein... The JTE lateral termination extension structure includes a JTE lateral termination extension region of a second conductivity type; On the cross-section of the terminal structure, at least one adjustment and compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region, so as to improve the voltage withstand capability of the terminal structure by utilizing the formed three-dimensional charge balance region.

[0007] A main junction of a second conductivity type is provided within the semiconductor substrate, and the main junction is adjacent to the JTE lateral termination extension structure. The junction depth of the JTE lateral terminal extension region is less than the junction depth of the main junction; On the cross-section of the terminal structure, when multiple adjustment and compensation units are provided in the JTE lateral terminal extension area, the multiple adjustment and compensation units are arranged sequentially along the direction from the main node to the JTE lateral extension structure, and adjacent adjustment and compensation units are separated by the JTE lateral terminal extension area.

[0008] The adjustment and compensation unit includes an adjustment and compensation trench disposed within the JTE lateral terminal extension region and a second conductivity type bottom doped region covering the bottom of the adjustment and compensation trench, wherein... The second conductivity type bottom doped region is located within the JTE lateral terminal extension region, and the doping concentration of the second conductivity type bottom doped region is greater than the corresponding doping concentration of the JTE lateral terminal extension region. The adjustment and compensation trench is filled with adjustment and compensation medium.

[0009] The cross-section of the terminal structure also includes several field limiting ring units arranged sequentially, wherein, The field limiting ring unit includes a second conductivity type field ring injection region located in the terminal region of the semiconductor substrate and a field limiting ring field plate adapted to be electrically connected to the second conductivity type field ring injection region. On the cross-section of the terminal structure, along the direction from the JTE lateral terminal extension structure to the edge of the semiconductor substrate, the width of the second conductivity type field confinement ring injection region gradually narrows.

[0010] For each field limiting ring unit, the field limiting ring field plate includes a field plate conductive polysilicon that is in contact with the injection region of the second conductivity type field ring and a field plate metal that is in ohmic contact with the injection region of the second conductivity type field ring, and the field plate metal is in ohmic contact with the field plate conductive polysilicon.

[0011] The junction depth of the second conductivity type field-limited ring injection region is no greater than the junction depth of the JTE lateral termination extension structure.

[0012] A method for preparing a composite terminal structure, used to prepare the terminal structure described above, wherein the preparation method includes: A semiconductor substrate of a first conductivity type is provided, and a front-side termination process is performed on the front side of the semiconductor substrate to form a JTE lateral termination extension structure in the termination region of the semiconductor substrate via the front-side termination process. The JTE lateral termination extension structure includes a JTE lateral termination extension region of a second conductivity type; On the cross-section of the terminal structure, at least one adjustment and compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region, so as to improve the voltage withstand capability of the terminal structure by utilizing the formed three-dimensional charge balance region.

[0013] The front-end terminal process includes: Fabricating a main junction of a second conductivity type within a semiconductor substrate. A JTE lateral termination extension region is fabricated within the termination region of a semiconductor substrate, and then at least one adjustment compensation trench is fabricated within the JTE lateral termination extension region. A second conductivity type bottom doping region is formed at the bottom of each adjustment compensation trench to cover the bottom of adjacent adjustment compensation trenches. Fill each adjustment and compensation trench with adjustment and compensation medium.

[0014] The material of the adjustment and compensation medium includes silicon dioxide or a high-k dielectric material, wherein... When the material of the adjustment compensation medium is silicon dioxide, the methods for filling the adjustment compensation medium include: Before fabricating the adjustment compensation trench within the JTE lateral termination extension region, a second conductivity type field ring injection region is first fabricated within the termination region of the semiconductor substrate, wherein... On the cross-section of the terminal structure, along the direction of the JTE lateral terminal extension structure pointing to the edge of the semiconductor substrate, the second conductivity type field ring injection regions are arranged sequentially. After a second conductivity type trench bottom doped region is prepared at the bottom of each adjustment compensation trench, an oxide base layer is formed on the front side of the semiconductor substrate using silicon dioxide. The oxide base layer covers the front side of the semiconductor substrate and fills the adjustment compensation trench, so as to form an adjustment compensation medium using the oxide base layer filled in the adjustment compensation trench.

[0015] After the JTE lateral termination extension structure is prepared by the front-side termination process, a back-side process is performed on the back side of the semiconductor substrate to prepare the back-side electrode structure.

[0016] Advantages of this invention: The adjustment compensation trench is filled with an adjustment compensation medium. By utilizing the difference in dielectric constant brought about by the adjustment compensation medium, the peak electric field that is prone to breakdown is transferred from the fragile semiconductor substrate surface to the more robust adjustment compensation medium. At the same time, the doping region at the bottom of the second conductivity type trench and the lateral termination extension region of the JTE form a doping gradient and form a local vertical PN junction with the epitaxial layer of the first conductivity type. Under high reverse bias, an additional depletion region is generated. Together with the depletion region of the lateral termination extension region of the JTE, a three-dimensional charge balance region is formed.

[0017] When a three-dimensional charge balance region is formed, two direct technical effects can be achieved: first, the electric field strength in the passivation layer is significantly reduced, fundamentally improving the reliability of the passivation layer; second, the process tolerance of doping in the JTE lateral terminal extension region is broadened, because longitudinal charge compensation can buffer the process fluctuations of doping in the JTE lateral terminal extension region to a certain extent.

[0018] Furthermore, when the termination structure includes several field-limiting ring units, the field-limiting ring units, in conjunction with the JTE lateral termination extension region, can provide a region within the termination region with extremely low doping concentration, large depletion width, and insensitivity to process fluctuations. This region serves as a buffer and endpoint for electric field extension, ensuring that even if the depletion of the JTE lateral termination extension region ahead is incomplete or the interface charge fluctuates, the final breakdown point can be stably confined within this wide depletion region. This greatly enhances the robustness of the entire termination structure, achieving a smooth, multi-level, and controllable distribution of the electric field from the active region to the edge of the termination region. The electric field peak is dispersed across multiple vertical and horizontal nodes, improving the withstand voltage and operational reliability of power semiconductor devices. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of an embodiment of the composite terminal structure of the present invention.

[0020] Figures 2-12 This is a cross-sectional view showing the fabrication process steps of an embodiment of the composite terminal structure of the present invention, wherein... Figure 2 This is a cross-sectional view of an embodiment of the semiconductor substrate of the present invention.

[0021] Figure 3 This is a cross-sectional view of one embodiment of the present invention after the main junction is fabricated in a semiconductor substrate.

[0022] Figure 4 This is a cross-sectional view of one embodiment of the present invention after obtaining the JTE lateral terminal extension region and the P-type field ring injection region.

[0023] Figure 5 This is a cross-sectional view of one embodiment of the adjusted compensation trench prepared according to the present invention.

[0024] Figure 6 This is a cross-sectional view of one embodiment of the P-type trench bottom doped region prepared according to the present invention.

[0025] Figure 7 This is a cross-sectional view of an embodiment of the oxidized base layer prepared according to the present invention.

[0026] Figure 8 This is a cross-sectional view of one embodiment of the conductive polycrystalline silicon field plate prepared according to the present invention.

[0027] Figure 9 This is a cross-sectional view of one embodiment of the present invention after the supporting oxide layer has been prepared.

[0028] Figure 10 This is a cross-sectional view of one embodiment of the field plate metal and source metal prepared according to the present invention.

[0029] Figure 11 This is a cross-sectional view of one embodiment of the present invention after the passivation layer has been prepared.

[0030] Figure 12 This is a cross-sectional view of an embodiment of the back electrode structure prepared by the back-side process of the present invention.

[0031] Explanation of reference numerals in the attached figures: 1-Backside metal, 2-P+ collector region, 3-N-type field cutoff layer, 4-N-type epitaxial layer, 5-Main junction, 6-Source metal, 7-Passivation layer, 8-P-type trench bottom doped region, 9-Adjustment compensation dielectric, 10-JTE lateral termination extension region, 11-P-type field ring implantation region, 12-Field plate conductive polysilicon, 13-Support oxide layer, 14-Field plate metal, 15-Semiconductor substrate, 16-Adjustment compensation trench, 17-Oxide base layer. Detailed Implementation

[0032] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0033] To effectively improve the voltage withstand capability of the terminal structure, this invention provides a composite terminal structure. Specifically, taking N-type conductivity as an example, the terminal structure includes a semiconductor substrate of N-type conductivity and a JTE lateral terminal extension structure disposed within the terminal region of the semiconductor substrate. The JTE lateral termination extension structure includes a P-conductive type JTE lateral termination extension region 10; On the cross-section of the terminal structure, at least one adjustment compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area 10. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region 10, so as to improve the withstand voltage of the terminal structure by utilizing the formed three-dimensional charge balance region.

[0034] It should be noted that the composite termination structure of the present invention is a termination structure used in power semiconductor devices. The composite termination structure is used to improve the withstand voltage of power semiconductor devices. The distribution position and corresponding function of the termination structure on the power semiconductor device are consistent with existing power semiconductor devices. Specifically, similar to the termination structure of existing power semiconductor devices, the termination structure of the present invention is located in the termination region of the semiconductor substrate. Figure 1 The figure shows a cross-sectional view of an embodiment of the composite terminal structure. As can be seen from the figure, the semiconductor substrate includes an N-type epitaxial layer 4, and the terminal structure includes a JTE (Junction Termination Extension) lateral terminal extension structure fabricated in the N-type epitaxial layer 4. It should be understood that the function of the JTE lateral terminal extension structure and its position in the terminal region are consistent with the existing ones. For example, the JTE lateral terminal extension structure should include at least a JTE lateral terminal extension region 10.

[0035] To further improve the voltage withstand capability of the terminal structure, this invention provides at least one adjustment and compensation unit within the JTE lateral terminal extension region 10. This adjustment and compensation unit enables adjustment of the longitudinal electric field and charge compensation. Here, "lateral" refers to the extension direction of the JTE lateral terminal extension region 10, and "longitudinal" is the direction perpendicular to the lateral direction. Generally, the longitudinal direction coincides with the thickness direction of the N-type epitaxial layer 4. The number of adjustment and compensation units can be selected as needed. Figure 1 The image shows one embodiment with four adjustment compensation units.

[0036] In specific implementation, when the terminal structure is in reverse bias, a three-dimensional charge balance region can be formed based on the adjustment compensation unit and the JTE lateral terminal extension region 10 where it is located. The voltage withstand capability of the terminal structure can be improved by using the formed three-dimensional charge balance region, thereby realizing the adjustment of the longitudinal electric field and charge compensation. The situation where the terminal structure is in reverse bias is consistent with the existing situation, and will not be elaborated here.

[0037] In one embodiment of the present invention, a P-conductivity type main junction 5 is provided in the semiconductor substrate, and the main junction 5 is adjacent to the JTE lateral termination extension structure. The junction depth of the JTE lateral terminal extension area 10 is less than the junction depth of the main junction 5; On the cross-section of the terminal structure, when multiple adjustment compensation units are provided in the JTE lateral terminal extension area 10, the multiple adjustment compensation units are arranged sequentially along the direction from the main node 5 to the JTE lateral extension structure, and adjacent adjustment compensation units are spaced apart by the JTE lateral terminal extension area 10.

[0038] Depend on Figure 1 As can be seen, in this invention, a main junction 5 is provided within the N-type epitaxial layer 4. The main junction 5 is generally located at the junction of the active region and the termination region. The main junction 5 extends vertically downward from the surface of the N-type epitaxial layer 4, and its function is consistent with that of the prior art. Figure 1 It can be seen that the main junction 5 is adjacent to the JTE lateral termination extension structure, specifically, the main junction 5 is adjacent to the JTE lateral termination extension area 10. In addition, the junction depth of the JTE lateral termination extension area 10 should be less than the junction depth of the main junction 5, that is, the bottom of the JTE lateral termination extension area should be located above the corresponding bottom of the main junction 5. The extension direction of the JTE lateral termination extension area 10 is the direction from the main junction 5 to the edge of the semiconductor substrate.

[0039] It is understood that there can be one or more adjustment compensation units. When multiple adjustment compensation units are set in the JTE lateral terminal extension area 10, all adjustment compensation units should be arranged sequentially along the direction from the main node 5 to the JTE lateral extension structure, that is, the arrangement direction of all adjustment compensation units is lateral. Since the adjustment compensation units are located in the JTE lateral terminal extension area 10, adjacent adjustment compensation units can be spaced apart through the JTE lateral terminal extension area 10.

[0040] In one embodiment of the present invention, the adjustment compensation unit includes an adjustment compensation trench 16 disposed within the JTE lateral terminal extension region 10 and a P-type trench bottom doping region 8 covering the bottom of the adjustment compensation trench 16, wherein, The P-type trench bottom doped region 8 is located within the JTE lateral terminal extension region 10, and the doping concentration of the P-type trench bottom doped region 8 is greater than the corresponding doping concentration of the JTE lateral terminal extension region 10. The adjustment compensation trench 16 is filled with adjustment compensation medium 9.

[0041] Figure 1 and Figure 12The figure illustrates an embodiment of the adjustment compensation unit of the present invention. Each adjustment compensation unit includes an adjustment compensation trench 16 and an adjustment compensation medium 9 filled within the trench 16. Furthermore, a P-type bottom doped region 8 is provided at the bottom of the adjustment compensation trench 16, covering the bottom of the trench 16. In specific implementation, the trench depth of the adjustment compensation trench 16 should be less than the junction depth of the JTE lateral terminal extension region 10, so that the P-type bottom doped region 8 can be prepared within the JTE lateral terminal extension region 10, and the doping concentration of the P-type bottom doped region 8 is greater than the doping concentration of the JTE lateral terminal extension region 10.

[0042] In practical implementation, when the P-type trench bottom doped region 8 covers the bottom of the adjustment and compensation trench 16, it can prevent premature breakdown of the terminal caused by electric field concentration at the corner of the adjustment and compensation trench 16, thereby reducing the electric field on the surface of the semiconductor substrate. Specifically, the material used for the adjustment and compensation medium 9 can be a commonly used dielectric material, such as silicon dioxide or a high-k dielectric material. The material used for the adjustment and compensation medium 9 can be selected as needed, and will not be elaborated here.

[0043] In one embodiment of the present invention, the cross-section of the terminal structure further includes a plurality of field limiting loop units arranged sequentially, wherein, The field limiting ring unit includes a P-type field ring injection region 11 located in the terminal region of the semiconductor substrate and a field limiting ring field plate adapted to be electrically connected to the P-type field ring injection region 11. On the cross-section of the terminal structure, the width of the P-type field ring injection region 11 gradually narrows along the direction from the edge of the semiconductor substrate to the JTE lateral terminal extension structure.

[0044] To further improve withstand voltage, the termination structure should generally include several field limiting ring units. These field limiting ring units should generally be located outside the JTE lateral termination extension area 10, that is, in the area between the JTE lateral termination extension area 10 and the edge of the semiconductor substrate. Figure 1 and Figure 12 In the cross-section of the terminal structure, when there are multiple field limiting loop units, the multiple field limiting loop units are arranged sequentially. For example, along the direction from the edge of the JTE lateral terminal extension area 10, the field limiting loop units are arranged sequentially. It should be noted that the function of setting field limiting loop units in the terminal structure is consistent with the function of field limiting loops set in existing power semiconductor devices, and will not be elaborated here.

[0045] Similar to existing field limiting rings, the field limiting ring unit of this invention generally includes a P-type field ring injection region 11 and a field limiting ring field plate. The P-type field ring injection region 11 is generally located within the terminal region of the N-type epitaxial layer 4, while the field limiting ring field plate is generally located above the P-type field ring injection region 11, but the field limiting ring field plate should be electrically connected to the corresponding P-type field ring injection region 11. In specific implementations, when multiple field limiting ring units are arranged within the terminal structure, the width of the P-type field ring injection region 11 gradually narrows along the arrangement direction of the field limiting ring units, thereby achieving a smooth and uniform distribution of the electric field, thereby maximizing the breakdown voltage of the terminal structure and widening the process tolerance window of the terminal structure, such as... Figure 1 and Figure 12 As shown in the figure, the width of the P-type field ring injection region 11 specifically refers to... Figure 1 and Figure 12 The dimensions in the horizontal direction.

[0046] In specific implementation, the junction depth of the P-type field ring injection region 11 is not greater than the junction depth of the JTE lateral terminal extension structure, that is, the junction depth of the P-type field ring injection region 11 is not greater than the junction depth of the JTE lateral terminal extension region 10. Generally, the P-type field ring injection region 11 and the JTE lateral terminal extension region 10 are prepared by the same process step. At this time, the junction depth of the P-type field ring injection region 11 is the same as the junction depth of the JTE lateral terminal extension region 10, which can reduce the complexity of the preparation process.

[0047] In one embodiment of the present invention, for each field limiting ring unit, the field limiting ring field plate includes a field plate conductive polysilicon 12 that is in contact with the P-type field ring injection region 11 and a field plate metal 14 that is in ohmic contact with the P-type field ring injection region 11, and the field plate metal 14 is in ohmic contact with the field plate conductive polysilicon 12.

[0048] Figure 1 and Figure 12 An embodiment of a field limiting ring field plate is shown, wherein each field limiting ring field plate may include a field plate conductive polysilicon 12 and a field plate metal 14, and the metal field plate 13 should be in ohmic contact with the corresponding P-type field ring injection region 11 and the field plate conductive polysilicon 13, that is, the field limiting ring field plate of the present invention is a metal field plate. Figure 1 and Figure 12 In this structure, a supporting oxide layer 13 is disposed on the N-type epitaxial layer 4, and a field-conducting polysilicon 12 is located within the supporting oxide layer 13. One end of the field-conducting polysilicon 12 contacts the P-type field ring injection region 11. The electric field distribution on the surface of the power semiconductor device can be modulated through the field-conducting polysilicon 12 to prevent premature electric field concentration, thereby improving the breakdown voltage and long-term reliability of the terminal structure. A field-plate metal 14 is supported on the supporting oxide layer 13 and passes through the supporting oxide layer 13 to make ohmic contact with the P-type field ring injection region 11 and to make ohmic contact with the field-conducting polysilicon 12 within the supporting oxide layer 13.

[0049] Figure 1 and Figure 12 In this configuration, a passivation layer 7 is disposed above the N-type epitaxial layer 4, covering the supporting oxide layer 13 and the field metal 14 to protect the field metal 14. Furthermore, Figure 1 and Figure 12 The main junction 5 is also connected to the source metal 6, which can form the source electrode of the power semiconductor device. When a passivation layer 7 is provided, the passivation layer 7 is generally also covered on the source metal 6 so that the source metal 6 can also be protected by the passivation layer 7.

[0050] The working mechanism of the terminal structure of the present invention will be explained below. Specifically, the adjustment compensation trench 14 is filled with adjustment compensation medium 9. By utilizing the difference in dielectric constant brought about by the adjustment compensation medium 9, the peak electric field that is prone to breakdown is transferred from the fragile semiconductor substrate surface to the more robust adjustment compensation medium 9. At the same time, a doping gradient is formed between the P-type trench bottom doped region 8 and the JTE lateral terminal extension region 10, and a local vertical PN junction is formed with the N-type epitaxial layer 4. Under high reverse bias, an additional depletion region is generated, which works in conjunction with the depletion region of the lateral JTE lateral terminal extension region 10 to form a three-dimensional charge balance region.

[0051] When a three-dimensional charge balance region is formed, two direct technical effects can be achieved: First, the electric field strength in the adjustment compensation medium 9 is significantly reduced, fundamentally improving the reliability of the adjustment compensation medium 9; second, the process tolerance of the JTE lateral terminal extension region 10 doping is widened, because the longitudinal charge compensation can buffer the process fluctuations of the JTE lateral terminal extension region 10 doping to a certain extent.

[0052] Furthermore, when the termination structure includes several field-limiting ring units, the field-limiting ring units, in conjunction with the JTE lateral termination extension region 10, can provide a region within the termination region with extremely low doping concentration, large depletion width, and insensitivity to process fluctuations. This region serves as a buffer and endpoint for electric field extension, ensuring that even if the depletion of the JTE lateral termination extension region 10 ahead is incomplete or the interface charge fluctuates, the final breakdown point can be stably confined within this wide depletion region. This greatly enhances the robustness of the entire termination structure, achieving a smooth, multi-level, and controllable distribution of the electric field from the active region to the edge of the termination region. The electric field peak is dispersed across multiple vertical and horizontal nodes, improving the withstand voltage and operational reliability of power semiconductor devices.

[0053] for Figure 1 and Figure 12 The present invention provides a method for preparing a composite terminal structure, wherein the method comprises: A semiconductor substrate 15 of type N conductivity is provided, and a front-side termination process is performed on the front side of the semiconductor substrate 15 to form a JTE lateral termination extension structure in the termination region of the semiconductor substrate via the front-side termination process. The JTE lateral termination extension structure includes a P-conductive type JTE lateral termination extension region 10; On the cross-section of the terminal structure, at least one adjustment and compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region 10, so as to improve the withstand voltage of the terminal structure by utilizing the formed three-dimensional charge balance region.

[0054] Figures 2-12 The process of the preparation method of the present invention is shown in the figure. Figure 2 It is understood that the fabrication process should provide a semiconductor substrate 15. It should be noted that the semiconductor substrate 15 is used to form... Figure 1 The doping concentration of the N-type epitaxial layer 4 and the N+ substrate 3, such as the semiconductor substrate 15, should be consistent with the doping concentration of the N-type epitaxial layer 4. Figures 2-12 When fabricating the aforementioned composite terminal structure, a front-side terminal process should first be performed on the terminal region of the semiconductor substrate 15. The front side of the semiconductor substrate 15 is one surface of the semiconductor substrate 15, and its configuration can be consistent with existing technologies. During the process, the corresponding active region and terminal region within the semiconductor substrate 15 can generally be defined, and the division of the active region and terminal region can be consistent with existing technologies. The composite terminal structure fabricated through the front-side terminal process can be referenced. Figure 1 , Figure 12 And the corresponding explanations above.

[0055] In one embodiment of the present invention, the front-facing terminal process includes: A P-conductivity main junction 5 is fabricated within a semiconductor substrate 15. A JTE lateral termination extension region 10 is prepared in the termination region of the semiconductor substrate 15, and then at least one adjustment compensation trench 16 is formed in the JTE lateral termination extension region 10. A P-type bottom doping region 8 is formed at the bottom of each adjustment compensation trench 16 to cover the bottom of adjacent adjustment compensation trenches 16. Fill each adjustment and compensation groove 16 with adjustment and compensation medium 9.

[0056] Depend on Figure 3It is known that when performing the front-side termination process, the main junction 5 should be fabricated first. The main junction 5 is generally formed by placing P-type impurity ions on the front side of the semiconductor substrate 15. The fabrication method for the main junction 5 can be selected as needed and will not be elaborated here. After fabricating the main junction 5, the JTE lateral termination extension region 10 and the P-type field ring implantation region 11 are simultaneously fabricated within the termination region, as follows... Figure 4 As shown, the situation of JTE lateral terminal extension region 10 and P-type field ring injection region 11 can be referred to the above description, and will not be repeated here.

[0057] Figure 5 The illustration shows an embodiment in which a JTE lateral terminal extension region 10 is prepared, and a plurality of adjustment compensation trenches 16 are prepared within the JTE lateral terminal extension region 10. The method of preparing the adjustment compensation trenches 16 is consistent with the prior art. The depth of the adjustment compensation trenches 16 is less than the junction depth of the JTE lateral terminal extension region 10. Figure 6 The diagram illustrates the preparation of a P-type bottom doped region 8 at the bottom of each adjustment compensation trench 16. The method for preparing the P-type bottom doped region 8 is consistent with existing technology and will not be described in detail here. After preparing the P-type bottom doped region 8, the adjustment compensation trench 16 should be filled with an adjustment compensation medium 9. Since the medium material used for the adjustment compensation medium 9 can be different, the method for filling the adjustment compensation medium 9 will be explained in detail below.

[0058] In one embodiment of the present invention, the material of the adjustment compensation medium 9 includes silicon dioxide or a high-k dielectric material, wherein, When the material of the adjustment compensation medium 9 is silicon dioxide, the method of filling the adjustment compensation medium 9 includes: Before fabricating the adjustment compensation trench 16 within the JTE lateral termination extension region 10, a P-type field ring injection region 11 is first fabricated within the termination region of the semiconductor substrate 15, wherein... On the cross-section of the terminal structure, along the direction of the JTE lateral terminal extension structure pointing to the edge of the semiconductor substrate 15, the P-type field ring injection regions 11 are arranged sequentially. After a P-type trench bottom doped region 8 is prepared at the bottom of each adjustment compensation trench 16, an oxide base layer 17 is formed on the front side of the semiconductor substrate 15 using silicon dioxide. The oxide base layer 17 covers the front side of the semiconductor substrate 15 and fills the adjustment compensation trench 16, so as to form an adjustment compensation medium 9 by utilizing the oxide base layer 17 filled in the adjustment compensation trench 16.

[0059] In specific implementation, when the material of the adjustment compensation medium 9 is a high-K dielectric material, the high-K dielectric material can be directly filled into the adjustment compensation trench 16. The type of high-K dielectric material and the filling process in the adjustment compensation trench 16 can be consistent with existing technology, and will not be elaborated here. When silicon dioxide is selected as the material of the adjustment compensation medium 9, in order to ensure process compatibility and reduce process costs, Figure 7 The diagram shows that an oxide substrate 17 is first prepared on the front side of the semiconductor substrate 15. The thickness of the oxide substrate 17 should be less than the thickness of the supporting oxide layer 13 mentioned above. The prepared oxide substrate 17 will fill the adjustment compensation trench 16 and also cover the front side of the semiconductor substrate 15.

[0060] Figure 8 In the process, after the oxide substrate 17 is prepared, holes should be made in the region corresponding to the P-type field ring injection region 11. Then, field plate conductive polysilicon 12 is prepared. The field plate conductive polysilicon 12 is supported on the oxide substrate 17 and contacts the P-type field ring injection region 11 through the corresponding holes.

[0061] After preparing the field plate conductive polycrystalline silicon 12, in order to form the supporting oxide layer 13, an oxide layer process should be performed again. At this time, the supporting oxide layer 13 covering the field plate conductive polycrystalline silicon 12 can be formed, such as... Figure 9 As shown, the oxide layer process can be rotated as needed, and will not be elaborated further here. Figure 10 The diagram illustrates an embodiment of a front-side metallization process performed after the preparation of the supporting oxide layer 13. Specifically, during the front-side metallization process, the supporting oxide layer 13 is selectively masked and etched to form several metal deposition areas, after which deposition can be performed to form... Figure 10 The source metal 6 and field metal 14 mentioned above are described in the above description. That is, the front-side metal process is designed to form both the source metal 6 and the field metal 14. Of course, the front-side metal process generally also includes a gate metal, which can be used to form the gate electrode of a power semiconductor device. The gate metal and the formation of the gate electrode are consistent with existing technologies and will not be elaborated further here.

[0062] Figure 11 The diagram illustrates one embodiment of obtaining a passivation layer 7 after the front metallization process. Specifically, after the front metallization process, a passivation process should be performed, with the passivation process designed to form the passivation layer 7. Generally, once the passivation layer 7 is obtained, the front terminal process is complete, and the aforementioned composite terminal structure is obtained.

[0063] In one embodiment of the present invention, after the JTE lateral termination extension structure is prepared by the front-side termination process, a back-side process is performed on the back side of the semiconductor substrate 15 to prepare a back-side electrode structure.

[0064] Figure 1 and Figure 12 The diagram illustrates one embodiment of the back electrode structure when the power semiconductor device is an IGBT device. When the power semiconductor device is another type of power device, the back electrode fabrication method should correspond to the type of power device. Specifically, Figure 12 In this process, a doping process is performed on the back side of the semiconductor substrate 15 to prepare an N-type field cutoff layer 3 and a P+ collector region 2. At this time, an N-type epitaxial layer 4 can be formed in the remaining area of ​​the semiconductor substrate 15. The N-type field cutoff layer 3 is adjacent to the N-type epitaxial layer 4 and the P+ collector region 2.

[0065] After the P+ collector region 2 is prepared, metal processing can be performed on the P+ collector region 2 to form collector metal 1. Collector metal 1 is in ohmic contact with the P+ collector region 2, and collector metal 1 can be used to form the collector of the IGBT device.

Claims

1. A composite terminal structure, characterized in that, The terminal structure includes a semiconductor substrate of a first conductivity type and a JTE lateral terminal extension structure disposed within the terminal region of the semiconductor substrate, wherein... The JTE lateral termination extension structure includes a JTE lateral termination extension region of a second conductivity type; On the cross-section of the terminal structure, at least one adjustment and compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region, so as to improve the voltage withstand capability of the terminal structure by utilizing the formed three-dimensional charge balance region.

2. The composite terminal structure according to claim 1, characterized in that: in A main junction of a second conductivity type is provided in the semiconductor substrate, and the main junction is adjacent to the JTE lateral termination extension structure. The junction depth of the JTE lateral terminal extension region is less than the junction depth of the main junction; On the cross-section of the terminal structure, when multiple adjustment and compensation units are provided in the JTE lateral terminal extension area, the multiple adjustment and compensation units are arranged sequentially along the direction from the main node to the JTE lateral extension structure, and adjacent adjustment and compensation units are separated by the JTE lateral terminal extension area.

3. The composite terminal structure according to claim 1, characterized in that, The adjustment and compensation unit includes an adjustment and compensation trench disposed within the JTE lateral terminal extension region and a second conductivity type bottom doped region covering the bottom of the adjustment and compensation trench, wherein... The second conductivity type bottom doped region is located within the JTE lateral terminal extension region, and the doping concentration of the second conductivity type bottom doped region is greater than the corresponding doping concentration of the JTE lateral terminal extension region. The adjustment and compensation trench is filled with adjustment and compensation medium.

4. The composite terminal structure according to claim 1, characterized in that, The cross-section of the terminal structure also includes several field limiting ring units arranged sequentially, wherein, The field limiting ring unit includes a second conductivity type field ring injection region located in the terminal region of the semiconductor substrate and a field limiting ring field plate adapted to be electrically connected to the second conductivity type field ring injection region. On the cross-section of the terminal structure, along the direction from the JTE lateral terminal extension structure to the edge of the semiconductor substrate, the width of the second conductivity type field confinement ring injection region gradually narrows.

5. The composite terminal structure according to claim 4, characterized in that, For each field limiting ring unit, the field limiting ring field plate includes a field plate conductive polysilicon that is in contact with the injection region of the second conductivity type field ring and a field plate metal that is in ohmic contact with the injection region of the second conductivity type field ring, and the field plate metal is in ohmic contact with the field plate conductive polysilicon.

6. The composite terminal structure according to claim 4, characterized in that, The junction depth of the second conductivity type field-limited ring injection region is no greater than the junction depth of the JTE lateral termination extension structure.

7. A method for preparing a composite terminal structure, characterized in that, The method for preparing the terminal structure according to any one of claims 1 to 6 includes: A semiconductor substrate of a first conductivity type is provided, and a front-side termination process is performed on the front side of the semiconductor substrate to form a JTE lateral termination extension structure in the termination region of the semiconductor substrate via the front-side termination process. The JTE lateral termination extension structure includes a JTE lateral termination extension region of a second conductivity type; On the cross-section of the terminal structure, at least one adjustment and compensation unit for longitudinal electric field modulation and charge compensation is provided in the JTE lateral terminal extension area. When the terminal structure is in reverse bias, a three-dimensional charge balance region is formed based on the adjustment compensation unit and the JTE lateral terminal extension region, so as to improve the voltage withstand capability of the terminal structure by utilizing the formed three-dimensional charge balance region.

8. The method for preparing the composite terminal structure according to claim 7, characterized in that, The front-end terminal process includes: Fabricating a main junction of a second conductivity type within a semiconductor substrate. A JTE lateral termination extension region is fabricated within the termination region of a semiconductor substrate, and then at least one adjustment compensation trench is fabricated within the JTE lateral termination extension region. A second conductivity type bottom doping region is formed at the bottom of each adjustment compensation trench to cover the bottom of adjacent adjustment compensation trenches. Fill each adjustment and compensation trench with adjustment and compensation medium.

9. The method for preparing the composite terminal structure according to claim 8, characterized in that, The material of the adjustment and compensation medium includes silicon dioxide or a high-k dielectric material, wherein... When the material of the adjustment compensation medium is silicon dioxide, the methods for filling the adjustment compensation medium include: Before fabricating the adjustment compensation trench within the JTE lateral termination extension region, a second conductivity type field ring injection region is first fabricated within the termination region of the semiconductor substrate, wherein... On the cross-section of the terminal structure, along the direction of the JTE lateral terminal extension structure pointing to the edge of the semiconductor substrate, the second conductivity type field ring injection regions are arranged sequentially. After a second conductivity type trench bottom doped region is prepared at the bottom of each adjustment compensation trench, an oxide base layer is formed on the front side of the semiconductor substrate using silicon dioxide. The oxide base layer covers the front side of the semiconductor substrate and fills the adjustment compensation trench, so as to form an adjustment compensation medium using the oxide base layer filled in the adjustment compensation trench.

10. The method for preparing the composite terminal structure according to any one of claims 7 to 9, characterized in that, After the JTE lateral termination extension structure is prepared by the front-side termination process, a back-side process is performed on the back side of the semiconductor substrate to prepare the back-side electrode structure.

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