Electric field modulated p-GaN gate enhanced HEMT and preparation method thereof

Abstract

The invention discloses an electric field modulated p-GaN gate enhanced HEMT (High Electron Mobility Transistor) and a preparation method thereof, and the p-GaN gate enhanced HEMT comprises a substrate layer, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are sequentially superposed from bottom to top, a source electrode, a cap layer, a modulation layer array, a drain electrode and a grid electrode located on the cap layer are sequentially arranged from one end to the other end of the upper surface of the barrier layer; the modulation layer array comprises a plurality of modulation layers; the source electrode, the cap layer and the modulation layer array are arranged at intervals; and the modulation layer array and the drain electrode are arranged in a contact manner, so that the p-GaN gate enhanced HEMT which can effectively improve the electric field distribution between the gate electrode and the source electrode of the device and reduce the electric field intensity peak value of a channel below the drain electrode is provided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor transistor technology, specifically relating to an electric field modulated p-GaN (gallium nitride) gate enhancement type HEMT (High electron mobility transistor). Background Technology

[0002] Power semiconductor devices are widely used in power electronics and microwave communications, and in recent years the market has placed higher demands on their operating frequency, voltage withstand capability, and other performance characteristics. With silicon-based devices gradually approaching their theoretical limits, GaN materials, with their wide bandgap, high breakdown electric field, high temperature resistance, and radiation resistance, have shown great potential market value. Based on the high-density, high-mobility two-dimensional electron gas in AlGaN (aluminum gallium nitride) / GaN heterojunctions, HEMT devices with both high voltage withstand capability and high-frequency performance can be fabricated. However, precisely because of the presence of the two-dimensional electron gas at the heterojunction interface, such devices often require relatively complex gate drive circuits in practical applications. Therefore, realizing enhancement-mode GaN HEMTs has become an important technical goal in GaN HEMT applications.

[0003] Currently, the main technologies for realizing enhancement-mode GaN HEMTs include grooved gate structures, F (fluorine) ion implantation, p-type gates, and cascaded structures. Among these, p-type gate technology on AlGaN / GaN heterojunctions has potential advantages in terms of interface quality and device on-state characteristics. However, the introduction of p-GaN cap structures often results in electric field intensity peaks in the channel below the drain, affecting the improvement of device breakdown voltage.

[0004] Therefore, how to provide a p-GaN gate-enhanced HEMT that can effectively improve the electric field distribution between the gate and source of the device and reduce the peak electric field intensity of the channel below the drain has become an important issue. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an electric field modulated p-GaN gate-enhanced HEMT and its fabrication method.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides an electric field-modulated p-GaN gate enhancement HEMT, the p-GaN gate enhancement HEMT comprising: The substrate layer, nucleation layer, buffer layer, channel layer and barrier layer are stacked sequentially from bottom to top; A source, a cap layer, a modulation layer array, and a drain are sequentially disposed along one end of the upper surface of the barrier layer to the other end; the modulation layer array includes multiple modulation layers. The source, the cap layer, and the modulation layer array are spaced apart; the modulation layer array and the drain are in contact. The gate is located above the cap layer.

[0007] Optionally, a portion of the drain extends above the modulation layer array and covers a portion of the upper surface of the modulation layer array to form a field plate structure.

[0008] Optionally, the thickness of the cap layer is greater than the thickness of the modulation layer.

[0009] Optionally, the thickness difference between the cap layer and the modulation layer ranges from 40 to 70 nm.

[0010] Optionally, the plurality of modulation layers are arranged at intervals along the upper surface of the barrier layer, parallel to the drain near the gate side.

[0011] Optionally, each modulation layer in the modulation layer array has a length of 1000nm, a width of 1000nm, and a height of 70nm.

[0012] Optionally, the spacing between adjacent modulation layers is 2 μm.

[0013] Optionally, the substrate layer is made of silicon, sapphire, silicon carbide, gallium nitride, or diamond self-supporting substrate; the nucleation layer is made of AlN superlattice; the buffer layer is made of GaN or AlGaN; the channel layer is made of GaN; the barrier layer is made of AlGaN; the cap layer is made of p-GaN; and the modulation layer is made of p-GaN.

[0014] Optionally, the thickness of the nucleation layer can range from 0.5 to 2 nm; the thickness of the buffer layer can range from 0.2 to 1 μm; the thickness of the channel layer can range from 100 to 300 nm; and the thickness of the barrier layer can range from 10 to 30 nm.

[0015] Secondly, the present invention provides a method for fabricating an electric field-modulated p-GaN gate-enhanced HEMT, the method comprising: A core layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer are sequentially epitaxially grown on the substrate. A patterned gate region is defined using photolithography, and the portion of the p-GaN layer other than the gate region is etched to form an initial cap layer. A patterned modulation layer array region is defined using photolithography, and the portion of the p-GaN layer excluding the initial cap layer and the modulation layer array region is etched to obtain the cap layer and the modulation layer array; the modulation layer array includes multiple modulation layers. A source is fabricated on the upper surface of the barrier layer near the device edge of the cap layer, a drain is fabricated on the upper surface of the barrier layer near the device edge of the modulation layer array, and a gate is fabricated on the upper surface of the cap layer; wherein the source, the cap layer, and the modulation layer array are spaced apart; and the modulation layer array and the drain are in contact.

[0016] This invention provides an electric field-modulated p-GaN gate-enhanced HEMT. The modulation layer array, formed by multiple arrayed modulation layers, more effectively disperses and balances the peak electric field below the drain, preventing excessive concentration of the electric field in a single region. This results in a more uniform electric field patching across the entire drain edge, further enhancing the breakdown voltage. Simultaneously, it avoids completely depleting the underlying two-dimensional electron gas, ensuring the device maintains excellent current transport capability when powered on.

[0017] Furthermore, the fabrication process of the modulation layer at the drain edge is highly compatible with the mainstream p-GaN gate-enhanced HEMT manufacturing process, eliminating the need for complex or expensive special steps. This improves key device performance indicators while ensuring the feasibility and economy of large-scale production. Secondly, it eliminates the need for additional materials, simplifying the process and avoiding additional defects introduced when growing other materials as the modulation layer. This ensures the quality of the modulation layer and improves device reliability.

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an electric field modulated p-GaN gate enhancement HEMT provided in an embodiment of the present invention; Figure 2 This is a top view of an electric field modulated p-GaN gate enhancement HEMT provided in an embodiment of the present invention; Figure 3 This is a schematic flowchart of a method for fabricating an electric field-modulated p-GaN gate-enhanced HEMT according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the fabrication process of an electric field-modulated p-GaN gate-enhanced HEMT provided in an embodiment of the present invention.

[0020] Reference numerals: 01, Substrate; 02, Nucleation layer; 03, Buffer layer; 04, Channel layer; 05, Barrier layer; 06, Cap layer; 07, Modulation layer; 08, Source; 09, Drain; 10, Gate. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] To address the issue of excessively high peak electric field in the channel below the drain in existing p-GaN gate-enhanced GaN HEMTs, which limits the improvement of device breakdown voltage, this invention provides an electric field-modulated p-GaN gate-enhanced HEMT. (See [link to relevant documentation]). Figure 1 , Figure 1 This is a schematic diagram of the structure of an electric field modulated p-GaN gate enhancement HEMT provided in an embodiment of the present invention. The electric field modulated p-GaN gate enhancement HEMT includes a substrate layer 01, a nucleation layer 02, a buffer layer 03, a channel layer 04, a barrier layer 05, a cap layer 06, a modulation layer 07, a source 08, a drain 09, and a gate 10.

[0023] In this embodiment of the invention, the substrate layer 01, the nucleation layer 02, the buffer layer 03, the channel layer 04, and the barrier layer 05 are stacked sequentially from bottom to top.

[0024] Among them, the substrate layer 01 can be made of silicon, sapphire, silicon carbide, gallium nitride or diamond self-supporting substrate; the nucleation layer 02 can be made of AlN (aluminum nitride) superlattice; the buffer layer 03 can be made of GaN or AlGaN; the channel layer 04 can be made of GaN; the barrier layer 05 can be made of AlGaN; and the p-GaN layer is made of p-GaN.

[0025] The thickness of nucleation layer 02 can range from 0.5 to 2 nm, the thickness of buffer layer 03 can range from 0.2 to 1 μm, the thickness of channel layer 04 can range from 100 to 300 nm, and the thickness of barrier layer 05 can range from 10 to 30 nm.

[0026] In this embodiment of the invention, a source 08, a cap layer 06, a modulation layer 07 and a drain 09 are sequentially disposed along one end to the other on the upper surface of the barrier layer 05; the gate 10 is located on the cap layer 06.

[0027] The cap layer 06 is made of p-GaN, the modulation layer 07 is made of p-GaN; the source 08 is made of Ti (titanium) / Al / Ni (nickel) / Au (gold) or Ti / Al / Ti / Au stack; the drain 09 is made of Ti / Al / Ni / Au or Ti / Al / Ti / Au stack; the gate 10 is made of Ni / Au or Ni / TiN (titanium nitride) stack.

[0028] The thicknesses of Ti / Al / Ni / Au can be 20 / 120 / 50 / 45nm, respectively, and the thicknesses of Ni / Au can be 50 / 100nm, respectively.

[0029] In this embodiment of the invention, the modulation layer 07 is made of p-GaN. Utilizing its inherent semiconductor properties, the modulation layer 07 and the underlying channel material form a planned induced band structure, which can significantly reduce the carrier concentration in the two-dimensional electron gas channel directly below it. This reduction in concentration leads to modulation and a more uniform electric field distribution near the edge of the drain 09. By reducing the peak electric field near the edge of the drain 09, the breakdown voltage of the device is significantly improved, thereby enhancing the reliability and withstand performance of the device under high voltage operation.

[0030] In this embodiment of the invention, the thickness of the cap layer 06 is greater than the thickness of the modulation layer 07. The existence of the cap layer 06, which is made of p-GaN, is to completely deplete the two-dimensional electron gas under the gate to achieve the turn-off characteristic and thus realize the enhancement-mode device. The thickness of the modulation layer 07 cannot be too high because the function of the modulation layer 07 is to suppress the current at the edge of the drain electrode 09 by consuming the two-dimensional electron gas below through the p-type material of p-GaN, thereby achieving the effect of a uniform electric field.

[0031] If the thickness difference between the cap layer 06 and the modulation layer 07 is too large, it will completely block the conduction of the two-dimensional electron gas below. If it is too small, it will be difficult to achieve the effect of a uniform electric field. Therefore, the thickness difference between the cap layer 06 and the modulation layer 07 is preferably 40~70nm.

[0032] In this embodiment of the invention, a portion of the drain 09 extends above the modulation layer 07 array and covers a portion of the upper surface of the modulation layer array to form a field plate structure, further modulating the electric field, so that the electric field at the edge of the drain 09 is uniformly distributed, reducing the occurrence of its edge peak electric field, effectively mitigating the electric field concentration at the edge of the drain 09, which is beneficial to improving the withstand voltage of the device.

[0033] The drain electrode extends above the modulation layer array by a length less than that of modulation layer 07. Specifically, the thickness difference between cap layer 06 and modulation layer 07 is less than 100 nm.

[0034] In this embodiment of the invention, the modulation layer array includes at least two modulation layers 07; multiple modulation layers 07 are arranged at intervals along the upper surface of the barrier layer 05, parallel to the drain 09 near the gate 10. See also Figure 2 , Figure 2 This is a top view of an electric field modulated p-GaN gate enhancement HEMT provided in an embodiment of the present invention. By arraying the modulation layer 07, the electric field near the drain 09 can be more uniformly dispersed and modulated in the lateral dimension, avoiding excessive concentration of the electric field in a single location, thereby synergistically improving the overall breakdown voltage of the device.

[0035] In this embodiment of the invention, the shape of each modulation layer 07 can be hemispherical, cylindrical, or cuboid, etc. Among them, the cuboid shape is preferred. This shape can not only be achieved with high precision through standard photolithography and etching processes and is fully compatible with existing semiconductor manufacturing processes, but also facilitates the precise definition of its dimensions and prediction of its electric field modulation behavior in the design, thereby minimizing process complexity and manufacturing costs while ensuring the controllability and repeatability of device performance.

[0036] For example, each modulation layer 07 in the modulation layer array can be a cuboid with a length of 1000nm, a width of 1000nm, and a height of 70nm.

[0037] In this embodiment of the invention, the spacing between adjacent modulation layers 07 is designed to ensure that each modulation layer 07 can independently and effectively form electric field modulation in its underlying region, avoiding overlap and saturation of the electric field modulation areas due to excessively small spacing. Furthermore, this distance needs to be well-matched with the resolution of conventional semiconductor lithography processes, facilitating high-fidelity transfer and etching of patterns, ensuring the consistency and reliability of the array structure, thereby improving device breakdown voltage while maintaining manufacturing feasibility and yield. Therefore, in this embodiment of the invention, the spacing between adjacent modulation layers 07 is set to 2 μm.

[0038] In this embodiment of the invention, the modulation layer array formed by multiple arrayed modulation layers 07 can more effectively disperse and balance the peak electric field below the drain 09, avoiding excessive concentration of the electric field in a single region. This makes the electric field patching at the edge of the entire drain 09 more uniform, further consolidating the improvement effect on breakdown voltage. At the same time, it avoids completely depleting the two-dimensional electron gas below, ensuring that the device maintains excellent current transport capability when in the on state.

[0039] Furthermore, the fabrication process of the modulation layer 07 at the edge of the drain 09 is highly compatible with the mainstream p-GaN gate-enhanced HEMT manufacturing process, eliminating the need for complex or expensive special steps. This improves key device performance indicators while ensuring the feasibility and economy of large-scale production. Secondly, it eliminates the need for additional materials, simplifying the process and avoiding additional defects introduced when growing other materials as the modulation layer 07. This ensures the quality of the modulation layer 07 and improves device reliability.

[0040] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating an electric field-modulated p-GaN gate-enhanced HEMT, see [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic flowchart of a method for fabricating an electric field-modulated p-GaN gate-enhanced HEMT according to an embodiment of the present invention, which specifically includes the following steps: Step S301: On the substrate layer 01, the nucleation layer 02, the buffer layer 03, the channel layer 04, the barrier layer 05 and the p-GaN layer are epitaxially grown sequentially.

[0041] In this embodiment of the invention, a core layer 02, a buffer layer 03, a channel layer 04, a barrier layer 05, and a p-GaN layer can be sequentially grown on the surface of substrate layer 01 using metal-organic chemical vapor deposition (MOCVD). See [link to relevant documentation]. Figure 4 (a) in the middle Figure 4 This is a schematic diagram illustrating the fabrication process of an electric field-modulated p-GaN gate-enhanced HEMT provided in an embodiment of the present invention.

[0042] The substrate layer 01 is made of silicon, sapphire, silicon carbide, gallium nitride, or diamond self-supporting substrate; the nucleation layer 02 is made of AlN superlattice; the buffer layer 03 is made of GaN or AlGaN; the channel layer 04 is made of GaN; and the barrier layer 05 is made of AlGaN.

[0043] The thickness of nucleation layer 02 can range from 0.5 to 2 nm; the thickness of buffer layer 03 can range from 0.2 to 1 μm; the thickness of channel layer 04 can range from 100 to 300 nm; the thickness of barrier layer 05 can range from 10 to 30 nm; and the thickness of p-GaN layer can range from 70 to 120 nm, preferably 100 nm.

[0044] In step S302, a patterned gate region is defined by photolithography, and the portion of the p-GaN layer other than the gate region is etched to form an initial cap layer.

[0045] See Figure 4 In (b), photoresist is used to define a patterned gate region through a photolithography process.

[0046] Then, ICP (Inductively Coupled Plasma) technology is used to etch the portion of the p-GaN layer excluding the gate region to form the initial cap layer. The etching depth is less than 100 nm. (See [link to documentation]). Figure 4 (c) in the middle.

[0047] Step S303: Define the patterned modulation layer array region through photolithography, and etch the part of the p-GaN layer other than the initial cap layer and the modulation layer array region to obtain the cap layer 06 and the modulation layer array; the modulation layer array includes multiple modulation layers 07.

[0048] See Figure 4In step (d), a patterned modulation layer array region is defined using photolithography. Then, ICP technology is used to etch the portion of the p-GaN layer excluding the initial cap layer and the modulation layer array region until the etched portion of the p-GaN layer is completely removed, resulting in the cap layer 06 and the modulation layer array. The modulation layer array includes multiple modulation layers 07. The multiple modulation layers 07 are arranged at intervals along the upper surface of the barrier layer 05, parallel to the drain 09 near the gate 10.

[0049] Each modulation layer 07 in the modulation layer array has a length of 1000 nm, a width of 1000 nm, and a height of 70 nm. The spacing between adjacent modulation layers 07 is 2 μm.

[0050] In addition, after etching, the etched sample can be immersed in an NMP (N-methylpyrrolidone) solution at 110°C for 15 minutes to repair the etching damage. Then, mesa isolation etching is performed.

[0051] Patterned device mesas are obtained through photolithography, and ICP / RIE (reactive ion etching) technology is used for mesas isolation. The etching depth exceeds the sum of the thicknesses of the barrier layer 05 and the channel layer 04. Electrical isolation between adjacent devices can be achieved through mesas etching isolation.

[0052] In step S304, a source 08 is fabricated on the upper surface of the barrier layer 05 near the device edge of the cap layer 06, a drain 09 is fabricated on the upper surface of the barrier layer 05 near the device edge of the modulation layer array, and a gate 10 is fabricated on the upper surface of the cap layer 06; wherein the source 08, the cap layer 06, and the modulation layer array are spaced apart; the modulation layer array and the drain 09 are in contact.

[0053] First, the source electrode 08 and drain electrode 09 are fabricated, see [link to documentation]. Figure 4 In (e), a source electrode 08 is fabricated on the upper surface of the barrier layer 05 on the side of the cap layer 06 near the edge of the device, and a drain electrode 09 is fabricated on the upper surface of the barrier layer 05 on the side of the modulation layer array near the edge of the device.

[0054] Specifically, the regions of the source and drain electrodes can be patterned using photolithography, and then source and drain ohmic contact electrodes can be fabricated on the surface of the barrier layer 05. The source or drain electrode material can be a Ti / Al / Ni / Au or a Ti / Al / Ti / Au stack; after the metal electrodes are stripped, they are thermally annealed at a high temperature above 800°C for 15-60 seconds in a nitrogen atmosphere to form an ohmic alloy.

[0055] In this structure, a portion of the drain 09 extends above the modulation layer array and covers part of the upper surface of the modulation layer array to form a field plate structure.

[0056] In this embodiment of the invention, a gate 10 is prepared on the upper surface of the cap layer 06.

[0057] For details, see Figure 4 In step (f), the patterned gate 10 obtained through photolithography is deposited with a gate electrode, followed by metal stripping. The gate electrode is a Ni / Au or Ni / TiN stack.

[0058] In this embodiment of the invention, the source electrode 08, the cap layer 06, and the modulation layer array are spaced apart; the modulation layer array and the drain electrode 09 are in contact.

[0059] In the embodiments of the present invention, in the aforementioned etching, modulation layer array etching and mesa isolation etching, the gas is at least one of chlorine-based, fluorine-based, Ar (argon), N2 (nitrogen) or O2 (oxygen).

[0060] In this embodiment of the invention, the electric field modulation layer structure at the edge of the drain 09 is fabricated using a process highly compatible with mainstream p-GaN gate-enhanced HEMT manufacturing processes. Neither material epitaxial growth nor p-GaN selective etching requires complex or expensive special steps, ensuring both the feasibility and economy of large-scale production while improving key device performance indicators. Furthermore, the modulation layer 07 is made of p-GaN, eliminating the need for additional materials. This simplifies the process and avoids additional defects introduced when growing other materials as the modulation layer 07, ensuring the quality of the modulation layer 07 and improving device reliability.

[0061] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0063] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0064] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An electric field modulated p-GaN gate enhancement HEMT, characterized in that, The p-GaN gate-enhanced HEMT includes: The substrate layer, nucleation layer, buffer layer, channel layer and barrier layer are stacked sequentially from bottom to top; A source, a cap layer, a modulation layer array, and a drain are sequentially disposed along one end of the upper surface of the barrier layer to the other end; the modulation layer array includes multiple modulation layers. The source, the cap layer, and the modulation layer array are spaced apart; the modulation layer array and the drain are in contact. The gate is located above the cap layer.

2. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, A portion of the drain extends above the modulation layer array and covers a portion of the upper surface of the modulation layer array to form a field plate structure.

3. The p-GaN gate-enhanced HEMT according to claim 1, characterized in that, The thickness of the cap layer is greater than the thickness of the modulation layer.

4. The p-GaN gate enhancement HEMT according to claim 3, characterized in that, The thickness difference between the cap layer and the modulation layer ranges from 40 to 70 nm.

5. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, The plurality of modulation layers are arranged at intervals along the upper surface of the barrier layer, parallel to the drain near the gate.

6. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, Each modulation layer in the modulation layer array has a length of 1000nm, a width of 1000nm, and a height of 70nm.

7. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, The spacing between adjacent modulation layers is 2 μm.

8. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, According to claim 1, the p-GaN gate-enhanced HEMT is characterized in that the substrate layer is made of silicon, sapphire, silicon carbide, gallium nitride, or diamond self-supporting substrate; the nucleation layer is made of AlN superlattice; the buffer layer is made of GaN or AlGaN; the channel layer is made of GaN; the barrier layer is made of AlGaN; the cap layer is made of p-GaN; and the modulation layer is made of p-GaN.

9. The p-GaN gate enhancement HEMT according to claim 1, characterized in that, The thickness of the nucleation layer can range from 0.5 to 2 nm; the thickness of the buffer layer can range from 0.2 to 1 μm; the thickness of the channel layer can range from 100 to 300 nm; and the thickness of the barrier layer can range from 10 to 30 nm.

10. A method for fabricating an electric field-modulated p-GaN gate-enhanced HEMT, characterized in that, The preparation method includes: A core layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer are sequentially epitaxially grown on the substrate. A patterned gate region is defined using photolithography, and the portion of the p-GaN layer other than the gate region is etched to form an initial cap layer. A patterned modulation layer array region is defined using photolithography, and the portion of the p-GaN layer excluding the initial cap layer and the modulation layer array region is etched to obtain the cap layer and the modulation layer array; the modulation layer array includes multiple modulation layers. A source is fabricated on the upper surface of the barrier layer near the device edge of the cap layer, a drain is fabricated on the upper surface of the barrier layer near the device edge of the modulation layer array, and a gate is fabricated on the upper surface of the cap layer; wherein the source, the cap layer, and the modulation layer array are spaced apart; and the modulation layer array and the drain are in contact.

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