Semiconductor device structure and preparation method thereof

Abstract

The invention discloses a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductor devices.The method comprises the steps that a first epitaxial layer is formed on one side of a substrate in a two-step epitaxial growth mode, so that a P-type column region is formed in the first epitaxial layer which is relatively thin and is initially N-type; an electric field modulation region is formed on at least part of the side, away from the substrate, of the first epitaxial layer, the electric field modulation region comprises an N-type column region and a P-type column region which are adjacently arranged in the first direction, and a super junction structure is introduced; forming a second epitaxial layer on one side, deviating from the substrate, of the electric field modulation region, and preparing other functional structures by using the second epitaxial layer; therefore, various difficulties of introducing a super junction structure into a P-type column region formed in the wide bandgap semiconductor device are overcome, a transverse electric field is formed by using the super junction structure of the electric field modulation region, the electric field intensity of the electric field modulation region is approximately distributed in a rectangular shape, and the shackle relationship between the specific on-resistance and the breakdown voltage of the wide bandgap semiconductor device is greatly relieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] In recent years, wide-bandgap semiconductor materials such as gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), silicon carbide (SiC), and gallium nitride (GaN) have shown advantages over silicon (Si) in terms of physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices made from these materials, such as diodes, transistors, and power modules, exhibit superior electrical characteristics. They can overcome the shortcomings of silicon-based materials in meeting the requirements of high-power, high-voltage, high-frequency, and high-temperature applications, and are one of the breakthrough paths that can surpass Moore's Law. Therefore, they are widely used in the new energy field (photovoltaics, energy storage, charging piles, electric vehicles, etc.).

[0003] Despite the advantages of wide-bandgap semiconductor devices, such as high breakdown voltage, low specific on-resistance, high switching speed, and low switching losses, the one-dimensional theoretical limit of unipolar devices (the inherent, mutually exclusive relationship between breakdown voltage and specific on-resistance) still restricts their further development. Breaking through this one-dimensional theoretical limit and further alleviating the constraint between specific on-resistance and breakdown voltage in wide-bandgap semiconductor devices presents a significant challenge for wide-bandgap semiconductor power devices. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a semiconductor device structure and its fabrication method to further alleviate the constraint relationship between specific on-resistance and breakdown voltage in wide-bandgap semiconductor devices.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] In a first aspect, this application provides a semiconductor device structure, including:

[0007] Substrate;

[0008] A first epitaxial layer located on one side of the substrate, at least a portion of the first epitaxial layer facing away from the substrate is an electric field modulation region, the electric field modulation region including N-type pillar regions and P-type pillar regions arranged adjacent to each other along a first direction, the first direction being parallel to the plane of the substrate;

[0009] A second epitaxial layer is located on the side of the electric field modulation region away from the substrate. The second epitaxial layer includes a switching functional region and a first P-type connection region located on opposite sides of the switching functional region along the first direction. The switching functional region includes an N-type current diffusion region, a P-type channel region and an N-type source region stacked along the direction away from the substrate. The N-type current diffusion region is connected to the N-type pillar region.

[0010] The middle region of the switching function area on the side away from the electric field modulation area has a gate trench that extends into part of the N-type current diffusion region, and a gate structure is provided in the gate trench.

[0011] The source electrode is located on the side of the second epitaxial layer opposite to the substrate, and the drain electrode is located on the side of the substrate opposite to the first epitaxial layer. An interlayer dielectric layer is provided between the source electrode and the gate structure.

[0012] The P-type channel region is electrically connected to the source electrode through the first P-type connection region, and the P-type pillar region is electrically connected to the source electrode through at least a portion of the first P-type connection region.

[0013] Optionally, the P-type pillar region includes m layers of P-type sub-pillar regions stacked in a direction away from the substrate, where 2≤m≤4.

[0014] Optionally, in a direction perpendicular to the plane of the substrate, at least a portion of the P-type pillar region overlaps with the first P-type connection region.

[0015] Optionally, the doping concentration of the first P-type connection region is greater than the doping concentration of the P-type channel region;

[0016] The first P-type connection region has an auxiliary trench on the side facing away from the substrate;

[0017] The source electrode fills the auxiliary trench; or, the auxiliary trench is filled with an auxiliary source electrode, and the auxiliary source electrode is electrically connected to the source electrode.

[0018] Optionally, the first epitaxial layer includes the electric field modulation region and an N-type breakdown voltage region located between the electric field modulation region and the substrate, wherein the N-type breakdown voltage region and the N-type pillar region are connected.

[0019] Optionally, the semiconductor device structure further includes:

[0020] The P-type electric field shielding region located between the gate structure and a portion of the N-type pillar region overlaps at least partially with the gate structure in a direction perpendicular to the plane of the substrate.

[0021] The P-type electric field shielding area is electrically connected to the first P-type connection area or the P-type column area through the second P-type connection area.

[0022] Optionally, the P-type electric field shielding region and the second P-type connection region are located within the N-type column region;

[0023] Alternatively, the P-type electric field shielding region and the second P-type connection region are located within the N-type current diffusion region.

[0024] Optionally, in a direction perpendicular to the plane of the substrate, the P-type electric field shielding region is positioned directly opposite the gate structure;

[0025] Alternatively, in a direction perpendicular to the plane of the substrate, the P-type electric field shielding region does not overlap with the gate structure at least partially.

[0026] Optionally, the P-type electric field shielding region includes at least two P-type sub-electric field shielding regions spaced apart along a second direction, the second direction being parallel to the plane of the substrate and intersecting with the first direction;

[0027] Each of the P-type sub-electric field shielding regions is electrically connected to the first P-type connection region or the P-type column region through at least one second P-type connection region.

[0028] Secondly, this application provides a method for fabricating a semiconductor device structure, comprising:

[0029] Provide substrate;

[0030] A first epitaxial layer, initially of type N, is formed on one side of the substrate;

[0031] The first epitaxial layer, initially N-type, is processed such that at least a portion of the first epitaxial layer on the side away from the substrate forms an electric field modulation region, the electric field modulation region including N-type pillar regions and P-type pillar regions arranged adjacent to each other along a first direction, the first direction being parallel to the plane of the substrate.

[0032] A second epitaxial layer, initially of type N, is formed on the side of the electric field modulation region away from the substrate.

[0033] The second epitaxial layer, initially N-type, is sequentially implanted with P-type ions and N-type ions to form an N-type current diffusion region, a P-type channel region, and an N-type source region stacked in a direction away from the substrate.

[0034] A gate trench is formed by etching the middle region of the second epitaxial layer on the side away from the substrate, and the second epitaxial layer on both sides of the gate trench opposite to each other along the first direction is processed to form a first P-type connection region. The N-type source region, the P-type channel region and the N-type current diffusion region between the gate trench and the first P-type connection region are retained. The part between the two first P-type connection regions is a switching function region.

[0035] A gate structure is formed in the gate trench, and an interlayer dielectric layer is formed on the side of the gate structure facing away from the substrate.

[0036] A source is formed on the side of the second epitaxial layer away from the substrate, an interlayer dielectric layer is provided between the source and the gate structure, and a drain is formed on the side of the substrate away from the first epitaxial layer.

[0037] The N-type current diffusion region is connected to the N-type pillar region, the P-type channel region is electrically connected to the source through the first P-type connection region, and the P-type pillar region is electrically connected to the source through at least a portion of the first P-type connection region.

[0038] Optionally, processing the first epitaxial layer, which is initially of type N, such that at least a portion of the first epitaxial layer on the side facing away from the substrate forms an electric field modulation region includes:

[0039] The first epitaxial layer, initially N-type, is etched to form a first trench, and then the P-type pillar region is epitaxially formed inside and outside the first trench. The portion of the first epitaxial layer of the N-type adjacent to the P-type pillar region along the first direction constitutes the N-type pillar region.

[0040] Alternatively, m ion implantations are performed on the portion of the first epitaxial layer initially N-type to which the P-type pillar region is pre-formed, where 2≤m≤4, to form m layers of P-type sub-pillar regions stacked along the direction away from the substrate. The m layers of P-type sub-pillar regions constitute the P-type pillar region, and the portion of the first epitaxial layer of the N-type adjacent to the P-type pillar region along the first direction constitutes the N-type pillar region.

[0041] Optionally, processing the second epitaxial layer on both sides of the gate trench opposite each other along the first direction to form a first P-type connection region includes:

[0042] P-type ion implantation is performed on the second epitaxial layer on both sides of the gate trench opposite to each other along the first direction to directly form the first P-type connection region. The doping concentration of the first P-type connection region is greater than the doping concentration of the P-type channel region.

[0043] Alternatively, the second epitaxial layer on both sides of the gate trench along the first direction can be etched to form an auxiliary trench.

[0044] Then, P-type ion implantation is performed on the bottom and sidewalls of the auxiliary trench to form the first P-type connection region. The doping concentration of the first P-type connection region is greater than the doping concentration of the P-type channel region.

[0045] Subsequently, during the formation of the source electrode, the source electrode fills the auxiliary trench; or, the method for fabricating the semiconductor device structure further includes:

[0046] An auxiliary source electrode is filled in the auxiliary trench so that the auxiliary source electrode is electrically connected to the source electrode after the source electrode is formed.

[0047] Optionally, after forming the electric field modulation region and before forming the second epitaxial layer, the method for fabricating the semiconductor device structure further includes:

[0048] P-type ion implantation is performed on a portion of the N-type column region to form a P-type electric field shielding region and a second P-type connection region;

[0049] Alternatively, after forming the gate trench and before forming the gate structure within the gate trench, the method for fabricating the semiconductor device structure further includes:

[0050] Ion implantation is performed on the N-type current diffusion region to form a P-type electric field shielding region and a second P-type connection region;

[0051] In the direction perpendicular to the plane of the substrate, the P-type electric field shielding region at least partially overlaps with the gate structure, and the P-type electric field shielding region is electrically connected to the first P-type connection region or the P-type pillar region through the second P-type connection region.

[0052] Compared with existing technologies, the above technical solution has the following advantages:

[0053] The semiconductor device structure provided in this application embodiment uses a two-step epitaxial growth method. First, a first epitaxial layer is formed on one side of the substrate. A P-type pillar region is formed within this relatively thin, initially N-type first epitaxial layer. At least a portion of the first epitaxial layer facing away from the substrate forms an electric field modulation region. This electric field modulation region includes adjacent N-type and P-type pillar regions arranged along a first direction, thereby introducing a superjunction structure. The first direction is parallel to the plane of the substrate. Then, a second epitaxial layer is formed on the side of the electric field modulation region facing away from the substrate. A switching functional region and a region located along the first direction within the switching functional region are fabricated using this second epitaxial layer. The first P-type connection regions on opposite sides, the switching functional region includes an N-type current diffusion region, a P-type channel region, and an N-type source region stacked along the direction away from the substrate, the N-type current diffusion region being connected to the N-type pillar region; in the formed semiconductor device structure, the middle region of the switching functional region on the side away from the electric field modulation region has a gate trench extending into part of the N-type current diffusion region, and a gate structure is disposed in the gate trench; a source is disposed on the side of the second epitaxial layer away from the substrate, and an interlayer dielectric layer is disposed between the source and the gate structure; a drain is disposed on the side of the substrate away from the first epitaxial layer; and the P-type channel region is connected to the source through the first P-type connection region. The P-type pillar region is electrically connected to the source through at least a portion of the first P-type connection region. Thus, when the device is turned on, electrons can start from the source, pass through the N-type source region, the N-type channel of the P-type channel region, the N-type current diffusion region, the N-type pillar region, and the substrate, finally reaching the drain, forming a reverse current from the drain to the source. When the device is turned off, almost all the high voltage at the drain is applied to the electric field modulation region. Because the depletion region of the reverse PN junction formed by adjacent N-type and P-type pillar regions in the electric field modulation region introduces a transverse electric field, the electric field intensity in the electric field modulation region can be approximately rectangularly distributed. Therefore, for the same drift region thickness... The electric field modulation region with the superjunction structure in this application can withstand higher voltages, thereby improving the breakdown voltage and reliability of the device; or, under the same breakdown voltage requirements, this application can use an N-type drift region with a higher doping concentration (corresponding to an N-type pillar region), thereby reducing the specific on-resistance of the device and improving the high-current capability of the device while maintaining a high breakdown voltage; in summary, this application overcomes the various difficulties in forming a P-type pillar region and introducing a superjunction structure in a wide bandgap semiconductor device, and thus greatly alleviates the constraint relationship between the specific on-resistance and breakdown voltage of a wide bandgap semiconductor device by utilizing the superjunction structure. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device structure provided in an embodiment of this application;

[0056] Figure 2 The diagram shows the structure and corresponding electric field intensity distribution of the electric field modulation region, which includes N-type and P-type column regions arranged adjacent to each other along the first direction, and the traditional single N-type drift region.

[0057] Figure 3 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0058] Figure 4 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0059] Figure 5 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0060] Figure 6 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0061] Figure 7 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0062] Figure 8 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0063] Figure 9 This is a schematic diagram showing the structure and corresponding electric field intensity distribution of two semiconductor devices provided in the embodiments of this application, one with a P-type electric field shielding region and a second P-type connection region and the other without a P-type electric field shielding region and a second P-type connection region.

[0064] Figure 10 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0065] Figure 11 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0066] Figure 12 This is a cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application;

[0067] Figure 13 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application;

[0068] Figure 14A schematic diagram of a process step in the method for fabricating a semiconductor device structure provided in the embodiments of this application;

[0069] Figure 15 This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0070] Figures 16a-16b This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0071] Figures 17a-17c This is a schematic diagram of a structural step corresponding to another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0072] Figure 18 This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0073] Figure 19 This is a schematic diagram of a structural step corresponding to another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0074] Figure 20 This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0075] Figure 21 This is a schematic diagram of a structural step corresponding to another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0076] Figure 22 This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0077] Figure 23 This is a schematic diagram of another process step in the method for fabricating the semiconductor device structure provided in the embodiments of this application.

[0078] Explanation of reference numerals in the attached figures:

[0079] Substrate 10; First epitaxial layer 110; Electric field modulation region 20; First direction X; N-type pillar region 21; P-type pillar region 22; Second epitaxial layer 120; Switching function region 30; First P-type connection region 40; N-type current diffusion region 31; P-type channel region 32; N-type source region 33; Gate trench T1; Gate structure 50; Gate G; Gate dielectric layer 51; Source S; Interlayer dielectric layer 60; Drain D; Vertical direction Z; First trench W1; P-type sub-pillar region 221; N-type withstand voltage region 111; P-type electric field shielding region 70; Second P-type connection region 80; P-type sub-electric field shielding region 71; Second direction Y; Auxiliary trench W2; Auxiliary source S1; N-type drift region 201. Detailed Implementation

[0080] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0081] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0082] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the accompanying drawings illustrating the device structure may be partially enlarged, not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0083] As described in the background section, breaking through the one-dimensional theoretical limit of unipolar devices and further alleviating the constraint relationship between specific on-resistance and breakdown voltage of wide bandgap semiconductor devices is a huge challenge for wide bandgap semiconductor power devices.

[0084] In view of this, embodiments of this application provide a semiconductor device structure. Figure 1 A cross-sectional schematic diagram of a semiconductor device structure provided in an embodiment of this application is shown, as follows: Figure 1As shown, the semiconductor device structure includes a substrate 10 and a first epitaxial layer 110 located on one side of the substrate 10. At least a portion of the first epitaxial layer 110 facing away from the substrate 10 is an electric field modulation region 20. The electric field modulation region 20 includes N-type pillar regions 21 and P-type pillar regions 22 arranged adjacent to each other along a first direction X, which is parallel to the plane of the substrate. The side of the first epitaxial layer 110 facing away from the substrate 10 has a second epitaxial layer 120. The second epitaxial layer 120 includes a switching functional region 30 and first P-type connection regions 40 located on opposite sides of the switching functional region 30 along the first direction X. The switching functional region 30 includes N-type current diffusers stacked along the direction facing away from the substrate 10. The system includes a diffused region 31, a P-type channel region 32, and an N-type source region 33. The N-type source region can be an N+ source region, meaning it can be heavily doped with N-type. The switching functional region 30 has a gate trench T1 extending into a portion of the N-type current diffusion region 31 in the middle region on the side away from the electric field modulation region 20. A gate structure 50 is disposed in the gate trench T1. Specifically, the gate structure 50 can include a gate G and a gate dielectric layer 51 located between the gate G and the switching functional region 30. A source S is disposed on the side of the second epitaxial layer 120 away from the substrate 10, and an interlayer dielectric layer 60 is disposed between the source S and the gate structure 50. A drain D is disposed on the side of the substrate 10 away from the first epitaxial layer 110.

[0085] In specific operation, when the device needs to be turned on, a positive voltage higher than the device threshold voltage is applied to the gate G, and a positive voltage is applied to the drain D relative to the source S. The source S is grounded, and an inversion layer, i.e. an N-type channel, is formed on the surface of the P-type channel region 32 near the gate structure 50. This N-type channel connects the N-type source region 33 and the N-type current diffusion region 31. Thus, electrons can start from the source S, enter the N-type source region 33, enter the N-type current diffusion region 31 through the N-type channel, then enter the electric field modulation region 20, pass through the substrate 10, and finally reach the drain D, forming a reverse current from the drain D to the source S. That is, the current path starts from the drain D (high potential), passes through the N-type pillar region 21, the N-type current diffusion region 31, the P-type channel region 32, and the N-type source region 33 to reach the source S.

[0086] When the device needs to block high voltage, zero or negative voltage is applied to the gate G, a very high positive voltage is applied to the drain D, and the source S remains grounded. Because zero or negative voltage is applied to the gate G, the inversion layer of the P-type channel region 32 near the surface of the gate structure 50 disappears, the N-type channel is closed, the electron path between the N-type source region 33 and the N-type current diffusion region 31 is cut off, and almost all of the high voltage of the drain D is applied to the electric field modulation region 20.

[0087] In this embodiment, the electric field modulation region 20 is not a traditional single N-type drift region, but includes N-type pillar regions 21 and P-type pillar regions 22 arranged adjacent to each other along the first direction X. That is, in the electric field modulation region 20, along the first direction X, the adjacent side of the N-type pillar region 21 is the P-type pillar region 22, and the adjacent side of the P-type pillar region 22 is the N-type pillar region. Thus, the N-type pillar regions 21 and P-type pillar regions 22 arranged adjacent to each other along the first direction X in the electric field modulation region 20 constitute a superjunction structure. The N-type pillar regions 21 and P-type pillar regions 22 adjacent to each other along the first direction X satisfy the charge balance condition, that is, along the first direction X, the total amount of ionized donors in the N-type pillar region 21 per unit length is equal to the total amount of ionized acceptors in the P-type pillar region 22 per unit length.

[0088] To better understand, Figure 2 The diagram illustrates the structure and corresponding electric field intensity distribution of an electric field modulation region 20 comprising N-type column regions 21 and P-type column regions 22 arranged adjacently along the first direction X, and a conventional single N-type drift region 201. Figure 2 As shown, the electric field intensity of a conventional single N-type drift region 201 is triangularly distributed along the vertical direction Z. However, in the electric field modulation region 20 of this embodiment, a transverse electric field is generated by the ionized donors in the N-type pillar region 21 and the ionized acceptors in the adjacent P-type pillar region 22. In other words, the depletion region of the reverse PN junction formed by the adjacent N-type pillar region 21 and P-type pillar region 22 introduces a transverse electric field, thereby modulating the electric field intensity distribution of the electric field modulation region 20, making the electric field intensity of the electric field modulation region 20 approximately rectangular along the vertical direction Z. This means that, with the same drift region thickness, the electric field modulation region 20 of this application embodiment can withstand a higher voltage, thereby improving the breakdown voltage and reliability of the device; or, under the same withstand voltage requirements, this application embodiment can use an N-type drift region with a higher doping concentration (corresponding to the N-type pillar region 21), thereby reducing the specific on-resistance of the device and improving the high current capability of the device while maintaining a high breakdown voltage; thereby further alleviating the constraint relationship between the specific on-resistance and breakdown voltage of wide bandgap semiconductor devices.

[0089] In this embodiment, the P-type channel region 32 is electrically connected to the source S through the first P-type connection region 40. Specifically, the side of the P-type channel region 32 away from the gate structure 50 is electrically connected to the source S through the first P-type connection region 40. Since the source S is grounded, the side of the P-type channel region 32 away from the gate structure 50 is clamped to ground potential by the source S. In this way, the NPN bipolar transistor composed of the N-type source region 33, the P-type channel region 32 and the N-type current diffusion region 31 can be prevented from turning on, thus avoiding the "latch-up effect" of the device.

[0090] In this embodiment, the main function of the N-type current diffusion region 31 is to rapidly diffuse the relatively concentrated electron flow injected from the channel in the horizontal direction, so that the electron flow can then reach the drain D through the N-type pillar region 21. Therefore, the N-type current diffusion region 31 is connected to the N-type pillar region 21, that is, the N-type pillar region 21 in the electric field modulation region 20 needs to be set to be connected to the N-type current diffusion region 31.

[0091] In this embodiment, the P-type pillar region 22 in the electric field modulation region 20 is electrically connected to the source S through at least a portion of the first P-type connection region 40. Since the source S is grounded, the P-type pillar region 22 in the electric field modulation region 20 is also clamped to ground potential by the source S. In addition, the drain D (high potential) is electrically connected to the N-type pillar region 21. Therefore, a completely reverse-biased PN junction from the N-type pillar region 21 to the adjacent P-type pillar region 22 can be formed in the electric field modulation region 20. Furthermore, the P-type pillar region 22 can be synchronously and completely depleted from the side away from the substrate 10, so that the adjacent N-type pillar region 21 and P-type pillar region 22 along the first direction X satisfy the charge balance condition, thereby forming a rectangular electric field distribution in the electric field modulation region 20.

[0092] If the P-type pillar region 22 in the electric field modulation region 20 is not grounded through the source S, then on the one hand, during switching transients, the potential of the floating P-type pillar region 22 will lag, and the minority carriers (holes) in the P-type pillar region 22 will not be replenished in time, failing to respond promptly to changes in the drain voltage. This will lead to the existence of extended depletion regions in certain local areas of the N-type pillar region 21, severely narrowing the current conduction path and increasing device losses. On the other hand, the potential of the floating P-type pillar region 22 may float to a very high value (e.g., close to the drain voltage). In this case, the potential difference between the P-type pillar region 22 and the N-type pillar region 21 may become very small, and the depletion regions of both cannot fully expand, failing to form an effective transverse electric field, and the device's breakdown voltage may drop sharply. Therefore, the P-type pillar region 22 in the electric field modulation region 20 is electrically connected to the source S through at least a portion of the first P-type connection region 40, ensuring good switching characteristics of the device and the modulation effect of the superjunction structure on the electric field.

[0093] However, due to the characteristics of wide-bandgap semiconductor materials, it is almost impossible to achieve the traditional fabrication method of first epitaxially growing an N-type epitaxial layer from the substrate 10 to the N-type source region 33, and then fabricating a deeper P-type pillar region within the N-type epitaxial layer to form a superjunction structure. For example, for silicon carbide (SiC) and gallium nitride (GaN) materials, the diffusion coefficient of impurity atoms in their lattice is extremely low at conventional process temperatures, almost not diffusing. This means that it is impossible to form a deep P-type pillar region through mature deep junction thermal diffusion processes (i.e., ion implantation followed by high-temperature annealing diffusion). The only option is to rely on the depth of the ion implantation itself, but the ion implantation depth is energy-limited and introduces lattice damage. Furthermore, for materials such as gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN), achieving P-type or N-type doping through ion implantation is quite difficult.

[0094] Based on this, refer to Figure 1 As shown, the semiconductor device structure provided in this application embodiment no longer first grows an N-type epitaxial layer from the substrate 10 to the N-type source region 33. Instead, it first grows a first epitaxial layer 110 (initially N-type) on one side of the substrate 10. The first epitaxial layer 110 is processed so that at least a portion of the first epitaxial layer 110 facing away from the substrate 10 forms an electric field modulation region 20. The electric field modulation region 20 includes N-type pillar regions 21 and P-type pillar regions 22 arranged alternately along the first direction X. Then, a second epitaxial layer 120 (initially N-type) is formed on the side of the electric field modulation region 20 facing away from the substrate 10. The second epitaxial layer 120 is processed to form a switching functional region 30 and a first P-type connection region 40. In this way, a superjunction structure can be formed by forming a P-type pillar region in the relatively thin, initially N-type first epitaxial layer 110. This greatly reduces the difficulty of forming a P-type pillar region in a wide bandgap semiconductor layer and improves the feasibility of introducing a superjunction structure in a wide bandgap semiconductor device.

[0095] One method for forming the P-type pillar region 21 in the relatively thin, initially N-type first epitaxial layer 110 is trench etching followed by epitaxial filling, as described in the reference. Figure 1 As shown, the first epitaxial layer 110, which is initially N-type, is etched to form a first trench W1. Then, a P-type pillar region 22 is formed inside and outside the first trench W1. The portion of the N-type first epitaxial layer 110 adjacent to the P-type pillar region 22 along the first direction X constitutes the N-type pillar region 21, thereby forming the N-type pillar region 21 and the P-type pillar region 22 arranged adjacent to each other along the first direction X.

[0096] Another method is multiple ion implantation, see reference. Figure 3 As shown, Figure 3This illustration shows a cross-sectional view of another semiconductor device structure provided in an embodiment of this application. The portion of the first epitaxial layer 110 initially being N-type, pre-formed with P-type pillar regions, undergoes m ion implantations (2≤m≤4) to form m layers of P-type sub-pillar regions 221 stacked along the direction away from the substrate 10. These m layers of P-type sub-pillar regions 221 constitute P-type pillar regions 22. The portion of the N-type first epitaxial layer 110 adjacent to the P-type pillar regions 22 along the first direction X constitutes an N-type pillar region 21, thereby forming N-type pillar regions 21 and P-type pillar regions 22 arranged adjacently along the first direction X. It is understood that in this semiconductor device structure, the P-type pillar region 22 includes m layers of P-type sub-pillar regions 221 stacked along the direction away from the substrate 10. Since the thickness of the first epitaxial layer 110 is relatively thin, the number of ion implantations required to form the P-type pillar region 22 is relatively small (2≤m≤4).

[0097] Optionally, high-energy ion implantation can be performed first to form a deep P-type sub-pillar region 221. Then, the ion implantation energy can be successively reduced to form P-type sub-pillar regions 221 with decreasing implantation depths, ultimately resulting in a P-type pillar region 22. Thus, in the P-type pillar region 22, the thickness of each P-type sub-pillar region 221 can decrease sequentially along the direction away from the substrate 10. However, this application does not limit the energy and dose of each ion implantation, which can be determined according to the actual situation.

[0098] It should be noted that, according to the traditional fabrication method, after first growing an N-type epitaxial layer from the substrate 10 to the N-type source region 33, even if trench etching and epitaxial filling are used to form the P-type pillar region (i.e., first etching to form a deep trench, and then epitaxially forming the P-type pillar region inside and outside the deep trench), the newly grown P-type semiconductor material is prone to voids when epitaxially filling the high aspect ratio trench etched. Even if trench etching and multiple epitaxial layers and ion implantation are used to form the P-type pillar region, deep doping cannot be formed through thermal diffusion in wide bandgap semiconductor materials. Therefore, the P-type doped pillar structure can only be formed by multiple thin epitaxial layers and P-type ion implantation. This also has the problems of high cost of multiple epitaxial layers and difficulty in aligning multiple ion implantations.

[0099] The embodiments of this application ingeniously combine two-step epitaxial growth with trench etching plus epitaxial filling or multiple ion implantation to form P-type pillar regions. This not only enables the formation of P-type pillar regions in wide-bandgap semiconductor devices, thus introducing superjunction structures, but also, since the thickness of the first epitaxial layer formed in the first step is relatively thin, the aspect ratio of the first trench etched when forming P-type pillar regions using trench etching plus epitaxial filling is relatively small, making it less prone to voids. When forming P-type pillar regions using multiple ion implantation, the number of ion implantations is relatively small, resulting in lower costs and better alignment.

[0100] Therefore, the semiconductor device structure provided in this application embodiment, through a two-step epitaxial growth method, first forms a first epitaxial layer on one side of the substrate, to form a P-type pillar region in the relatively thin, initially N-type first epitaxial layer, such that at least a portion of the first epitaxial layer away from the substrate forms an electric field modulation region, which includes N-type pillar regions and P-type pillar regions arranged adjacently along a first direction, thereby introducing a superjunction structure, the first direction being parallel to the plane of the substrate; then, a second epitaxial layer is formed on the side of the electric field modulation region away from the substrate, and a switching functional region and a region located along the first direction of the switching functional region are fabricated using the second epitaxial layer. The first P-type connection regions on opposite sides of the switching functional region include an N-type current diffusion region, a P-type channel region, and an N-type source region stacked along the direction away from the substrate. The N-type current diffusion region is connected to the N-type pillar region. In the formed semiconductor device structure, the middle region of the switching functional region away from the electric field modulation region has a gate trench that extends into part of the N-type current diffusion region, and a gate structure is disposed in the gate trench. A source is disposed on the side of the second epitaxial layer away from the substrate, and an interlayer dielectric layer is disposed between the source and the gate structure. A drain is disposed on the side of the substrate away from the first epitaxial layer. Furthermore, the P-type channel region passes through the first P-type connection region. The P-type pillar region is electrically connected to the source via at least a portion of the first P-type connection region. Thus, when the device is turned on, electrons can travel from the source, through the N-type source region, the N-type channel of the P-type channel region, the N-type current diffusion region, the N-type pillar region, and the substrate, ultimately reaching the drain, forming a reverse current from the drain to the source. When the device is turned off, almost all the high voltage at the drain is applied to the electric field modulation region. Because the depletion region of the reverse PN junction formed by adjacent N-type and P-type pillar regions in the electric field modulation region introduces a transverse electric field, the electric field intensity in the electric field modulation region can be approximately rectangularly distributed. Therefore, with the same drift region thickness... In this application, the electric field modulation region with a superjunction structure can withstand higher voltages, thereby improving the breakdown voltage and reliability of the device. Alternatively, under the same breakdown voltage requirements, this application can use an N-type drift region (corresponding to an N-type pillar region) with a higher doping concentration, thereby reducing the specific on-resistance of the device and improving the high-current capability of the device while maintaining a high breakdown voltage. In summary, this application overcomes the various difficulties in forming a P-type pillar region and introducing a superjunction structure in a wide bandgap semiconductor device, and thus greatly alleviates the constraint relationship between the specific on-resistance and breakdown voltage of the wide bandgap semiconductor device by utilizing the superjunction structure.

[0101] As previously known, the P-type pillar region 22 is electrically connected to the source S through at least a portion of the first P-type connection region 40. To facilitate the electrical connection of the P-type pillar region 22 to the source S through at least a portion of the first P-type connection region 40, optionally, as follows: Figure 1 and Figure 3As shown, at least a portion of the P-type pillar region 22 can be provided in a direction perpendicular to the plane of the substrate 10, overlapping with the first P-type connection region 40, so that at least a portion of the P-type pillar region 22 is in contact with the first P-type connection region 40, and then electrically connected to the source S through the first P-type connection region 40.

[0102] Among them, optional, such as Figure 1 and Figure 3 As shown, the width of the P-type column region 22 along the first direction X can be equal to the width of the first P-type connecting region 40 along the first direction X. Alternatively, as... Figure 4 As shown, Figure 4 A cross-sectional schematic diagram of another semiconductor device structure provided in this application embodiment is shown. It can be seen that the width of the P-type pillar region 22 along the first direction X may not be equal to the width of the first P-type connection region 40 along the first direction X; for example, the width of the P-type pillar region 22 along the first direction X is less than the width of the first P-type connection region 40 along the first direction X; of course, the width of the P-type pillar region 22 along the first direction X may also be greater than the width of the first P-type connection region 40 along the first direction X, as long as the P-type pillar region 22 and the N-type pillar region 21 satisfy the charge balance condition.

[0103] Furthermore, this application does not limit the number of P-type pillar regions 22 in the electric field modulation region 20, as long as the P-type pillar regions 22 are electrically connected to the source S through at least a portion of the first P-type connection region 40, and the P-type pillar regions 22 and N-type pillar regions 21 satisfy the charge balance condition. Optionally, such as... Figure 1 , Figure 3 and Figure 4 As shown, the number of P-type pillar regions 22 and the number of first P-type connection regions 40 are equal, and they are set one-to-one. At this time, the first P-type connection region 40 and the N-type current diffusion region 31 can be regarded as extensions of the adjacent P-type pillar regions 22 and N-type pillar regions 21 in the electric field modulation region 20. That is, the first P-type connection region 40 and the N-type current diffusion region 31 can also play a certain electric field modulation role, which can further alleviate the constraint relationship between the specific on-resistance and breakdown voltage of the wide bandgap semiconductor device.

[0104] Other options, such as Figure 5 As shown, Figure 5 A cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application is shown. It can be seen that the number of P-type pillar regions 22 and the number of first P-type connection regions 40 may not be equal. For example, in a cell structure of a semiconductor device, there are two first P-type connection regions 40 and one P-type pillar region 22. The one P-type pillar region 22 is electrically connected to the source S through a corresponding first P-type connection region 40. Alternatively, in a cell structure of a semiconductor device, there are two first P-type connection regions 40 and three P-type pillar regions 22. These three P-type pillar regions 22 are electrically connected to the source S through the first P-type connection regions 40.

[0105] For the first P-type connection region 40, in order to form a good electrical connection with the source S, optionally, refer to... Figure 1 , Figures 3-5 As shown, the doping concentration of the first P-type connection region 40 is greater than that of the P-type channel region 32. In other words, the first P-type connection region 40 can be heavily doped with P-type (i.e., P+ doped), which makes the contact resistance between the first P-type connection region 40 and the source S smaller, thereby forming a good electrical connection with the source S.

[0106] Based on the premise that the first P-type connection region 40 is heavily P-type doped, optionally, such as Figure 1 , Figures 3-5 As shown, the first P-type connection region 40 on the side facing away from the substrate 10 may have an auxiliary trench W2, and the source S fills the auxiliary trench W2, forming a good ohmic contact with the first P-type connection region 40. Alternatively, as... Figure 6 As shown, Figure 6 A cross-sectional schematic diagram of another semiconductor device structure provided in the embodiments of this application is shown. It can be seen that the first P-type connection region 40 also has an auxiliary trench W2 on the side away from the substrate 10. However, the difference is that the auxiliary trench W2 is filled with an auxiliary source S1, and the auxiliary source S1 is electrically connected to the source S. Optionally, the material of the auxiliary source S1 can be polycrystalline silicon.

[0107] Figure 7 A cross-sectional schematic diagram of another semiconductor device structure provided in an embodiment of this application is shown, as follows: Figure 7 As shown, the first P-type connection region 40 may not have an auxiliary trench W2. In this case, the first P-type heavily doped connection region 40 can be directly formed by P-type high-energy ion implantation or channel implantation of the initially N-type second epitaxial layer 120.

[0108] Understandably, directly forming the heavily p-doped first p-type connection region 40 by p-type high-energy ion implantation or channel implantation into the initially n-type second epitaxial layer 120 requires significant implantation energy and depth, resulting in relatively high costs. However, if the first p-type connection region 40 has an auxiliary trench W2, the auxiliary trench W2 can be etched into the initially n-type second epitaxial layer 120 first, and then p-type ion implantation can be performed on the bottom and sidewall portions of the auxiliary trench W2 to form the first p-type connection region 40 with the auxiliary trench W2. This reduces the energy and depth of p-type ion implantation, simplifies the process, and saves costs.

[0109] As is known from the foregoing, at least a portion of the first epitaxial layer 110 on the side opposite to the substrate 10 forms an electric field modulation region 20, optionally, such as Figure 1 , Figures 3-7As shown, the first epitaxial layer 110 is integrally formed as an electric field modulation region 20, including N-type pillar regions and P-type pillar regions arranged adjacent to each other along the first direction. Alternatively, as... Figure 8 As shown, Figure 8 A cross-sectional schematic diagram of another semiconductor device structure provided in this application embodiment is shown. It can be seen that a portion of the first epitaxial layer 110 on the side away from the substrate 10 can form an electric field modulation region 20. In this case, the first epitaxial layer 110 includes the electric field modulation region 20 and an N-type breakdown voltage region 111 located between the electric field modulation region 20 and the substrate 10. The N-type breakdown voltage region 111 is connected to the N-type pillar region 110. The electric field modulation region 20 is a semi-superjunction structure, which can further improve the blocking capability of the device.

[0110] Based on any of the above embodiments, considering that although the breakdown voltage of the device is significantly improved due to the introduction of the superjunction structure, when the device is turned off and subjected to high voltage, the high voltage electric field of the drain may be severely concentrated through the bottom corner of the gate trench T1 (where the geometry changes abruptly), forming a very high local electric field peak. Since the gate dielectric layer 51 is typically a silicon dioxide layer, it is possible that the device may fail before reaching the theoretical breakdown voltage because the gate dielectric layer 51 cannot withstand the high electric field. Therefore, alternatively, in some embodiments of this application, such as... Figure 1 , Figures 3-8 As shown, the semiconductor device structure also includes a P-type electric field shielding region 70 located between the gate structure 50 and a portion of the N-type pillar region 21. In a direction perpendicular to the plane of the substrate 10, the P-type electric field shielding region 70 at least partially overlaps with the gate structure 50. Furthermore, the P-type electric field shielding region 70 is electrically connected to the first P-type connection region 40 or the P-type pillar region 22 through a second P-type connection region 80, and then electrically connected to the source S. With this configuration, the P-type electric field shielding region 70 located between the gate structure 50 and the portion of the N-type pillar region 21 is clamped at ground potential by being electrically connected to the source S, thereby playing a role in shielding the electric field between the gate structure 50 and the portion of the N-type pillar region 21, reducing the electric field strength around the gate oxide layer, and improving the reliability of the device.

[0111] To better understand, Figure 9 This application provides an embodiment of a semiconductor device with and without a P-type electric field shielding region and a second P-type connection region, and a schematic diagram showing the structure and corresponding electric field intensity distribution. Figure 9 As shown, after setting a P-type electric field shielding region 70 between the gate structure 50 and part of the N-type pillar region 21, the electric field strength of the N-type current diffusion region 31 is significantly reduced, that is, the electric field strength at the bottom of the gate oxide layer 51 is significantly reduced, thereby improving the reliability of the device.

[0112] The position of the P-type electric field shielding region 70 in the vertical Z direction can be optionally set as follows: Figure 1 , Figures 3-8 As shown, the P-type electric field shielding region 70 and the second P-type connection region 80 can be located within the N-type pillar region 21. Specifically, ion implantation can be performed within the N-type pillar region 21 to form the P-type electric field shielding region 70 and the second P-type connection region 80. In this case, although a portion of the thickness of the N-type pillar region 21 will be sacrificed, slightly reducing the device's breakdown voltage, the overall performance of the device is still improved because the electric field strength around the gate oxide layer can be reduced, thereby improving the device's reliability.

[0113] Another option, such as Figure 10 As shown, Figure 10 A cross-sectional schematic diagram of another semiconductor device structure provided in this application embodiment is shown. It can be seen that the P-type electric field shielding region 70 and the second P-type connection region 80 can also be located within the N-type current diffusion region 31. This arrangement can reduce the impact of introducing the P-type electric field shielding region 70 on improving the blocking characteristics of the electric field modulation region 20. Furthermore, the P-type electric field shielding region 70 is closer to the bottom of the gate structure 50, which can further reduce the electric field strength around the gate oxide layer and improve the reliability of the device. Optionally, the P-type electric field shielding region 70 can be in direct contact with the bottom of the gate structure 50, which can further reduce the electric field strength around the gate oxide layer and improve the reliability of the device.

[0114] The location of the P-type electric field shielding region 70 in the first direction X can be optionally configured as follows: Figure 1 , Figures 3-8 , Figure 10 As shown, in the direction perpendicular to the plane of the substrate 10, the P-type electric field shielding region 70 can be directly opposite the gate structure 50, that is, the P-type electric field shielding region 70 is located directly below the gate structure 50.

[0115] Another option, such as Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 The cross-sectional schematic diagrams of two more semiconductor device structures provided in the embodiments of this application show that the P-type electric field shielding region 70 can also be offset relative to the gate structure 50 in the first direction X. Specifically, in the direction perpendicular to the plane of the substrate 10, the P-type electric field shielding region 70 and the gate structure 50 do not overlap at least partially. This arrangement allows for adjustment of the resistance of local areas in the cell structure of the device, thereby adjusting the current distribution across the entire power device and improving device reliability. For example, as... Figure 11As shown, if the P-type electric field shielding region 70 is offset to the left relative to the gate structure 50 in the first direction X, the current path between the P-type electric field shielding region 70 and the left-side P-type pillar region 22 will be narrowed, and the resistance of this part will increase; for example, as Figure 12 As shown, the P-type electric field shielding region 70 is offset to the right relative to the gate structure 50 in the first direction X. As a result, the current path between the P-type electric field shielding region 70 and the P-type pillar region 22 on the right side will become narrower, and the resistance of this part will increase.

[0116] Figure 13 A top view schematic diagram of a semiconductor device structure provided in an embodiment of this application is shown, as follows: Figure 13 As shown, optionally, the P-type electric field shielding region 70 may include at least two P-type sub-electric field shielding regions 71 spaced apart along a second direction Y. The second direction Y is parallel to the plane of the substrate 10 and intersects with the first direction X, for example, the second direction Y is perpendicular to the first direction X. Each P-type sub-electric field shielding region 71 is electrically connected to the first P-type connection region 40 or the P-type pillar region 22 through at least one second P-type connection region 80. With this configuration, firstly, the N-type pillar region 21 between adjacent P-type sub-electric field shielding regions 71 maintains its complete thickness, which can reduce the impact of introducing the P-type electric field shielding region 70 on improving the device blocking characteristics of the electric field modulation region 20; secondly, the electron flow can directly pass through a portion of the N-type pillar region 21 between adjacent P-type sub-electric field shielding regions 71, making the current distribution more uniform and reducing the impact on the device's on-resistance. It should be noted that... Figure 12 To demonstrate the spacing of the P-type sub-electric field shielding region 71 and the second P-type connection region 80 in the second direction Y, the switching function region 30 is omitted.

[0117] Accordingly, embodiments of this application also provide a method for fabricating a semiconductor device structure, the method comprising:

[0118] S1: As Figure 14 As shown, a substrate 10 is provided. The substrate 10 may be N-type doped.

[0119] S2: As Figure 15 As shown, a first epitaxial layer 110 initially of type N is formed on one side of the substrate 10.

[0120] S3: As Figures 16a-16b As shown, or as Figures 17a-17c As shown, the first epitaxial layer 110, which is initially N-type, is processed such that at least a portion of the first epitaxial layer 110 on the side away from the substrate 10 forms an electric field modulation region 20. The electric field modulation region 20 includes N-type pillar regions 21 and P-type pillar regions 22 arranged adjacent to each other along a first direction X, and the first direction X is parallel to the plane of the substrate.

[0121] Optionally, the electric field modulation region 20 can be formed by trench etching followed by epitaxial filling. Specifically, firstly... Figure 16a As shown, the first epitaxial layer 110, initially of type N, is etched to form the first trench W1, and then as shown... Figure 16b As shown, a P-type pillar region 22 is formed inside and outside the first trench W1. The portion of the first epitaxial layer 110 of the N-type adjacent to the P-type pillar region 22 along the first direction X constitutes the N-type pillar region 21, thereby forming the N-type pillar region 21 and the P-type pillar region 22 arranged adjacent to each other along the first direction X, forming an electric field modulation region 20 with a superjunction structure.

[0122] Alternatively, the electric field modulation region 20 can be formed using multiple ion implantations. Specifically, for example... Figures 17a-17c As shown, m ion implantations are performed on the portion of the pre-formed P-type pillar region in the initial N-type first epitaxial layer 110, where 2≤m≤4, to form m layers of P-type sub-pillar regions 221 stacked along the direction away from the substrate 10. The m layers of P-type sub-pillar regions 221 constitute P-type pillar regions 22. That is, the formed P-type pillar regions 22 include m layers of P-type sub-pillar regions 221 stacked along the direction away from the substrate 10. The portion of the N-type first epitaxial layer 110 adjacent to the P-type pillar regions 22 along the first direction X constitutes N-type pillar regions 21, thereby forming N-type pillar regions 21 and P-type pillar regions 22 arranged adjacently along the first direction X, forming an electric field modulation region 20 with a superjunction structure.

[0123] Optionally, high-energy ion implantation can be performed first to form a deep P-type sub-pillar region 221. Then, the ion implantation energy can be successively reduced to form P-type sub-pillar regions 221 with decreasing implantation depths, ultimately resulting in a P-type pillar region 22. Thus, in the P-type pillar region 22, the thickness of each P-type sub-pillar region 221 can decrease sequentially along the direction away from the substrate 10. However, this application does not limit the energy and dose of each ion implantation, which can be determined according to the actual situation.

[0124] It is understandable that, regardless of whether trench etching and epitaxial filling are used or multiple ion implantation are employed, if the depth of the formed P-type pillar region 22 penetrates the first epitaxial layer 110, then the first epitaxial layer 110 as a whole becomes the electric field modulation region 20. Figures 16a-16b As shown, and as Figures 17a-17c As shown; if the depth of the formed P-type pillar region 22 only penetrates a portion of the first epitaxial layer 110, then a portion of the first epitaxial layer 110 on the side facing away from the substrate 10 forms an electric field modulation region 20. At this time, the reference... Figure 8 As shown, the first epitaxial layer 110 includes an electric field modulation region 20 and an N-type breakdown voltage region 111 located between the electric field modulation region 20 and the substrate 10. The N-type breakdown voltage region 111 is connected to the N-type pillar region 110. The electric field modulation region 20 is a semi-superjunction structure.

[0125] After forming the electric field modulation region 20, optionally, if a P-type electric field shielding region 70 and a second P-type connection region 80 are to be formed within the N-type pillar region 21, the method may further include:

[0126] S4: As Figure 18 As shown, P-type ion implantation is performed on a portion of the N-type column region 21 to form a P-type electric field shielding region 70 and a second P-type connection region 80.

[0127] The P-type electric field shielding region 70 and the second P-type connection region 80 can be formed simultaneously in one P-type ion implantation or in stages, depending on the specific circumstances.

[0128] S5: As Figure 19 As shown, a second epitaxial layer 120 initially of type N is formed on the side of the electric field modulation region 20 away from the substrate 10.

[0129] S6: As Figure 20 As shown, the second epitaxial layer 120, which is initially N-type, is sequentially implanted with P-type ions and N-type ions to form an N-type current diffusion region 31, a P-type channel region 32 and an N-type source region 33 stacked in a direction away from the substrate 10.

[0130] It is understandable that an N-type source region can be an N+ source region, meaning that an N-type source region can be heavily doped with N-type.

[0131] S7: As Figure 21 and Figure 22 As shown, the middle region of the second epitaxial layer 120 away from the substrate 10 is etched to form a gate trench T1, and the second epitaxial layers 120 on both sides of the gate trench T1 opposite to each other along the first direction X are processed to form a first P-type connection region 40. The N-type source region 33, the P-type channel region 32 and the N-type current diffusion region 31 between the gate trench T1 and the first P-type connection region 40 are retained. The part between the two first P-type connection regions 40 is the switching function region 30.

[0132] Optionally, the second epitaxial layer 120 on both sides of the gate trench T1 opposite to each other along the first direction X is processed to form a first P-type connection region 40, including:

[0133] S71: As Figure 21 As shown, the second epitaxial layer 120 on both sides of the gate trench T1 along the first direction X is first etched to form the auxiliary trench W2.

[0134] S72: As Figure 22As shown, P-type ion implantation is then performed on the bottom and sidewalls of the auxiliary trench W2 to form the first P-type connection region 40. The doping concentration of the first P-type connection region 40 is greater than the doping concentration of the P-type channel region 32, that is, the first P-type connection region 40 can be heavily doped with P-type (i.e., P+ doped).

[0135] It is understandable that the gate trench T1 and the auxiliary trench W2 can be etched simultaneously or in stages, depending on the specific circumstances.

[0136] Another option is to refer to Figure 7 As shown, the first P-type connection region 40 may not have an auxiliary trench W2. In this case, the first P-type connection region 40 can be directly formed by P-type ion implantation on the second epitaxial layer 120 on both sides of the gate trench T1 along the first direction X. The doping concentration of the first P-type connection region 40 is greater than the doping concentration of the P-type channel region 32.

[0137] Understandably, performing P-type ion implantation on the second epitaxial layer 120 on both sides of the gate trench T1 along the first direction X to directly form the first P-type connection region 40 requires a large implantation energy and a deep implantation depth, resulting in relatively high costs. However, if the first P-type connection region 40 has an auxiliary trench W2, the auxiliary trench W2 can be etched first in the initially N-type second epitaxial layer 120, and then P-type ion implantation can be performed on the bottom and sidewall portions of the auxiliary trench W2 to form the first P-type connection region 40 with the auxiliary trench W2. This reduces the energy and depth of P-type ion implantation, simplifies the process, and saves costs.

[0138] Optionally, based on the auxiliary trench W2 in the first P-type connection region 40, the source S can be filled with the auxiliary trench W2 during subsequent formation of the source S, thereby achieving electrical connection between the first P-type connection region 40 and the source S. Alternatively, one can refer to... Figure 6 As shown, an auxiliary source S1 is filled in the auxiliary trench W2 so that the auxiliary source S1 can be electrically connected to the source S after the source S is formed; optionally, the material of the auxiliary source S1 can be polycrystalline silicon.

[0139] The following explanation will continue with the example of the first P-type connection region 40 having an auxiliary trench W2 and the subsequent source S directly filling the auxiliary trench W2.

[0140] S8: As Figure 23 As shown, a gate structure 50 is formed in the gate trench T1. The gate structure 50 includes a gate G and a gate dielectric layer 51 located between the gate G and the switching functional region 30. An interlayer dielectric layer 60 is formed on the side of the gate structure 50 away from the substrate 10.

[0141] S9: As Figure 1As shown, a source S is formed on the side of the second epitaxial layer 120 away from the substrate 10, an interlayer dielectric layer 60 is provided between the source S and the gate structure 50, and a drain D is formed on the side of the substrate 10 away from the first epitaxial layer 110.

[0142] The N-type current diffusion region 31 is connected to the N-type pillar region 21, the P-type channel region 32 is electrically connected to the source S through the first P-type connection region 40, and the P-type pillar region 22 is electrically connected to the source S through at least part of the first P-type connection region 40.

[0143] Considering the characteristics of wide-bandgap semiconductor materials, the conventional fabrication method involves first epitaxially growing an N-type epitaxial layer from the substrate 10 to the N-type source region 33, and then fabricating a deeper P-type pillar region within the N-type epitaxial layer to form a superjunction structure. This is almost impossible to achieve. However, the fabrication method provided in this application embodiment first epitaxially grows a first epitaxial layer 110 (initially N-type) on one side of the substrate 10, and processes the first epitaxial layer 110 so that at least a portion of the first epitaxial layer 110 facing away from the substrate 10 forms an electric field modulation region 20. The electric field modulation region 20 includes a region along the first direction... The N-type pillar regions 21 and P-type pillar regions 22 are arranged alternately in the X direction; then, a second epitaxial layer 120 (initially N-type) is formed on the side of the electric field modulation region 20 away from the substrate 10. The second epitaxial layer 120 is processed to form a switching functional region 30 and a first P-type connection region 40. In this way, a superjunction structure can be formed by forming P-type pillar regions in the relatively thin first epitaxial layer 110, which is initially N-type. This greatly reduces the difficulty of forming P-type pillar regions in a wide bandgap semiconductor layer and improves the feasibility of introducing a superjunction structure in a wide bandgap semiconductor device.

[0144] Among them, for the method of forming P-type pillar region 21 in the relatively thin first epitaxial layer 110 that is initially N-type, one method is trench etching plus epitaxial filling, and the other method is multiple ion implantation.

[0145] Following the traditional fabrication method, an N-type epitaxial layer is first grown from the substrate 10 to the N-type source region 33. Even if a trench etching and epitaxial filling method is used to form the P-type pillar region (i.e., first etching to form a deep trench, and then epitaxially forming the P-type pillar region inside and outside the deep trench), voids are easily generated in the newly grown P-type semiconductor material when the high aspect ratio trench is filled. Even if a trench etching and multiple epitaxial layers and ion implantation are used to form the P-type pillar region, deep doping cannot be formed through thermal diffusion in wide-bandgap semiconductor materials. Therefore, the P-type doped pillar structure can only be formed by multiple thin epitaxial layers and P-type ion implantation. This also has the problems of high cost of multiple epitaxial layers and difficulty in aligning multiple ion implantations.

[0146] The embodiments of this application ingeniously combine two-step epitaxial growth with trench etching plus epitaxial filling or multiple ion implantation to form P-type pillar regions. This not only enables the formation of P-type pillar regions in wide-bandgap semiconductor devices, thus introducing superjunction structures, but also, since the thickness of the first epitaxial layer formed in the first step is relatively thin, the aspect ratio of the first trench etched when forming P-type pillar regions using trench etching plus epitaxial filling is relatively small, making it less prone to voids. When forming P-type pillar regions using multiple ion implantation, the number of ion implantations is relatively small, resulting in lower costs and better alignment.

[0147] The above explanation uses the example of the P-type electric field shielding region 70 and the second P-type connection region 80 located within the N-type pillar region 21. Alternatively, the P-type electric field shielding region 70 and the second P-type connection region 80 may not be located within the N-type pillar region 21, but rather after the gate trench T1 is formed and before the gate structure 50 is formed within the gate trench T1, as described above. Figure 10 As shown, the method for fabricating this semiconductor device structure may further include:

[0148] S10: Ion implantation is performed on the N-type current diffusion region 31 to form a P-type electric field shielding region 70 and a second P-type connection region 80.

[0149] Regardless of whether the P-type electric field shielding region 70 and the second P-type connection region 80 are in the N-type pillar region 21 or in the N-type current diffusion region 31, in the direction perpendicular to the plane of the substrate 10, the P-type electric field shielding region overlaps at least partially with the gate structure, and the P-type electric field shielding region is electrically connected to the first P-type connection region or the P-type pillar region through the second P-type connection region.

[0150] The semiconductor device structure prepared by the method provided in this application has been described in detail in the foregoing embodiments, and will not be repeated here.

[0151] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0152] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device structure, characterized by, The semiconductor device structure comprises: a substrate; a first epitaxial layer located on one side of the substrate, at least part of the side of the first epitaxial layer away from the substrate is an electric field modulation region, the electric field modulation region comprises N-type column regions and P-type column regions arranged adjacent along a first direction, the first direction is parallel to the plane in which the substrate lies; a second epitaxial layer located on the side of the electric field modulation region away from the substrate, the second epitaxial layer comprises a switching function region and a first P-type connection region located on the two sides of the switching function region along the first direction, the switching function region comprises an N-type current diffusion region, a P-type channel region and an N-type source region stacked in the direction away from the substrate, the N-type current diffusion region is in communication with the N-type column region; the intermediate region on the side of the switching function region away from the electric field modulation region has a gate trench extending into the N-type current diffusion region, and a gate structure is arranged in the gate trench; a source electrode located on the side of the second epitaxial layer away from the substrate and a drain electrode located on the side of the substrate away from the first epitaxial layer, and the source electrode and the gate structure have an interlayer dielectric layer therebetween; wherein the P-type channel region is electrically connected to the source electrode through the first P-type connection region, and the P-type column region is electrically connected to the source electrode through at least part of the first P-type connection region.

2. The semiconductor device structure of claim 1, wherein, The P-type column region comprises m layers of P-type sub-column regions stacked in the direction away from the substrate, 2≤m≤4.

3. The semiconductor device structure of claim 1, wherein, In the direction perpendicular to the plane in which the substrate lies, at least part of the P-type column region overlaps the first P-type connection region.

4. The semiconductor device structure of claim 1, wherein, The doping concentration of the first P-type connection region is greater than the doping concentration of the P-type channel region; The first P-type connection region has an auxiliary trench on the side away from the substrate; The source electrode fills the auxiliary trench; Alternatively, the auxiliary trench is filled with an auxiliary source electrode, and the auxiliary source electrode is electrically connected to the source electrode.

5. The semiconductor device structure of claim 1, wherein, The first epitaxial layer comprises the electric field modulation region and an N-type voltage withstanding region located between the electric field modulation region and the substrate, and the N-type voltage withstanding region is in communication with the N-type column region.

6. The semiconductor device structure of any of claims 1-5, wherein, The semiconductor device structure further comprises: a P-type electric field shielding region located between the gate structure and part of the N-type column region, and in the direction perpendicular to the plane in which the substrate lies, the P-type electric field shielding region at least partially overlaps the gate structure; The P-type electric field shielding region is electrically connected to the first P-type connection region or the P-type column region through a second P-type connection region.

7. The semiconductor device structure of claim 6, wherein, The P-type electric field shielding region and the second P-type connection region are located in the N-type column region; Alternatively, the P-type electric field shielding region and the second P-type connection region are located in the N-type current diffusion region.

8. The semiconductor device structure of claim 6, wherein, In the direction perpendicular to the plane in which the substrate lies, the P-type electric field shielding region is arranged opposite to the gate structure; Alternatively, in the direction perpendicular to the plane in which the substrate lies, the P-type electric field shielding region at least partially does not overlap the gate structure.

9. The semiconductor device structure of claim 6, wherein, The P-type electric field shielding region comprises at least two P-type sub-electric field shielding regions spaced apart along a second direction, the second direction is parallel to the plane in which the substrate lies, and the second direction intersects the first direction; Each of the P-type sub-electric field shielding regions is electrically connected with the first P-type connection region or the P-type column region through at least one of the second P-type connection regions.

10. A method of fabricating a semiconductor device structure, characterized by, The application comprises: providing a substrate; forming a first epitaxial layer initially of N-type on one side of the substrate; processing the first epitaxial layer initially of N-type so that at least part of the first epitaxial layer on the side away from the substrate forms an electric field modulation region, the electric field modulation region comprising N-type column regions and P-type column regions arranged adjacently along a first direction, the first direction being parallel to the plane in which the substrate lies; forming a second epitaxial layer initially of N-type on the side of the electric field modulation region away from the substrate; sequentially performing P-type ion implantation and N-type ion implantation on the second epitaxial layer initially of N-type to form N-type current diffusion regions, P-type channel regions and N-type source regions stacked along the direction away from the substrate; etching a middle region of the second epitaxial layer on the side away from the substrate to form a gate trench, and processing the second epitaxial layer on both sides of the gate trench opposite along the first direction to form first P-type connection regions, the N-type source regions, the P-type channel regions and the N-type current diffusion regions between the gate trench and the first P-type connection regions being reserved, and the part between the two first P-type connection regions being a switching functional region; forming a gate structure in the gate trench, and forming an interlayer dielectric layer on the side of the gate structure away from the substrate; forming a source electrode on the side of the second epitaxial layer away from the substrate, the source electrode and the gate structure being separated by the interlayer dielectric layer, and forming a drain electrode on the side of the substrate away from the first epitaxial layer; wherein the N-type current diffusion regions are in communication with the N-type column regions, the P-type channel regions are electrically connected with the source electrode through the first P-type connection regions, and the P-type column regions are electrically connected with the source electrode through at least part of the first P-type connection regions.

11. The method of fabricating a semiconductor device structure of claim 10, wherein, The processing of the first epitaxial layer initially of N-type so that at least part of the first epitaxial layer on the side away from the substrate forms an electric field modulation region comprises: etching the first epitaxial layer initially of N-type to form a first trench, and then epitaxially forming the P-type column regions in the first trench, the parts of the first epitaxial layer initially of N-type adjacent along the first direction constituting the N-type column regions; or, performing m times of ion implantation on the part of the first epitaxial layer initially of N-type in which the P-type column regions are pre-formed, 2≤m≤4, to form m layers of P-type sub-column regions stacked along the direction away from the substrate, the m layers of P-type sub-column regions constituting the P-type column regions, and the parts of the first epitaxial layer initially of N-type adjacent along the first direction constituting the N-type column regions.

12. The method of fabricating a semiconductor device structure of claim 10, wherein, The processing of the second epitaxial layer on both sides of the gate trench opposite along the first direction to form first P-type connection regions comprises: performing P-type ion implantation on the second epitaxial layer on both sides of the gate trench opposite along the first direction to directly form the first P-type connection regions, the doping concentration of the first P-type connection regions being greater than the doping concentration of the P-type channel regions; Or, the second epitaxial layer on two sides of the gate trench opposite in the first direction is etched to form auxiliary trenches; The bottom and sidewall of the auxiliary trenches are implanted with P-type ions to form the first P-type connection region, and a doping concentration of the first P-type connection region is greater than a doping concentration of the P-type channel region; Subsequently, the source fills the auxiliary trenches when the source is formed; or the semiconductor device structure preparation method further comprises: The auxiliary trenches are filled with auxiliary sources, so that the auxiliary sources are electrically connected with the source after the source is formed.

13. The method of fabricating a semiconductor device structure of claim 10, wherein, After the electric field modulation region is formed and before the second epitaxial layer is formed, the semiconductor device structure preparation method further comprises: Part of the N-type column region is implanted with P-type ions to form a P-type electric field shielding region and a second P-type connection region; Or, after the gate trench is formed and before the gate structure is formed in the gate trench, the semiconductor device structure preparation method further comprises: The N-type current diffusion region is implanted with ions to form a P-type electric field shielding region and a second P-type connection region; In a direction perpendicular to a plane in which the substrate is located, the P-type electric field shielding region at least partially overlaps with the gate structure, and the P-type electric field shielding region is electrically connected with the first P-type connection region or the P-type column region through the second P-type connection region.

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