Photodetecting transistor and manufacturing method thereof and corresponding photodetecting method

Abstract

The application provides a photodetecting transistor, comprising, from bottom to top, a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a source-drain electrode partially contacting the active layer, and a passivation layer; wherein the active layer comprises intrinsic hydrogenated amorphous silicon, and in the region contacting the source-drain electrode, the active layer further comprises heavily doped hydrogenated amorphous silicon. The application also discloses a corresponding photodetecting pixel circuit, a photodetector and a manufacturing method thereof.

Description

TECHNICAL FIELD

[0001] The present application relates to a photodetector, in particular to a photodetector integrated with an amorphous silicon detection transistor and an oxide switch transistor, a manufacturing method thereof and a corresponding photodetection method. BACKGROUND

[0002] Photodetectors and image sensors play an extremely important role in numerous medical electronics, consumer electronics, military electronic devices. For example, X-ray images are the gold criterion for the diagnosis of various diseases such as orthopedics, pneumopathy, and cardio-cerebrovascular diseases; fingerprint recognition has become a standard security lock for smart phones; hyperspectral and multispectral imaging is an important modern military detection means. In these applications, photodetectors and image sensors with high responsivity and high resolution for weak light signals and transient photoelectric signals have always been the focus of research.

[0003] Existing image sensor technologies mainly include imaging technologies based on charge-coupled devices (CCD) and complementary metal-oxide (CMOS) transistors, and flat panel detection imaging technologies based on amorphous silicon (a-Si) photodiodes (PD) and a-Si transistors (TFT), the latter being the current mainstream X-ray image sensor technology. However, the light responsivity of photodiodes is low, and increasing the number of detected photons requires increasing the exposure area, which in turn leads to a decrease in detection resolution.

[0004] Compared with photodiodes, photo-TFTs are another alternative light sensor device and have obvious advantages in some aspects. Photo-TFTs themselves have photoconductive amplification capability, which is beneficial to improving light responsivity; at the same time, the size of the photo-current is related to the shape of the channel region of the device, so higher responsivity and higher resolution can be achieved. Due to these advantages, photo-TFTs have always been an important research direction of photoelectric sensor devices. SUMMARY

[0005] The present application provides a photodetection pixel circuit, which includes a switch transistor, including a substrate, a first bottom gate electrode, a first bottom gate dielectric layer, a first active layer, a first source-drain electrode in partial contact with the first active layer, and a first passivation layer, stacked in order from bottom to top; and a photodetection transistor coupled with the switch transistor, including a second bottom gate electrode, a second bottom gate dielectric layer, a second active layer, a second source-drain electrode in partial contact with the second active layer, and a second passivation layer, all located above the first passivation layer and stacked in order from bottom to top, wherein the second active layer includes intrinsic hydrogenated amorphous silicon, and in the region in contact with the second source-drain electrode, the second active layer further includes heavily doped hydrogenated amorphous silicon; the mobility of the first active layer is higher than the mobility of the second active layer.

[0006] In particular, a projection of one of the second bottom gate electrode and the first source / drain electrode on the substrate at least partially overlaps.

[0007] In particular, the switch detection transistor further comprises a first top gate dielectric layer and a first top gate electrode above the first active layer.

[0008] In particular, the light detection transistor further comprises a second top gate dielectric layer and a second top gate electrode above the second active layer.

[0009] In particular, the pixel circuit further comprises a scintillator above the first passivation layer and the second passivation layer.

[0010] The present application also provides a method for preparing a photodetection pixel circuit, comprising forming a first bottom gate electrode layer on a substrate, and patterning a first bottom gate electrode; forming a first bottom gate dielectric layer on the substrate and the first bottom gate electrode; forming a first active layer on the first bottom gate dielectric layer, and patterning a first active region; forming a first source / drain electrode layer on the first active region, and patterning a first source / drain electrode partially in contact with the first active layer; forming a first passivation layer of a switch transistor on the first active region, the first source / drain electrode, and the first bottom gate dielectric layer; forming a second bottom gate electrode layer on the first passivation layer away from the first source / drain electrode, and patterning a second bottom gate electrode; forming a second bottom gate dielectric layer on the second bottom gate electrode; forming a second active layer on the second bottom gate dielectric layer opposite the second bottom gate electrode, the mobility of the first active layer being higher than that of the second active layer, and patterning a second active region, wherein the second active region comprises an intrinsic hydrogenated amorphous silicon layer on the second bottom gate dielectric layer and a heavily doped hydrogenated amorphous silicon layer above the intrinsic hydrogenated amorphous silicon; forming a through hole above the first source / drain electrode close to the second bottom gate electrode; forming a second source / drain electrode layer on the second active region, and patterning a second source / drain electrode in contact with the heavily doped hydrogenated amorphous silicon layer; removing the heavily doped hydrogenated amorphous silicon layer between the second source / drain electrodes to expose the intrinsic hydrogenated amorphous silicon layer; and forming a second passivation layer on the intrinsic hydrogenated amorphous silicon layer and the second source / drain electrode.

[0011] In particular, the method further comprises forming a scintillator layer on the first passivation layer and the second passivation layer.

[0012] In particular, a projection of one of the second bottom gate electrode and the first source / drain electrode on the substrate at least partially overlaps.

[0013] This application also provides a photodetector, including a scan control circuit and a readout circuit, and a pixel array coupled thereto including the photodetector pixel circuit as described above.

[0014] The photodetector pixel scheme described in this application can solve the problems of low responsivity and low resolution in amorphous silicon photodiodes, and can also achieve a faster response speed than oxide photodiodes (TFTs) to reduce exposure dose. At the same time, replacing traditional amorphous silicon switches with high-mobility oxide switches helps to reduce readout time and improve the frame rate of dynamic imaging, thereby obtaining a photodetector with better overall performance. Attached Figure Description

[0015] The embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0016] Figure 1 The diagram shows a single-gate probe transistor and a dual-gate switch transistor.

[0017] Figure 2 The figure shows the characteristic curves of the amorphous silicon probe transistor in the dark state and under different light intensities;

[0018] Figure 3 The diagram shown is a schematic representation of the change in current of a dual-gate switching transistor in the dark state as a function of the top gate electrode voltage, according to an embodiment of this application.

[0019] Figure 4a -e shows a schematic diagram of five photodetector pixel circuits according to embodiments of this application;

[0020] Figure 5 The diagram shown is the timing diagram of the photodetector pixel circuit.

[0021] Figure 6a The diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 6b-6m The image shows the preparation process. Figure 6a A schematic flow chart of the Zhongguang Optoelectronic Pixel Circuit;

[0022] Figure 7a The diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 7b-7m The image shows the preparation process. Figure 7a A schematic flow chart of the Zhongguang Optoelectronic Pixel Circuit;

[0023] Figure 8a The diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 8b-8m The image shows the preparation process. Figure 8a A schematic flow chart of the photoelectric detection pixel circuit; and

[0024] Figure 9 A schematic diagram of a photodetector according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0026] The transistor in the present application can be a bipolar transistor or a field effect transistor. The transistor includes a control electrode, a first electrode and a second electrode, the first or second control electrode is coupled to a control metal layer, the first electrode and the second electrode are coupled to an active layer, and a dielectric layer is between the control metal layer and the semiconductor layer. The conductance characteristic of the active layer of the detection transistor changes under the modulation of input light. When the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode refers to the collector or the emitter of the bipolar transistor, and the corresponding second electrode is the emitter or the collector of the bipolar transistor; when the transistor is a field effect transistor, the control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or the source of the field effect transistor, and the corresponding second electrode can be the source or the drain of the field effect transistor. Generally, in an N-type transistor, the voltage of the drain should be greater than or equal to the voltage of the source, so the positions of the source and the drain change with the bias state of the transistor. Since the transistor used in the display is usually a thin film transistor (TFT), the embodiments of the present application take the MOS thin film transistor as an example for description, and the drain and the source of the transistor in the embodiments of the present application can change with the bias state of the transistor.

[0027] In the field of ultra-low dose X-ray detection, it is necessary to reduce the X-ray dose received by the human body by reducing the exposure time, so as to reduce the damage of X-rays to the human body. Although the oxide phototransistor has high responsivity, it has the problem of slow response speed. In comparison, the device size of the amorphous silicon phototransistor is small, the responsivity is between that of the oxide phototransistor and that of the amorphous silicon photodiode, and the amorphous silicon phototransistor can well solve the problems of low resolution and low responsivity in the amorphous silicon photodiode, and its light response speed is also significantly better than that of the oxide phototransistor, so it has better comprehensive detection performance.

[0028] In the scheme in the present application, the fast light response speed of amorphous hydrogenated silicon and its amplification effect are utilized to reduce the exposure time of the light sensitive unit and improve the signal-to-noise ratio and responsivity of the photodetector. In the application where the incident optical signal is weak or the irradiation time is short, for example in X-ray medical imaging equipment, the use of amorphous silicon detection transistor can reduce the X-ray exposure time to avoid harm to the human body while reducing the pixel size to ensure clear images.

[0029] In addition, the scheme in the present application uses high mobility oxide switch tube to replace the traditional amorphous silicon switch tube, which helps to reduce the readout time and thus improve the frame rate of dynamic imaging.

[0030] Figure 1 The single-gate detection transistor and the double-gate switch transistor are shown in the schematic diagram. For the single-gate detection transistor, it is always in the off-state working area of the transistor during the integration stage. Since there is no photo-generated current in the single-gate detection transistor in the dark state, the off-state leakage current is small; while in the case of light irradiation, the off-state current of the detection transistor will increase significantly due to the photo-generated current, thereby utilizing the difference before and after light irradiation to detect the optical signal. The active layer of the detection transistor includes an intrinsic hydrogenated amorphous silicon layer (a-Si:H) and a heavily doped hydrogenated amorphous silicon layer on the intrinsic hydrogenated amorphous silicon layer. Among them, the so-called heavily doped hydrogenated amorphous silicon, the impurities in the hydrogenated amorphous silicon can be phosphorus, and the doping level of the so-called heavy doping can be 10 19 -10 20 According to an embodiment, only the heavily doped hydrogenated amorphous silicon is in contact with the source and drain electrodes of the detection transistor.

[0031] The detection transistor mainly adopts a single-gate structure to obtain greater light absorption. Before exposure, the gate voltage Vg is set at a level that makes the detection transistor in the off-state working area; during the exposure integration stage, the photodetector is irradiated and the photodetector is in the off-state working area and its channel current is much larger than the dark state current. In the read stage after the integration stage and before the read stage starts, the photodetector is in the off-state working area and its channel current is substantially equal to the dark state current. In the reset stage, the photodetector is in the on-state working area.

[0032] In addition, the detection transistor can also adopt a double-gate structure, and the responsivity of the detection transistor to light detection and the amplification effect of the photo-generated current are directly related to the control ability of the gate electrode to the channel layer.

[0033] The switch transistor can adopt a double-gate structure. If the light comes from the top surface, the top gate electrode of the switch transistor is made of light-proof material, which can shield light, thereby reducing the influence of light conditions on the switching characteristics and dark current of the switch transistor. In the reading stage, the voltages of the bottom gate electrode and the top gate electrode of the switch transistor are the same, so that the switch transistor is in the on-state working area. In other detection stages, the switch transistor is in the off-state working area, and the channel current thereof is substantially equal to the dark-state current.

[0034] In addition, if the active layer material is not sensitive to light, the switch transistor can also adopt a single-gate structure.

[0035] Figure 2 Fig. 1 shows a schematic diagram of the light sensing characteristics of an amorphous silicon double-gate light detection transistor according to an embodiment of the present application. For example, the channel width W of the photodetection transistor is preferably 240 μm, the length L is 5 μm, the light wavelength is 550 nm, the light power range is 5-200 μW / cm 2 , the source-drain voltage Vds is always 10 V, the bottom gate voltage is the horizontal axis Vgs, and the vertical axis is the detection transistor current Ids. It can be seen that in the off-state working area of the double-gate light detection transistor, there is a significant difference between the leakage current in the absence of light and the leakage current after the above light.

[0036] Figure 3 Fig. 2 shows a schematic diagram of the dark-state current of a double-gate switch transistor varying with the voltage of the top gate electrode according to an embodiment of the present application. The voltage Vtg is applied to the top gate, the voltage Vbg is applied to the bottom gate, and the bottom gate is operated in the bottom gate mode (BG mode), that is, the top gate is the auxiliary electrode and the voltage is fixed, and the bottom gate voltage is scanned. It can be seen that when the fixed voltage of the top gate is changed to Vtg = -10 V, 0 V, 10 V, the threshold voltage of the switch transistor decreases with the increase of the top gate voltage and appears to be negative. However, no matter how the voltages of the top gate and the bottom gate change, the level of the dark-state leakage current is basically the same when the transistor is in the off-state. Therefore, the top gate electrode not only can shield light, but also can realize compensation and adjustment of the threshold voltage of the switch transistor by adjusting the voltage of the top gate.

[0037] Figures 4a-4e Fig. 3 shows schematic diagrams of five kinds of pixel circuits of light detectors according to embodiments of the present application. Figure 4a The pixel circuit shown can include a detection transistor T1, a storage unit, and a switch transistor T2, wherein T1 and T2 are both single-gate transistors, the active area of T1 can adopt hydrogenated amorphous silicon in the manufacturing process, and the active area of T2 can adopt a high-mobility (the mobility of the active area of T2 is higher than that of the active area of T1) and light-insensitive semiconductor material, for example, IGZO.

[0038] As shown in the figure, the first terminal of the photodetector transistor T1 can be configured to receive a high level, such as Vdd, and its second terminal can be coupled to a memory cell, such as a capacitor C. px The upper plate, capacitor C px The lower plate of T1 can be configured to receive a reference potential Vref or a low level Vss. The first control electrode / gate of T1 is configured to receive the gate scan signal Vg[n+1] of row n+1 as the control voltage. The first electrode of the switching transistor T2 can be coupled to the second electrode of T1 or capacitor C. px The upper plate of the switching transistor T2 has its second electrode serving as the output terminal of the detector pixel for reading the detection signal. The first control electrode of the switching transistor T2 is configured to receive the gate scan signal Vg[n] of the n+1th row as the control voltage. Taking the pixel of the current row (the nth row) as a reference, T2 should read out the charge when the scan signal of the nth row arrives; considering the reset process, the gate of T1 can be controlled by the gate scan signal of the n+1th row.

[0039] Compared to Figure 4a pixel circuit, Figure 4b The capacitor C of the pixel circuit shown px The overlapping parasitic capacitance of the source and drain electrodes of transistor T1 helps to further reduce the device size, thereby improving the resolution of the photodetector.

[0040] Compared to Figure 4a pixel circuit, Figure 4c The pixel circuit shown uses a dual-gate transistor for its switching transistor T2, with its top gate electrode made of an opaque conductive material to provide a light-shielding effect. The first and second control electrodes of the switching transistor T2 are configured to receive either Vbg[n] or Vtg[n] control voltages. The active region of T2 uses a high-mobility semiconductor material. Taking the pixel in the current row (row n) as a reference, T2 should read out the charge when the scan signal for row n arrives; considering the reset process, the gate of T1 can be controlled by the gate scan signal for row n+1.

[0041] Compared to Figure 4c pixel circuit, Figure 4d The capacitor C of the pixel circuit shown px The overlapping parasitic capacitance of the source and drain electrodes of transistor T1 helps to further reduce the device size, thereby improving the resolution of the photodetector.

[0042] In particular, the photodetector transistor T1 can also be a dual-gate transistor for detection.

[0043] Figure 4eThe pixel circuit shown further includes an amplifying transistor T3, whose gate is coupled to the upper terminal of capacitor Cpx, its drain is coupled to a high-level voltage Vdd, and its source is coupled to the drain of switching transistor T2. The photocurrent generated by the sensing transistor modulates the voltage change on Cpx, which is then converted into a larger output current by the amplifying transistor, thereby increasing the amount of signal charge within the image sensing pixel and improving the signal-to-noise ratio of the pixel circuit. Taking the pixel of the current row (row n) as a reference, T2 should read out the charge when the scan signal of row n arrives; considering the reset process, the gate of T1 can be controlled by the gate scan signal of row n+1.

[0044] Figure 5 As shown Figures 4a-4e The timing diagram of the photodetector pixel circuit. (See diagram below.) Figure 5 As shown, in the dark state, there is a dark current in the probe transistor, which is on the order of magnitude very low. In the dark state, both the probe transistor T1 and the switch transistor T2 are off, and all gate voltages (e.g., Vg[n+1], Vg[n] / Vbg[n], Vtg[n]) are negative, for example, -20V.

[0045] During the exposure integration stage, under illumination, Vdd is at a high level, causing the detection transistor T1 to generate a photocurrent, and simultaneously supplying C... px During charging, the value of the photocurrent is greater than the dark current in T1.

[0046] During the readout stage, if the switching transistor is a single-gate device, the gate voltage Vg[n] of T2 is set to a positive voltage to turn on T2, for example, 10V; if the switching transistor is a dual-gate device, the bottom gate and top gate voltages Vbg[n] and Vtg[n] of T2 are both set to positive voltages to turn on T2, for example, both are 10V, so that the detected signal can be read out of the pixel circuit.

[0047] After the readout phase ends, the gate voltage Vg[n+1] of the probe transistor T1 is set to a positive voltage to turn T1 on, and Vdd is set to a low level, thus controlling the connection between T1 and capacitor C. px The reset operation is performed. Although a relatively large current flows through transistor T1 during this stage, it will not adversely affect the accuracy of the detection since the read operation has already ended.

[0048] Figure 6a The diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 6b-6m The image shows the preparation process. Figure 6a A schematic flow chart of the middle pixel circuit. This photodetector pixel circuit includes phototransistors, or detector transistors, for detecting or capturing light signals, as well as switching transistors, or non-detector transistors, for forming other circuits in the detector array.

[0049] Wherein, each of the switch transistor and the detection transistor can be a single-gate or double-gate transistor. And, a scintillator can be provided on the top of the pixel circuit.

[0050] As shown in FIG. 6A, a bottom gate electrode layer 602 of the switch transistor can be formed on a substrate 601 first. Figure 6b According to an embodiment, light irradiation can come from the direction of the bottom gate, so the bottom gate electrode material of the switch transistor needs to be opaque.

[0051] As shown in FIG. 6B, the bottom gate electrode layer 602 can be patterned to form a bottom gate electrode 6021 of the switch transistor. Figure 6c As shown in FIG. 6C, a bottom gate dielectric layer 603 of the switch transistor can be formed on the substrate 601 and the bottom gate electrode 6021 of the switch transistor.

[0052] Figure 6d As shown in FIG. 6D, an active layer 604 of the switch transistor can be formed on the bottom gate dielectric layer of the switch transistor and patterned to form an active region 604 of the switch transistor. According to an embodiment, the material of the active layer 604 can be a material with high mobility and not sensitive to light, such as IGZO.

[0053] As shown in FIG. 6E, a source electrode 6051 and a drain electrode 6052 of the switch transistor can be formed on the active region 604 and the bottom gate dielectric layer 603 of the switch transistor. Figure 6e As shown in FIG. 6F, a top gate dielectric layer 606 of the switch transistor can be formed on the source and drain electrodes 6051 and 6052, the active region 604, and the bottom gate dielectric layer 603 of the switch transistor.

[0054] Figure 6f As shown in FIG. 6G, a bottom gate electrode layer of the detection transistor can be formed on the region of the top gate dielectric layer 606 of the switch transistor away from the source electrode 6051 and the drain electrode 6052 and patterned to form a bottom gate electrode 607 of the detection transistor. According to an embodiment, light irradiation can come from the direction of the bottom gate, so the bottom gate electrode material of the detection transistor needs to be transparent.

[0055] As shown in FIG. 6H, a bottom gate dielectric layer 608 of the detection transistor can be formed on the bottom gate electrode 607 of the detection transistor and the top gate dielectric layer 606 of the switch transistor. Figure 6g As shown in FIG. 61, a top gate dielectric layer 609 of the detection transistor can be formed on the bottom gate dielectric layer 608 of the detection transistor.

[0056] Figure 6h As shown in FIG. 6J, a top gate electrode 610 of the detection transistor can be formed on the top gate dielectric layer 609 of the detection transistor.

[0057] As shown in FIG. 6K, a top gate dielectric layer 611 of the scintillator can be formed on the top gate electrode 610 of the detection transistor. Figure 6i As shown in FIG. 6L, a top gate electrode 612 of the scintillator can be formed on the top gate dielectric layer 611 of the scintillator.

[0058] Figure 6j ​​​​As shown, an active layer of the probe transistor is formed on the region of the bottom gate dielectric layer 608 of the probe transistor opposite to the bottom gate electrode 607 of the probe transistor. This active layer includes an intrinsic hydrogenated amorphous silicon layer (a-Si:H) 609 located on the bottom gate dielectric layer 608 of the probe transistor and a heavily doped hydrogenated amorphous silicon layer (n-Si:H) located on the intrinsic hydrogenated amorphous silicon layer 609. + a-Si:H)610.

[0059] like Figure 6k As shown, a through-hole is formed above the source or drain electrode 6052 of the switching transistor.

[0060] like Figure 6l As shown, firstly, a conductive material is formed in the vias on the heavily doped hydrogenated amorphous silicon layer 610 of the probe transistor, the bottom gate dielectric layer 608 of the probe transistor, and the source or drain electrode 6052 of the switching transistor. Then, the source electrode 6111 and drain electrode 6112 of the probe transistor are patterned, exposing the heavily doped hydrogenated amorphous silicon layer 610 between 6111 and 6112. Then, the heavily doped hydrogenated amorphous silicon (n0) between the source and drain electrodes 6111 and 6112 of the probe transistor... + The a-Si:H layer is etched away to expose the intrinsic hydrogenated amorphous silicon layer 609 (a-Si:H). For example, dry etching such as RIE can be used to etch away the heavily doped hydrogenated amorphous silicon layer; the specific etching gas can be CF4+O2 or SF6+O2, etc.

[0061] like Figure 6m As shown, a passivation layer 612 is formed on the intrinsic hydrogenated amorphous silicon layer 609, the source / drain electrodes 6111 and 6112 exposed between the source / drain electrodes of the probe transistor 6111 and 6112, and the bottom gate dielectric layer 608. A scintillator may also be formed on the passivation layer.

[0062] This approach effectively couples two devices manufactured using different process technologies into the same pixel structure, such as an amorphous silicon detector transistor (a-Si:H TFT) for photodetection and a metal-oxide-semiconductor thin-film transistor (MO TFT) for signal readout. Compared to current high-performance amorphous silicon photodiodes (a-Si PD) and amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs), the proposed detection scheme offers higher photoresponsivity and enables detection with lower doses. Furthermore, replacing the photodiode with a detector transistor helps to further reduce pixel size, thereby improving the image resolution of the detection panel. Simultaneously, using IGZO as the active layer for the switching transistor results in higher mobility, shorter readout time, and a higher achievable frame rate. Moreover, since both the switching and detector transistors employ a bottom-gate structure, fewer voltage signals are required during detection, simplifying the pixel structure and detection timing.

[0063] Figure 7a The diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 7b-7m The image shows the preparation process. Figure 7a A schematic flow chart of the mid-pixel circuit.

[0064] Both the switching transistor and the detection transistor can be single-gate or dual-gate transistors. Furthermore, a scintillator can be located at the top of this pixel circuit.

[0065] like Figure 7b As shown, the bottom gate electrode layer 702 of the switching transistor can first be formed on the substrate 701. According to one embodiment, light can be emitted from the bottom gate direction, so the bottom gate electrode material of the switching transistor should be an opaque material.

[0066] like Figure 7c As shown, the bottom gate electrode layer 702 can be patterned to form the bottom gate electrode 7021 of the switching transistor.

[0067] like Figure 7d As shown, a bottom gate dielectric layer 703 of the switching transistor is formed on the substrate 701 and the bottom gate electrode 70211 of the switching transistor.

[0068] like Figure 7e As shown, an active layer 704 is formed on the bottom gate dielectric layer of the switching transistor, and patterned thereon to form the active region 704 of the switching transistor. According to one embodiment, the material of the active layer 704 can be a material with high mobility and insensitive to light, such as IGZO.

[0069] like Figure 7f As shown, the source electrode 7051 and drain electrode 7052 of the switching transistor are formed on the active region 704 and the bottom gate dielectric layer 703 of the switching transistor.

[0070] like Figure 7g As shown, a top gate dielectric layer 706 of the switching transistor is formed on the source and drain electrodes 7051 and 7052, the active region 704, and the bottom gate dielectric layer 703.

[0071] like Figure 7h As shown, a bottom gate electrode 7072 of the probe transistor is formed in a region of the top gate dielectric layer 706 of the switching transistor that is away from the source electrode 7051 and the drain electrode 7052, and a top gate electrode 7071 of the switching transistor is formed directly above the bottom gate electrode 7072. According to one embodiment, light can be emitted from the bottom gate direction, so the bottom gate electrode material of the probe transistor should be a transparent material.

[0072] likeFigure 7i As shown, a bottom gate dielectric layer 708 of the probe transistor is formed on the bottom gate electrode 7072 of the probe transistor and the top gate electrode 7071 of the switch transistor and their top gate dielectric layer 706.

[0073] like Figure 7j As shown, an active layer of the probe transistor is formed on the region of the bottom gate dielectric layer 708 opposite to the bottom gate electrode 7072 of the probe transistor. This active layer includes an intrinsic hydrogenated amorphous silicon layer (a-Si:H) 709 on the bottom gate dielectric layer 708 and a heavily doped hydrogenated amorphous silicon layer (n-Si:H) on the intrinsic hydrogenated amorphous silicon layer 709. + a-Si:H)710.

[0074] like Figure 7k As shown, a through-hole is formed above the drain electrode 7052 of the switching transistor.

[0075] like Figure 7l As shown, firstly, a conductive material is formed in the vias on the heavily doped hydrogenated amorphous silicon layer 710 of the probe transistor, the bottom gate dielectric layer 708, and the drain electrode 7052 of the switching transistor. Then, the source electrode 7111 and drain electrode 7112 of the probe transistor are patterned, exposing the heavily doped hydrogenated amorphous silicon layer 710 between 7111 and 7112. Next, the heavily doped hydrogenated amorphous silicon (n...) is deposited in the active region between the source and drain electrodes of the probe transistor. + The a-Si:H layer 710 is etched away to expose the intrinsic hydrogenated amorphous silicon layer 709 (a-Si:H). For example, dry etching such as RIE can be used to etch away the heavily doped hydrogenated amorphous silicon layer; the specific etching gas can be CF4+O2 or SF6+O2, etc.

[0076] like Figure 7m As shown, a passivation layer is formed on the intrinsic hydrogenated amorphous silicon layer 709, source / drain electrodes 711, and bottom gate dielectric layer 708 of the probe transistor, which are exposed between the source electrode 7111 and the drain electrode 7112. A scintillator may also be formed on the passivation layer.

[0077] Compared to the previous approach, this process forms the top gate electrode of the switching transistor simultaneously with the bottom gate electrode of the probe transistor. In this case, regardless of whether light shines from the top or bottom gate electrode, the opaque top or bottom gate electrode can achieve a light-blocking effect. There is no need to consider whether the high-mobility material of the switching transistor is affected by light, reducing the limitations on the selection of high-mobility active layer materials. This reduces the off-state leakage current of the switching transistor during the exposure integration stage while ensuring the normal operation of the pixel circuit.

[0078] Figure 8aThe diagram shown is a schematic diagram of a photoelectric detection pixel circuit according to an embodiment of this application. Figures 8b-8m The image shows the preparation process. Figure 8a A schematic flow chart of the mid-pixel circuit.

[0079] Both the switching transistor and the detection transistor can be single-gate or dual-gate transistors. Furthermore, a scintillator can be located at the top of this pixel circuit.

[0080] like Figure 8b As shown, the bottom gate electrode layer 802 of the switching transistor can first be formed on the substrate 801. According to one embodiment, light can be emitted from the bottom gate direction, so the bottom gate electrode material of the switching transistor should be an opaque material.

[0081] like Figure 8c As shown, the bottom gate electrode layer 802 can be patterned to form the bottom gate electrode 8021 of the switching transistor.

[0082] like Figure 8d As shown, a bottom gate dielectric layer 803 of the switching transistor is formed on the substrate 801 and the bottom gate electrode 802 of the switching transistor.

[0083] like Figure 8e As shown, an active layer 804 is formed on the bottom gate dielectric layer of the switching transistor, and patterned thereon to form the active region 804 of the switching transistor. According to one embodiment, the material of the active layer 804 can be a material with high mobility and insensitive to light, such as IGZO.

[0084] like Figure 8f As shown, the source electrode 8051 and drain electrode 8052 of the switching transistor are formed on the active region 804 and the bottom gate dielectric layer 803 of the switching transistor. The source or drain electrode 8052 of the switching transistor extends away from the switching transistor and has a large overlap area with the bottom gate electrode of the subsequent detection transistor to generate overlapping parasitic capacitance as a storage cell of the pixel circuit.

[0085] like Figure 8g As shown, a top gate dielectric layer 806 of the switching transistor is formed on the source and drain electrodes 8051 and 8052, the active region 804, and the bottom gate dielectric layer 803.

[0086] like Figure 8h As shown, a bottom gate electrode 8072 of a probe transistor is formed in a region of the top gate dielectric layer 806 of the switching transistor that is away from the source electrode 8051 and the drain electrode 8052, and a top gate electrode 8071 of the switching transistor is formed directly above the bottom gate electrode 8072 of the switching transistor.

[0087] likeFigure 8i As shown, a bottom gate dielectric layer 808 of the probe transistor is formed on the bottom gate electrode 8072 of the probe transistor and the top gate electrode 8071 of the switching transistor and their top gate dielectric layer 806.

[0088] like Figure 8j As shown, an active layer of the probe transistor is formed on the region of the bottom gate dielectric layer 808 of the probe transistor directly opposite the bottom gate electrode 8072 of the probe transistor. This active layer includes an intrinsic hydrogenated amorphous silicon layer (a-Si:H) 809 located on the bottom gate dielectric layer 808 of the probe transistor and a heavily doped hydrogenated amorphous silicon layer (n-Si:H) located on the intrinsic hydrogenated amorphous silicon layer 809. + a-Si:H)810.

[0089] like Figure 8k As shown, a through-hole is formed above the drain electrode 8052 of the switching transistor.

[0090] like Figure 8l As shown, firstly, a conductive material is formed in the vias on the heavily doped hydrogenated amorphous silicon layer 810 of the probe transistor, the bottom gate dielectric layer 808, and the drain electrode 8052 of the switching transistor. Then, the source electrode 8111 and drain electrode 8112 of the probe transistor are patterned, exposing the heavily doped hydrogenated amorphous silicon layer 810 between 8111 and 8112. Next, the heavily doped hydrogenated amorphous silicon (n...) is deposited in the active region between the source and drain electrodes of the probe transistor... + The a-Si:H layer 810 is etched away to expose the intrinsic hydrogenated amorphous silicon layer 809 (a-Si:H). For example, dry etching such as RIE can be used to etch away the heavily doped hydrogenated amorphous silicon layer; the specific etching gas can be CF4+O2 or SF6+O2, etc.

[0091] like Figure 8m As shown, a passivation layer is formed on the intrinsic hydrogenated amorphous silicon layer 809, source / drain electrodes 811, and bottom gate dielectric layer 808 of the probe transistor, which are exposed between the source electrode 8111 and the drain electrode 8112. A scintillator may also be formed on the passivation layer.

[0092] Compared to the previous approach, this process effectively utilizes the overlapping parasitic capacitance between the drain electrode and the bottom gate electrode of the probe transistor as a signal storage capacitor, which helps to further reduce the size of individual pixels and thus improve the image resolution of the probe panel.

[0093] Figure 9Fig. 1 is a schematic diagram of a photodetector according to an embodiment of the present application. As shown, the photodetector can include at least a photodetector pixel array, a scan control circuit, and a readout circuit. The photodetector pixel array and other circuit portions can be formed simultaneously using the methods described herein. Further, the photodetector pixel array can include one or more photodetection transistors as described above.

[0094] The light referred to in the present application can be visible light, invisible light, or other radiation, etc.

[0095] The above embodiments are only used to illustrate the present application, but not to limit it. Those skilled in the art can make various modifications and variations without departing from the scope of the present application. Therefore, all equivalent technical solutions should belong to the scope of the present application.

Claims

1. A photodetection pixel circuit, comprising a switch transistor comprising, from bottom to top, a substrate, a first bottom gate electrode, a first bottom gate dielectric layer, a first active layer, a first source-drain electrode partially in contact with the first active layer, a first passivation layer; and a photodetection transistor coupled to the switch transistor, comprising, from bottom to top, a second bottom gate electrode, a second bottom gate dielectric layer, a second active layer, a second source-drain electrode partially in contact with the second active layer, a second passivation layer, all above the first passivation layer, wherein the second active layer comprises intrinsic hydrogenated amorphous silicon, and in the region in contact with the second source-drain electrode, the second active layer further comprises heavily doped hydrogenated amorphous silicon; the first active layer has a higher mobility than the second active layer.

2. The pixel circuit of claim 1, wherein, a projection of one of the second bottom gate electrode and the first source-drain electrode on the substrate at least partially overlaps. 3.The pixel circuit of claim 1, wherein the switch transistor further comprises a first top gate dielectric layer and a first top gate electrode above the first active layer. 4.The pixel circuit of claim 1, wherein the photodetection transistor further comprises a second top gate dielectric layer and a second top gate electrode above the second active layer. 5.The pixel circuit of claim 1, further comprising a scintillator above the first passivation layer and the second passivation layer. 6.A method for fabricating a photodetection pixel circuit, comprising forming a first bottom gate electrode layer on a substrate, and patterning a first bottom gate electrode; forming a first bottom gate dielectric layer on the substrate and the first bottom gate electrode; forming a first active layer on the first bottom gate dielectric layer, and patterning a first active region; forming a first source-drain electrode layer on the first active region, and patterning a first source, drain electrode partially in contact with the first active layer; forming a first passivation layer of the switch transistor on the first active region, the first source, drain electrode, and the first bottom gate dielectric layer; forming a second bottom gate electrode layer on the first passivation layer away from the first source, drain electrode, and patterning a second bottom gate electrode; forming a second bottom gate dielectric layer on the second bottom gate electrode; forming a second active layer on the second bottom gate dielectric layer opposite to the second bottom gate electrode, the first active layer has a higher mobility than the second active layer, and patterning a second active region, wherein the second active region comprises an intrinsic hydrogenated amorphous silicon layer on the second bottom gate dielectric layer and a heavily doped hydrogenated amorphous silicon layer above the intrinsic hydrogenated amorphous silicon; forming a via hole above the first source, drain electrode close to the second bottom gate electrode; forming a second source-drain electrode layer on the second active region, and patterning a second source-drain electrode in contact with the heavily doped hydrogenated amorphous silicon layer; removing the heavily doped hydrogenated amorphous silicon layer between the second source-drain electrodes, exposing the intrinsic hydrogenated amorphous silicon layer; forming a second passivation layer on the intrinsic hydrogenated amorphous silicon layer, the second source-drain electrode.

7. The method of claim 6, further comprising forming a scintillator layer on the first passivation layer and the second passivation layer.

8. The method of claim 6, wherein a projection of one of the second bottom gate electrode and the first source, drain electrode on the substrate at least partially overlaps.

9. A photodetector comprising a scan control circuit and a readout circuit, and a pixel array coupled thereto comprising the photodetector pixel circuit of any one of claims 1-5.

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