Three-level dc-dc converter and control circuit

Abstract

Disclosed is a three-level DC-DC converter. The embodiment of the application stabilizes the voltage value of the flying capacitor at a predetermined value by adjusting the phase difference between the first power tube and the second power tube in the three-level DC-DC converter and the duty cycle of each power tube, wherein the variation of the duty cycle is proportional to the variation of the phase difference. The scheme is effective in any load condition, which improves the efficiency and stability of the circuit.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and more specifically, to a three-level DC-DC converter and its control circuit. Background Technology

[0002] The three-level DC-DC converters used in existing technologies, such as Figure 1 The diagram shows a three-level Buck converter, comprising power transistors S1-S4, a flying capacitor Cf, an inductor L, and an output capacitor Co. The drive signals G for power transistors S1 and S4 are... S1 and G S4 Complementary, the drive signals G of power transistors S2 and S3 S2 and G S3 Complementary. Furthermore, the drive signals G for power transistors S1 and S2... S1 and G S2 The duty cycles are equal, and the drive signals G of power transistors S1 and S2 are equal. S1 and G S2 The phase difference α is 180° (π radians).

[0003] However, due to factors such as parasitic parameters in the circuit and errors in various circuit components, the voltage across the flying capacitor Cf may exceed 1 / 2V. in or less than 1 / 2V in Unbalanced conditions can cause unstable current in inductor L, thereby reducing the reliability of the entire circuit.

[0004] There are many existing control methods to solve the voltage imbalance problem of flying capacitors. Based on the voltage of the flying capacitor and 1 / 2V... in The phase difference α between the drive signals of power transistors S1 and S2 is adjusted by the difference between the two signals. Assuming the original phase difference α = π, D1 = D2 = D, and the voltage V across capacitor Cf is... cf Less than 1 / 2V in Increasing the phase difference α will increase the amount of charge Q charged by the flying capacitor. c Discharge quantity Q d That is, the charge increased by ΔQ. Similarly, if the voltage across the capacitor V... cf Greater than 1 / 2V in If the phase difference α is reduced, Q can be made to... c d This means that the charge amount decreased by ΔQ. However, the method of balancing the voltage across the flying capacitor by phase-shift control alone has a weak voltage equalization capability when the duty cycle is close to 0 or close to 1 in CCM operating mode. In DCM operating mode, when D < 0.5, the voltage equalization capability of phase-shift control is 0 and cannot perform voltage equalization. Summary of the Invention ​

[0005] In view of this, embodiments of the present invention provide a three-level DC-DC converter and control circuit to overcome the shortcomings of phase-shift voltage equalization control, which has weak voltage equalization capability when the duty cycle is close to 0 or close to 1 in CCM operating mode and cannot perform voltage equalization when D<0.5 in DCM operating mode. This ensures that the voltage value of the flying capacitor can be stabilized within a predetermined range under any load, thereby improving the reliability of the system.

[0006] According to a first aspect of the present invention, a control circuit for a three-level DC-DC converter is provided, the three-level DC-DC converter comprising first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between a common node of the first and second power transistors and a common node of the third and fourth power transistors, characterized in that the control circuit is configured to:

[0007] The phase difference between the driving signals of the first power transistor and the second power transistor, as well as the duty cycle of the driving signals, are adjusted according to the error between the voltage value of the flying capacitor and the preset value, so that the voltage value of the flying capacitor is stabilized at the preset value.

[0008] Specifically, when the voltage value of the flying capacitor is greater than the preset value, the control circuit is configured to control the phase difference to decrease, the duty cycle of the first power transistor to decrease, and the duty cycle of the second power transistor to increase; when the voltage value of the flying capacitor is less than the preset value, the control circuit is configured to control the phase difference to increase, the duty cycle of the first power transistor to increase, and the duty cycle of the second power transistor to decrease.

[0009] Specifically, the change in duty cycle is proportional to the change in phase difference.

[0010] Specifically, the proportionality coefficient between the change in duty cycle and the change in phase difference is a constant.

[0011] Specifically, the proportionality coefficient between the change in duty cycle and the change in phase difference is a function related to the duty cycle.

[0012] Specifically, the control circuit includes:

[0013] The feedback compensation circuit is configured to compensate for the error between the feedback signal characterizing the output signal of the three-level DC-DC converter and the reference signal characterizing the expected value of the output signal to generate a feedback compensation signal.

[0014] A capacitor balancing circuit is configured to adjust the phase difference between the drive signals of the first power transistor and the second power transistor based on the error between the voltage value of the flying capacitor and the preset value.

[0015] The drive circuit is configured to generate drive signals for controlling the power transistors in the three-level DC-DC converter based on the compensation signal and the duty cycle adjustment signal, wherein the duty cycle adjustment signal is generated based on the change in the phase difference.

[0016] Specifically, the capacitor balancing circuit includes:

[0017] A capacitor compensation circuit is configured to generate a first capacitor compensation signal based on the error between the voltage value of the flying capacitor and a preset value, and to obtain a second capacitor compensation signal based on the sum of the first capacitor compensation signal and a bias voltage; and

[0018] The sawtooth wave generation circuit is configured to generate a first sawtooth wave signal and a second sawtooth wave signal with a period equal to the switching period and peak-to-peak values ​​equal, based on the switching period and the second capacitor compensation signal.

[0019] Specifically, the first capacitor compensation signal is used to characterize the change in phase difference between the first sawtooth wave signal and the second sawtooth wave signal.

[0020] Specifically, the bias voltage is equal to half the peak-to-peak value of the first sawtooth wave signal.

[0021] Specifically, the capacitor compensation circuit includes:

[0022] The sampling circuit is configured to acquire a capacitor voltage sampling signal that characterizes the voltage value of the flying capacitor;

[0023] An error amplifier is configured to acquire the error between the capacitor voltage sampling signal and a reference signal characterizing the preset value;

[0024] A compensation network is configured to compensate for the error to obtain a first capacitance compensation signal; and

[0025] A bias circuit is configured to acquire the sum of the first capacitor compensation signal and the bias voltage to generate the second capacitor compensation signal.

[0026] Specifically, the sawtooth wave generating circuit includes:

[0027] A first sawtooth wave generating circuit is configured to generate a first clock signal with a period equal to the switching period, and is controlled by the first clock signal to generate the first sawtooth wave signal; and

[0028] The second sawtooth wave generating circuit is configured to compare the first sawtooth wave signal with the second capacitor compensation signal to generate a second clock signal, and generate the second sawtooth wave signal according to the second clock signal, wherein the peak-to-peak values ​​of the first and second sawtooth wave signals are the same.

[0029] Specifically, the second sawtooth wave generating circuit includes:

[0030] A clock generation circuit is configured to generate a second clock signal based on a second capacitor compensation signal and a first clock signal, wherein the second capacitor compensation signal is used to adjust the phase difference between the first clock signal and the second clock signal; and

[0031] A sawtooth wave generator, controlled by the second clock signal to generate the second sawtooth wave signal, wherein the period of the second sawtooth wave signal is the same as the period of the second clock signal.

[0032] Specifically, the driving circuit includes:

[0033] A first driving circuit is configured to generate a first driving signal based on a comparison result of a first compensation signal and a first sawtooth wave signal, so as to control the first and fourth power transistors according to the first driving signal; and

[0034] The second drive circuit is configured to generate a second drive signal based on a comparison result of a second compensation signal and a second sawtooth wave signal, so as to control the second and third power transistors according to the second drive signal, wherein...

[0035] The first compensation signal is the sum of the feedback compensation signal and the duty cycle adjustment signal; the second compensation signal is the difference between the feedback compensation signal and the duty cycle adjustment signal.

[0036] Specifically, the duty cycle adjustment signal is proportional to the first capacitor compensation signal.

[0037] Specifically, the preset value is 1 / 2 of the input voltage.

[0038] According to a second aspect of the present invention, a three-level DC-DC converter is provided, characterized in that it comprises:

[0039] The first to fourth power transistors are connected in series between the input voltage and the reference ground;

[0040] A flying capacitor is connected to the common node of the first and second power transistors and the common node of the third and fourth power transistors; and

[0041] The control circuit described in any of the above items.

[0042] Specifically, the three-level DC-DC converter further includes:

[0043] An inductor is connected between the common node of the second and third power transistors and the output terminal.

[0044] Specifically, when the three-level DC-DC converter is in continuous current mode, the drive signals of the first power transistor and the fourth power transistor are complementary, the drive signals of the second power transistor and the third power transistor are complementary, and there is a phase difference between the drive signals of the first power transistor and the second power transistor.

[0045] Specifically, when the three-level DC-DC converter is in discontinuous current mode, the fourth power transistor is turned on by the turn-off time of the first power transistor and turns off when the inductor current reaches zero; the third power transistor is turned on by the turn-off time of the second power transistor and turns off when the inductor current reaches zero, and there is a phase difference between the drive signals of the first power transistor and the second power transistor.

[0046] The technical solution of this invention adjusts the phase difference between the first and second power transistors in a three-level DC-DC converter based on the error between the voltage value of the flying capacitor and a preset value, and simultaneously adjusts the duty cycle based on the change in the phase difference. This ensures that the voltage value of the flying capacitor can be stabilized within a predetermined range under any load, thereby reducing the voltage required to withstand by each power transistor in the DC-DC converter and improving the reliability of the system. Attached Figure Description

[0047] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0048] Figure 1 This is a circuit diagram of a prior art three-level DC-DC converter;

[0049] Figure 2 This is a waveform diagram of a three-level DC-DC converter in CCM operating mode.

[0050] Figure 3 This is a waveform diagram of a three-level DC-DC converter in DCM operating mode.

[0051] Figure 4 This is a waveform diagram of the three-level DC-DC converter in CCM operating mode according to an embodiment of the present invention;

[0052] Figure 5 This is a waveform diagram of the three-level DC-DC converter in DCM operating mode according to an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the control circuit of a three-level DC-DC converter according to an embodiment of the present invention; and

[0054] Figure 7This is a control waveform diagram of a three-level DC-DC converter according to an embodiment of the present invention. Detailed Implementation

[0055] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0056] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0057] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0058] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0059] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0060] Figure 2 The operating waveforms of a prior art three-level DC-DC converter in CCM mode are presented. Figure 3 The operating waveforms of a prior art three-level DC-DC converter in DCM operating mode are presented. Figure 1 Taking the three-level buck converter shown as an example, the driving signals G of the power transistors S1 and S2 are adjusted. S1 and G S2 The phase difference α is used to balance the flying capacitor voltage V. cf Where s1 and s2 are defined as the inductor currents I and I, respectively. L The magnitude of the slopes of the ascent and descent can be used to derive the following equation:

[0061]

[0062]

[0063] 1) In CCM working mode

[0064] Assuming the change in phase difference α is Δα, then the magnitude of the change in charge ΔQ of the flying capacitor at this time is shown in equation (2), where T s Let D be the switching cycle. Clearly, when D < 0.5, the magnitude of ΔQ is proportional to D and Δα; when D > 0.5, the magnitude of ΔQ is proportional to (1-D) and Δα. Therefore, when D is close to 0 and close to 1, ΔQ is close to 0. Thus, phase-shift control has weak voltage equalization capability when the duty cycle is close to 0 or close to 1.

[0065]

[0066] 2) In DCM working mode

[0067] Assuming the change in phase difference α is Δα, the magnitude of the charge change ΔQ of the flying capacitor at this time is shown in equation (3). Obviously, when D < 0.5, the voltage equalization capability of phase shift control is 0, and voltage equalization cannot be performed.

[0068]

[0069] The specific analysis process will not be elaborated here; those skilled in the art can derive the above equation through simple analysis. In summary, using only phase difference adjustment to balance the flying capacitor voltage results in weak voltage equalization capability when the duty cycle is close to 0 or 1 in CCM operating mode, and inability to equalize voltage when D < 0.5 in DCM operating mode. Therefore, it cannot be guaranteed that the flying capacitor voltage can be maintained at the predetermined value across the entire load range.

[0070] Therefore, this invention proposes a novel capacitor voltage equalization control method for a three-level DC-DC converter. The method adjusts the phase difference (hereinafter referred to as phase difference) between the first and second power transistors of the three-level DC-DC converter based on the error between the voltage value of the flying capacitor and a preset value, and simultaneously adjusts the duty cycle based on the change in phase difference, thereby ensuring that the voltage value of the flying capacitor can be stabilized within a predetermined range under any load.

[0071] Specifically, when the voltage V across capacitor Cf cf >1 / 2V in When the phase difference α decreases by Δα, the duty cycle D1 of power transistor S1 decreases by ΔD, and the duty cycle D2 of power transistor S2 increases by ΔD; when the voltage V across capacitor Cf... cf <1 / 2V inWhen the phase difference α increases by Δα, the duty cycle D1 of power transistor S1 increases by ΔD, and the duty cycle D2 of power transistor S2 decreases by ΔD; and ΔD and Δα have the same trend of change, ΔD increases as Δα increases and decreases as Δα decreases. It should be understood that ΔD and Δα mentioned here refer to the absolute values ​​of the changes. Preferably, Δα and ΔD are directly proportional. Preferably, ΔD = kΔα / (2π), k>0.

[0072] The principle behind the control strategy of the present invention, which can effectively balance the voltage across the flyaway capacitor across the entire load range, is explained in detail below.

[0073] Assuming the initial phase difference α = π, duty cycle D1 = D2 = D, and charging charge Q... c = Discharge charge Q d If the voltage across the capacitor V cf <1 / 2V in If the phase difference α increases by Δα, the duty cycle D1 of power transistor S1 increases by ΔD, and the duty cycle D2 of power transistor S2 decreases by ΔD, and ΔD=k1Δα (where k1=k / (2π)), as Figure 4 and Figure 5 As shown. This is true for both cases where D < 0.5 and D > 0.5, during the charging time T... c The freewheeling time of the inductor current previously decreased due to the increase in phase difference, causing the inductor current I to... L The starting point during charging is higher, and the inductor current I during charging is higher. L There has been an increase, and the charging time T c As the duty cycle D1 increases and becomes longer, the charging charge Q... c Increase; before the discharge time Td, the inductor current I L The freewheeling time increases due to the increase in phase difference, causing the inductor current I to... L The starting point during discharge becomes lower, and I during discharge... L It decreased somewhat, and the discharge time T... d The shortening decreases due to the decrease in duty cycle D2, therefore the discharge charge Q d The decrease results in an increase in charge ΔQ, and the voltage V across capacitor Cf. cf Increase. Similarly, if the voltage across the capacitor V increases... cf >1 / 2V in Then the phase difference α decreases by Δα, D1 decreases by ΔD, D2 increases by ΔD, and ΔD = k1Δα, which reduces the charge by ΔQ, and the flying capacitor voltage V cf Therefore, this control strategy can effectively balance the voltage across the flying capacitor.

[0074] Specifically, in the CCM working mode, by Figure 4The expression for ΔQ can be derived as shown in equation (4):

[0075]

[0076] Since equation (4) requires ΔQ to be greater than 0, that is, Io is at least 0 under the full load range, it is also necessary to ensure that Δα / 2π-ΔD>0. Since ΔD=kΔα / (2π), then (1-k)Δα>0, therefore k is less than 1. It should be understood that k can be any constant less than 1, and of course k can also be a variable, as long as it is guaranteed that k is less than 1 at any time. For example, k can be a function related to the duty cycle D, i.e., k=2D or k=1 / 2D+0.5, etc., which can make k less than 1 at any time. Of course, the above range of k is under the premise of the full load range. In specific applications, if the minimum value of the load current Io is greater than 0, then k greater than 1 can also make ΔQ greater than 0. Therefore, the value of k needs to be selected according to the actual load conditions.

[0077] Obviously, it can be seen from the above equation (4) that in the cases of D<0.5 and D>0.5, the expression of ΔQ consists of two parts. The first part increases with the increase of the load current Io and is independent of the duty cycle D. Therefore, there is no problem of weak voltage equalization capability when the duty cycle D is close to 0 or 1.

[0078] In addition, in DCM working mode, by Figure 5 The expression for ΔQ can be derived as shown in equation (5):

[0079]

[0080] Similarly, equation (5) also needs to satisfy ΔQ > 0. It can be seen from equation (5) that when D is less than 0.5, ΔQ is independent of k, so k only needs to be greater than 0; when D is greater than 0.5, it is necessary to ensure that Δα / 2π-ΔD > 0. As mentioned above, in order to satisfy this equation in the full load range, k can only take the range between 0 and 1.

[0081] Therefore, after adopting the control method of this embodiment, when D<0.5 in DCM mode, ΔQ is obviously greater than 0, and has a certain voltage equalization capability. Thus, this control makes up for the disadvantage that the voltage equalization capability of phase shift control is 0 at this time.

[0082] Figure 6 This is a schematic diagram of the control circuit of a three-level DC-DC converter according to an embodiment of the present invention. Figure 1 Taking the three-level buck converter shown as an example, its control circuit will be explained. Figure 6As shown, the control circuit includes a feedback compensation circuit 1, a capacitor balancing circuit 2, and a drive circuit 3. The feedback compensation circuit 1 is configured to generate a feedback compensation signal Vc based on the error between a feedback signal Vfb representing the output voltage Vout and a reference signal Vref representing the desired output voltage value. The capacitor balancing circuit 2 is configured to generate a feedback compensation signal Vc based on the voltage V across the flying capacitor Cf. cf The phase difference between power transistors S1 and S2 is adjusted based on the error between the input and output values ​​and the preset values. The capacitor balancing circuit 2 includes a capacitor compensation circuit 21 and a sawtooth wave generation circuit 22. The capacitor compensation circuit 21 is configured to adjust the phase difference between the power transistors S1 and S2 based on the voltage V across the flying capacitor Cf. cf The error with the preset value generates a first capacitor compensation signal Δv, and the second capacitor compensation signal Vb is obtained by summing the first capacitor compensation signal Δv and the bias voltage Vbias. The sawtooth wave generation circuit 22 is used to generate a first sawtooth wave signal Vramp1 controlling power transistors S1 and S4 according to the switching cycle, and to generate a second sawtooth wave signal Vramp2 controlling power transistors S2 and S3 according to the switching cycle and the second capacitor compensation signal Vb, wherein the periods of Vramp1 and Vramp2 are equal to the switching cycle and their peak-to-peak values ​​are equal. In this embodiment, the first capacitor compensation signal Δv represents the change in phase difference between the first and second sawtooth wave signals, that is, the change in phase difference Δα between power transistors S1 and S2, and the bias voltage Vbias is equal to half the peak-to-peak value of Vramp1. The driving circuit 3 generates drive signals for power transistors S1-S4 based on the feedback compensation signal Vc and the duty cycle adjustment signal Vd. The duty cycle adjustment signal Vd is proportional to the first capacitor compensation signal Δv, i.e., Vd = kΔv, and is used to adjust the duty cycle of the power transistors. Specifically, the driving circuit 3 generates a first feedback compensation signal Vc1 based on the sum of the feedback compensation signal Vc and the duty cycle adjustment signal Vd, and a second feedback compensation signal Vc2 based on the difference between the feedback compensation signal Vc and the duty cycle adjustment signal Vd. The first compensation signal Vc1 is compared with a first sawtooth wave signal Vramp1 to generate drive signals for power transistors S1 and S4, and the second compensation signal Vc2 is compared with a second sawtooth wave signal Vramp2 to generate drive signals for power transistors S2 and S3. The drive signals for power transistors S1 and S4 are complementary, as are the drive signals for power transistors S2 and S3. The drive signals for power transistors S1 and S2 have a phase difference α.

[0083] Specifically, the feedback compensation circuit 1 includes an error amplifier 1a for receiving a feedback signal Vfb and a reference signal Vref to generate an error signal; and a compensation network 1b for compensating the error signal to generate a feedback compensation signal Vc.

[0084] The capacitor compensation circuit 21 includes a sampling circuit (not shown in the figure) for sampling the voltage V across the flying capacitor Cf.cf The circuit generates a capacitor voltage sampling signal Vcf1; an error amplifier 2a is used to acquire the error between the capacitor voltage sampling signal Vcf1 and the reference signal Def, which represents a preset value (1 / 2Vin); a compensation network 2b is used to compensate for the error to obtain a first capacitor compensation signal Δv; and a bias circuit is used to superimpose the first capacitor compensation signal Δv with a bias voltage Vbias to obtain a second capacitor compensation signal Vb as the output signal of the capacitor compensation circuit 21, wherein the bias voltage Vbias is set so that when the first capacitor compensation signal Δv is zero, the phase difference is π.

[0085] The sawtooth wave generation circuit 22 includes a first sawtooth wave generation circuit 221 and a second sawtooth wave generation circuit 222. The first sawtooth wave generation circuit 221 includes a pulse generator 221a for generating a first clock signal Clk1 according to a set switching period; and a sawtooth wave generator 221b controlled by the first clock signal Clk1 to generate a first sawtooth wave signal Vramp1, wherein the peak-to-peak value of the first sawtooth wave signal Vramp1 is Vpk, and its period is the same as the switching period. The second sawtooth wave generation circuit 222 includes a clock signal generation circuit 222a and a sawtooth wave generator 222b, wherein the clock signal generation circuit 222a is used to generate a second clock signal Clk2 according to a second capacitor compensation signal Vb and the first clock signal Clk1, wherein the second capacitor compensation signal Vb is used to adjust the phase difference between the first clock signal Clk1 and the second clock signal Clk2. Specifically, the clock signal generation circuit 222a includes a comparator cmpr1 and a single-trigger circuit oneshot. The comparator cmpr1 compares the second capacitor compensation signal Vb with the first sawtooth wave signal Vramp to generate a first control signal CTR1. The single-trigger circuit oneshot generates a second clock signal Clk2 based on the first control signal CTR1. The second clock signal Clk2 has the same period as the first clock signal Clk1, and the phase difference between them is adjusted by the second capacitor compensation signal Vb. The sawtooth wave generator 222b is controlled by the second clock signal Clk2 to generate a second sawtooth wave signal Vramp2. The peak-to-peak value of the second sawtooth wave signal Vramp2 is Vpk, and its period is the same as the switching period. That is, the second sawtooth wave signal Vramp2 has the same period and amplitude as the first sawtooth wave signal Vramp1, only their phases are different, and the phase difference between them is adjusted by the second capacitor compensation signal Vb.

[0086] The drive circuit 3 includes a first drive circuit 31, configured to generate a drive signal G for controlling power transistors S1 and S4 based on a comparison result of a first compensation signal Vc1 and a first ramp signal Vramp1. S1 and G S4The sum of the feedback compensation signal Vc and the duty cycle adjustment signal Vd is the first compensation signal Vc1; and the second drive circuit 32 is configured to generate a drive signal G for controlling power transistors S2 and S3 based on the comparison result of the second compensation signal Vc2 and the second ramp signal Vramp2. S2 and G S3 The difference between the feedback compensation signal Vc and the duty cycle adjustment signal Vd is the second compensation signal Vc2. The duty cycle adjustment signal Vd is proportional to the first capacitor compensation signal Δv, i.e., Vd = kΔv, where k = 1 / 2 in this embodiment.

[0087] To simplify the explanation, this embodiment uses the example where the peak-to-peak values ​​of the first sawtooth wave signal Vramp1 and the second sawtooth wave signal Vramp2 are both 1. Those skilled in the art will understand that, according to the control principle, the feedback compensation signal Vc is equal to the duty cycle D without this scheme. The first capacitor compensation signal Δv is used to characterize the change in phase difference Δα between power transistors S1 and S2, where Δv × 2π = Δα. Based on the above principle analysis, ΔD should be equal to kΔα / (2π), that is, ΔD = k × Δv × 2π / (2π) = kΔv. Therefore, adding kΔv to the feedback compensation signal Vc yields the first compensation signal Vc1, which is equivalent to obtaining a new first duty cycle D1 = D + ΔD. Subtracting kΔv from the feedback compensation signal Vc yields the second compensation signal Vc2, which is equivalent to obtaining a new second duty cycle D2 = D - ΔD. Thus, based on adjusting the phase difference, the duty cycle is further adjusted to balance the flying capacitor voltage V. cf This ensures that it can be balanced at a preset value (1 / 2Vin) across the entire load range.

[0088] Specifically, the first driving circuit includes a comparator cmpr2, whose first input terminal (i.e., non-inverting input terminal) receives a first compensation signal Vc1, and its second input terminal (i.e., inverting input terminal) receives a first sawtooth wave signal Vramp1. After comparison, a logic driving signal CTR2 with a duty cycle of D1 is generated at the output terminal. After being amplified by the driver, a driving signal G is generated. S1 and G S4 The second driving circuit includes a comparator cmpr3, whose first input (i.e., non-inverting input) receives the second compensation signal Vc2, and its second input (i.e., inverting input) receives the second sawtooth wave signal Vramp2. After comparison, a logic driving signal CTR3 with a duty cycle of D2 is generated at the output. This signal is then amplified by the driver to generate the driving signal G. S2 G S3 .

[0089] Of course, those skilled in the art will understand that if the peak-to-peak values ​​of the first sawtooth wave signal Vramp1 and the second sawtooth wave signal Vramp2 are not 1, but other values, it will not affect the control method. In this case, the first compensation signal Vc1 is still obtained by feeding back the compensation signal Vc+kΔv, so that the first duty cycle D1=D+ΔD; the second compensation signal Vc2 is obtained by subtracting kΔv from the feedback compensation signal Vc, so that the second duty cycle D2=D-ΔD.

[0090] In summary, when the capacitor voltage V... cf When the value is less than the preset value (1 / 2Vin), the drive signal G S1 and G S2 The phase difference between them increases by Δα, while the duty cycle D1 increases by ΔD and the duty cycle D2 decreases by ΔD, causing the charging charge to be greater than the discharging charge, thus increasing the flying capacitor voltage V. cf Gradually increase to near the preset value; when the capacitor voltage V jumps across... cf When the value is greater than the preset value (1 / 2Vin), the drive signal G S1 and G S2 The phase difference between them decreases by Δα, while the duty cycle D1 decreases by ΔD and the duty cycle D2 increases by ΔD, making the discharged charge greater than the charged charge, thus increasing the flying capacitor voltage V. cf Gradually decrease it to near the preset value.

[0091] Figure 7 This is a control waveform diagram of a three-level DC-DC converter according to an embodiment of the present invention. The flying capacitor voltage V... cf Let's take a value greater than the preset value as an example for explanation.

[0092] Before t1, the circuit is in a steady state, and the capacitor voltage V is flying across. cf The voltage stabilizes at 1 / 2Vin, therefore the second capacitor compensation signal Vb is equal to half the peak-to-peak value of Vramp1, resulting in a phase difference α = π between the second clock signal Clk2 and the first clock signal Clk1. The error between the feedback signal Vfb and the reference signal Vref is compensated by the compensation network to generate a feedback compensation signal Vc, which controls the output voltage Vout to the desired value. The feedback compensation signal Vc generates a first compensation signal Vc1 and a second compensation signal Vc2, respectively, so that when the first sawtooth wave signal Vramp1 rises to the first compensation signal Vc1, the drive signal G... S1 Invalid, G S1 It is effective when the first clock signal Clk1 arrives; when the second sawtooth wave signal Vramp2 rises to the second compensation signal Vc2, the drive signal G is activated. S2 Invalid, G S2 It is effective when the second clock signal Clk2 arrives. Before t1, Vc1 = Vc2 = Vc, therefore D1 = D2 = D.

[0093] At time t1, the voltage across the capacitor V cf When the value is greater than the predetermined value 1 / 2Vin, Δv decreases, the second capacitor compensation signal Vb decreases, and thus the phase difference α decreases. After stabilization, the phase difference between the first clock signal Clk1 and the second clock signal Clk2 is equal to α - Δα, where Δα is positive. Since the first compensation signal Vc1 = Vc + Δv and the second compensation signal Vc2 = Vc - Δv, the first compensation signal Vc1 decreases, and the second compensation signal Vc2 increases. This shortens the time for the first sawtooth wave signal Vramp1 to rise to the first compensation signal Vc1, i.e., the duty cycle D1 decreases. After stabilization, D1 is equal to D - ΔD. Conversely, the time for the second sawtooth wave signal Vramp2 to rise to the second compensation signal Vc2 increases, i.e., the duty cycle D2 increases. After stabilization, D2 = D + ΔD.

[0094] As the duty cycle D1 decreases and D2 increases, the charging time Tr of the flying capacitor cf decreases and the discharging time Tf increases. Simultaneously, due to the decreased phase difference, the freewheeling time of inductor L after the charging phase ends decreases, resulting in a greater average current flowing through inductor L during the discharging phase than during the charging phase. In other words, the amount of charge Q charged into the flying capacitor Cf during the charging phase... c The integral of current IL over charging time Tr is less than the charge Q released by the flying capacitor Cf during the discharge phase. d (The integral of current IL with respect to charging time Tf). Therefore, this reduces the voltage across the flying capacitor Cf to within a predetermined range.

[0095] Similarly, when the voltage across the flying capacitor Cf is less than the predetermined value 1 / 2Vin, Δv increases, and the drive signal G... S1 and G S2 The phase difference increases, and simultaneously, the duty cycle D1 increases while the duty cycle D2 decreases. This results in the average current flowing through inductor L during the discharge phase of the flying capacitor Cf being less than the average current flowing through inductor L during the charging phase of the flying capacitor Cf. In other words, the amount of charge Q charged into the flying capacitor Cf during the charging phase is less than the average current flowing through inductor L during the charging phase of the flying capacitor Cf. c The amount of charge Q released by the flying capacitor Cf during the discharge phase is greater than the amount of charge Q. d Therefore, this causes the voltage across the flying capacitor Cf to increase to a preset value.

[0096] It is easy to understand that the technical solution of this embodiment is also applicable to the case where the duty cycle D ≥ 0.5.

[0097] In this embodiment, by adjusting the phase difference between the first and second power transistors in the three-level DC-DC converter, as well as the duty cycle of each power transistor, the voltage value of the flying capacitor is stabilized at a predetermined value, wherein the change in duty cycle is proportional to the change in phase difference. This scheme is effective under any load condition, which improves the efficiency and stability of the circuit.

[0098] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control circuit for a three-level DC-DC converter, the three-level DC-DC converter comprising first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between the common node of the first and second power transistors and the common node of the third and fourth power transistors, characterized in that, The control circuit is configured as follows: The phase difference between the driving signals of the first power transistor and the second power transistor is adjusted according to the error between the voltage value of the flying capacitor and the preset value, and the duty cycle of the driving signal is adjusted according to the phase difference, so that the voltage value of the flying capacitor is stabilized at the preset value. In this configuration, the duty cycle of the first power transistor changes in the same direction as the phase difference, while the duty cycle of the second power transistor changes in the opposite direction to the phase difference.

2. The control circuit according to claim 1, characterized in that, When the voltage value of the flying capacitor is greater than the preset value, the control circuit is configured to control the phase difference to decrease, the duty cycle of the first power transistor to decrease, and the duty cycle of the second power transistor to increase; when the voltage value of the flying capacitor is less than the preset value, the control circuit is configured to control the phase difference to increase, the duty cycle of the first power transistor to increase, and the duty cycle of the second power transistor to decrease.

3. The control circuit according to claim 1, characterized in that, The change in duty cycle is proportional to the change in phase difference.

4. The control circuit according to claim 3, characterized in that, The proportionality coefficient between the change in duty cycle and the change in phase difference is a constant.

5. The control circuit according to claim 3, characterized in that, The proportionality coefficient between the change in duty cycle and the change in phase difference is a function related to the duty cycle.

6. The control circuit according to claim 1, characterized in that, include: The feedback compensation circuit is configured to compensate for the error between the feedback signal characterizing the output signal of the three-level DC-DC converter and the reference signal characterizing the expected value of the output signal to generate a feedback compensation signal. A capacitor balancing circuit is configured to adjust the phase difference between the drive signals of the first power transistor and the second power transistor based on the error between the voltage value of the flying capacitor and the preset value. The drive circuit is configured to generate drive signals for controlling the power transistors in the three-level DC-DC converter based on the compensation signal and the duty cycle adjustment signal, wherein the duty cycle adjustment signal is generated based on the change in the phase difference.

7. The control circuit according to claim 6, characterized in that, The capacitor balancing circuit includes: A capacitor compensation circuit is configured to generate a first capacitor compensation signal based on the error between the voltage value of the flying capacitor and a preset value, and to obtain a second capacitor compensation signal based on the sum of the first capacitor compensation signal and a bias voltage; and The sawtooth wave generation circuit is configured to generate a first sawtooth wave signal and a second sawtooth wave signal with a period equal to the switching period and peak-to-peak values ​​equal, based on the switching period and the second capacitor compensation signal.

8. The control circuit according to claim 7, characterized in that, The first capacitor compensation signal is used to characterize the change in phase difference between the first sawtooth wave signal and the second sawtooth wave signal.

9. The control circuit according to claim 7, characterized in that, The bias voltage is equal to half the peak-to-peak value of the first sawtooth wave signal.

10. The control circuit according to claim 7, characterized in that, The capacitor compensation circuit includes: The sampling circuit is configured to acquire a capacitor voltage sampling signal that characterizes the voltage value of the flying capacitor; An error amplifier is configured to acquire the error between the capacitor voltage sampling signal and a reference signal characterizing the preset value; A compensation network is configured to compensate for the error to obtain a first capacitance compensation signal; and A bias circuit is configured to acquire the sum of the first capacitor compensation signal and the bias voltage to generate the second capacitor compensation signal.

11. The control circuit according to claim 7, characterized in that, The sawtooth wave generation circuit includes: A first sawtooth wave generating circuit is configured to generate a first clock signal with a period equal to the switching period, and is controlled by the first clock signal to generate the first sawtooth wave signal; and The second sawtooth wave generating circuit is configured to compare the first sawtooth wave signal with the second capacitor compensation signal to generate a second clock signal, and generate the second sawtooth wave signal according to the second clock signal, wherein the peak-to-peak values ​​of the first and second sawtooth wave signals are the same.

12. The control circuit according to claim 11, characterized in that, The second sawtooth wave generating circuit includes: A clock generation circuit is configured to generate a second clock signal based on a second capacitor compensation signal and a first clock signal, wherein the second capacitor compensation signal is used to adjust the phase difference between the first clock signal and the second clock signal; and A sawtooth wave generator, controlled by the second clock signal to generate the second sawtooth wave signal, wherein the period of the second sawtooth wave signal is the same as the period of the second clock signal.

13. The control circuit according to claim 7, characterized in that, The driving circuit includes: A first driving circuit is configured to generate a first driving signal based on a comparison result of a first compensation signal and a first sawtooth wave signal, so as to control the first and fourth power transistors according to the first driving signal; and The second drive circuit is configured to generate a second drive signal based on a comparison result of a second compensation signal and a second sawtooth wave signal, so as to control the second and third power transistors according to the second drive signal, wherein... The first compensation signal is the sum of the feedback compensation signal and the duty cycle adjustment signal; the second compensation signal is the difference between the feedback compensation signal and the duty cycle adjustment signal.

14. The control circuit according to claim 13, characterized in that, The duty cycle adjustment signal is proportional to the first capacitor compensation signal.

15. The control circuit according to claim 1, characterized in that, The preset value is 1 / 2 of the input voltage.

16. A three-level DC-DC converter, characterized in that, include: The first to fourth power transistors are connected in series between the input voltage and the reference ground; A flying capacitor is connected to the common node of the first and second power transistors and the common node of the third and fourth power transistors; as well as The control circuit according to any one of claims 1-15.

17. The three-level DC-DC converter according to claim 16, characterized in that, Also includes: An inductor is connected between the common node of the second and third power transistors and the output terminal.

18. The three-level DC-DC converter according to claim 17, characterized in that, When the three-level DC-DC converter is in continuous current mode, the drive signals of the first power transistor and the fourth power transistor are complementary, the drive signals of the second power transistor and the third power transistor are complementary, and there is a phase difference between the drive signals of the first power transistor and the second power transistor.

19. The three-level DC-DC converter according to claim 17, characterized in that, When the three-level DC-DC converter is in discontinuous current mode, the fourth power transistor is turned on by the turn-off time of the first power transistor and turns off when the inductor current reaches zero; the third power transistor is turned on by the turn-off time of the second power transistor and turns off when the inductor current reaches zero, and there is a phase difference between the drive signals of the first power transistor and the second power transistor.

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