inverters, logic circuits, word line circuits, memories, and integrated systems

Abstract

An inverter (500), logic circuit, word line circuit, memory and integrated system, wherein the inverter (500) mainly comprises an inverting circuit (501) and an adjusting circuit (502-1). The inverting circuit (501) is used for inverting an input signal, and the adjusting circuit (502-1) is used for providing a smaller pull-up voltage for the inverting circuit (501) in standby mode and a larger pull-up voltage for the inverting circuit (501) in working mode according to a control signal. The adjusting circuit (502-1) provides the smaller pull-up voltage in standby mode, thereby reducing the leakage current of the inverter (500) in standby mode, and also reducing the influence on the working performance of the inverting circuit (501) in working mode of the inverter (500), so that the inverter (500) can work normally.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic science, and in particular, to an inverter, a logic circuit, a word line circuit, a memory and an integrated system. BACKGROUND

[0002] An inverter is a basic electronic device and is applied in many logic circuits. Generally, an inverter can include a pull-up end, a pull-down end, a signal input end and a signal output end. The pull-up end is used to receive a pull-up voltage, the pull-down end is used to receive a pull-down voltage (ground), the signal input end is used to receive an input signal, and the signal output end is used to output a signal. The input signal and the output signal are both digital signals, and the output signal is an inverted signal of the input signal.

[0003] It can be understood that in a digital signal, "0" and "1" are generally distinguished by the level of the digital signal. Generally, 1 level is a high level and 0 level is a low level. In the working process of the inverter, if the input signal is 1 level, the inverter can output an output signal of 0 level by using the pull-down voltage. If the input signal is 0 level, the inverter can output an output signal of 1 level by using the pull-up voltage.

[0004] However, the pull-up voltage and the pull-down voltage are generally continuously applied to the pull-up end and the pull-down end of the inverter, so that there is a continuous leakage current in the inverter. For most logic circuits, the inverters therein do not need to work continuously. The leakage current generated in the standby time of the inverter in the non-working time increases the overall power consumption of the logic circuit.

[0005] Therefore, the current inverter needs further research. SUMMARY

[0006] The embodiments of the present application provide an inverter, a logic circuit, a word line circuit, a memory and an integrated system, which are used to reduce the leakage current of the inverter.

[0007] In a first aspect, an inverter is provided. The inverter mainly comprises an inverting circuit and an adjusting circuit. The inverting circuit comprises a first terminal, a second terminal, an input terminal and an output terminal. The first terminal of the inverting circuit can receive a first pull-up voltage or a second pull-up voltage. The second terminal of the inverting circuit can receive a pull-down voltage. The input terminal of the inverting circuit can receive an input signal. The output terminal of the inverting circuit can output an inverted signal of the input signal. The adjusting circuit comprises a first path and a second path connected in parallel. The first terminal of the first path and the first terminal of the second path can be connected to a pull-up power supply. The second terminal of the first path and the second terminal of the second path are connected to the first terminal of the inverting circuit. The adjusting circuit can provide the first pull-up voltage for the inverting circuit through the first path when the first path is turned on, and provide the second pull-up voltage for the inverting circuit through the second path when the second path is turned on. The first pull-up voltage is smaller than the second pull-up voltage.

[0008] In the inverter provided in the embodiments of the present application, the adjusting circuit can provide different pull-up voltages for the inverting circuit. For example, when the inverter is waiting, the adjusting circuit can provide a smaller pull-up voltage, i.e., the first pull-up voltage, for the inverting circuit. In the case where the pull-down voltage received by the second terminal of the inverting circuit is unchanged, the adjusting circuit can reduce the bias voltage between the first terminal and the second terminal of the inverting circuit by providing the smaller pull-up voltage for the first terminal of the inverting circuit, thereby facilitating the reduction of the leakage current generated by the inverting circuit, and thus the leakage current of the inverter when waiting can be reduced. When the inverter is working, the adjusting circuit can provide a larger pull-up voltage, i.e., the second pull-up voltage, for the inverting circuit, which is conducive to reducing the influence of the adjusting circuit on the working performance of the inverting circuit, so that the inverter can work normally.

[0009] For example, the inverter provided in the embodiments of the present application can have at least the following two possible implementation manners:

[0010] In one possible implementation manner, the first path can comprise a first transistor, and the second path can comprise a second transistor. The first transistor is an N-type metal oxide semiconductor transistor (NMOS), and the second transistor is a P-type metal oxide semiconductor transistor (PMOS). The first electrode of the first transistor can be connected to the pull-up power supply. The second electrode of the first transistor is connected to the first terminal of the inverting circuit. The gate of the first transistor is configured to receive a first control signal. The first transistor can provide the first pull-up voltage for the inverting circuit according to the first control signal. The first electrode of the second transistor can be connected to the pull-up power supply. The second electrode of the second transistor is connected to the first terminal of the inverting circuit. The gate of the second transistor is configured to receive a second control signal. The second transistor can provide the second pull-up voltage for the inverting circuit according to the second control signal.

[0011] The threshold loss often occurs when the voltage is transmitted through the transistor. The threshold loss occurs when the high voltage is transmitted through the NMOS, resulting in the voltage reduction, and the threshold loss occurs when the low voltage is transmitted through the PMOS, resulting in the voltage increase. In the inverter provided in the embodiments of the present application, the first transistor is the NMOS. When the first transistor is turned on by the first control signal, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverting circuit through the first transistor. Since the threshold loss occurs when the first transistor transmits the pull-up voltage, the voltage value of the pull-up voltage is reduced, so that the first pull-up voltage with a lower voltage is provided for the first end of the inverting circuit. The second transistor is the PMOS. When the second transistor is turned on by the second control signal, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverting circuit through the second transistor. Since the threshold loss does not occur when the second transistor transmits the pull-up voltage, the second pull-up voltage with a higher voltage is provided for the first end of the inverting circuit, thereby facilitating the reduction of the influence of the adjusting circuit on the working performance of the inverting circuit.

[0012] Generally, the smaller the first pull-up voltage, the smaller the leakage current of the inverter during the standby. Therefore, in the embodiments of the present application, the first transistor can be a high threshold voltage (HVT) transistor. The HVT transistor can generate a larger threshold loss. In the case where the pull-up voltage output by the pull-up power supply is unchanged, the use of the HVT transistor facilitates the further reduction of the first pull-up voltage, thereby facilitating the further reduction of the leakage current of the inverter during the standby.

[0013] Unlike the first pull-up voltage, the closer the second pull-up voltage to the pull-up voltage output by the pull-up power supply, the more conducive to reducing the influence of the adjusting circuit on the working performance of the inverting circuit. Therefore, in the embodiments of the present application, the second transistor can be a standard threshold voltage (SVT) transistor or a low threshold voltage (LVT) transistor. The SVT transistor or the LVT transistor has a larger source-drain current. The use of the SVT transistor or the LVT transistor facilitates the maintenance of the voltage value of the pull-up voltage, so that the second pull-up voltage provided for the inverting circuit is closer to the pull-up voltage output by the pull-up power supply.

[0014] As can be seen from the above description, the channel types of the first transistor and the second transistor are opposite, and the on and off states are also opposite. Therefore, in a possible implementation, the first control signal and the second control signal can be the same signal. In this way, the number of control signals can be reduced, thereby facilitating the simplification of the control of the inverter.

[0015] In another possible implementation, the gate of the first transistor can be connected with the output end of the inverting circuit, and the first control signal can be the output signal of the inverting circuit. In this way, the number of control signals can also be reduced, thereby facilitating the simplification of the control of the inverter.

[0016] For example, when the inverter is waiting, the first control signal is at a level of 1, so that the second transistor is turned off. The turning on or turning off of the first transistor is determined by the output of the inverting circuit. When the input signal of the inverting circuit is at a level of 1, the output signal of the inverting circuit is at a level of 0, and the first transistor is turned off, so that the impedance of the transmission of the pull-up voltage to the ground can be increased, and the leakage current can be reduced. When the input signal of the inverting circuit is at a level of 0, the output signal of the inverting circuit is at a level of 1, and the first transistor is turned on. Since the first transistor can cause threshold loss, the inverting circuit can be provided with a lower first pull-up voltage. When the inverter is working, the first control signal is at a level of 0, so that the second transistor is turned on. At this time, no matter whether the first transistor is turned on or turned off, the second transistor can provide a second pull-up voltage for the inverting circuit, so that the inverter can work normally.

[0017] It should be understood that the above adjusting circuit is only an example, and the embodiments of the present application do not limit the specific implementation mode of the adjusting circuit. For example, the first path can include a first transistor and a first adjusting circuit, and the second path can include a second transistor. One end of the first adjusting resistor is used to connect the pull-up power supply, the other end of the first adjusting resistor is connected with the first electrode of the first transistor, the second electrode of the first transistor is connected with the first end of the inverting circuit, and the gate of the first transistor is used to receive the first control signal. The first electrode of the second transistor is used to connect the pull-up power supply, the second electrode of the second transistor is connected with the first end of the inverting circuit, and the gate of the second transistor is used to receive the second control signal. The first transistor can provide a first pull-up voltage for the inverting circuit according to the first control signal. The second transistor can provide a second pull-up voltage for the inverting circuit according to the second control signal.

[0018] When the inverter is waiting, the first transistor can be turned on by the first control signal. After the first transistor is turned on, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverting circuit through the first transistor and the first adjusting resistor. Since the pull-up voltage will cause a voltage drop when passing through the first adjusting resistor, the first adjusting resistor can provide a smaller pull-up voltage, i.e., the first pull-up voltage, for the inverting circuit, so as to reduce the leakage current in the inverting circuit.

[0019] Generally, the second end of the inverting circuit in the embodiments of the present application can be grounded.

[0020] In a second aspect, the embodiments of the present application provide an inverter, and the main difference between the inverter and the first aspect is that the adjusting circuit in the inverter provided by the second aspect of the embodiments of the present application can provide the first pull-down voltage or the second pull-down voltage for the inverting circuit. The technical effects of the corresponding solutions in the second aspect can be obtained by referring to the technical effects of the corresponding solutions in the first aspect, and the repeated parts will not be described in detail. For example, the inverter includes an inverting circuit and an adjusting circuit. The inverting circuit includes a first end, a second end, an input end and an output end. The first end of the inverting circuit can receive a pull-up voltage. The second end of the inverting circuit can receive the first pull-down voltage or the second pull-down voltage. The input end of the inverting circuit can receive an input signal of a low-leakage inverter. The output end of the inverting circuit can output an inverted signal of the input signal. The adjusting circuit includes a third path and a fourth path in parallel. The first end of the third path and the first end of the fourth path are connected with the second end of the inverting circuit. The second end of the third path and the second end of the fourth path are grounded. When the third path is turned on, the adjusting circuit provides the first pull-down voltage for the inverting circuit through the third path. When the fourth path is turned on, the adjusting circuit provides the second pull-down voltage for the inverting circuit through the fourth path. The first pull-down voltage is greater than the second pull-down voltage.

[0021] In the above-mentioned inverter provided by the embodiments of the present application, the adjusting circuit can provide different pull-down voltages for the inverting circuit. For example, when the inverter is waiting, the adjusting circuit can provide a larger pull-down voltage, i.e., the first pull-down voltage, for the inverting circuit. In the case that the pull-up voltage received by the second end of the inverting circuit is unchanged, the adjusting circuit can reduce the bias voltage between the first end and the second end of the inverting circuit by providing a smaller pull-up voltage for the first end of the inverting circuit, thereby facilitating the reduction of the leakage current generated by the inverting circuit, and thus the leakage current of the inverter when waiting can be reduced. When the inverter is working, the adjusting circuit can provide a larger pull-up voltage, i.e., the second pull-up voltage, for the inverting circuit, which is beneficial to reduce the influence of the adjusting circuit on the working performance of the inverting circuit, so that the inverter can work normally.

[0022] For example, the inverter provided by the embodiments of the present application can have at least the following two possible implementation manners:

[0023] In a possible implementation, the third path can include a third transistor, and the fourth path can include a fourth transistor, where the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor; a first electrode of the third transistor is connected to the second terminal of the inverter circuit, a second electrode of the third transistor is grounded, and a gate of the third transistor is configured to receive a third control signal; a first electrode of the fourth transistor is connected to the second terminal of the inverter circuit, a second electrode of the fourth transistor is grounded, and a gate of the fourth transistor is configured to receive a fourth control signal. In this way, the third transistor can provide the first pull-down voltage for the inverter circuit according to the third control signal, and the fourth transistor can provide the second pull-down voltage for the inverter circuit according to the fourth control signal.

[0024] In the inverter provided in the embodiments of the present application, the third transistor is a PMOS transistor, the first electrode of the third transistor is connected to the second terminal of the inverter circuit, and the second electrode of the third transistor is grounded. When the third control signal turns on the third transistor, the third transistor will have threshold loss when transmitting the pull-down voltage, so that the voltage of the second electrode of the third transistor is higher than the voltage of the first electrode of the third transistor. Therefore, the third transistor can apply a larger pull-down voltage, i.e., the first pull-down voltage, to the second terminal of the inverter circuit. The fourth transistor is an NMOS transistor, and when the fourth control signal turns on the fourth transistor, the fourth transistor will not have threshold loss when transmitting the pull-down voltage. Therefore, the fourth transistor can provide a lower second pull-down voltage (0V) to the second terminal of the inverter circuit, thereby facilitating reduction of the influence of the adjustment circuit on the working performance of the inverter circuit.

[0025] For example, the third transistor can be an HVT transistor. In this case, the threshold loss of the third transistor can be further increased, thereby further increasing the second pull-down voltage applied to the second terminal of the inverter circuit by the third transistor, and thereby facilitating further reduction of the leakage current in the inverter.

[0026] For example, the fourth transistor can be an SVT transistor or an LVT transistor. The SVT transistor or the LVT transistor has a larger source-drain current, thereby facilitating further reduction of the influence of the adjustment circuit on the working performance of the inverter circuit.

[0027] In order to reduce the number of control signals in the inverter, in a possible implementation, the third control signal and the fourth control signal can be the same signal. In another possible implementation, the gate of the third transistor is connected to the output terminal of the inverter circuit, and the third control signal is the output signal of the inverter circuit. The specific principle is similar to that of the first control signal and the second control signal in the first aspect, and thus will not be described herein.

[0028] In another possible implementation, the third path can include a third transistor and a second adjusting resistor, and the fourth path can include a fourth transistor. The first electrode of the third transistor is connected to the second end of the inverting circuit, the second electrode of the third transistor is connected to one end of the second adjusting resistor, the gate of the third transistor is configured to receive a third control signal, and the other end of the second adjusting resistor is grounded. The first electrode of the fourth transistor is connected to the second end of the inverting circuit, the second electrode of the fourth transistor is grounded, and the gate of the fourth transistor is configured to receive a fourth control signal. On this basis, the third transistor can provide a first pull-down voltage for the inverting circuit according to the third control signal, and the fourth transistor can provide a second pull-down voltage for the inverting circuit according to the fourth control signal.

[0029] Generally, the first end of the inverting circuit in the embodiments of the present application can be connected to the pull-up power supply.

[0030] In a third aspect, the embodiments of the present application provide an inverter, which includes a first adjusting circuit, a second adjusting circuit, and an inverting circuit. The inverting circuit includes a first end, a second end, an input end, and an output end. The first end of the inverting circuit can receive a first pull-up voltage or a second pull-up voltage. The second end of the inverting circuit can receive a first pull-down voltage or a second pull-down voltage. The input end of the inverting circuit can receive an input signal. The output end of the inverting circuit can output an inverted signal of the input signal. The first adjusting circuit includes a first path and a second path in parallel. The first end of the first path and the first end of the second path can be connected to a pull-up power supply. The second end of the first path and the second end of the second path are connected to the first end of the inverting circuit. The first adjusting circuit can provide the first pull-up voltage for the inverting circuit through the first path when the first path is turned on, and provide the second pull-up voltage for the inverting circuit through the second path when the second path is turned on. The first pull-up voltage is smaller than the second pull-up voltage. The second adjusting circuit includes a third path and a fourth path in parallel. The first end of the third path and the first end of the fourth path are connected to the second end of the inverting circuit. The second end of the third path and the second end of the fourth path are grounded. The second adjusting circuit can provide the first pull-down voltage for the inverting circuit through the third path when the third path is turned on, and provide the second pull-down voltage for the inverting circuit through the fourth path when the fourth path is turned on. The first pull-down voltage is greater than the second pull-down voltage.

[0031] In the inverter provided by the embodiment of the present application, the first adjusting circuit can provide different pull-up voltages for the inverting circuit, and the second adjusting circuit can provide different pull-down voltages for the inverting circuit. For example, when the inverter is waiting, the first adjusting circuit can provide a smaller pull-up voltage, i.e., a first pull-up voltage, for the inverting circuit, and the second adjusting circuit can provide a larger pull-down voltage, i.e., a first pull-down voltage, for the inverting circuit. Thus, the bias voltage between the first terminal and the second terminal of the inverting circuit can be reduced, and the leakage current generated by the inverting circuit can be reduced, so that the leakage current of the inverter when waiting can be reduced. When the inverter is working, the first adjusting circuit can provide a larger pull-up voltage, i.e., a second pull-up voltage, for the inverting circuit, and the second adjusting circuit can provide a smaller pull-down voltage, i.e., a second pull-down voltage, for the inverting circuit, so as to reduce the influence of the first adjusting circuit and the second adjusting circuit on the working performance of the inverting circuit, and the inverter can work normally.

[0032] For example, the first adjusting circuit provided by the embodiment of the present application can have at least the following two possible implementation manners:

[0033] In a possible implementation manner, the first path can include a first transistor, and the second path can include a second transistor, and the first transistor is an N-type metal oxide semiconductor transistor (NMOS), and the second transistor is a P-type metal oxide semiconductor transistor (PMOS). The first electrode of the first transistor can be connected to a pull-up power supply, the second electrode of the first transistor is connected to the first terminal of the inverting circuit, and the gate of the first transistor is configured to receive a first control signal; the first electrode of the second transistor can be connected to the pull-up power supply, the second electrode of the second transistor is connected to the first terminal of the inverting circuit, and the gate of the second transistor is configured to receive a second control signal; the first transistor can provide a first pull-up voltage for the inverting circuit according to the first control signal; and the second transistor can provide a second pull-up voltage for the inverting circuit according to the second control signal.

[0034] The threshold loss often occurs when the voltage is transmitted through the transistor. The threshold loss occurs when the high voltage is transmitted through the NMOS, resulting in the voltage reduction, and the threshold loss occurs when the low voltage is transmitted through the PMOS, resulting in the voltage increase. In the inverter provided in the embodiments of the present application, the first transistor is the NMOS. When the first transistor is turned on by the first control signal, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverting circuit through the first transistor. Since the threshold loss occurs when the first transistor transmits the pull-up voltage, the voltage value of the pull-up voltage is reduced, so that the first pull-up voltage with a lower voltage is provided for the first end of the inverting circuit. The second transistor is the PMOS. When the second transistor is turned on by the second control signal, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverting circuit through the second transistor. Since the threshold loss does not occur when the second transistor transmits the pull-up voltage, the second pull-up voltage with a higher voltage is provided for the first end of the inverting circuit, thereby facilitating the reduction of the influence of the adjusting circuit on the working performance of the inverting circuit.

[0035] Generally, the smaller the first pull-up voltage, the smaller the leakage current of the inverter during the standby. Therefore, in the embodiments of the present application, the first transistor can be a high threshold voltage (HVT) transistor. The HVT transistor can generate a larger threshold loss. In the case where the pull-up voltage output by the pull-up power supply is unchanged, the use of the HVT transistor facilitates the further reduction of the first pull-up voltage, thereby facilitating the further reduction of the leakage current of the inverter during the standby.

[0036] Unlike the first pull-up voltage, the closer the second pull-up voltage to the pull-up voltage output by the pull-up power supply, the more conducive to the reduction of the influence of the adjusting circuit on the working performance of the inverting circuit. Therefore, in the embodiments of the present application, the second transistor can be a standard threshold voltage (SVT) transistor or a low threshold voltage (LVT) transistor. The SVT transistor or the LVT transistor has a larger source-drain current. The use of the SVT transistor or the LVT transistor facilitates the maintenance of the voltage value of the pull-up voltage, so that the second pull-up voltage provided for the inverting circuit is closer to the pull-up voltage output by the pull-up power supply.

[0037] As can be seen from the above description, the channel types of the first transistor and the second transistor are opposite, and the on and off states are also opposite. Therefore, in a possible implementation, the first control signal and the second control signal can be the same signal. In this way, the number of control signals can be reduced, thereby facilitating the simplification of the control of the inverter.

[0038] In another possible implementation, the gate of the first transistor can be connected with the output end of the inverting circuit, and the first control signal can be the output signal of the inverting circuit. In this way, the number of control signals can also be reduced, thereby facilitating the simplification of the control of the inverter.

[0039] It should be understood that the above first adjusting circuit is only an example, and embodiments of the present application do not limit the specific implementation of the first adjusting circuit. For example, the first path can include a first transistor and the first adjusting circuit, and the second path can include a second transistor; wherein one end of the first adjusting resistor is used to connect the pull-up power supply, the other end of the first adjusting resistor is connected with the first electrode of the first transistor, the second electrode of the first transistor is connected with the first end of the inverter circuit, and the gate of the first transistor is used to receive the first control signal; the first electrode of the second transistor is used to connect the pull-up power supply, the second electrode of the second transistor is connected with the first end of the inverter circuit, and the gate of the second transistor is used to receive the second control signal; the first transistor can provide the first pull-up voltage for the inverter circuit according to the first control signal; and the second transistor can provide the second pull-up voltage for the inverter circuit according to the second control signal.

[0040] When the inverter is waiting, the first transistor can be turned on by the first control signal. After the first transistor is turned on, the pull-up voltage output by the pull-up power supply can be transmitted to the first end of the inverter circuit through the first transistor and the first adjusting resistor. Since the pull-up voltage will generate a voltage drop when passing through the first adjusting resistor, the first adjusting resistor can provide a smaller pull-up voltage, i.e. the first pull-up voltage, for the inverter circuit, thereby reducing the leakage current in the inverter circuit.

[0041] For example, the second adjusting circuit provided by the embodiments of the present application can have at least the following two possible implementation manners:

[0042] In one possible implementation manner, the third path can include a third transistor, and the fourth path can include a fourth transistor, wherein the third transistor is a PMOS, and the fourth transistor is an NMOS; the first electrode of the third transistor is connected with the second end of the inverter circuit, the second electrode of the third transistor is grounded, and the gate of the third transistor is used to receive the third control signal; the first electrode of the fourth transistor is connected with the second end of the inverter circuit, the second electrode of the fourth transistor is grounded, and the gate of the fourth transistor is used to receive the fourth control signal. On this basis, the third transistor can provide the first pull-down voltage for the inverter circuit according to the third control signal; and the fourth transistor can provide the second pull-down voltage for the inverter circuit according to the fourth control signal.

[0043] In the inverter provided in the embodiments of the present application, the third transistor is a PMOS, the first electrode of the third transistor is connected to the second end of the adjusting circuit, and the second electrode of the third transistor is grounded. When the third transistor is turned on by the third control signal, the third transistor will have threshold loss when transmitting the pull-down voltage, so that the voltage of the second electrode of the third transistor is higher than the voltage of the first electrode. Therefore, the third transistor can apply a larger pull-down voltage, i.e., the first pull-down voltage, to the second end of the inverting circuit. The fourth transistor is an NMOS, and when the fourth transistor is turned on by the fourth control signal, the fourth transistor will not have threshold loss when transmitting the pull-down voltage, so that the fourth transistor provides a lower (0V) second pull-down voltage to the second end of the inverting circuit, thereby facilitating the reduction of the influence of the adjusting circuit on the working performance of the inverting circuit.

[0044] For example, the third transistor can be an HVT transistor. In this case, the threshold loss generated by the third transistor can be further increased, thereby further increasing the second pull-down voltage applied by the third transistor to the second end of the inverting circuit, thereby facilitating the further reduction of the leakage current in the inverter.

[0045] For example, the fourth transistor can be an SVT transistor or an LVT transistor. The SVT transistor or the LVT transistor has a larger source-drain current, which facilitates the further reduction of the influence of the adjusting circuit on the working performance of the inverting circuit.

[0046] In order to reduce the number of control signals in the inverter, in a possible implementation, the third control signal and the fourth control signal can be the same signal. In another possible implementation, the gate of the third transistor is connected to the output end of the inverting circuit, and the third control signal is the output signal of the inverting circuit. The specific principle is similar to the first control signal and the second control signal in the first aspect, and thus will not be described here.

[0047] In another possible implementation, the third path can include a third transistor and a second adjusting resistor, and the fourth path can include a fourth transistor. The first electrode of the third transistor is connected to the second end of the inverting circuit, the second electrode of the third transistor is connected to one end of the second adjusting resistor, the gate of the third transistor is configured to receive the third control signal, and the other end of the second adjusting resistor is grounded. The first electrode of the fourth transistor is connected to the second end of the inverting circuit, the second electrode of the fourth transistor is grounded, and the gate of the fourth transistor is configured to receive the fourth control signal. On this basis, the third transistor can provide the first pull-down voltage to the inverting circuit according to the third control signal, and the fourth transistor can provide the second pull-down voltage to the inverting circuit according to the fourth control signal.

[0048] In a fourth aspect, an embodiment of the present application provides a logic circuit, which can include a control circuit and an inverter provided in any one of the first aspect to the third aspect; wherein the control circuit can output a control signal to the inverter. The technical effects of the corresponding solutions in the third aspect can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repeated parts will not be described in detail.

[0049] Specifically, the control circuit can be connected with the control end of the adjusting circuit in the inverter, and the control circuit can output a control signal to the inverter to control the adjusting circuit in the inverter to provide the first pull-up voltage or the second pull-up voltage for the inverting circuit. The control circuit can also output a control signal to the inverter to control the adjusting circuit in the inverter to provide the first pull-down voltage or the second pull-down voltage for the inverting circuit.

[0050] In a fifth aspect, an embodiment of the present application provides a word line circuit, and the technical effects of the corresponding solutions in the fifth aspect can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect to the third aspect. For example, the word line circuit provided by an embodiment of the present application can include a signal generation circuit and an inverter chain, wherein the inverter chain includes an inverter provided in the first aspect or the second aspect. The signal generation circuit is connected with the control end of the inverter in the inverter chain, and the signal generation circuit can generate a control signal for controlling the inverter.

[0051] In the word line circuit provided by an embodiment of the present application, the signal generation circuit can generate a control signal. When the word line circuit is waiting, the control signal can control the adjusting circuit in the inverter in the inverter chain to provide the first pull-up voltage or the first pull-down voltage for the inverting circuit, thereby reducing the leakage current of each inverter, and further facilitating to reduce the power consumption of the word line circuit. When the word line circuit is working, the control signal can control the adjusting circuit in the inverter in the inverter chain to provide the second pull-up voltage or the second pull-down voltage for the inverting circuit, thereby reducing the influence of the adjusting circuit on the working performance of the inverting circuit, and further facilitating to ensure the working performance of the word line circuit.

[0052] In the word line circuit provided by an embodiment of the present application, there are various possible implementation manners of the inverter in the inverter chain, for example:

[0053] For example, the inverter chain in the word line circuit includes at least one first inverter. In the first inverter, the adjusting circuit can include a first transistor and a second transistor, wherein the first transistor is NMOS and the second transistor is PMOS; a first electrode of the first transistor is connected to the pull-up power supply, a second electrode of the first transistor is connected to the first end of the inverter circuit, and a gate of the first transistor can receive a first control signal; a first electrode of the second transistor is connected to the pull-up power supply, a second electrode of the second transistor is connected to the first end of the inverter circuit, and a gate of the second transistor can also receive the first control signal.

[0054] In the embodiments of the present application, the control signal generated by the signal generation circuit includes a first control signal. In the first inverter, the first transistor and the second transistor are controlled by the first control signal at the same time. For example, when the first inverter is waiting, the first control signal is at a level of 1, so that the first transistor is turned on and the second transistor is turned off, and the adjusting circuit can provide a first pull-up voltage for the inverter circuit to reduce the leakage current. When the first inverter is working, the first control signal is at a level of 0, so that the first transistor is turned off and the second transistor is turned on, so that the adjusting circuit can provide a second pull-up voltage for the inverter circuit, so that the first inverter can work normally.

[0055] For another example, in the word line circuit provided by the embodiments of the present application, the inverter chain in the word line circuit can also include at least one second inverter. In the second inverter, the adjusting circuit can include a first transistor and a second transistor, wherein the first transistor is NMOS and the second transistor is PMOS; a first electrode of the first transistor is connected to the pull-up power supply, a second electrode of the first transistor is connected to the first end of the inverter circuit, and a gate of the first transistor is connected to the output end of the inverter circuit; a first electrode of the second transistor is connected to the pull-up power supply, a second electrode of the second transistor is connected to the first end of the inverter circuit, and a gate of the second transistor can receive a first control signal.

[0056] The control signal generated by the signal generation circuit in the embodiment of the present application comprises a first control signal. In the second inverter, the output signal of the inverting circuit controls the first transistor, and the first control signal controls the second transistor. For example, when the second inverter is waiting, the first control signal is at a level of 1, so that the second transistor is turned off. The turn-on or turn-off of the first transistor is determined by the output of the inverting circuit. When the input signal of the inverting circuit is at a level of 1, the output signal of the inverting circuit is at a level of 0, and the first transistor is turned off, so that the impedance of the pull-up voltage transmitted to the ground can be increased, and the leakage current can be reduced. When the input signal of the inverting circuit is at a level of 0, the output signal of the inverting circuit is at a level of 1, and the first transistor is turned on, so that the first pull-up voltage can be provided for the inverting circuit. When the second inverter is working, the first control signal is at a level of 0, so that the second transistor is turned on. At this time, no matter whether the first transistor is turned on or turned off, the second pull-up voltage can be provided for the inverting circuit by the second transistor, so that the second inverter can work normally.

[0057] For example, the first transistor can be a high-threshold-voltage (HVT) transistor. The second transistor can be a standard-threshold-voltage (SVT) transistor or a low-threshold-voltage (LVT) transistor.

[0058] For example, in the word line circuit provided in the embodiment of the present application, the inverter chain in the word line circuit can further comprise at least one third inverter. In the third inverter, the adjusting circuit can comprise a third transistor and a fourth transistor, wherein the third transistor is a PMOS, and the fourth transistor is an NMOS; a first electrode of the third transistor is connected with a second end of the inverting circuit, a second electrode of the third transistor is grounded, and a gate of the third transistor can receive a third control signal; a first electrode of the fourth transistor is connected with the second end of the inverting circuit, a second electrode of the fourth transistor is grounded, and a gate of the fourth transistor can receive the third control signal.

[0059] The control signal generated by the signal generation circuit in the embodiment of the present application can further comprise a third control signal. In the word line circuit, the third transistor and the fourth transistor are simultaneously controlled by the third control signal. For example, when the third inverter is waiting, the third control signal is at a level of 0, so that the third transistor is turned on, and the fourth transistor is turned off. The adjusting circuit can provide the first pull-down voltage for the inverting circuit, so as to reduce the leakage current. When the third inverter is waiting, the first control signal is at a level of 1, so that the third transistor is turned off, and the fourth transistor is turned on. The adjusting circuit can provide the second pull-down voltage for the inverting circuit, so that the third inverter can work normally.

[0060] For another example, in the word line circuit provided in the embodiments of the present application, the inverter chain in the word line circuit can further include at least one fourth inverter. In the fourth inverter, the adjustment circuit can include a third transistor and a fourth transistor, wherein the third transistor is a PMOS and the fourth transistor is an NMOS; a first electrode of the third transistor is connected with a second terminal of the inverter circuit, a second electrode of the third transistor is grounded, and a gate of the third transistor is connected with an output terminal of the inverter circuit; a first electrode of the fourth transistor is connected with the second terminal of the inverter circuit, a second electrode of the fourth transistor is grounded, and a gate of the fourth transistor can receive a third control signal.

[0061] In the embodiments of the present application, the control signal generated by the signal generation circuit includes the third control signal. In the fourth inverter, the output signal of the inverter circuit controls the third transistor, and the third control signal controls the fourth transistor. For example, when the fourth inverter is waiting, the third control signal is at a 0 level, so that the fourth transistor is turned off. The conduction or non-conduction of the third transistor is determined by the output condition of the inverter circuit. When the input signal of the inverter circuit is at a 1 level, the output signal of the inverter circuit is at a 0 level, and the first transistor is turned on, so that the first pull-down voltage can be provided for the inverter circuit. When the input signal of the inverter circuit is at a 0 level, the output signal of the inverter circuit is at a 1 level, and the third transistor is turned off, so that the impedance of the transmission of the pull-up voltage to the ground can be increased, and the leakage current can be reduced. When the fourth inverter is working, the third control signal is at a 1 level, so that the fourth transistor is turned on. At this time, no matter whether the third transistor is turned on or turned off, the second pull-down voltage can be provided for the inverter circuit by the fourth transistor, so that the fourth inverter can work normally.

[0062] For example, the third transistor can be an HVT transistor. The fourth transistor can be an SVT transistor or an LVT transistor.

[0063] In a possible implementation, the word line circuit can further include a switch circuit; wherein a first input terminal of the switch circuit is connected with the signal generation circuit, a second input terminal of the switch circuit is used for receiving a clock signal, and an output terminal of the switch circuit is connected with the inverter chain; on this basis, the switch circuit can output an initial signal according to the control signal and the clock signal; and the inverter chain can output the word line signal according to the initial signal.

[0064] The word line signal can control the opening or closing of the memory cell row corresponding to the word line circuit. In the embodiments of the present application, in order to make the word line signal completely close the memory cell row, in one possible implementation, the adjusting circuit is connected to the first end of the inverter circuit and the second end of the inverter circuit is grounded in the inverter at the output end of the inverter chain. In this case, the second end of the inverter circuit is grounded, so that the inverter circuit can output a word line signal with a lower signal voltage (close to 0V), thereby completely closing the memory cell row, which is beneficial to reducing the power consumption of the memory cell row.

[0065] As can be seen from the above embodiments, the control signal generated by the signal generation circuit can control the adjusting circuit of the inverter in the inverter chain. For example, the signal generation circuit can generate a control signal of a first level according to the decoding selection signal when the decoding selection signal indicates that the word line circuit is waiting, and generate a control signal of a second level according to the decoding selection signal when the decoding selection signal indicates that the word line circuit is working. The control signal of the first level can turn on the first path in the adjusting circuit, and the control signal of the second level can turn on the second path in the adjusting circuit; or the control signal of the first level can turn on the third path in the adjusting circuit, and the control signal of the second level can turn on the fourth path in the adjusting circuit.

[0066] In the sixth aspect, the technical effects of the corresponding solutions can be referred to the technical effects of the corresponding solutions in the fifth aspect, and the repeated parts will not be described in detail. In the memory provided by the embodiments of the present application, the output ends of the N word line circuits are connected to the N memory cell rows one by one. Each of the N word line circuits can output a word line signal, and the word line signal can open or close the memory cell row corresponding to the word line circuit.

[0067] In the memory, a plurality of memory cells are often integrated, that is, the value of N is large, and the inverter chain of the word line circuit further includes at least one inverter (which can include a large number of inverters), so that the memory as a whole includes a large number of inverters. There is a large leakage current in the existing inverters, and the superposition effect caused by the number of inverters further causes a large power consumption of the memory. The embodiments of the present application can reduce the leakage current of a single inverter, thereby significantly reducing the power consumption of the memory.

[0068] Exemplarily, the memory provided by the embodiments of the present application can further comprise a decoding circuit, which can output decoding selection signals to N word line circuits respectively, wherein the decoding selection signal output to the target word line circuit can indicate that the target word line circuit works, and the decoding selection signal output to the word line circuit other than the target word line circuit can indicate that the word line circuit waits; each word line circuit in the memory can output a word line signal according to the decoding selection signal, wherein when the decoding selection signal indicates that the word line circuit works, the word line signal output by the word line circuit can open the storage unit row corresponding to the word line circuit, and when the decoding selection signal indicates that the word line circuit waits, the word line signal output by the word line circuit can close the storage unit row corresponding to the word line circuit.

[0069] In a seventh aspect, the embodiments of the present application provide an integrated system, which can be an integrated chip such as a CPU, a SoC, an ECU, etc., or an electronic device. Exemplarily, the integrated system can comprise a processor and the memory provided in any one of the above-mentioned sixth aspects, wherein the processor can send address information to the memory.

[0070] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0071] Figure 1 An integrated system structure schematic diagram;

[0072] Figure 2 A word line circuit structure schematic diagram;

[0073] Figure 3 A common inverter circuit structure schematic diagram;

[0074] Figure 4a A hibernation inverter circuit structure schematic diagram;

[0075] Figure 4b An inverter circuit structure schematic diagram comprising a hibernation inverter;

[0076] Figure 5 One of the inverter circuit structure schematic diagrams provided by the embodiments of the present application;

[0077] Figure 6 Another of the inverter circuit structure schematic diagrams provided by the embodiments of the present application;

[0078] Figure 7 Still another of the inverter circuit structure schematic diagrams provided by the embodiments of the present application;

[0079] Figure 8 Still another of the inverter circuit structure schematic diagrams provided by the embodiments of the present application;

[0080] Figure 9 Fig. 5 is a schematic diagram of a circuit structure of an inverter according to an embodiment of the present application;

[0081] Figure 10 Fig. 6 is a schematic diagram of a circuit structure of an inverter according to an embodiment of the present application;

[0082] Figure 11 Fig. 7 is a schematic diagram of a circuit structure of an inverter according to an embodiment of the present application;

[0083] Figure 12 Fig. 8 is a schematic diagram of a logic circuit according to an embodiment of the present application;

[0084] Figure 13 Fig. 9 is a schematic diagram of a possible connection relationship between inverters according to an embodiment of the present application;

[0085] Figure 14 Fig. 10 is a comparison diagram of a leakage simulation effect according to an embodiment of the present application;

[0086] Figure 15 Fig. 11 is a comparison diagram of a performance simulation effect according to an embodiment of the present application;

[0087] Figure 16 Fig. 12 is a comparison diagram of a peak current simulation effect according to an embodiment of the present application. DETAILED DESCRIPTION

[0088] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. The specific operation method in the method embodiment can also be applied to the device embodiment or the system embodiment. It should be noted that in the description of the present application, “at least one” refers to one or more, wherein more refers to two or more. Therefore, in the present application, “more” can also be understood as “at least two”. “And / or”, which describes the association relationship of the associated objects, means that there can be three relationships, for example, A and / or B, which can represent the existence of A alone, the existence of A and B together, and the existence of B alone. In addition, the character “ / ”, if not specially stated, generally represents an “or” relationship between the associated objects. In addition, it should be understood that in the description of the present application, “first”, “second”, etc. are used only for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0089] It should be noted that the "connection" in the embodiments of the present application refers to electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements. For example, A and B are connected, which can be direct connection between A and C, direct connection between C and B, and connection between A and B through C.

[0090] It should be noted that, for the convenience of description, the first electrode of the transistor in the present application can refer to the drain, and the second electrode can refer to the source. Alternatively, the first electrode of the transistor can refer to the source, and the second electrode of the transistor can refer to the drain.

[0091] The inverter is a basic electronic device that can receive an input signal and output an output signal opposite to the input signal. Generally, the input signal of the inverter can be a digital signal, and the level of the input signal can be divided into 1 level and 0 level. If the inverter receives a 1 level input signal, the inverter can output a 0 level output signal, and if the inverter receives a 0 level input signal, the inverter can output a 1 level output signal.

[0092] It should be understood that "1" and "0" in 1 level and 0 level in digital signal are "1" and "0" in logic operation, and are not the voltage value of the signal voltage of the digital signal. In most cases, 1 level in digital signal refers to that the signal voltage of the digital signal is greater than the threshold voltage, and 0 level refers to that the signal voltage of the digital signal is less than the threshold voltage. For the convenience of description, the high level is used to represent 1 level in digital signal, and the low level is used to represent 0 level in digital signal in the embodiments of the present application.

[0093] The inverter is applied in many logic circuits, for example, there are a large number of inverters in the word line circuit of the memory such as static random access memory (SRAM). Figure 1 An exemplary structure schematic diagram of an integrated system is shown, which can be a central processing unit (CPU), a system on chip (SOC), an electronic control unit (ECU), etc. The integrated system 100 can also be an electronic device, such as a smart phone, a notebook computer, a tablet computer, etc. The embodiments of the present application do not limit this too much.

[0094] As Figure 1As shown, the integrated system 100 includes a processor 101 and a memory 102, where the memory 102 can be an SRAM, a dynamic random access memory (DRAM), or the like. Figure 1 In an embodiment, the memory 102 mainly includes a plurality of memory cells, which form an N x M memory array, where M and N are both integers greater than or equal to 1.

[0095] In addition, the memory 102 also includes a row decoding circuit 1021 and word line circuits 1 to N, where the input ends of the word line circuits 1 to N are respectively connected to the output ends of the row decoding circuit 1021, and the output ends of the word line circuits 1 to N are respectively connected to the control ends of the N rows of memory cells in a one-to-one correspondence.

[0096] In the running process of the processor 101, the data in the memory 102 can be read and written. Specifically, the processor 101 can send address information to the memory 102, where the address information can indicate the storage address of the target data in the memory 102. For example, the address information sent by the processor 101 includes row address information and column address information, and the memory 102 connected to the processor 101 can receive the address information output by the processor 101. In the memory 102, the row decoding circuit 1021 is a row decoder, which can decode the row address information to determine the target memory cell row where the target data is located, and the target word line circuit corresponding to the target memory cell row. For example, the row decoding circuit 1021 can determine that the target memory cell row is the second row of memory cells, and the target word line circuit is the word line circuit 2.

[0097] The row decoding circuit 1021 can further send decoding selection signals to the word line circuits 1 to N respectively. Wherein the decoding selection signal sent to the target word line circuit can indicate that the target word line circuit works, and the decoding selection signal sent to the other word line circuits except the target word line circuit can indicate that the other word line circuits wait.

[0098] For example, in the above example, the word line circuit 2 is the target word line circuit, so the decoding selection signal sent to the word line circuit 2 can indicate that the word line circuit 2 works, and the decoding selection signals sent to the word line circuits 1 and 3 to N can indicate that the word line circuits wait.

[0099] In one possible example, the decoding selection signal can indicate that the word line circuit works or waits through different level states. For example, when the decoding selection signal is at a high level, it can indicate that the word line circuit receiving the decoding selection signal works, and when the decoding selection signal is at a low level, it can indicate that the word line circuit receiving the decoding selection signal waits.

[0100] In yet another possible example, the decode selection signal can also carry selection information, and the word line circuit can determine the next operation or standby by analyzing the selection information carried by the decode selection signal.

[0101] The word line circuit can operate or standby according to the decode selection signal. The word line circuit can output a word line signal to the corresponding memory cell row, and the word line signal can turn on or turn off the corresponding memory cell row. Generally, the word line signal turns on or turns off the memory cell row by different level states. For example, when the word line signal is at a high level, the word line signal can turn on the memory cell row, and when the word line signal is at a low level, the word line signal can turn off the memory cell row. When the decode selection signal indicates that the word line circuit operates, the word line signal output by the word line circuit can be at a high level, thereby turning on the corresponding memory cell row. When the decode selection signal indicates that the word line circuit standby, the word line circuit can be kept at a low level, thereby turning off the corresponding memory cell row.

[0102] As shown in Figure 1 , the memory 102 further includes a read-write driving circuit 1022 and a column decode circuit 1023. The column decode circuit 1023 can decode the column address information to determine the target column memory cell where the target data is located. Further, the column decode circuit 1023 sends indication information to the read-write driving circuit 1022 to instruct the read-write driving circuit 102 to read and write data in the column target memory cell. At this time, only the target memory cell row is turned on, so the read-write driving circuit 102 can read and write data in the target column memory cell in the target memory cell row.

[0103] As can be seen from the above example, the memory 102 includes a large number of word line circuits, and the word line circuits generally have the same circuit structure. In the commonly used word line circuit, a large number of inverters are further used. Therefore, the performance of the inverter has a huge cumulative impact on the performance of the memory 102.

[0104] Figure 2 An exemplary structure diagram of a word line circuit is shown, as shown in Figure 2 , the word line circuit 200 mainly includes a signal generation circuit 201 and an inverter chain 203, and in some possible implementation manners, the word line circuit 200 can further include a switch circuit 202. Next, the signal generation circuit 201, the switch circuit 202 and the inverter chain 203 are further exemplarily described.

[0105] I. Signal Generation Circuit 201

[0106] As shown in Figure 2As shown, the signal generation circuit 201 may include multiple inverters connected in series (inverters I1 to I3). The input of the signal generation circuit 201 can receive a decoding selection signal, generate a control signal WS1, and control the switching circuit 202 to output an initial signal S0 via the control signal WS1. The multiple inverters in the signal generation circuit 201 can amplify the signal transmitted in the signal generation circuit 201 stage by stage, so that the control signal WS1 output by the signal generation circuit 201 has a large signal strength, sufficient to drive the switching circuit 202 to operate.

[0107] Specifically, when the decoding selection signal indicator word line circuit 200 is working, the control signal WS1 generated by the signal generation circuit 201 can turn on the switching circuit 202. When the decoding selection signal indicator word line circuit 200 is waiting, the control signal WS1 generated by the signal generation circuit 201 can turn off the switching circuit 202.

[0108] In one possible implementation, such as Figure 2 As shown, the signal generation circuit 201 can also generate a control signal WS2, and the control signal WS2 and the control signal WS1 are inverse signals. Figure 2 In the signal generation circuit 201 shown, the phase of the control signal WS2 is the same as that of the decoding selection signal, and the phase of the control signal WS1 is opposite to that of the decoding selection signal. Assuming the decoding selection signal is high, the control signal WS2 is also high, while the control signal WS1 is low. The control signals WS2 and WS1 together control the switching circuit 202 to output the initial signal S0.

[0109] II. Switching circuit 202 and inverter chain

[0110] like Figure 2 As shown, the signal generation circuit 201 can generate control signal WS1 and control signal WS2, which together control the switching circuit 202 to output the initial signal S0. In this case, as... Figure 2 As shown, the switching circuit 202 may include transistor Ta, transistor Tb, transistor Tc and NAND gate A.

[0111] In the switching circuit 202, the first electrode of transistor Ta is connected to the first electrode of transistor Tb, and the second electrode of transistor Ta is connected to the second electrode of transistor Tb and the first input terminal of NAND gate A. The gate (control electrode) of transistor Ta is connected to the output terminal of inverter I3, and the gate of transistor Tb is connected to the output terminal of inverter I2.

[0112] The first electrode of transistor Tc is connected to the first input terminal of NAND gate A, the second electrode of transistor Tc is grounded, and the gate of transistor Tc is connected to the output terminal of inverter I3. The second input terminal of NAND gate A is connected to the reference signal R, and the output terminal of NAND gate A is connected to the input terminal of inverter chain 203. The reference signal R is an adaptive signal; during the operation of word line circuit 200, when clock signal Clk is high, reference signal R is also high, and NAND gate A can output a low-level signal. After read / write drive circuit 1022 completes read / write, it can switch reference signal R to low, and NAND gate A can output a high-level initial signal S0.

[0113] In this configuration, transistors Tb and Tc have the same channel type, which is the opposite of that of transistor Ta. For example, transistor Ta is a P-type metal-oxide-semiconductor (PMOS). Transistors Tb and Tc are N-type metal-oxide-semiconductor (NMOS).

[0114] The switching circuit 202 can output an initial signal S0 based on the received clock signal Clk, control signal WS1, and control signal WS2. The inverter chain 203 includes multiple inverters connected in series (inverter 1 to inverter 3). The inverter chain 203 receives the initial signal S0 and generates word line signals based on it.

[0115] Next, with Figure 2 Taking the word line circuit shown as an example, the states of the word line circuit 200 during operation and waiting will be further illustrated.

[0116] Work status

[0117] When the row decoding circuit 1021 outputs a high-level decoding selection signal to the word line circuit 200 to indicate that the word line circuit 200 is working, the signal generation circuit 201 generates a high-level control signal WS2 and a low-level control signal WS1. This causes transistors Ta and Tb to turn on, transistor Tc to turn off, and the clock signal Clk can be transmitted to the first input terminal of the NAND gate A.

[0118] When the clock signal Clk is low, the reference signal R is also low, and the NAND gate A outputs a high-level initial signal S0. The inverter chain 203 receives this high-level initial signal S0, and after being transmitted sequentially through inverters 1 to 3, it outputs a low-level word line signal, thereby turning off the memory cell row corresponding to the word line circuit 200.

[0119] When the clock signal Clk rises to a high level, the reference signal R also rises to a high level, and the NAND gate A outputs a low-level initial signal S0. The inverter chain 203 receives this low-level initial signal S0, and after being transmitted sequentially through inverters 1 to 3, it outputs a high-level word line signal, thereby enabling the memory cell row corresponding to the word line circuit 200.

[0120] After the read / write drive circuit 1022 completes the read / write operation, it switches the reference signal R to a low level, and the NAND gate A outputs a high-level initial signal S0. The inverter chain 203 receives this high-level initial signal S0, and after being transmitted sequentially through inverters 1 to 3, it outputs a low-level word line signal, thereby turning off the memory cell row corresponding to the word line circuit 200.

[0121] waiting state

[0122] While the row decoding circuit 1021 outputs a low-level decoding selection signal to the word line circuit 200 to indicate that the word line circuit 200 is waiting, the signal generation circuit 201 generates a low-level control signal WS2 and a high-level control signal WS1. This causes transistors Ta and Tb to turn off, while transistor Tc turns on, and the NAND gate A outputs a continuously high-level initial signal S0. The inverter chain 203 receives this high-level initial signal S0, and after being transmitted sequentially through inverters 1 to 3, outputs a low-level word line signal, thereby turning off the memory cell row corresponding to the word line circuit 200.

[0123] In the current word line circuit 200, the power consumption of the word line circuit 200 is relatively high due to the performance limitations of the inverters, which in turn leads to a relatively high power consumption of the memory 102. Next, a further illustrative description of the inverters in the inverter chain 203 will be provided.

[0124] Figure 3 An exemplary circuit diagram of an inverter is shown, such as... Figure 3 As shown, inverter 300 mainly includes transistor T1 and transistor T2, where transistor T1 is an NMOS and transistor T2 is a PMOS. Figure 3 As shown, transistor T2 includes a first electrode, a second electrode, and a control electrode (gate). The first electrode of transistor T2 can receive a pull-up voltage V. u The second electrode of transistor T2 can output the output signal D. o The control electrode of transistor T2 can receive the input signal D. i .

[0125] Transistor T1 includes a first electrode, a second electrode, and a control electrode. The first electrode of transistor T1 is connected to the second electrode of transistor T1, and the second electrode of transistor T1 can receive a pull-down voltage V. dGenerally, the second electrode of the transistor T1 can be grounded to serve as a pull-down voltage V d . The control electrode of the transistor T1 is connected to the control electrode of the transistor T2 and can also receive the input signal D i .

[0126] Assuming that the input signal D i is low, the transistor T1 is off, the transistor T2 is on, and the voltage at the second electrode of the transistor T2 is the pull-up voltage V u , so the inverter 300 can output the output signal D o with a high level. Assuming that the input signal D i is high, the transistor T1 is on, the transistor T2 is off, and the voltage at the first electrode of the transistor T1 is the pull-down voltage V d , so the inverter 300 can output the output signal D o with a low level.

[0127] However, the word line circuit 200 is often not required to work continuously. When the word line circuit 200 works, the inverters in the word line circuit 200 work. When the word line circuit 200 waits, the inverters in the word line circuit 200 wait. It is to be noted that the waiting of the inverter 300 in the present application means that the output signal D o of the inverter 300 is a continuous low or high level signal, that is, the level of the output signal D o of the inverter 300 does not flip when the inverter 300 does not work, that is, when the inverter 300 waits.

[0128] For example, the inverter 300 can be any inverter in the inverter chain 203. During the waiting of the word line circuit 200, the inverters in the inverter chain 203 do not work. Among them, the inverter 1 and the inverter 3 can output continuous low level signals, and the inverter 2 can output a continuous high level signal.

[0129] During the waiting of the inverter 300, the pull-up voltage V u and the pull-down voltage V d are continuously applied to the pull-up end and the pull-down end of the inverter 300, so that there is a continuous leakage current in the inverter 300. For example, when the inverter 300 does not work, the input signal D i is low. The transistor T2 is on, the transistor T1 is off, the voltage at the first electrode of the transistor T1 is the pull-up voltage V u , and the voltage at the second electrode of the transistor T1 is the pull-down voltage V d . At this time, there is a continuous leakage current from the first electrode to the second electrode in the transistor T1, thereby increasing the power consumption of the inverter 300.

[0130] For example, when inverter 300 is waiting, the input signal D i If the voltage is high, then transistor T2 is off, transistor T1 is on, and the voltage at the first electrode of transistor T2 is the pull-up voltage V. u The voltage at the second electrode of transistor T2 is the pull-down voltage V. d At this time, leakage current will continuously flow from the first electrode to the second electrode of transistor T2, which will increase the power consumption of inverter 300.

[0131] In summary, the inverter 300 will have continuous leakage current during the waiting period, which will increase the power consumption of the inverter 300, and in turn increase the power consumption of the word line circuit 203 and the memory 102, which is not conducive to further improvement of the performance of the memory 102.

[0132] In view of this, several solutions have emerged to reduce the leakage current of inverter 300. Common solutions mainly include: high threshold transistor solutions and sleep inverter solutions. In the high threshold transistor solution, transistors T1 and T2 in inverter 300 are both high threshold voltage (HVT) transistors, that is, transistors T1 and T2 have higher threshold voltages, resulting in smaller leakage current through transistors T1 and T2, thereby reducing the overall leakage current of inverter 300.

[0133] However, high-threshold transistors have significant turn-on and turn-off delays. While setting both transistors T1 and T2 as high-threshold transistors can reduce leakage current, it also introduces a significant delay, meaning that inverter 300 cannot respond to changes in the input signal level in a timely manner, thus reducing the performance of inverter 300.

[0134] In a sleep inverter scheme, such as Figure 4a As shown, the inverter 400 includes not only transistors T1 and T2 as described above, but also a sleep transistor S1 connected to transistor T1 and a sleep transistor S2 connected to transistor T2. The first terminal of the sleep transistor S1 can receive a pull-up voltage V. u The second terminal of the sleep transistor S1 is connected to the first terminal of the transistor T2, and the control terminal of the sleep transistor S1 can receive the first sleep signal. The connection method of transistors T1 and T2 is similar to that in inverter 300, and will not be described again. The first terminal of the sleep transistor S2 is connected to the second terminal of transistor T1, and the second terminal of the sleep transistor S2 is grounded. The control terminal of the sleep transistor S2 can receive the second sleep signal. The first and second sleep signals are inverted signals.

[0135] When the inverter 400 is waiting, the first sleep signal controls the sleep transistor S1 to be off, and the second sleep signal controls the sleep transistor S2 to be off, so that the transistor T1 and the transistor T2 no longer receive the pull-up voltage V u and the pull-down voltage V d , thereby reducing the leakage current of the inverter 400 during the waiting period.

[0136] When the inverter 400 is working, the first sleep signal controls the sleep transistor S1 to be on, and the second sleep signal controls the sleep transistor S2 to be on, so that the transistor T1 and the transistor T2 can receive the pull-up voltage V u and the pull-down voltage V d , thereby enabling the inverter 400 to work normally.

[0137] However, during the waiting period of the word line circuit 200, the word line circuit 200 needs to output a word line signal at the 0 level, and the signal voltage of the word line signal at the 0 level can be a lower voltage value (ideally 0 V), thereby enabling the corresponding row of storage units to be completely turned off. However, for the inverter 400, since the transistor T1 and the transistor T2 no longer receive the pull-up voltage V u and the pull-down voltage V d when the inverter 400 is waiting, the output voltage D o of the inverter 400 is an undetermined voltage. That is, when the inverter 400 is used as an inverter at the output end of the inverter chain 203, the word line circuit 200 cannot output a word line signal at 0 V.

[0138] In view of this, as Figure 4b , a pull-down switch S3 is currently added at the output end of the inverter chain 203. The first end of the pull-down switch S3 is connected to the output end of the inverter chain 203, the second end of the pull-down switch S3 is grounded, and the control end of the pull-down switch S3 can receive the first sleep signal.

[0139] When the inverter 400 is working, the first sleep signal controls the pull-down switch S3 to be off, so that the inverter chain 203 can normally output a word line signal. When the inverter 400 is waiting, the first sleep signal controls the pull-down switch S3 to be on, so that the output end of the inverter chain 203 can be kept at 0 potential, that is, a word line signal at 0 V can be continuously output.

[0140] Since the pull-down switch S3 is introduced in the word line circuit 203 in most current sleep inverter schemes, the word line circuit 203 has a large peak current and a long response delay. Moreover, in actual use, since the pull-down switch S3 needs to be kept on when the inverter 400 is waiting, and the input and / or output of each inverter in the word line circuit 203 is undetermined, the addition of the pull-down switch S3 can also increase the overall leakage current of the word line circuit 203.

[0141] In summary, the leakage current in the current inverter still needs to be further reduced, so that the power consumption of the logic circuit using the inverter can be optimized.

[0142] Therefore, the voltage difference between the pull-up voltage and the pull-down voltage of the inverting circuit can be changed by turning on different paths, so that the inverting circuit has a smaller leakage current when waiting, and the inverting circuit has a faster response speed when working.

[0143] For example, the inverter provided by the embodiments of the present application has at least the following four possible implementation manners:

[0144] Inverter one

[0145] In the inverter provided by the embodiments of the present application, the adjusting circuit can provide the inverting circuit with a first pull-up voltage and a second pull-up voltage, wherein the first pull-up voltage is smaller than the second pull-up voltage. Figure 5 For example, a structure schematic diagram of an inverter provided by the embodiments of the present application is shown, which can be called half sleep stack up (HSSU). As shown in Figure 5 The inverter 500 includes an inverting circuit 501 and an adjusting circuit 502-1. The adjusting circuit 502-1 is connected with the first end QP of the inverting circuit 501. When the inverter 500 is waiting, the adjusting circuit 502-1 can provide the inverting circuit 501 with a first pull-up voltage, and when the inverter 500 is working, the adjusting circuit 502-1 can provide the inverting circuit 501 with a second pull-up voltage.

[0146] Specifically, the first path P1 of the adjusting circuit 502-1 includes a transistor MN2 (first transistor), and the second path P2 of the adjusting circuit 502-1 includes a transistor MP2 (second transistor), wherein the transistor MN2 is an NMOS, and the transistor MP2 is a PMOS. The first electrode of the transistor MN2 is used to connect the pull-up power supply and can receive the pull-up voltage V u The second electrode of the transistor MN2 is connected with the first end QP of the inverting circuit 501, and the gate of the transistor MN2 can receive a first control signal D1. The first electrode of the transistor MP2 is used to connect the pull-up power supply and can receive the pull-up voltage V uThe second electrode of the transistor MP2 is connected with the first end QP of the inverter 501, and the gate of the transistor MP2 can receive the second control signal D2.

[0147] Based on the inverter 500, when the first control signal D1 controls the transistor MN2 to be turned on, the transistor MN2 can provide the first pull-up voltage for the inverter 501, and it can be understood that at this time, the second control signal D2 can control the transistor MP2 to be turned off. When the second control signal D2 controls the transistor MP2 to be turned on, the transistor MP2 can provide the second pull-up voltage for the inverter 501, and it can be understood that at this time, the first control signal D1 can control the transistor MN2 to be turned off.

[0148] Specifically, threshold loss often occurs after the voltage is transmitted through the transistor. Among them, threshold loss occurs after the high voltage is transmitted through the NMOS, resulting in a decrease in voltage, and threshold loss occurs after the low voltage is transmitted through the PMOS, resulting in an increase in voltage.

[0149] In Figure 5 the inverter 500 shown in the figure, the transistor MN2 is an NMOS. When the first control signal D1 turns on the transistor MN2, the pull-up voltage V u is transmitted to the first end QP of the inverter 501 through the transistor MN2. Since threshold loss occurs when the transistor MN2 transmits the pull-up voltage V u , the voltage value transmitted to the first end QP is lower than the pull-up voltage V u , so that the first pull-up voltage lower than the pull-up voltage V u is provided for the first end QP.

[0150] Figure 5 The inverter 500 shown in the figure is beneficial to realize smaller leakage current when the inverter 500 is waiting. For example, when the inverter 500 is waiting, the transistor MN2 can be turned on through the first control signal D1, and the transistor MP2 can be turned off through the second control signal D2, so that the first pull-up voltage is applied to the first end QP of the inverter 501. In a possible implementation manner, the second end QN of the inverter 501 is grounded. Since the first pull-up voltage is small, in the case that the pull-down voltage V d is fixed, the bias of the first end QP and the second end QN of the inverter 501 can be small, which is beneficial to reduce the leakage current in the inverter 501. Compared with the inverter 300 (such as Figure 3 ) directly receiving the pull-up voltage V u in the prior art, the embodiment of the present application can realize smaller leakage current when the inverter 500 is waiting.

[0151] The transistor MP2 in the adjusting circuit 502-1 can reduce the influence of the adjusting circuit 502-1 on the working performance of the inverter 500. Specifically, the transistor MP2 in the adjusting circuit 502-1 is a PMOS. When the inverter 500 is working, the transistor MP2 is turned on, and the pull-up voltage V u is transmitted to the first terminal QP through the transistor MP2. The pull-up voltage V u does not have threshold loss when transmitted through the transistor MP2, and thus can still provide the inverting circuit with a pull-up voltage close to the pull-up voltage V u , i.e., a second pull-up voltage, which is conducive to reducing the influence of the adjusting circuit 502-1 on the working performance of the inverting circuit 501 and enabling the inverter 500 to work normally.

[0152] Generally, the transistor MP2 can be a standard threshold voltage (SVT) transistor or a low threshold voltage (LVT) transistor, so as to respond to the control of the second control signal D2 faster and provide a larger input current for the inverting circuit 501, and thus further reduce the influence of the adjusting circuit 502-1 on the working performance of the inverter 500.

[0153] For transistors of the same threshold voltage type, the specific threshold voltage of the transistor is also related to the process technology of the transistor. For example, as shown in Table 1 below:

[0154] Table 1

[0155]

[0156] As shown in Table 1, the threshold voltage of the NMOS in the LVT transistor prepared by using the first process technology is 0.175V, and the threshold voltage of the PMOS is -0.264V. The threshold voltage of the NMOS in the SVT transistor prepared by using the first process technology is 0.321V, and the threshold voltage of the PMOS is -0.348V. The threshold voltage of the NMOS in the HVT transistor prepared by using the first process technology is 0.4477V, and the threshold voltage of the PMOS is -0.559V.

[0157] The threshold voltage of the NMOS in the LVT transistor prepared by using the second process technology is 0.161V, and the threshold voltage of the PMOS is -0.2553V. The threshold voltage of the NMOS in the SVT transistor prepared by using the second process technology is 0.28V, and the threshold voltage of the PMOS is -0.367V. The threshold voltage of the NMOS in the HVT transistor prepared by using the second process technology is 0.433V, and the threshold voltage of the PMOS is -0.574V.

[0158] It should be understood that the threshold voltage types, the relationship between the threshold voltage and the process technology shown in Table 1 are only examples. In actual implementation, other process technologies can also exist, so that the specific threshold voltages of the HVT, SVT and LVT transistors can be changed, and the embodiments of the present application do not make too many limitations thereon.

[0159] For example, the inverter circuit 501 in the embodiments of the present application has a similar circuit structure to the inverter 300. As shown in Figure 5 , the inverter circuit 501 mainly includes a transistor MP1 and a transistor MN1, wherein the first electrode of the transistor MP1 can serve as a first end QP of the inverter circuit 501, the second electrode of the transistor MP1 is connected with the first electrode of the transistor MN1, and the second electrode of the transistor MN1 can serve as a second end QN of the inverter circuit 501. In Figure 5 , the second electrode of the transistor MN1 is grounded. The gate of the transistor MP1 and the gate of the transistor MP2 can receive an input signal D i , and the second electrode of the transistor MP1 can output an output signal D o . Wherein the transistor MP1 is a PMOS, and the transistor MN1 is an NMOS.

[0160] During the standby period of the inverter 500, the transistor MN2 is turned on, and the transistor MP2 is turned off. When the input signal D i is high, the transistor MN1 is turned on, and the transistor MP1 is turned off. At this time, since the adjusting circuit 502-1 applies a smaller first pull-up voltage to the first end QP, the voltage at the first electrode of the transistor MP1 is the smaller first pull-up voltage, the voltage at the second electrode of the transistor MP1 is the pull-down voltage V d , and thus the bias voltage between the first electrode and the second electrode of the transistor MP1 is smaller, and thus the leakage current from the first electrode to the second electrode in the transistor MP1 is smaller, so that a smaller leakage current can be achieved.

[0161] When the input signal D i is low, the transistor MP1 is turned on, and the transistor MN1 is turned off. At this time, the voltage at the first electrode of the transistor MN1 is the first pull-up voltage, and the voltage at the second electrode of the transistor MN1 is the pull-down voltage V d . Since the first pull-up voltage is smaller, the bias voltage between the first electrode and the second electrode of the transistor MN1 is smaller, and thus the leakage current from the first electrode to the second electrode in the transistor MN1 is smaller, so that a smaller leakage current can be achieved.

[0162] As can be seen from the above analysis, the smaller the first pull-up voltage, the smaller the leakage current of inverter 500 during the waiting period. Therefore, transistor MN2 in this embodiment can be an HVT transistor. HVT transistors can produce a larger threshold voltage drop, thus increasing the voltage drop between the first and second electrodes in transistor MN2, thereby obtaining a smaller first pull-up voltage.

[0163] It can be understood that transistor MN2 can be turned on when inverter 500 is in standby mode, and transistor MP2 can be turned on when inverter 500 is operating. In other words, the on and off states of transistors MN2 and MP2 are opposite. Furthermore, the channel types of transistors MN2 and MP2 are also opposite. Therefore, the same control signal can be used to control transistors MN2 and MP2 respectively; that is, the first control signal D1 and the second control signal D2 are the same signal. This implementation reduces the number of control signals, simplifying the control of inverter 500.

[0164] In another possible implementation, such as Figure 6 As shown, the structure of this inverter 500 can be called a half-sleep stack feedback up (HSSUF). The gate of transistor MN2 can also be connected to the output of the inverter circuit 501. In this case, the output signal D of the inverter circuit 501... o This can then be used as the first control signal D1 to control transistor MN2.

[0165] Specifically, while inverter 500 is waiting, the second control signal D2 can control transistor MP2 to turn off. When input signal D... i When it is low, the output signal D o When the signal is high, transistors MN2 and MP1 are turned on, and transistor MN1 is turned off. At this time, transistor MN2 can provide a first pull-up voltage to the first terminal QP of the inverter circuit 501, thereby reducing the bias voltage between the first and second electrodes of transistor MN1, which in turn helps to reduce the leakage current in the inverter circuit 501. When the input signal D... i When it is high, the output signal D o When the signal is low, transistor MN1 is turned on, while transistors MN2 and MP1 are turned off. The transmission path of transistor MP1 is increased by adding a transistor in the off state (transistor MN2), which can reduce the leakage current from the first electrode to the second electrode of transistor MP1.

[0166] When inverter 500 is operating, the second control signal D2 can control transistor MP2 to turn on. When input signal D... i When it is low, the output signal Do is high, transistor MN2 and transistor MP1 are turned on, and transistor MN1 is turned off. However, since transistor MP2 does not cause threshold loss, it can short transistor MN2 when transmitting the high-level pull-up voltage V u , thereby reducing the influence of the adjustment circuit 502-1 on the working performance of the inverter 500. When the input signal D i is high, the output signal D o is low, transistor MN1 is turned on, and transistor MP1 is turned off. Since transistor MP1 is turned off, the output signal D o is not affected by the voltage of the current first end QP.

[0167] The inverter two

[0168] Based on the same principle, in another possible implementation, the adjustment circuit can also provide the first pull-down voltage and the second pull-down voltage for the inverting circuit, where the first pull-down voltage is greater than the second pull-down voltage. When the inverter is waiting, the adjustment circuit provides the larger pull-down voltage (the first pull-down voltage) for the inverting circuit, which can also reduce the leakage current in the inverter.

[0169] As Figure 7 shown, the structure of the inverter 700 can be referred to as a half sleep stack down (HSSD). Wherein the third path P3 of the adjustment circuit 502-2 includes transistor MP3, and the fourth path P4 of the adjustment circuit 502-1 includes transistor MN3, where the transistor MP3 is PMOS, and the transistor MN3 is NMOS. The first electrode of the transistor MP3 is connected with the second end QN of the inverting circuit 501, the second electrode of the transistor MP3 is grounded, and the gate of the transistor MP3 can receive the third control signal D3. The first electrode of the transistor MN3 is connected with the second end QN of the inverting circuit 501, the second electrode of the transistor MN3 is grounded, and the gate of the transistor MN3 can receive the fourth control signal D4.

[0170] Based on the inverter 700, when the third control signal D3 controls the transistor MP3 to be turned on, the transistor MP3 can provide the first pull-down voltage for the inverting circuit 501. It can be understood that at this time, the fourth control signal D4 can control the transistor MN3 to be turned off. When the fourth control signal D4 controls the transistor MN3 to be turned on, the transistor MN3 can provide the second pull-down voltage for the inverting circuit 501. It can be understood that at this time, the third control signal D3 can control the transistor MP3 to be turned off.

[0171] Specifically, the second electrode of the transistor MP3 and the second electrode of the transistor MN3 are both grounded, which can be regarded as the voltages of the second electrodes of the transistor MP3 and the transistor MN3 are both pull-down voltages V dSince transistor MP3 is a PMOS transistor, when the third control signal turns on transistor MP3, transistor MP3 transmits the pull-down voltage V. d At this time, a threshold voltage loss occurs, and the voltage at the first electrode of transistor MP3 is greater than the voltage at the second electrode. Consequently, transistor MP3 can provide a voltage greater than the pull-down voltage V to the second terminal QN of inverter circuit 501. d The pull-down voltage, i.e., the first pull-down voltage.

[0172] based on Figure 7 The inverter 700 shown can, while waiting, turn on transistor MP3 via a third control signal D3 and turn off transistor MN3 via a fourth control signal D4, thereby applying a first pull-down voltage to the second terminal QN of the inverter circuit 501. In one possible implementation, the first terminal QP of the inverter circuit 501 can be connected to a pull-up power supply to receive a pull-up voltage V. u Because the first pull-down voltage is relatively large, the pull-up voltage V... u With a fixed bias, the bias voltages at the first terminal QP and the second terminal QN of the inverter circuit 501 can be smaller, which helps to reduce the leakage current in the inverter circuit 501, compared to the inverter 300 in the prior art (such as...). Figure 3 By directly grounding the inverter 500, this embodiment can achieve a smaller leakage current while the inverter 500 is waiting.

[0173] The transistor MN3 in the regulating circuit 502-2 can reduce the impact of the regulating circuit 502-2 on the operating performance of the inverter circuit 501. Specifically, the transistor MN3 in the regulating circuit 502-2 is an NMOS. When the inverter 700 is operating, the transistor MN3 is turned on, pulling down the voltage V. d The voltage is transferred to the second terminal QN via transistor MN3. Pull-down voltage V d No threshold voltage loss occurs during transmission through transistor MN3, thus still providing an inverting circuit 501 with a voltage close to the pull-down voltage V. d The pull-down voltage, i.e. the second pull-down voltage, helps to reduce the impact on the operating performance of the inverter circuit 501.

[0174] Generally, transistor MN3 can be a common SVT transistor or LVT transistor, which can respond to the control of the fourth control signal D4 more quickly and provide a larger input current for the inverter circuit 501. Therefore, it is beneficial to further reduce the impact of the regulation circuit 502-2 on the working performance of the inverter circuit 501.

[0175] For example, during the wait period of inverter 700, transistor MP3 is turned on and transistor MN3 is turned off. When the input signal D... iWhen the input signal D is high, the transistor MN1 is turned on, and the transistor MP1 is turned off. At this time, the voltage at the first electrode of the transistor MN1 is the pull-up voltage V u , and the voltage at the second electrode is the larger first pull-down voltage. Since the first pull-down voltage is large, the bias between the first electrode and the second electrode of the transistor MN1 is small, and thus the leakage current from the first electrode to the second electrode of the transistor MN1 is small, so that a smaller leakage current can be achieved.

[0176] When the input signal D i is low, the transistor MP1 is turned on, and the transistor MN1 is turned off. At this time, the voltage at the first electrode of the transistor MN1 is the pull-up voltage V u , and the voltage at the second electrode is the larger first pull-down voltage. Since the first pull-down voltage is large, the bias between the first electrode and the second electrode of the transistor MN1 is small, and thus the leakage current from the first electrode to the second electrode of the transistor MN1 is small, so that a smaller leakage current can be achieved.

[0177] As can be seen from the above analysis, the larger the first pull-down voltage, the smaller the leakage current of the inverter 700 during standby. Therefore, the transistor MP3 in the embodiment of the present application can be an hvt transistor. The hvt transistor can generate a larger threshold loss, so that the voltage drop between the first electrode and the second electrode of the transistor MP3 can be increased, and thus a larger first pull-down voltage can be obtained.

[0178] It can be understood that the on and off states of the transistor MP3 and the transistor MN3 are opposite, and the channel types are also opposite, so the same control signal can be used to control the transistor MP3 and the transistor MN3, that is, the third control signal D3 and the fourth control signal D4 are the same signal. By using this implementation manner, the number of control signals can be reduced, which is conducive to simplifying the control of the inverter 700.

[0179] In another possible implementation manner, as shown in Figure 8 , the structure of the inverter 700 can be referred to as a half sleep stack feedback down (HSSFD). In this case, the gate of the transistor MP3 can also be connected to the output end of the inverting circuit 501. In this case, the output signal D o of the inverting circuit 501 can be used as the third control signal D3 of the transistor MP3.

[0180] Specifically, when the inverter 700 is waiting, the fourth control signal D4 can control the transistor MN3 to be turned off. When the input signal D iWhen it is low, the output signal D o When the signal is high, transistor MP1 is turned on, while transistors MN1 and MP3 are turned off. At this time, the transmission path of the leakage current from the first electrode to the second electrode of transistor MN1 is increased by the transistor (transistor MP3) in the off state, thereby reducing the leakage current in transistor MN1 from the first electrode to the second electrode.

[0181] When the input signal D i When it is high, the output signal D o When the voltage is low, transistor MN1 is turned on, and transistors MP3 and MP1 are turned off. At this time, transistor MP3 can provide a first pull-down voltage to the second terminal QN of the inverter circuit 501, thereby reducing the bias voltage between the first and second electrodes of transistor MN1, which in turn helps to reduce the leakage current in the inverter circuit 501.

[0182] When inverter 700 is operating, the fourth control signal D4 can control transistor MN3 to conduct. When input signal D... i When it is low, the output signal D o When the signal is high, transistor MP1 is turned on, and transistor MN1 is turned off. Because transistor MN1 is off, the output signal D... o It will not be affected by the current voltage of the second terminal QN.

[0183] When the input signal D i When it is high, the output signal D o When the voltage is low, transistors MN1 and MP3 are turned on. However, since transistor MN3 does not incur threshold voltage loss, it is pulled down by the low-level voltage V. d The transistor MP3 can be short-circuited, thereby reducing the impact of the regulating circuit 502-2 on the performance of the inverting circuit 501.

[0184] Inverter 3

[0185] It should be noted that the adjustment circuit provided in this application embodiment is not limited to threshold loss, and it can also output a smaller pull-up voltage or a larger pull-down voltage to the inverting circuit in other ways.

[0186] For example Figure 9 As shown, the first path P1 of the adjustment circuit 502-3 may include a first transistor K1 and a first adjusting resistor, and the second path P2 includes a second transistor MP2. One end of the first adjusting resistor R1 can be connected to a pull-up power supply to receive the pull-up voltage V. uThe other end of the first adjusting resistor R1 is connected with the first electrode of the first transistor K1, the second electrode of the first transistor K1 is connected with the first end QP of the inverter circuit 501, and the gate of the first transistor K1 can receive the first control signal D1. The first electrode of the second transistor MP2 can be connected with the pull-up power supply to receive the pull-up voltage V u The second electrode of the second transistor MP2 is connected with the first end QP of the inverter circuit 501, and the gate of the second transistor MP2 can receive the second control signal.

[0187] When the inverter 900 is waiting, the transistor K1 can be turned on by the first control signal D1. After the transistor K1 is turned on, the pull-up voltage V u is transmitted to the first end QP of the inverter circuit 501 through the first adjusting resistor R1 and the transistor K1. Since the first adjusting resistor R1 can generate a voltage drop, the first adjusting resistor R1 can provide a pull-up voltage lower than the pull-up voltage V u for the inverter circuit 501, i.e., a first pull-up voltage, which can in turn reduce the leakage current in the inverter circuit 501. It can be understood that at this time, the second control signal D2 turns off the transistor MP2.

[0188] The implementation of the transistor MP2 can refer to the transistor MP2 in the adjusting circuit 502-1, and details are not described herein.

[0189] It should be noted that the transistor K1 in the adjusting circuit 502-3 can be either NMOS or PMOS. In a possible implementation, the transistor K1 can be NMOS, and in this case, the first control signal D1 and the second control signal D2 can be the same control signal, thereby reducing the number of control signals and simplifying the control of the inverter 900.

[0190] It can be understood that the first control signal D1 and the second control signal D2 for controlling the inverter 900 are similar to the first control signal D1 and the second control signal D2 for controlling the inverter 500, and details are not described herein.

[0191] Inverter four

[0192] For another example Figure 10As shown, the third path P3 of the adjustment circuit 502-4 may include transistor K2 and a second adjustment resistor, and the fourth path P4 may include transistor MN3. Specifically, the first electrode of transistor K2 is connected to the second terminal QN of the inverting circuit 501, the second electrode of transistor K2 is connected to one end of the second adjustment resistor R2, the gate of transistor K2 is used to receive the third control signal D3, and the other end of the second adjustment resistor R2 is grounded. Similarly, the first electrode of transistor MN3 is connected to the second terminal QN of the inverting circuit 501, the second electrode of transistor MN3 is grounded, and the gate of transistor MN3 is used to receive the fourth control signal D4.

[0193] While inverter 1000 is waiting, transistor K2 can be turned on via the third control signal D3. After transistor K1 is turned on, the second terminal QN of inverter circuit 501 and the pull-down voltage V... d This forms a circuit. Since the second regulating resistor R2 will produce a voltage drop, it can provide the inverter circuit 501 with a voltage greater than the pull-down voltage V. d The pull-down voltage, i.e., the first pull-down voltage, can reduce the leakage current in the inverter circuit 501. It can be understood that at this time, the fourth control signal D4 disconnects transistor MN3.

[0194] The implementation of transistor MN3 can be referenced from transistor MP2 in the adjustment circuit 502-2, and will not be elaborated further.

[0195] It should be noted that transistor K2 in the adjustment circuit 502-4 can be either an NMOS or a PMOS. In one possible implementation, transistor K2 can be a PMOS. In this case, the third control signal D3 and the fourth control signal D4 can be the same control signal, thereby reducing the number of control signals and simplifying the control of the inverter 900.

[0196] It is understood that the control methods of the third control signal D3 and the fourth control signal D4 controlling the inverter 1000 are similar to those of the third control signal D3 and the fourth control signal D4 controlling the inverter 700, and will not be elaborated further.

[0197] It should be understood that there are many possible implementations of the adjustment circuit, and the embodiments of this application will not list them all.

[0198] Inverter 5

[0199] In one implementation method, such as Figure 11 As shown, the inverter 1100 includes a first adjustment circuit 1101, a second adjustment circuit 1102, and an inverting circuit 501. The specific implementation of the inverting circuit 501 can be found in the above embodiments and will not be repeated here.

[0200] The first adjusting circuit 1101 can include a first path P1 and a second path P2 in parallel, wherein the first end of the first path P1 and the first end of the second path P2 can be connected to the pull-up power supply, and the second end of the first path P1 and the second end of the second path P2 are connected to the first end of the inverting circuit. The first adjusting circuit can provide the first pull-up voltage for the inverting circuit through the first path P1 when the first path P1 is turned on, and provide the second pull-up voltage for the inverting circuit through the second path P2 when the second path P2 is turned on, wherein the first pull-up voltage is less than the second pull-up voltage.

[0201] The specific implementation of the first adjusting circuit 1101 can refer to the adjusting circuit 502-1 and the adjusting circuit 502-3 described above, and details are not repeated here.

[0202] The second adjusting circuit 1102 can include a third path P3 and a fourth path P4 in parallel, wherein the first end of the third path P3 and the first end of the fourth path P4 are connected to the second end of the inverting circuit, the second end of the third path P3 and the second end of the fourth path P4 are grounded, and the second adjusting circuit provides the first pull-down voltage for the inverting circuit through the third path P3 when the third path P3 is turned on, and provides the second pull-down voltage for the inverting circuit through the fourth path P4 when the fourth path P4 is turned on, wherein the first pull-down voltage is greater than the second pull-down voltage.

[0203] The specific implementation of the second adjusting circuit 1102 can refer to the adjusting circuit 502-2 and the adjusting circuit 502-4 described above, and details are not repeated here.

[0204] In the inverter provided in the embodiments of the present application, the first adjusting circuit 1101 can provide different pull-up voltages for the inverting circuit, and the second adjusting circuit 1102 can provide different pull-down voltages for the inverting circuit 501. For example, when the inverter 1100 is waiting, the first adjusting circuit 1101 can provide a smaller pull-up voltage, i.e. the first pull-up voltage, for the inverting circuit 501, and the second adjusting circuit 1102 can provide a larger pull-down voltage, i.e. the first pull-down voltage, for the inverting circuit 501. Therefore, the bias voltage between the first end and the second end of the inverting circuit 501 can be reduced, and the leakage current generated by the inverting circuit 501 can be reduced, so that the leakage current of the inverter 1100 when waiting can be reduced. When the inverter 1100 is working, the first adjusting circuit 1101 can provide a larger pull-up voltage, i.e. the second pull-up voltage, for the inverting circuit 501, and the second adjusting circuit 1102 can provide a smaller pull-down voltage, i.e. the second pull-down voltage, for the inverting circuit 501, which is beneficial to reduce the influence of the first adjusting circuit 1101 and the second adjusting circuit 1102 on the working performance of the inverting circuit, so that the inverter 1100 can work normally.

[0205] The inverter provided by the embodiments of the present application is exemplarily described by the above examples. It should be understood that the inverter provided by the embodiments of the present application can be applied to any logic circuit using inverting logic operation. For example, as shown in Figure 12 The logic circuit 1200 can include a control circuit 1201 and an inverter 1202, and the inverter 1202 can be any of the inverters provided by the embodiments of the present application.

[0206] The control circuit 1201 can output a control signal, such as the first control signal D1 and the second control signal D2, or the third control signal D3 and the fourth control signal D4. The control circuit 1201 can control the adjusting circuit in the inverter 1202 through the control signal, so as to reduce the leakage current in the inverter 1202 during the standby period of the logic circuit 1200, and further reduce the power consumption of the logic circuit 1200.

[0207] For example, the logic circuit 1200 can be the word line circuit 200 as shown in Figure 2 In this case, the signal generation circuit 201 can correspond to the control circuit 1201, and the inverter provided by the embodiments of the present application can be applied to the inverter chain 203, and the signal generation circuit 201 can control the state of the adjusting circuit in each inverter in the inverter chain 203 through the control signal WS1 and / or WS2.

[0208] Specifically, the output terminals of the signal generation circuit 201 are connected to the control terminals of the adjusting circuits in each inverter, and the signal generation circuit 201 can generate the control signal WS1 and the control signal WS2 according to the decode selection signal. For example, the level relationship among the decode selection signal, the control signal WS1 and the control signal WS2 can be as shown in Table 1:

[0209] Table 2

[0210] Wait Work Decode select signal Low level High level Control signal WS1 High level Low level Control signal WS2 Low level High level

[0211] As shown in Table 2, the decode selection signal is low when indicating that the word line circuit 200 is in standby, and the signal generation circuit 201 can generate the control signal WS1 at high level and the control signal WS2 at low level according to the decode selection signal. The decode selection signal is high when indicating that the word line circuit 200 is in operation, and the signal generation circuit 201 can generate the control signal WS1 at low level and the control signal WS2 at high level according to the decode selection signal.

[0212] According to the level relationship shown in Table 2, when the inverter 500 as shown in Figure 5 is applied to the inverter chain 203, the control signal WS1 can control the adjusting circuit 502-1 as the first control signal D1 and the second control signal D2, and the control signal WS2 can control the adjusting circuit 502-2 as the third control signal D3 and the fourth control signal D4. Figure 6When the inverter 500 shown is applied to the inverter chain 203, the control signal WS1 can control the adjusting circuit 502-1 as the second control signal D2, so that the adjusting circuit 502-1 provides the first pull-up voltage for the inverting circuit 501 when the word line circuit 200 is waiting, and provides the second pull-up voltage for the inverting circuit 501 when the word line circuit 200 is working.

[0213] When the inverter 700 shown is applied to the inverter chain 203, the control signal WS2 can control the adjusting circuit 502-2 as the third control signal D3 and the fourth control signal D4, so that the adjusting circuit 502-2 provides the first pull-down voltage for the inverting circuit 501 when the word line circuit 200 is waiting, and provides the second pull-down voltage for the inverting circuit 501 when the word line circuit 200 is working. Figure 7 When the inverter 700 shown is applied to the inverter chain 203, the control signal WS2 can control the adjusting circuit 502-2 as the third control signal D3 and the fourth control signal D4, so that the adjusting circuit 502-2 provides the first pull-down voltage for the inverting circuit 501 when the word line circuit 200 is waiting, and provides the second pull-down voltage for the inverting circuit 501 when the word line circuit 200 is working. Figure 8 When the inverter 700 shown is applied to the inverter chain 203, the control signal WS2 can control the adjusting circuit 502-2 as the fourth control signal D4, so that the adjusting circuit 502-2 provides the first pull-down voltage for the inverting circuit 501 when the word line circuit 200 is waiting, and provides the second pull-down voltage for the inverting circuit 501 when the word line circuit 200 is working.

[0214] It should be noted that during the waiting period of the word line circuit 200, the signal voltage of the word line signal output by the inverter chain 203 is low enough to completely close the corresponding row of memory cells. Therefore, during the working period of the word line circuit 200, the signal voltage of the word line signal output by the inverter chain 203 is high enough to open the corresponding row of memory cells. Figure 2 In the inverter chain 203 shown, the inverter 3 at the output end of the inverter chain 203 can adopt the structure of the HSSU as shown in Figure 5 or the structure of the HSSFU as shown in Figure 6 During the waiting period of the word line circuit 200, the input signal D i of the inverter 3 is high, and the output signal D o is low. Since the second terminal of the transistor MN1 in the inverter 3 is directly grounded, after the transistor MN1 is turned on, the voltage at the second electrode and the first electrode of the transistor MN1 can be the pull-down voltage V d , so that a word line signal with a signal voltage low enough (tending to 0V) can be output.

[0215] The inverters 1 and 2 in the word line circuit 200 can be any inverter provided by the embodiments of the present application. For example, the inverter 2 can be any one of the structures of the HSSU, the HSSFU, the HSSD and the HSSFD, Figure 13 Exemplarily, three possible connection modes between the inverter 2 and the inverter 3 are shown. As shown in Figure 13

[0216] In the first structure, the inverter 2 and the inverter 3 are both HSSU structures, and the control signals of the two are both WS1. The input signal of the inverter 2 is D i -2, and the output signal of the inverter 2 is D o ​-2. The output of the inverter 2 is connected to the input of the inverter 3, and the output signal D o -2 of the inverter 3 is D i -3. The output signal of the inverter 3 is D o -3.

[0217] In structure two, the inverter 2 and the inverter 3 are both HSSFU structures. Among them, WS1 can be used as the control signal of the inverter 2 and the inverter 3.

[0218] In structure three, the inverter 2 is an HSSD structure, and the inverter 3 is an HSSU structure. Among them, WS2 can be used as the control signal of the inverter 2, and WS1 can be used as the control signal of the inverter 3.

[0219] It should be understood that there can be other possible structures of the inverter 2 and the inverter 3, and the embodiments of the present application will not be enumerated one by one.

[0220] In order to verify the effectiveness of the technical solutions of the present application, the embodiments of the present application also comprehensively evaluate the word line circuits provided by the prior art and the embodiments of the present application from the aspects of leakage, performance, peak current, etc. Among them, the inverter chain in the word line circuit adopts the structure of two inverters, and the connection structure of the two inverters can be referred to Figure 13 .

[0221] (1) Leakage

[0222] Taking the worst case of leakage as an example, the simulation results are as shown in Figure 14 .

[0223] Figure 14 Among them, NORMAL is a normal mode of a conventional word line circuit, and the inverter chain in the word line circuit can be composed of inverters as shown in Figure 3 . HVT corresponds to a conventional high threshold word line circuit, and the transistors of the inverters in the inverter chain of the word line circuit can adopt HVT transistors. SLEEP_M corresponds to a word line circuit adopting a sleep inverter, and a pull-down transistor T3 is added in the word line circuit. SLEEP corresponds to another word line circuit, which adopts a sleep inverter but does not add a pull-down transistor T3. HSSU, HSSFU, and HSSUD correspond to structure one, structure two, and structure three as shown in Figure 13 .

[0224] Figure 14In the figure, the ordinate represents the relative size of the leakage current in the word line circuit, and the normal mode of the conventional word line circuit (NORMAL) is the control circuit, and its leakage current is 100%. Compared with the normal mode of the conventional word line circuit, the high threshold word line circuit (HVT) can reduce the leakage current to 17.05%, the structure one (HSSU) in the figure can reduce the leakage current to 12.87%, the structure two (HSSFU) in the figure can reduce the leakage current to 11.20%, the structure three (HSSUD) in the figure can reduce the leakage current to 10.79%, the word line circuit (SLEEP_M) using the sleep inverter and provided with the pull-down transistor T3 can reduce the leakage current to 36.23%, and the word line circuit (SLEEP) using the sleep inverter and not provided with the pull-down transistor T3 can reduce the leakage current to 0.010%. Figure 13 Figure 13 Figure 13

[0225] It can be found from the analysis result shown in the figure that, compared with the normal mode of the conventional word line circuit (NORMAL), the word line circuit provided by the embodiment of the application can save about 90% of the leakage current. The word line circuit (SLEEP) using the sleep inverter and not provided with the pull-down transistor T3 has the best leakage current suppression, but the output end of the inverter chain is in an indefinite state during the standby period, and therefore cannot be applied to the memory. The word line circuit (SLEEP_M) using the sleep inverter and provided with the pull-down transistor T3 increases the leakage current in the word line circuit, and the suppression effect on the leakage current is not ideal. Figure 14

[0226] (2) Performance

[0227] For example, the simulation result in the case of poor performance can be as shown in the figure. Figure 15 The performance can be understood as the time delay of the word line circuit in the case of opening or closing.

[0228] Figure 15 In the figure, the ordinate represents the relative size of the performance of the word line circuit, and the lower the ordinate value, the better the performance of the word line circuit. The normal mode of the conventional word line circuit (NORMAL) is the control circuit, and its performance is 100%. Compared with the conventional word line circuit (Normal), the high threshold word line circuit (HVT) increases the performance to 164.50%, and deteriorates the performance of the word line circuit by 64.5%. Figure 13 The structure one (HSSU) in the figure can increase the performance to 126.61%, and deteriorate the performance of the word line circuit by 26.61%. Figure 13 ​​​​The structure two (HSSFU) in the figure can increase the performance to 127.76%, and deteriorate the performance of the word line circuit by 27.76%. Figure 13 The structure three (HSSUD) in the figure can increase the performance to 147.69%, and deteriorate the performance of the word line circuit by 47.69%. The word line circuit (SLEEP_M) with the sleep inverter and the pull-down transistor T3 can increase the performance to 176.24%, and deteriorate the performance of the word line circuit by 76.24%. The word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3 can increase the performance to 175.40%, and deteriorate the performance of the word line circuit by 75.40%.

[0229] Therefore, the word line circuit provided by the embodiment of the present application deteriorates the performance more lightly than the high threshold word line circuit (HVT), the word line circuit (SLEEP_M) with the sleep inverter and the pull-down transistor T3, and the word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3.

[0230] (3) Peak current

[0231] From the comprehensive effect evaluation of the performance and the leakage current, the word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3 and the word line circuit provided by the embodiment of the present application can be used to suppress the leakage current. The embodiment of the present application further compares the peak current of the word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3 and the word line circuit provided by the embodiment of the present application.

[0232] As shown in the current curve in the figure Figure 16 , the peak current of the word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3 is 3.2 mA, while Figure 13 , the peak current of the structure one (HSSU) in the figure is 1.36 mA, Figure 13 , the peak current of the structure two (HSSFU) in the figure is 1.94 mA. Therefore, the word line circuit provided by the embodiment of the present application can optimize the peak current, and further be beneficial to improve the stability of the memory.

[0233] As shown in the voltage curve in the figure Figure 16 , when the word line circuit (SLEEP) with the sleep inverter and without the pull-down transistor T3 is started, the voltage of the first end QP in the internal sleep inverter rises slowly, so that the starting response time of the sleep inverter is longer, which further affects the performance of the word line circuit. While the structure two (HSSFU) in the figure Figure 13 and the structure three (HSSUD) in the figure Figure 13The voltage of the first end QP of the structure one (HSSU) can reach a steady state faster, so the starting time of the inverter provided by the embodiment of the application is shorter, and the performance of the word line circuit is further improved.

[0234] Obviously, various modifications and changes can be made to the application without departing from the scope of the application. It is intended that the application embrace all such modifications and changes and, accordingly, the application to be limited only by the scope of the following claims.

Claims

1. An inverter, characterized by, The inverting circuit comprises a first end, a second end, an input end and an output end, wherein the first end of the inverting circuit is used for receiving a first pull-up voltage or a second pull-up voltage, the second end of the inverting circuit is used for receiving a pull-down voltage, the input end of the inverting circuit is used for receiving an input signal of the inverter, and the output end of the inverting circuit is used for outputting an inverted signal of the input signal. The adjusting circuit comprises a first path and a second path in parallel, wherein a first end of the first path and a first end of the second path are both used for connecting a pull-up power supply, a second end of the first path and a second end of the second path are both connected with the first end of the inverting circuit, and the adjusting circuit is used for: providing the first pull-up voltage for the inverting circuit through the first path when the first path is turned on; providing the second pull-up voltage for the inverting circuit through the second path when the second path is turned on, the first pull-up voltage being smaller than the second pull-up voltage; turning on the first path when the inverter is in a standby state; turning on the second path when the inverter is in a working state. The first path comprises a first transistor, and the second path comprises a second transistor, the first transistor being an N-type metal oxide semiconductor transistor (NMOS), and the second transistor being a P-type metal oxide semiconductor transistor (PMOS); 2. The inverter of claim 1, wherein, a first electrode of the first transistor is used for connecting the pull-up power supply, a second electrode of the first transistor is connected with the first end of the inverting circuit, and a gate of the first transistor is used for receiving a first control signal; a first electrode of the second transistor is used for connecting the pull-up power supply, a second electrode of the second transistor is connected with the first end of the inverting circuit, and a gate of the second transistor is used for receiving a second control signal; the first transistor is used for providing the first pull-up voltage for the inverting circuit according to the first control signal; the second transistor is used for providing the second pull-up voltage for the inverting circuit according to the second control signal. The first transistor is a high threshold voltage (HVT) transistor.

3. The inverter of claim 2, wherein, The second transistor is a standard threshold voltage (SVT) transistor or a low threshold voltage (LVT) transistor.

4. The inverter according to claim 2 or 3, characterized by The first control signal and the second control signal are the same signal.

5. The inverter according to claim 2 or 3, characterized by The gate of the first transistor is connected with the output end of the inverting circuit, and the first control signal is an output signal of the inverting circuit.

6. The inverter according to claim 2 or 3, characterized by The first path comprises a first transistor and a first adjusting resistor, and the second path comprises a second transistor; 7. The inverter of any one of claims 1 to 3, wherein, one end of the first adjusting resistor is used for connecting the pull-up power supply, the other end of the first adjusting resistor is connected with a first electrode of the first transistor, a second electrode of the first transistor is connected with the first end of the inverting circuit, and a gate of the first transistor is used for receiving a first control signal; a first electrode of the second transistor is used for connecting the pull-up power supply, a second electrode of the second transistor is connected with the first end of the inverting circuit, and a gate of the second transistor is used for receiving a second control signal; ​ The first transistor is configured to provide the first pull-up voltage for the inverter circuit according to the first control signal. The second transistor is configured to provide the second pull-up voltage for the inverter circuit according to the second control signal.

8. The inverter of any one of claims 1 to 3, wherein, The second end of the inverter circuit is grounded.

9. An inverter, characterized by The inverter circuit and the adjusting circuit are included. The inverter circuit includes a first end, a second end, an input end and an output end, wherein the first end of the inverter circuit is configured to receive a pull-up voltage, the second end of the inverter circuit is configured to receive a first pull-down voltage or a second pull-down voltage, the input end of the inverter circuit is configured to receive an input signal of the inverter, and the output end of the inverter circuit is configured to output an inverted signal of the input signal. The adjusting circuit includes a third path and a fourth path in parallel, wherein the first end of the third path and the first end of the fourth path are both connected with the second end of the inverter circuit, the second end of the third path and the second end of the fourth path are both grounded, and the adjusting circuit is configured to: provide the first pull-down voltage for the inverter circuit through the third path when the third path is turned on; provide the second pull-down voltage for the inverter circuit through the fourth path when the fourth path is turned on, the first pull-down voltage being greater than the second pull-down voltage; turn on the third path when the inverter is in a standby state; turn on the fourth path when the inverter is in a working state.

10. The inverter of claim 9, wherein, The third path includes a third transistor, and the fourth path includes a fourth transistor, the third transistor being a PMOS, and the fourth transistor being an NMOS. The first electrode of the third transistor is connected with the second end of the inverter circuit, the second electrode of the third transistor is grounded, and the gate of the third transistor is configured to receive a third control signal. The first electrode of the fourth transistor is connected with the second end of the inverter circuit, the second electrode of the fourth transistor is grounded, and the gate of the fourth transistor is configured to receive a fourth control signal. The third transistor is configured to provide the first pull-down voltage for the inverter circuit according to the third control signal. The fourth transistor is configured to provide the second pull-down voltage for the inverter circuit according to the fourth control signal.

11. The inverter of claim 10, wherein, The third transistor is an HVT transistor.

12. The inverter according to claim 10 or 11, characterized by The fourth transistor is an SVT transistor or an LVT transistor.

13. The inverter of claim 10 or 11, wherein, The third control signal and the fourth control signal are the same signal.

14. The inverter of claim 10 or 11, wherein, The gate of the third transistor is connected with the output end of the inverter circuit, and the third control signal is an output signal of the inverter circuit.

15. The inverter of any one of claims 9 to 11, wherein, The third path includes a third transistor and a second adjusting resistor, and the fourth path includes a fourth transistor. The first electrode of the third transistor is connected with the second end of the inverter circuit, the second electrode of the third transistor is connected with one end of the second adjusting resistor, the gate of the third transistor is configured to receive a third control signal, and the other end of the second adjusting resistor is grounded. The first electrode of the fourth transistor is connected with the second end of the inverter circuit, the second electrode of the fourth transistor is grounded, and the gate of the fourth transistor is configured to receive a fourth control signal; The third transistor is configured to provide the first pull-down voltage for the inverter circuit according to the third control signal. The fourth transistor is configured to provide the second pull-down voltage for the inverter circuit according to the fourth control signal.

16. The inverter of any one of claims 9 to 11, wherein, The first end of the inverter circuit is configured to be connected with a pull-up power supply.

17. A logic circuit, characterized by The inverter comprises a control circuit and the inverter according to any one of claims 1 to 16. The control circuit is configured to output a control signal to the inverter.

18. A word line circuit, comprising: The inverter chain comprises inverters according to any one of claims 1 to 16, and the signal generation circuit is connected with the control ends of the inverters in the inverter chain respectively. The signal generation circuit is configured to generate a control signal.

19. The word line circuit of claim 18, wherein, The word line circuit further comprises a switch circuit. The first input end of the switch circuit is connected with the signal generation circuit, the second input end of the switch circuit is configured to receive a clock signal, and the output end of the switch circuit is connected with the inverter chain. The switch circuit is configured to output an initial signal according to the control signal and the clock signal. The inverter chain is specifically configured to output a word line signal according to the initial signal.

20. The word line circuit of claim 18 or 19, wherein, The adjusting circuit is connected with the first end of the inverter circuit, and the second end of the inverter circuit is grounded.

21. The word line circuit of claim 18 or 19, wherein, The signal generation circuit is specifically configured to: generate a control signal of a first level when a decode selection signal indicates that the word line circuit is waiting; and generate a control signal of a second level when the decode selection signal indicates that the word line circuit is working. When the word line circuit comprises the inverter according to any one of claims 1 to 8, the control signal of the first level is used to turn on the first path, and the control signal of the second level is used to turn on the second path; or when the word line circuit comprises the inverter according to any one of claims 9 to 16, the control signal of the first level is used to turn on the third path, and the control signal of the second level is used to turn on the fourth path.

22. A memory, comprising: The word line circuit according to any one of claims 18 to 21, and N word line circuits are connected with N rows of storage units respectively and correspondingly. Each of the N word line circuits is configured to output a word line signal, and the word line signal is used to turn on or turn off the corresponding storage unit row of the word line circuit.

23. The memory of claim 22, wherein, The decoding circuit is further configured to: output a decode selection signal to each of the N word line circuits, wherein the decode selection signal output to a target word line circuit is used to indicate that the target word line circuit is working, and the decode selection signal output to other word line circuits except the target word line circuit is used to indicate that the other word line circuits are waiting; and each word line circuit is specifically configured to: According to the decoding selection signal, a word line signal is output, wherein when the decoding selection signal indicates that the word line circuit is working, the word line signal is used to open the memory cell row corresponding to the word line circuit, and when the decoding selection signal indicates that the word line circuit is waiting, the word line signal is used to close the memory cell row corresponding to the word line circuit.

24. An integrated system characterized by, The memory as claimed in claim 22 or 23, comprising a processor. The processor is configured to send address information to the memory.

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