A data storage and exchange method and architecture for SAR imaging system

Abstract

The present invention relates to a data storage and exchange method and architecture for a SAR imaging system. The method comprises: performing matrix block division on the original data to obtain at least one submatrix; performing equal division on the submatrix in the range direction or in the azimuth direction; three-dimensionally cross-mapping the equally divided submatrix to a first access memory and a second access memory respectively; the first access memory, the second access memory, the first cache module, the second cache module, and the processing engine perform data caching, reading or writing. In the present invention, when the processing engine processes the data of the second cache module, the first access memory, the second access memory and the first cache module perform data reading or writing, so that the idle time of the pipeline is very small and the cache resources are fully utilized; and the processing such as equal division of the original data makes the distance length and the azimuth length of the single burst transmission data equal; thereby improving the data access efficiency.

Description

Technical Field

[0001] The present invention relates to the field of data storage and exchange, and in particular to a data storage and exchange method and architecture for a SAR imaging system. Background Art

[0002] At present, when storing and exchanging data in spaceborne SAR imaging systems, the commonly used matrix transposition scheme is the matrix block three-dimensional mapping method, which uses a single-channel pipeline to read and write data operations to achieve data storage exchange, and uses a sub-matrix linear mapping method to store data in DDR3 (DDR3 refers to the third-generation double data rate synchronous dynamic random access memory).

[0003] 1. Matrix block three-dimensional mapping

[0004] The matrix block three-dimensional mapping method makes full use of the cross-bank (memory bank) priority data access feature of the DDR3 chip to perform matrix block on the SAR raw data, dividing it into several sub-matrices of equal size, and mapping the continuous sub-matrices to different banks in DDR3. The so-called "three-dimensional mapping" means that the continuous sub-matrices in the range and azimuth directions (assuming that each row of the SAR raw data matrix is ​​the range direction and each column is the azimuth direction) will be mapped to different rows in different banks in DDR3, rather than mapping them to continuous rows of the same bank as in the conventional sequential mapping scheme. In this way, the data points in the SAR raw data matrix will be mapped to different banks, different rows, and different columns, that is, mapped to three-dimensional space.

[0005] 2. Single-channel pipeline

[0006] Pipeline technology refers to a quasi-parallel processing implementation technology in which multiple instructions are overlapped during program execution. Pipeline technology can improve the system read and write access efficiency, such as Figure 1 As shown, the current pipeline is a single channel, that is, when data is read out from DDR3A and transmitted to the processing engine for processing, DDR3A simultaneously reads the next distance or azimuth data, and when the processing is completed, the processed data is written to DDR3B. While writing to DDR3B, the processing engine processes the data read from DDR3A, and at this time DDR3A processes the read operation state again to achieve the pipeline processing mode. In the pipeline stage of the single-channel pipeline design, DDR3A and DDR3B have a large pipeline waiting stage, and the pipeline idle time is long, resulting in a large waste of pipeline resources.

[0007] 3. Submatrix linear mapping method

[0008] like Figure 2As shown in the figure, the existing matrix block three-dimensional mapping method stores the data in the sub-matrix into a row in DDR3 by linear mapping. Under this mapping strategy, the adjacent Nr point data in each row of DDR3 belong to the same distance direction, but belong to different azimuth directions. However, the access data in DDR3 adopts the burst mode, that is, reading and writing several storage units continuously, which leads to the limitation of the linear mapping method in terms of on-chip resource utilization and hardware logic design.

[0009] Taking the burst length BL=8 as an example, completing a DDR3 read or write operation will complete the access of 8 consecutive storage units. The 8 data accessed each time belong to the same distance direction and eight different azimuth directions. This makes the access efficiency in the distance direction and azimuth direction greatly unbalanced, reducing the access efficiency of data.

[0010] According to the commonly used matrix transposition scheme for data storage and exchange in existing SAR imaging systems, the pipeline stage of the single-channel pipeline is adopted, and DDR3A and DDR3B have a large pipeline waiting stage, and the pipeline idle time is long, resulting in a large waste of pipeline resources. In addition, the sub-matrix linear mapping method used, the data accessed using the burst mode belongs to the same range direction, but to different azimuth directions, resulting in a large imbalance in the access efficiency in the range direction and azimuth direction. Both aspects reduce the access efficiency of data. Summary of the invention

[0011] The purpose of this application is to solve the defects of the prior art.

[0012] The present application provides a data storage and exchange method and architecture for a SAR imaging system, which reduces pipeline idle time, improves the utilization efficiency of pipeline resources, and balances the access efficiency in range and azimuth directions, thereby improving data access efficiency.

[0013] In a first aspect, the present application provides a data storage and exchange method for a SAR imaging system, the data storage and exchange method comprising: performing matrix block division on original data to obtain at least one sub-matrix, wherein the size of the sub-matrix is ​​obtained after matching with an access memory; performing equal division of the sub-matrix in range or azimuth, wherein the condition for the equal division in range or azimuth is: when reading or writing data in range or azimuth with the total burst length of a first access memory and a second access memory, the range length and azimuth length of a single burst transmission data are equal; three-dimensionally cross-mapping the equally divided sub-matrices to the first access memory and the second access memory, respectively, wherein the three-dimensional cross-mapping condition of the sub-matrix is: three-dimensionally cross-mapped adjacent sub-matrices in range or azimuth to the first access memory. A first access memory and a second access memory have different banks; read first data from the first access memory and the second access memory, and cache the first data in a first cache module; transmit the first data cached in the first cache module to a processing engine for processing data, and at the same time, the first access memory and the second access memory read second data, and cache the second data in the second cache module; transmit the second data cached in the second cache module to a processing engine for processing data, and at the same time, cache the first data processed by the processing engine in the first cache module, write the first data cached in the first cache module to the first access memory and the second access memory, and read third data from the first access memory and the second access memory, and cache the third data in the first cache module.

[0014] In a feasible embodiment, the sub-matrix size is obtained after matching with the access memory, including: the sub-matrix size of the matrix block is equal to the total length of a single distance dimension in the access memory.

[0015] In a feasible embodiment, the three-dimensional cross-mapping of the sub-matrices in adjacent distance directions or adjacent azimuth directions to different banks of the first access memory and the second access memory includes: mapping the sub-matrices in different azimuth directions from the 0th distance upward to the first access memory, bank0 of the second access memory and consecutive rows of the adjacent bank in sequence; mapping the sub-matrices in different azimuth directions from the 1st distance upward to the first access memory, bank1 of the second access memory and consecutive rows of the adjacent bank in sequence; repeating the above steps until the cross-bank three-dimensional cross-matrix mapping of all distance directions and all azimuth directions to the first access memory and the second access memory is completed.

[0016] In a feasible embodiment, the reading of data includes: reading data in range or reading data in azimuth; the writing of data includes: writing data in range or writing data in azimuth.

[0017] In a feasible embodiment, the first cache module and the second cache module include: Ping RAM or Pong RAM in a ping-pong cache module.

[0018] In a second aspect, the present application provides a data storage exchange architecture for a SAR imaging system, the data storage exchange architecture comprising: a matrix partitioning module, used to perform matrix partitioning on raw data to obtain at least one sub-matrix; an equal division module, used to perform equal division on the sub-matrix in range or azimuth; a three-dimensional cross-mapping module, used to cross-map the equally divided sub-matrix to a first access memory and a second access memory across banks in three dimensions; a superscalar pipeline module, comprising: a first access memory, a second access memory, a first cache module, a second cache module, and a processing engine, used for superscalar pipeline data caching, reading or writing between the first access memory, the second access memory and the first cache module, the second cache module, and the first cache module, the second cache module and the processing engine when reading or writing data in range or azimuth (superscalar pipeline means that the CPU supports instruction-level parallelism and can issue multiple instructions per cycle).

[0019] In a feasible embodiment, the first access memory and the second access memory are DDR3A and DDR3B.

[0020] In a feasible embodiment, the sub-matrix size is obtained after matching with the first access memory and the second access memory: the original data and the intermediate processed data are both 16K*16K*64bit, that is, the length of the distance direction and the azimuth direction are both 16K points, and the data size of each point is 64bit. After matching with the length of a row in DDR3A and DDR3B, the sub-matrix size is 64*32=2048 points.

[0021] In a feasible embodiment, the equal division of the sub-matrix in the distance direction or azimuth direction includes: when DDR3A and DDR3B are read or written at the same time, the total burst length is 16, the 16 data read or written belong to 4 consecutive azimuth directions and 4 consecutive distance directions respectively, and the two consecutive distance direction data of the sub-matrix are mapped to the same DDR3, and the equal division of the sub-matrix in the distance direction is: the 0th distance direction, the 1st distance direction, the 4th distance direction, the 5th distance direction...; and the 2nd distance direction, the 3rd distance direction, the 6th distance direction, the 7th distance direction...

[0022] In a feasible embodiment, the three-dimensional cross-mapping of the equally divided sub-matrices to the first access memory and the second access memory includes: mapping the 256 sub-matrices in the 0th distance direction to the 0th row, 1st row, ... 31st row of bank0 to bank7 in DDR3A and DDR3B in a cross-bank manner, and completing the mapping of the 256 sub-matrices in the 0th distance direction. The sub-matrices in the 1st distance direction will be mapped starting from bank1, and will be mapped to bank1-...-bank7-bank0 respectively, and the mapping will start from the 32nd row in the bank until the mapping of the 256 sub-matrices in the 1st distance direction is completed. Repeat the above steps until all sub-matrices in all distance directions are mapped to DDR3A and DDR3B.

[0023] The present application provides a data storage exchange method and architecture for a SAR imaging system. The data storage exchange method and architecture are as follows: in each superscalar pipeline stage, while a processing engine processes data of a second cache module, a first access memory, a second access memory and a first cache module read or write data, so that there is little pipeline idle time and cache resources are fully utilized; and after matrix block and equal-amount division processing is performed on the original data, three-dimensional cross-mapping is performed to the first access memory and the second access memory, and the range length and azimuth length of the data after single burst transmission mapping are equal, and the access efficiency in the range and azimuth directions is balanced; therefore, the present application improves the access efficiency of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the working principle of a single-channel pipeline according to the background technology of the present invention;

[0025] Figure 2 A schematic diagram of the working principle of a submatrix linear mapping of the background technology of the present invention;

[0026] Figure 3 This is a flow chart of a data storage and exchange method for a SAR imaging system according to an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of a process of a data storage and exchange method for a SAR imaging system according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of equally dividing sub-matrices according to an embodiment of the present invention;

[0029] Figure 6 is a schematic diagram of three-dimensional cross mapping according to an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of a distance reading process of a ping-pong cache solution according to an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of an azimuth reading process of a ping-pong cache solution according to an embodiment of the present invention;

[0032] Fig. 9 A schematic diagram of a distance writing process of a ping-pong cache solution according to an embodiment of the present invention;

[0033] Fig.10 A schematic diagram of the azimuth writing process of the ping-pong cache solution according to an embodiment of the present invention;

[0034] Fig.11 A schematic diagram of the composition of a data storage and exchange architecture of a SAR imaging system according to an embodiment of the present invention;

[0035] Fig.12 Schematic diagram of the composition of a superscalar pipeline module according to an embodiment of the present invention;

[0036] Fig.13 A schematic diagram of a non-pipelined working process of an embodiment of the present invention;

[0037] Fig.14 A schematic diagram of the working process of a single-channel pipeline according to an embodiment of the present invention;

[0038] Fig.15 The figure is a schematic diagram of the working process of the superscalar pipeline according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by technicians in the technical field without making creative work are within the scope of protection of the present invention.

[0040] In order to make the public have a better understanding of the present invention, some specific details are described in detail in the following detailed description of the present invention. For those skilled in the art, the present invention can be fully understood without the description of these details.

[0041] Example 1

[0042] Figure 3 The present application provides a flow chart of a data storage and exchange method based on a superscalar pipeline. Figure 1 As shown, the data storage exchange method includes the following steps:

[0043] Step S110, dividing the original data into blocks into matrices to obtain at least one sub-matrix, wherein the size of the sub-matrix is ​​obtained after matching with the access memory;

[0044] Step S120, dividing the sub-matrix equally in the distance direction or in the azimuth direction, wherein the condition for the equal division in the distance direction or in the azimuth direction is that when reading or writing data in the distance direction or in the azimuth direction with the total burst length of the first access memory and the second access memory, the distance length and the azimuth length of a single burst transmission data are equal;

[0045] Step S130, three-dimensionally cross-map the equally divided sub-matrices to the first access memory and the second access memory respectively, and the three-dimensional cross-mapping condition of the sub-matrices is that the sub-matrices in adjacent distance directions or adjacent azimuth directions are three-dimensionally cross-mapped to different banks of the first access memory and the second access memory;

[0046] Step S140, reading first data from the first access memory and the second access memory, and caching the first data in a first cache module;

[0047] Step S150, transmitting the first data cached in the first cache module to the processing engine for processing, and at the same time, the first access memory and the second access memory read the second data, and cache the second data in the second cache module;

[0048] Step S160, transmitting the second data cached in the second cache module to the processing engine for processing, and at the same time, caching the first data processed by the processing engine in the first cache module, writing the first data cached in the first cache module to the first access memory and the second access memory, and reading third data from the first access memory and the second access memory, and caching the third data in the first cache module;

[0049] In step S110, matrix partitioning is performed on the original data to obtain at least one sub-matrix, wherein the size of the sub-matrix is ​​obtained after matching with the access memory.

[0050] For example, Figure 4 FIG. 1 is a process diagram of a data storage and exchange method based on a superscalar pipeline according to an embodiment of the present invention. Figure 4 As shown in the figure, the original data is divided into blocks. The original data and the intermediate result data of SAR imaging processing are both 16K*16K*64bit, that is, the length of the range and azimuth directions are both 16K points, and the data size of each point is 64bit. The size of each block is 64*32=2048 points, which is exactly the length of a row in DDR3A and DDR3B; therefore, the sub-matrix size is designed to be 64*32=2048 points, which can divide the sub-matrix into equal parts and map it to DDR3A and DDR3B in three dimensions.

[0051] In step S120, the sub-matrix is ​​divided equally in the range direction or the azimuth direction.

[0052] First, the matrix block three-dimensional mapping method is retained to make full use of the cross-bank priority data access characteristics of the DDR3 chip. Then, the matrix block three-dimensional mapping method of this application is different from the previous matrix block three-dimensional mapping method in that the present design scheme divides the data of each sub-matrix equally again according to the design size of its sub-matrix, and maps them to a row in the dual-channel DDR3A and DDR3B respectively. DDR3A and DDR3B perform read or write operations at the same time. During the read operation, the data is read from DDR3A and DDR3B in the distance direction or azimuth direction, and enters the processing engine for processing. After processing, the data is written into DDR3A and DDR3B again, and the operation process is cyclic.

[0053] For example, Figure 5 This is a schematic diagram of equal division of sub-matrices according to an embodiment of the present invention. The sub-matrix is ​​equally divided through the equal division scheme of the sub-matrix to meet the requirement of mapping to DDR3A and DDR3B at the same time.

[0054] The two groups of DDR3 can be regarded as a whole with twice the bit width, capacity and bandwidth of a single group of DDR3. When the system issues an access command to the matrix transposition module, the two groups of DDR3 execute the same read or write command together. Since the burst length of a single group of DDR3 is 8, the burst length can be considered to be 16 when the two groups of DDR3 read and write at the same time, that is, 16 data are continuously read or written within 4 clock cycles. And these 16 data can be mapped to a group of data arranged in a square structure in the sub-matrix. These 16 data belong to 4 continuous azimuth directions and 4 continuous distance directions respectively. When a single burst transmission is completed, the 16 data can be stored in the corresponding 4 cache RAMs, so that the RAM can be 100% utilized in each access cycle. These 16 data can be divided into two equal groups in any way and stored in DDR3A and DDR3B respectively. The mapping scheme is as follows. Figure 4 shown.

[0055] In this mapping scheme, two consecutive rows of data in the sub-matrix are mapped to the same DDR3. For example, rows 0 and 1 in the sub-matrix are mapped to DDR3A, rows 2 and 3 are mapped to DDR3B, and so on. The 16 data in the box are the data for the first burst transmission. After the 16 data are burst-transmitted, if it is a distance access, 16 data are transmitted in the distance direction, and if it is an azimuth access, 16 data are transmitted in the azimuth direction, and so on.

[0056] Dividing the data into equal amounts and storing them in DDR3A and DDR3B respectively can increase the amount of data that can be stored in each DDR3 block. With the demand for storage capabilities for massive data, storage capacity is also part of the design considerations.

[0057] In step S130, the equally divided sub-matrices are three-dimensionally cross-mapped to the first access memory and the second access memory respectively, and the three-dimensional cross-mapping condition of the sub-matrices is that the sub-matrices in adjacent distance directions or adjacent azimuth directions are three-dimensionally cross-mapped to different banks of the first access memory and the second access memory.

[0058] For example, Figure 6 Schematic diagram of three-dimensional cross mapping of an embodiment of the present invention. After the matrix is ​​divided into blocks and equal amounts, the sub-matrices are three-dimensionally cross-mapped to DDR3, and the data in each block sub-matrix is ​​equally divided and mapped to a row in DDR3A and DDR3B. Assume that each row of the SAR data matrix is ​​in the range direction, and each column is in the azimuth direction. A row of data in the range direction is called a range line, and a column of data in the azimuth direction is called an azimuth line. According to the following, Figure 6 The three-dimensional mapping scheme shown first maps the 256 sub-matrices on the 0th distance line to the 0th row of bank0 to bank7 in DDR3A and DDR3B in a cross-bank manner. Since the number of sub-matrices on the 0th distance line is greater than the number of banks, after being mapped to bank7, it returns to bank0 and continues mapping from the 1st row of bank0, followed by the 1st row of bank1, the 1st row of bank2...the 1st row of bank7. Currently, rows 0 to 1 of bank0 to bank7 have all been mapped, and then mapping continues from the 2nd row of bank0, the 2nd row of bank1, the 2nd row of bank2...the 2nd row of bank7, and so on and so forth until the 256 sub-matrices on the 0th distance line are mapped.

[0059] Through calculation, the mapping of 256 sub-matrices on the 0th distance line is completed, which requires 32 rows in each bank, that is, bank0~7. Therefore, as shown in the above figure, the R=0th to R=31th rows in bank0~7 of DDR3A and DDR3B will complete the mapping of the 256 sub-matrices on the 0th distance line.

[0060] In order to ensure that the azimuth access also meets the cross-bank principle, the submatrix on the first distance line will start mapping from bank1, and the 32nd row of bank1, the 32nd row of bank2...the 32nd row of bank7, and the 32nd row of bank0 are mapped to bank1-bank7-bank0 respectively. The mapping starts from the 32nd row in the bank, followed by the 33rd row of bank1...the 33rd row of bank7, and the 33rd row of bank0. Subsequent distance lines are also mapped according to the above rules. At this point, all data can be mapped to DDR3A and DDR3B.

[0061] In step S140, first data is read from the first access memory and the second access memory, and the first data is cached in a first cache module.

[0062] For example, Figure 7 Schematic diagram of the distance reading process of the ping-pong cache solution of an embodiment of the present invention (Ping-pong cache is a double cache mechanism used to speed up devices that have both I / O operations and data processing operations. One cache is used to store old versions of data for the read device to read, while the other cache stores the new version of data generated by the write device. When the new data is completed, the read device and the write device will exchange the two caches. The double cache mechanism will improve the throughput of the device and ultimately help avoid the generation of bottlenecks). Figure 7 As shown, when performing distance reading, 8 data in the cache data will be read from DDR3A, belonging to two consecutive distance directions, and stored in the cache Ping RAM0 and Ping RAM1 corresponding to DD3A, while the other 8 data in the cache data will be read from DDR3B, also belonging to two consecutive distance directions, and stored in the cache Ping RAM0 and Ping RAM1 corresponding to DD3B. After the 16 data in the 4 distance directions are read, because it is a distance operation, the other data in the 4 distance directions are read again. When the data in the 4 distance directions in the sub-matrix are read, the sub-matrix of the same distance direction adjacent to it is read again. Repeat the operation until all the data in the 4 distance directions are read.

[0063] After the first four distance data are read and stored in the corresponding DDR3A and DDR3B Ping RAM buffers, DDR3A and DDR3B start reading the next four distance data at the same time. Figure 7As shown, 8 data in the transmission data will be read from DDR3A, belonging to two consecutive distance directions, and the other 8 data in the transmission data will be read from DDR3B, also belonging to two consecutive distance directions. These 4 distance direction data will be stored in the Pong RAM corresponding to DDR3A and DDR3B, and form a pipeline design mode with the Ping RAM corresponding to DDR3A and DDR3B. At this time, while the PongRAM corresponding to DDR3A and DDR3B is caching these 4 distance direction data, the Ping RAM corresponding to DDR3A and DDR3B transmits the previous 4 distance direction data that have been cached to the Computer Core for processing.

[0064] For example, Figure 8 FIG. 1 is a schematic diagram of the azimuth reading process of the ping-pong cache solution according to an embodiment of the present invention. Figure 8 As shown, when performing azimuth reading, 8 data in the cache data will be read from DDR3A, belonging to 4 consecutive azimuths, and stored in the cache RAM0-RAM3 corresponding to DD3A, while the other 8 data in the cache data will be read from DDR3B, belonging to the same azimuth of 4 adjacent distance directions, and stored in the cache RAM0-RAM3 corresponding to DD3B. After the total of 16 data in 4 azimuths are read, since it is an azimuth operation, the operation is repeated to read the other data in these 4 azimuths. When the data in these 4 azimuths in the sub-matrix are read, the sub-matrix in the same azimuth adjacent to it is read in the azimuth until all the data in these 4 azimuths are read.

[0065] After the first four azimuth data are read and stored in the corresponding DDR3A and DDR3B Ping RAM buffers, DDR3A and DDR3B start reading the next four azimuth data at the same time. Figure 8 As shown, 8 data in the transmission data will be read from DDR3A, belonging to 4 consecutive azimuth directions, and the other 8 data in the transmission data will be read from DDR3B, belonging to the same azimuth direction of 4 adjacent distance directions. These 4 azimuth direction data will be stored in the PongRAM corresponding to DDR3A and DDR3B, and form a pipeline design mode with the Ping RAM corresponding to DDR3A and DDR3B. At this time, while the Pong RAM corresponding to DDR3A and DDR3B is caching these 4 azimuth direction data, the Ping RAM corresponding to DDR3A and DDR3B transmits the previous 4 azimuth direction data that have been cached to the Computer Core for processing.

[0066] In step S160, the first data processed by the processing engine is cached in the first cache module, and the first data cached in the first cache module is written into the first access memory and the second access memory, which is further described.

[0067] For example, Fig. 9 FIG. 4 is a schematic diagram of a distance writing process of a ping-pong cache solution according to an embodiment of the present invention. Fig. 9 As shown, when writing in the distance direction, the data belonging to two consecutive distance directions are stored in the cache Ping RAM0 and Ping RAM1 corresponding to DD3A, and the data belonging to the other two consecutive adjacent distance directions are stored in the cache Ping RAM0 and Ping RAM1 corresponding to DD3B. The 8 data in the cache Ping RAM0 and Ping RAM1 corresponding to DD3A are written into the corresponding DD3A, and the 8 data in the cache Ping RAM0 and Ping RAM1 corresponding to DD3B are written into the corresponding DD3B. After the 16 data in the 4 distance directions are written, since it is a distance operation, the other data in the 4 distance directions are written. Repeat the operation until all the data in the 4 distance directions are written.

[0068] After the above 4 distance data are written and stored in the corresponding DDR3A and DDR3B, DDR3A and DDR3B start writing the next 4 distance data at the same time. The Pong RAM corresponding to DDR3A and DDR3B starts caching the next 4 distance data at the same time. Fig. 9 As shown, all data belonging to two consecutive distance directions are stored in the cache Pong RAM0 and Pong RAM1 corresponding to DD3A, and all data belonging to the other two consecutive distance directions are stored in the cache Pong RAM0 and Pong RAM1 corresponding to DD3B. The four distance direction data are written from the cache Pong RAM0 and Pong RAM1 to the corresponding DDR3A and DDR3B, and a pipeline design mode is formed with the Ping RAM corresponding to DDR3A and DDR3B. Exemplarily, while the four distance direction data are stored in the Pong RAM corresponding to DDR3A and DDR3B, the Ping RAM corresponding to DDR3A and DDR3B writes the last four distance direction data that have been cached to the corresponding DDR3A and DDR3B.

[0069] For example, Fig.10 FIG. 1 is a schematic diagram of the azimuth writing process of the ping-pong cache solution according to an embodiment of the present invention. Fig.10As shown, when writing in azimuth, the first 8 data of the 16 data belonging to 4 consecutive azimuths are stored in the cache Ping RAM0-RAM3 corresponding to DD3A, and the last 8 data of the 16 data belonging to the same 4 consecutive azimuths are stored in the cache Ping RAM0-RAM3 corresponding to DD3B, and the operation is repeated until all data in the 4 azimuths are cached. Write the 8 data in the cache Ping RAM0-RAM3 corresponding to DD3A into the corresponding DD3A, and write the 8 data in the cache Ping RAM0-RAM3 corresponding to DD3B into the corresponding DD3B. After the writing of the 16 data of the 4 azimuths is completed, since it is an azimuth operation, the other data of the 4 azimuths are written. Repeat the operation until all data in the 4 azimuths are written.

[0070] After the above 4 azimuth data are written and stored in the Ping RAM cache corresponding to DDR3A and DDR3B, DDR3A and DDR3B simultaneously start writing the next 4 azimuth data, and the Pong RAM corresponding to DDR3A and DDR3B simultaneously start caching the next 4 azimuth data, such as Fig.10 As shown, like the above-mentioned 4-way azimuth data caching method, all 4-way azimuth data are cached in the cache Pong RAM0-RAM3 corresponding to DD3A and the Pong RAM0-RAM3 corresponding to DD3B. Then, the 4-way distance data are written from the cache Pong RAM0-RAM3 to the corresponding DDR3A and DDR3B, and a pipeline design mode is formed with the Ping RAM corresponding to DDR3A and DDR3B. Exemplarily, while the 4-way azimuth data are cached in the Pong RAM corresponding to DDR3A and DDR3B, the Ping RAM corresponding to DDR3A and DDR3B writes the 4-way azimuth data that have been cached to the corresponding DDR3A and DDR3B.

[0071] Example 2

[0072] Fig.11 FIG. 1 is a schematic diagram of a data storage and exchange architecture of a SAR imaging system according to an embodiment of the present invention. Fig.11 As shown, the data storage exchange architecture includes:

[0073] A matrix partitioning module is used to partition the original data into matrix blocks to obtain at least one sub-matrix;

[0074] An equal-amount division module, used for performing equal-amount division of the submatrix in the range direction or the azimuth direction;

[0075] A three-dimensional cross-mapping module, used for three-dimensionally cross-mapping the equally divided sub-matrices to the first access memory and the second access memory across banks;

[0076] A superscalar pipeline module includes: a first access memory, a second access memory, a first cache module, a second cache module, and a processing engine, which is used for superscalar pipeline data caching, reading or writing between the first access memory, the second access memory and the first cache module, the second cache module, and the first cache module, the second cache module and the processing engine when reading or writing data in range or azimuth (superscalar pipeline means that the CPU supports instruction-level parallelism and can issue multiple instructions per cycle).

[0077] Fig.12 FIG. 1 is a schematic diagram of the composition of a superscalar pipeline module according to an embodiment of the present invention. Fig.12 As shown, the data storage exchange architecture of the embodiment of the present application includes: DDR3A, DDR3B: third-generation double data rate synchronous dynamic random access memory; DDR3_TOP: DDR3 protocol control integrated module; DCU Reg: DDR3 control unit register; MIG: multi-layer interconnect signal generator; FIFO IN: write data temporary cache module; WR: write data module;

[0078] ADDR_TOP: address generation module; RD: data reading module; FIFO OUT: temporary data reading cache module; DDR3A_CTRL: DDR3A control integration module; DDR3B_CTRL: DDR3B control integration module; Dline_buf: dual-channel cache integration module; DEU Reg: data exchange unit register; Ping_RAM0, Ping_RAM1, Ping_RAM2, Ping_RAM3: Ping-pong data cache Ping RAM; Pong_RAM0, Pong_RAM1, Pong_RAM2, Pong_RAM3: Ping-pong data cache PongRAM; Data ManageA CTRL, Data ManageB CTRL: data path control module of Ping-PongRAM corresponding to DDR3A or DDR3B; RAMsA Ctrl, RAMsB Ctrl: Ping-PongRAM pipeline and data cache control module corresponding to DDDR3A or DDR3B.

[0079] DDR3A, DDR3B: DDR3 is the third generation of double data rate synchronous dynamic random access memory. DDR SDRAM is a memory chip developed based on SDRAM memory, often referred to as DDR. The biggest feature of DDR is that it has a double transmission rate, that is, data is transmitted once at the rising edge and once at the falling edge of the clock. DDR has gone through several generations of development, from the initial DDR1 to DDR2 and DDR3, and the transmission rate and storage capacity have been continuously improved. DDR3 chips can read and write at 8 times the core frequency of the chip, and have become a commonly used external storage medium in radar signal processing systems.

[0080] DDR3_TOP: DDR3 read / write control top-level module, which integrates the DDR3 read / write control module.

[0081] DCU Reg: DDR3 control unit register. It is used to control the operation flow of DDR3 interaction, such as distance writing, azimuth writing, azimuth reading, etc. It belongs to the DDR3_TOP module.

[0082] MIG: Memory interface control IP core. Used to read and write data with off-chip DDR3. It is the most direct IP core to interact with DDR3.

[0083] FIFO IN: write data to temporary buffer module. Will enter DDR3_CTRL to write to DDR3 for asynchronous FIFO buffer.

[0084] WR: Write data module. It is used to read the data input from Dline_buf to DDR3_TOP module and after passing through DDR3A_CTRL module, and write the data back to DDR3 storage through MIG core;

[0085] ADDR_TOP: Address generation module. It generates the physical address of the data (i.e., page address, row address, and column address) according to the three-dimensional cross-mapping rule of equal division of the dual-channel sub-matrix. It is responsible for generating access addresses with different jump modes according to the corresponding access mode when accessing DDR3, and finally outputs them to the MIG controller to complete the data read / write operation.

[0086] RD: Read data module. Used to read data from DDR3, output after passing through the DDR3_TOP module, and transfer the data to the RAM in the Dline_buf module

[0087] FIFO OUT: Temporary buffering module for read data. The data read from DDR3 and output via DDR3_CTRL is buffered in asynchronous FIFO.

[0088] DDR3A_CTRL: DDR3A control module. Used to control the reading and writing of DDR3A, including the cross-bank reading and writing address and data path of DDR3A.

[0089] DDR3B_CTRL: DDR3B control module. Used to control the reading and writing of DDR3B, including the cross-bank reading and writing address and data path of DDR3B.

[0090] Dline_buf: data cache top-level module. It is used for data interaction buffer between DDR3 and computing engine to ensure that computing is not blocked and form a superscalar pipeline to improve data exchange efficiency.

[0091] DEU Reg: Data exchange unit register. It is used to control the DDR3 output data buffer to be processed and the data buffer to be stored after processing, and belongs to the Dline_buf module.

[0092] Ping_RAM0, Ping_RAM1, Ping_RAM2, Ping_RAM3: Ping RAM for ping-pong data cache; Pong_RAM0, Pong_RAM1, Pong_RAM2, Pong_RAM3: Pong RAM for ping-pong data cache. Used for data cache when DDR3 reads or writes in the distance and azimuth directions.

[0093] Data ManageA CTRL, Data ManageB CTRL: Data path control module of Ping-Pong RAM corresponding to DDR3A or DDR3B. Used to control the data path of Ping-Pong RAM corresponding to DDR3A / B.

[0094] RAMsA Ctrl, RAMsB Ctrl: Ping-Pong RAM pipeline and data cache control module corresponding to DDDR3A or DDR3B. Used to control the Ping-Pong RAM pipeline and data cache corresponding to DDR3A / B.

[0095] Fig.13 A schematic diagram of a non-pipelined working process of an embodiment of the present invention; Fig.14 A schematic diagram of the working process of a single-channel pipeline according to an embodiment of the present invention; Fig.15 FIG. 1 is a schematic diagram of the working process of the superscalar pipeline according to an embodiment of the present invention. Fig.13 , Fig.14 , Fig.15 To further explain, the DDR3A or DDR3B above the "processing engine" and the DDR3A or DDR3B below are the same DDR3A or DDR3B in different working states.

[0096] like Fig.13 , Fig.14 , Fig.15 As shown in the figure, compared with the non-pipelined solution and the single-channel pipeline solution, the superscalar pipeline solution can concurrently execute dual-channel DDR3 read and write operations (dual-channel, that is, designing two memory controllers in the chip, these two memory controllers can work independently of each other, each controller controls a memory channel, and the CPU can address and read data in these two memory channels respectively, thereby doubling the memory bandwidth), that is, performing read or write operations on DDR3A and DDR3B at the same time, increasing data access parallelism. In each pipeline stage, DDR3A and DDR3B are working, which can greatly reduce the idle waiting time in conventional pipeline or non-pipelined design, making the pipeline idle time very small and fully utilizing pipeline resources.

[0097] The storage bandwidth of the traditional single-channel technical solution is limited. The massive data in the SAR imaging system needs to frequently interact with storage media such as DDR3. However, problems such as DDR3's "storage wall (the phenomenon of storage barriers caused by communication bandwidth and latency)" limit the storage bandwidth. Taking the single-channel technical solution as an example, the peak write data bandwidth of DDR3A is B=800M*64bit*2=12.8GB / s. At present, the matrix three-dimensional mapping DDR3 range / azimuth write efficiency is 67%. Therefore, the theoretical write data bandwidth is 8.58GB / s. At this time, after the pipeline is started, the peak read data bandwidth of DDR3B is also B=12.8GB / s, and the DDR3 range / azimuth read efficiency is 80%, so the theoretical read data bandwidth is 10.24GB / s.

[0098] The solution provided by this application is dual-channel DDR3 simultaneous reading and writing. The peak bandwidth of DDR3A and DDR3B writing data at the same time is B=800M*64bit*2*2=25.6GB / s. According to the distance / azimuth writing efficiency of 67%, the theoretical writing bandwidth is B=25.6GB / s*67%=17.15GB / s; compared with a single channel, it has a significant improvement. The peak bandwidth of DDR3A and DDR3B reading data at the same time is B=800M*64bit*2*2=25.6GB / s. According to the distance / azimuth reading efficiency of 80%, the theoretical reading bandwidth is B=25.6GB / s*80%=20.48GB / s. Dual-channel DDR3 simultaneous reading and writing technology has a significant improvement in the theoretical writing bandwidth and theoretical reading bandwidth compared to the single-channel technical solution.

[0099] The first cache module and the first cache module, namely the Ping RAM and Pong RAM in the Ping-Pong cache module of this embodiment are further explained. The isolation of the multi-level bus in the traditional SAR imaging architecture makes data access dependent on the bus bandwidth, resulting in low data exchange efficiency and a serious imbalance between the storage access bandwidth and the data processing bandwidth. The embodiment of the present application no longer uses the multi-level bus mode through the design of the superscalar pipeline and storage mapping scheme. The data exchange efficiency is improved only through the data buffer module and the huge data routing between storage and calculation.

[0100] The present application improves the access bandwidth and storage capacity of two-dimensional data storage in the SAR imaging system, improves the efficiency of two-dimensional data exchange through superscalar pipeline technology, improves the data throughput in the system, and increases the real-time performance of data processing. In each pipeline stage, while the processing engine processes data, the first access memory and the second access memory are both in the working state of executing read or write operations, so that the pipeline idle time is very small and the pipeline resources are fully utilized.

[0101] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. Therefore, it is understood that the above is only one of the specific implementation methods of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data storage and exchange method for a SAR imaging system, characterized in that: The data storage exchange method comprises: Performing matrix block division on the original data to obtain at least one sub-matrix, wherein the size of the sub-matrix is ​​obtained after matching with the access memory; The sub-matrix is ​​divided equally in the distance direction or in the azimuth direction, and the condition for the equal division in the distance direction or in the azimuth direction is that when reading or writing data in the distance direction or in the azimuth direction with the total burst length of the first access memory and the second access memory, the distance length and the azimuth length of the single burst transmission data are equal; The sub-matrices divided equally are three-dimensionally cross-mapped to the first access memory and the second access memory respectively, and the three-dimensional cross-mapping condition of the sub-matrices is that the sub-matrices in adjacent distance directions or adjacent azimuth directions are three-dimensionally cross-mapped to different banks of the first access memory and the second access memory; Reading first data from the first access memory and the second access memory, and caching the first data in a first cache module; The first data cached in the first cache module is transmitted to the processing engine for processing, and the first access memory and the second access memory read the second data, and the second data is cached in the second cache module; The second data cached in the second cache module is transmitted to the processing engine for processing, and the first data processed by the processing engine is cached in the first cache module, and the first data cached in the first cache module is written into the first access memory and the second access memory, and the third data is read from the first access memory and the second access memory, and the third data is cached in the first cache module; The three-dimensional cross-mapping of the sub-matrices in the adjacent distance direction or the adjacent azimuth direction to different banks of the first access memory and the second access memory includes: Mapping sub-matrices in different azimuths upward from the 0th distance in sequence to the first access memory, bank0 of the second access memory and consecutive rows of adjacent banks; Mapping the sub-matrices in different azimuths in the first distance upward to the first access memory, bank 1 of the second access memory and consecutive rows of the adjacent bank in sequence; The above steps are repeated until the cross-bank three-dimensional cross mapping of all range-direction and all azimuth-direction sub-matrices to the first access memory and the second access memory is completed.

2. The data storage exchange method according to claim 1, characterized in that: The sub-matrix size is obtained after matching with the access memory and includes: The sub-matrix size of the matrix block is equal to the total length of a single distance dimension in the access memory.

3. The data storage exchange method according to claim 1, characterized in that: The read data includes: Read data in distance direction or in azimuth direction; The written data includes: Data is written in the distance direction or in the azimuth direction.

4. The data storage exchange method according to claim 1, characterized in that: The first cache module and the second cache module include: Ping RAM or Pong RAM in the Ping-Pong Cache module.

5. A data storage and exchange device for a SAR imaging system, characterized in that: The data storage exchange device comprises: A matrix partitioning module is used to partition the original data into matrix blocks to obtain at least one sub-matrix; An equal-amount division module, used for performing equal-amount division of the submatrix in the range direction or the azimuth direction; A three-dimensional cross-mapping module, used for three-dimensionally cross-mapping the equally divided sub-matrices to the first access memory and the second access memory across banks; the first access memory and the second access memory are DDR3A and DDR3B; wherein the three-dimensional cross-mapping of the equally divided sub-matrices to the first access memory and the second access memory across banks comprises: The 256 sub-matrices in the 0th distance direction are simultaneously mapped to the 0th row and the 1st row to the 31st row of bank0 to bank7 in DDR3A and DDR3B in a cross-bank manner, and the mapping of the 256 sub-matrices in the 0th distance direction is completed; The sub-matrices of the first distance direction will be mapped from bank1 to bank7 and bank0 respectively, and the mapping will start from the 32nd row in the bank until the mapping of the 256 sub-matrices of the first distance direction is completed; Repeat the above steps until all sub-matrices in all distance directions are mapped to DDR3A and DDR3B; A superscalar pipeline module includes: a first access memory, a second access memory, a first cache module, a second cache module, and a processing engine, which is used for superscalar pipeline data caching, reading or writing between the first access memory, the second access memory and the first cache module, the second cache module, and the first cache module, the second cache module and the processing engine when reading or writing data in range or azimuth. The superscalar pipeline requires the CPU to support instruction-level parallelism and can issue multiple instructions per cycle.

6. The data storage exchange device according to claim 5, characterized in that: The matrix partitioning of the original data to obtain at least one sub-matrix includes: The original data and the intermediate processed data are both 16K*16K*64bit, that is, the length of the range and azimuth directions are both 16K points, and the data size of each point is 64bit; after matching the length of a row in DDR3A and DDR3B, the sub-matrix size is 64*32=2048 points.

7. The data storage exchange device according to claim 5, characterized in that: The performing equal division of the submatrix in the distance direction or the azimuth direction comprises: When DDR3A and DDR3B are read or written at the same time, the total burst length is 16. The 16 data read or written belong to 4 consecutive azimuth directions and 4 consecutive distance directions respectively. The two consecutive distance direction data of the sub-matrix are mapped to the same DDR3, and the sub-matrix is ​​divided equally in the distance direction.

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