A neural network topology mapping method for many-core architecture

Abstract

The application discloses a neural network topology structure mapping method for a many-core architecture, uses a four-step algorithm framework based on scale reduction, preliminary segmentation, scale expansion and mapping scheme construction, saves the topology structure to a file system, and applies a graph partition algorithm and a force guiding algorithm, so that memory occupation during compilation of the topology structure of a large-scale neural network is greatly reduced, and the range of the neural network that can be deployed to a neural computing chip is expanded. Meanwhile, by using a heuristic algorithm specific to a mapping problem, the number of iterations and running time are greatly reduced, the compilation efficiency is improved, and the quality of the compilation result is ensured.

Description

Technical Field

[0001] This invention relates to the field of high-performance computer compilation technology, and in particular to a neural network topology mapping method for many-core architectures. Background Technology

[0002] To achieve higher performance, neural networks typically possess complex topologies and a massive number of learnable parameters. In a neural network, each neuron is connected to dozens or even thousands of other neurons, forming a vast and complex network of connections. During the learning and inference process, the computational load is relatively evenly distributed across each neuron. Neural computing chips designed to address this characteristic consist of a two-dimensional array of homogeneous cores. Each core has a certain computational and storage capacity and communicates through an on-chip network. The compilation process of the neural network topology involves dividing the network's topology into several sub-topologies, obtaining a one-to-one mapping between the sub-topologies and the neural computing chip cores, and ultimately outputting a many-to-one mapping between neurons and cores, thus enabling the deployment of the neural network on the neural computing chip.

[0003] Data transmission between neurons is ultimately accomplished through the on-chip network of the neural computing chip, thus requiring consideration of issues such as network congestion and latency. The transmission distance, transmission time, and transmission energy consumption on the neural computing chip are positively correlated. Reducing the transmission distance can lower latency and energy consumption, thereby enabling the neural network to execute more efficiently on the neural computing chip.

[0004] Researchers have designed various compilation techniques for neural network topologies. Techniques such as SNEAP proposed by Shiming Li et al. and SpiNeMap proposed by Adarsha Balaji et al. can solve the topology mapping problem for small-scale neural networks. These techniques divide the compilation process into two stages: a segmentation stage and a mapping stage. In the segmentation stage, the size of the neural network topology is first reduced using the concept of matching. Then, the Kernighan-Lin algorithm or its variants are used to segment the topology into several sub-topologies. Finally, the neural network is restored to its original topology, and optimization methods are applied to optimize the segmentation scheme during this process. After the segmentation stage, the set of neurons in the neural network is divided into several subsets. In the mapping stage, using general heuristic algorithms such as particle swarm optimization, each subset is assigned a neural computing chip core, ultimately obtaining a many-to-one mapping relationship between neurons and cores.

[0005] Because neural network topology mapping techniques operate on the topology of neural networks, they typically handle millions of neurons and hundreds of millions of connections. While the aforementioned compilation techniques reduce the size of neural networks, related papers only present experimental results for small-scale neural networks consisting of thousands of neurons, making it difficult to handle larger-scale networks. Secondly, the mapping relationships are obtained through general heuristic algorithms, which lack specificity for mapping problems, resulting in poor performance and efficiency. Therefore, it is necessary to design a neural network topology mapping technique capable of handling large-scale neural networks while possessing specificity for optimization problems in mapping. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a neural network topology mapping method for many-core architectures, which can handle large-scale neural networks, achieve better compilation performance, and expand the range of neural networks that can run on neural computing chips.

[0007] A method for mapping neural network topology for many-core architectures, comprising:

[0008] Step S1: Save the topology of the neural network as a binary file with a specific data structure. The topology generated in subsequent steps will be saved in the file system in this format and read and written using the specific data structure.

[0009] Step S2-1: Reduce the size of the neural network topology; randomly traverse all vertices in the current topology, select all vertex pairs that meet the conditions, and combine the two vertices in each vertex pair into a new vertex to generate the reduced new topology.

[0010] Step S2-2: For the new topology, repeat step S2-1 until the reduction rate of the number of vertices after reduction is lower than the set ratio.

[0011] Step S3-1: Divide the topology into two sub-topologies with similar numbers of vertices.

[0012] Step S3-2: Repeat the operation of step S3-1 on the newly generated sub-topology until the sum of the vertex sizes in all sub-topologies does not exceed the capacity limit of the neural computing chip core.

[0013] Step S4: Number all sub-topologies to obtain a many-to-one mapping relationship from vertices to sub-topologies;

[0014] Step S5-1: Map the obtained mapping relationship to the topology before reduction; define the weight sum of the edges across the sub-topology as C, traverse all vertices in random order, and transfer the vertices to the sub-topology that reduces C the most.

[0015] Step S5-2: Repeat step S5-1 until a many-to-one mapping relationship between the vertex indices of the original graph and the sub-topology is obtained.

[0016] Step S6: Pack the neurons in each sub-topology into a neuron group to obtain the mapping from neuron number to neuron group number;

[0017] Step S7: Locate the target region for compilation on the neural computing chip or neural computing chip array;

[0018] Step S8-1: Divide the target region into two sub-regions and divide the neuron group into two subgroups; ensure that the size of the subgroup does not exceed the capacity limit of the corresponding sub-region during the division.

[0019] Step S8-2: Repeat step S8-1 until there is only one neuron group in each group, corresponding to one core on the neural computing chip, to obtain a preliminary mapping scheme;

[0020] Step S9-1: Calculate the imaginary force on each neuron group and move the neuron group with the greatest force in the direction of the force.

[0021] Step S9-2: Repeat step S9-1 until the maximum number of iterations is reached;

[0022] Step S10: Deconstruct the neuron group to obtain the many-to-one mapping relationship between neural network neurons and the core of the neural computing chip, that is, the final result of the topological structure mapping.

[0023] Furthermore, in step S1, saving the topology of the neural network as a binary file with a specific data structure specifically involves:

[0024] The vertex index, weight, and size information are all stored using a variable-length type; in each byte, the highest bit indicates whether this byte is the last byte, with 0 representing the last byte and 1 representing that it is not the last byte.

[0025] All connections in the topology are organized by vertex, and the connections adjacent to each vertex are written to the same file. In this file, the number of connections in the file is recorded first, and then the relevant information of each connection is saved in the order of label information, the index of the other vertex of the connection, size, and weight. Finally, the deflate compression algorithm is used to save all files to a zip file.

[0026] In step S2-1, all vertex pairs that meet the conditions are selected. The specific conditions are:

[0027] The two vertices are not marked by other vertex pairs, and the size of the merged vertices does not exceed 1 / 15 of the core capacity limit of the neural computing chip.

[0028] When reducing the size of a neural network topology, it is necessary to calculate the sum of the weights of all connections in the original topology and the sum of the weights of all connections in the new topology to obtain the reduction in the weight sum. Since a random order is used when traversing the vertices, this process needs to be repeated 4 to 8 times to select the new topology with the largest reduction in weight sum as the final output.

[0029] In step S2-2, this continues until the number of vertices after reduction is less than 20% of the number before reduction.

[0030] The specific processes of steps S3-1 and S3-2 are as follows:

[0031] At the start of the segmentation process, all vertices are in the unselected set, and the selected set is empty. First, a vertex is randomly selected from the unselected set and added to the selected set. For each vertex in the unselected set, its selection cost needs to be calculated. The selection cost of a vertex is the difference between the sum of the weights of the connections connecting vertices in the unselected set and the sum of the weights of the connections connecting vertices in the selected set.

[0032] In each iteration, the vertex with the lowest selection cost is moved from the unselected set to the selection set, and then the selection cost of the vertices adjacent to that vertex is updated; a minimum priority queue is used to maintain the selection cost data of the vertices, avoiding sorting or traversing all vertices in each iteration;

[0033] Repeat the iteration until the size of the selection set reaches half the number of vertices in the original topology; at this point, the sum of the weights of all connections that are adjacent to vertices in both the unselected set and the selection set is the splitting cost of this splitting scheme.

[0034] Since the initial value of the selection set is constructed by random selection, the above steps need to be repeated 4 to 8 times to select the segmentation scheme with the lowest segmentation cost. For the two new sub-topologies obtained by segmentation, if the sum of the sizes of the vertices exceeds the capacity limit of the neural computing chip core, then the above segmentation steps are executed recursively, and all the sub-topologies obtained in the end satisfy the capacity limit of the neural computing chip core.

[0035] In step S7, the number of cores in the target region is equal to the number of sub-topologies in the segmentation scheme.

[0036] The specific process of step S9-1 is as follows:

[0037] For each connection in the initial mapping scheme, assuming it connects sub-topologies u and v, let w be the weight of this connection, and (Xu,Yu) and (Xv,Yv) be the coordinates of u and v on the chip or chip array, respectively; then the force on sub-topology u is Fu = (Xv-Xu,Yv-Yu), and the force on sub-topology v is Fv = (Xu-Xv,Yu-Yv); for each sub-topology, the resultant force is calculated using an algorithm; the sub-topologies are sorted according to the magnitude of the resultant force, and the 5% of sub-topologies with the largest resultant force are traversed in descending order;

[0038] For each traversed sub-topology, find another sub-topology to exchange with in the direction of its expected movement; the sum of the change in the net force on the current sub-topology and the change in the net force on the exchanged sub-topology is the exchange cost; find the exchange scheme with the lowest exchange cost and carry out the exchange.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] This invention presents a neural network topology mapping technique for many-core architectures. It employs a four-step algorithm framework based on scaling down, initial partitioning, scaling up, and constructing a mapping scheme. By saving the topology to the file system and applying graph partitioning and force-guided algorithms, it significantly reduces memory usage when compiling the topology of large-scale neural networks, thereby expanding the range of neural networks deployable on neural computing chips. Simultaneously, by using heuristic algorithms specific to the mapping problem, it greatly reduces the number of iterations and runtime, improving compilation efficiency while ensuring the quality of the compilation results. Attached Figure Description

[0041] Figure 1 This is a flowchart of a neural network topology mapping method for many-core architecture according to the present invention;

[0042] Figure 2 This is a binary file diagram illustrating the topology structure in this invention;

[0043] Figure 3 This is a schematic diagram illustrating the scale reduction of the topology in this invention;

[0044] Figure 4 This is a schematic diagram of the hypothetical force acting on the subtopological structure in this invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the embodiments described below are intended to facilitate the understanding of the present invention and do not constitute any limitation thereof.

[0046] like Figure 1 As shown, a neural network topology mapping method for many-core architectures is based on a four-step algorithm framework of scaling down, initial segmentation, scaling up, and constructing a mapping scheme. Specifically, it includes the following steps:

[0047] Step S1: Save the neural network topology as a binary file with a specific structure for easy reading in subsequent steps. All topologies generated in the following steps are saved in this format in the file system and read and written using specific data structures.

[0048] Step S2-1: Reduce the size of the neural network topology. Select all vertex pairs that meet the conditions, and combine the two vertices in each vertex pair into a new vertex to generate the reduced new topology.

[0049] Step S2-2: Repeat step S2-1 until the reduction of the vertices after reduction is below a certain percentage.

[0050] Step S3-1: Divide the topology into two sub-topologies with similar numbers of vertices.

[0051] Step S3-2: Repeat the operation of step S3.1 on the newly generated sub-topologies until the sum of the vertex sizes in all sub-topologies does not exceed the capacity limit of the neural computing chip core.

[0052] Step S4: Number all sub-topologies to obtain a many-to-one mapping relationship between vertices and sub-topologies.

[0053] Step S5-1: Map the obtained mapping relationship to the original topology. Define the sum of the weights of edges across sub-topologies as C. Traverse all vertices in random order and transfer the vertices to the sub-topology that causes the C to decrease the most.

[0054] Step S5-2: Repeat step S5-1 until a many-to-one mapping relationship between the vertex indices of the original graph and the sub-topology is obtained.

[0055] Step S6: Pack the neurons in each sub-topology into a neuron group to obtain the mapping from neuron number to neuron group number.

[0056] Step S7: Locate a usable region on the neural computing chip or neural computing chip array as the target region for compilation.

[0057] Step S8-1: Divide the target region into two sub-regions, and simultaneously divide the neuron group into two subgroups. During division, ensure that the size of each subgroup does not exceed the capacity limit of its corresponding sub-region.

[0058] Step S8-2: Repeat step S8-1 until there is only one neuron group in each group, corresponding to one core on the neural computing chip.

[0059] Step S9-1: Calculate the imaginary force on each neuron group and move the neuron group with the greatest force in the direction of the force.

[0060] Step S9-2: Repeat step S9-1 until the maximum number of iterations is reached.

[0061] Step S10: Deconstruct the neuron group to obtain the many-to-one mapping relationship between neural network neurons and the core of the neural computing chip, that is, the final result of the topological structure mapping.

[0062] The following provides a detailed description of each step and optimization method of the present invention.

[0063] Saving and retrieving topology

[0064] Neural network topologies can contain hundreds of millions of connections, making them difficult to store in memory. To reduce memory usage, the topology is often stored in a file system. A neural network with hundreds of millions of connections, when saved as a file, can reach several gigabytes in size. Furthermore, the mapping process for the topology generates numerous intermediate results. Therefore, the method of saving as a file also requires careful design.

[0065] To save space, vertex indices, weights, dimensions, and other information are stored using variable-length data types. In each byte, the highest bit indicates whether it is the last byte. 0 represents the last byte, and 1 represents not the last byte. For example... Figure 2 As shown in the left figure, the data represented are 000010010101010010101 and 0001101. All connections in the topology are organized by vertex, with adjacent connections of each vertex written to the same file. This file first lists the number of connections within the file, then sequentially saves the relevant information for each connection in the order of its label, the index of the other vertex connected to that edge, its size, and its weight. Finally, the deflate compression algorithm is used to save all files into a zip file, significantly reducing the space occupied by the topology file.

[0066] Reduce the size of the topology

[0067] To reduce the size of the topology, we need to select vertex pairs that meet certain conditions, and then combine the two vertices in each pair into a single vertex, such as... Figure 3As shown. To filter vertex pairs, all vertices in the topology are traversed in random order. For each vertex, the connection with the largest adjacent weight is found. A connection is considered a vertex pair if the following conditions are met:

[0068] (1) The two vertices are not marked by other vertex pairs.

[0069] (2) The size of the merged two vertices does not exceed 1 / 15 of the core capacity limit of the neural computing chip.

[0070] After traversing all vertices, the marked vertex pairs are merged to obtain a new topology. The sum of the weights of all connections in the original topology and the sum of the weights of all connections in the new topology are calculated to obtain the reduction in the weight sum. Since a random order was used when traversing the vertex pairs, this process needs to be repeated 4 to 8 times. The new topology with the largest reduction in weight sum is selected as the output to avoid the influence of randomness on the algorithm.

[0071] Repeat the above process until the number of vertices in the new topology after reduction is less than 20% of the original number. An excessively low reduction rate indicates that the vertex size in the topology is close to 1 / 15 of the core capacity of the neural computing chip, making it impossible to obtain vertex pairs that meet the requirements.

[0072] Construct a preliminary segmentation scheme

[0073] Reducing the number of vertices and connections in the topology can significantly reduce the runtime of subsequent steps. This process constructs a preliminary partitioning scheme on the reduced topology, that is, dividing the vertices in the topology into a certain number of subsets, while ensuring that the size of the vertices in each subset does not exceed the capacity limit of the neural computing chip core.

[0074] At the start of the partitioning process, all vertices are in the unselected set, and the selected set is empty. First, a vertex is randomly selected from the unselected set and added to the selected set. For each vertex in the unselected set, its selection cost needs to be calculated. The selection cost of a vertex is the difference between the sum of the weights of all its adjacent connections to vertices in the unselected set and the sum of the weights of all its adjacent connections to vertices in the selected set. In each iteration, the vertex with the lowest selection cost is moved from the unselected set to the selected set, and then the selection costs of all vertices adjacent to that vertex are updated. Using a minimum priority queue to maintain the vertex selection cost data avoids sorting or traversing all vertices in each iteration.

[0075] Repeat the iteration until the size of the selection set reaches half the number of vertices in the original topology. At this point, the sum of the weights of all connections that are adjacent to vertices in both the unselected set and the selected set is the partitioning cost of this partitioning scheme.

[0076] Since the initial values ​​of the selection set are constructed randomly, the above steps need to be repeated 4 to 8 times to select the segmentation scheme with the lowest cost. For the two new sub-topologies obtained from the segmentation, if the sum of the sizes of their vertices exceeds the capacity limit of the neural computing chip core, then the above segmentation steps are recursively executed. Ultimately, all the resulting sub-topologies satisfy the capacity limit of the neural computing chip core.

[0077] Expand the initial segmentation scheme to the original topology.

[0078] The initial segmentation scheme obtained in the previous step is based on the reduced topology. Therefore, the reduction process needs to be reversed and applied to the initial segmentation scheme to obtain the segmentation scheme based on the original topology. During this process, the initial segmentation also needs to be optimized. The transformation from the original topology to the final topology used to construct the initial segmentation scheme may have involved several reductions. This transformation process sequentially reverses these reduction schemes, and before each reverse application, an optimization algorithm is used to optimize the initial segmentation scheme.

[0079] For each vertex, its degree relative to each sub-topology needs to be calculated. Assume the original topology has been divided into n sub-topologies, numbered V1 to Vn, through the aforementioned steps. For a vertex v located at Vi, calculate the sum of weights for all connections between v and vertices in each of the n sub-topologies. Since there are n sub-topologies, we can obtain n weight sums, named W1 to Wn. Here, the Wi-th weight is the sum of weights for all connections between vertex v and other vertices in its sub-topology. At this point, we can calculate the transfer cost of vertex i. The transfer cost of moving vertex i to the k-th sub-topology is Cik = Wi - Wk, because it increases the overall cost of the partitioning scheme by Cik.

[0080] During optimization, the algorithm traverses all vertices in random order, calculating the lowest possible transfer cost for each vertex. If the lowest transfer cost is negative, it attempts to transfer the vertex to the sub-topology corresponding to the lowest transfer cost. If the sum of the sizes of all vertices in the sub-topology after the transfer does not exceed the capacity limit of the neural computing chip core, the transfer is successful. If the transfer fails, it continues to attempt to transfer the vertex to other sub-topologies in ascending order of transfer cost. Vertex transfers affect the transfer costs of other vertices; therefore, after a vertex transfer occurs, the transfer costs of other vertices need to be updated.

[0081] After optimization, the vertex pairs merged into a single vertex in this reduction are restored, resulting in the partitioning scheme for the previous topology. This process of optimization and transfer continues until the partitioning scheme for the original topology is obtained.

[0082] A preliminary mapping scheme is constructed using the bisection method.

[0083] First, a rectangular region needs to be planned on the neural computing chip or chip array as the target region. The number of cores in this target region should be equal to the number of sub-topologies in the partitioning scheme. Some cores in the rectangular region can be marked as unusable to meet the requirement of equal number.

[0084] If both the number of cores and the number of sub-topologies are 1, then they are bound together; that is, in the mapping scheme, the sub-topology will be mapped to this core. Otherwise, the following binary search algorithm is performed. The target region is divided into two sub-target regions at half the length of the longer side; using the algorithm in the initial segmentation scheme construction step, the set of sub-topologies is divided into two subsets. Then, the above steps are repeated for the two sub-target regions and the two subsets respectively.

[0085] After the above process is completed, each sub-topology will be bound to a neural computing chip core, resulting in a preliminary mapping scheme.

[0086] Optimize the initial mapping scheme using the force-guided algorithm.

[0087] The hypothetical forces acting on the subtopology in the force-guided algorithm, such as Figure 4 As shown. For each connection in the above mapping scheme, assuming it connects sub-topologies u and v, let w be the weight of this connection, and (Xu,Yu) and (Xv,Yv) be the coordinates of u and v on the chip or chip array, respectively. Then the force on sub-topology u is Fu = (Xv-Xu,Yv-Yu), and the force on sub-topology v is Fv = (Xu-Xv,Yu-Yv). For each sub-topology, the algorithm calculates its resultant force. The sub-topologies are sorted according to the magnitude of their resultant forces, and the algorithm iterates through the top 5% of sub-topologies with the largest resultant forces in descending order.

[0088] For each traversed sub-topology, find another sub-topology to exchange with in the desired direction of movement. The sum of the change in the net force on this sub-topology and the change in the net force on the exchanged sub-topology is the exchange cost. Find the exchange scheme with the lowest exchange cost and perform the exchange.

[0089] Repeat the above steps until there are no more feasible exchange options, or the maximum number of iterations has been reached.

[0090] Generate compilation results

[0091] Each vertex in the topology corresponds to a neuron. Based on the optimized mapping scheme, a many-to-one mapping from the topology vertices to the core of the neural computing chip can be obtained. This is essentially a many-to-one mapping relationship from neural network neurons to the core of the neural computing chip, which is the target output of the neural network topology mapping.

[0092] The embodiments described above provide a detailed explanation of the technical solutions and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for mapping the topology of neural networks for many-core architectures, characterized in that, include: Step S1: Save the topology of the neural network as a binary file with a specific data structure. The topology generated in subsequent steps will be saved in the file system in this format and read and written using the specific data structure. Step S2-1: Reduce the size of the neural network topology; randomly traverse all vertices in the current topology, select all vertex pairs that meet the conditions, and combine the two vertices in each vertex pair into a new vertex to generate the reduced new topology. Step S2-2: For the new topology, repeat step S2-1 until the reduction rate of the number of vertices after reduction is lower than the set ratio. Step S3-1: Divide the topology into two sub-topologies with similar numbers of vertices. Step S3-2: Repeat the operation of step S3-1 on the newly generated sub-topology until the sum of the vertex sizes in all sub-topologies does not exceed the capacity limit of the neural computing chip core. Step S4: Number all sub-topologies to obtain a many-to-one mapping relationship from vertices to sub-topologies; Step S5-1: Map the obtained mapping relationship to the topology before reduction; define the weight sum of the edges across the sub-topology as C, traverse all vertices in random order, and transfer the vertices to the sub-topology that reduces C the most. Step S5-2: Repeat step S5-1 until a many-to-one mapping relationship between the vertex indices of the original graph and the sub-topology is obtained. Step S6: Pack the neurons in each sub-topology into a neuron group to obtain the mapping from neuron number to neuron group number; Step S7: Locate the target region for compilation on the neural computing chip or neural computing chip array; Step S8-1: Divide the target region into two sub-regions and divide the neuron group into two subgroups; ensure that the size of the subgroup does not exceed the capacity limit of the corresponding sub-region during the division. Step S8-2: Repeat step S8-1 until there is only one neuron group in each group, corresponding to one core on the neural computing chip, to obtain a preliminary mapping scheme; Step S9-1: Calculate the imaginary force on each neuron group and move the neuron group with the greatest force in the direction of the force; the specific process is as follows: For each connection in the initial mapping scheme, assuming it connects sub-topologies u and v, let w be the weight of this connection, and (Xu,Yu) and (Xv,Yv) be the coordinates of u and v on the chip or chip array, respectively; then the force on sub-topology u is Fu = (Xv-Xu,Yv-Yu), and the force on sub-topology v is Fv = (Xu-Xv,Yu-Yv); for each sub-topology, the resultant force is calculated using an algorithm; the sub-topologies are sorted according to the magnitude of the resultant force, and the 5% of sub-topologies with the largest resultant force are traversed in descending order; For each traversed sub-topology, find another sub-topology to exchange with in the direction of its desired movement; the sum of the change in the net force on the current sub-topology and the change in the net force on the exchanged sub-topology is the exchange cost; find the exchange scheme with the lowest exchange cost and perform the exchange. Step S9-2: Repeat step S9-1 until the maximum number of iterations is reached; Step S10: Deconstruct the neuron group to obtain the many-to-one mapping relationship between neural network neurons and the core of the neural computing chip, that is, the final result of the topological structure mapping.

2. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, In step S1, saving the topology of the neural network as a binary file with a specific data structure involves: The vertex index, weight, and size information are all stored using a variable-length type; in each byte, the highest bit indicates whether this byte is the last byte, with 0 representing the last byte and 1 representing that it is not the last byte. All connections in the topology are organized by vertex, and the connections adjacent to each vertex are written to the same file. In this file, the number of connections in the file is recorded first, and then the relevant information of each connection is saved in the order of label information, the index of the other vertex of the connection, size, and weight. Finally, the deflate compression algorithm is used to save all files to a zip file.

3. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, In step S2-1, all vertex pairs that meet the conditions are selected. The specific conditions are: The two vertices are not marked by other vertex pairs, and the size of the merged vertices does not exceed 1 / 15 of the core capacity limit of the neural computing chip.

4. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, In step S2-1, when reducing the size of the neural network topology, it is necessary to calculate the sum of the weights of all connections in the original topology and the sum of the weights of all connections in the new topology to obtain the reduction in the weight sum. Since a random order is used when traversing the vertices, this process needs to be repeated 4 to 8 times to select the new topology with the largest reduction in weight sum as the final output.

5. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, In step S2-2, this continues until the number of vertices after reduction is less than 20% of the number before reduction.

6. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, The specific processes of steps S3-1 and S3-2 are as follows: At the start of the segmentation process, all vertices are in the unselected set, and the selected set is empty. First, a vertex is randomly selected from the unselected set and added to the selected set. For each vertex in the unselected set, its selection cost needs to be calculated. The selection cost of a vertex is the difference between the sum of the weights of the connections connecting vertices in the unselected set and the sum of the weights of the connections connecting vertices in the selected set. In each iteration, the vertex with the lowest selection cost is moved from the unselected set to the selection set, and then the selection cost of the vertices adjacent to that vertex is updated; a minimum priority queue is used to maintain the selection cost data of the vertices, avoiding sorting or traversing all vertices in each iteration; Repeat the iteration until the size of the selection set reaches half the number of vertices in the original topology; at this point, the sum of the weights of all connections that are adjacent to vertices in both the unselected set and the selection set is the splitting cost of this splitting scheme. Since the initial value of the selection set is constructed by random selection, the above steps need to be repeated 4 to 8 times to select the segmentation scheme with the lowest segmentation cost. For the two new sub-topologies obtained by segmentation, if the sum of the sizes of the vertices exceeds the capacity limit of the neural computing chip core, then the above segmentation steps are executed recursively, and all the sub-topologies obtained in the end satisfy the capacity limit of the neural computing chip core.

7. The neural network topology mapping method for many-core architecture according to claim 1, characterized in that, In step S7, the number of cores in the target region is equal to the number of sub-topologies in the segmentation scheme.

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