Peripheral circuit and memory device for memory cell array

Abstract

The present disclosure relates to a peripheral circuit for a memory cell array, wherein the memory cell array includes multiple memory planes, and the peripheral circuit includes: multiple global word lines; multiple asynchronous multi-plane independent (AMPI) read voltage selection modules, which are used to select one of the voltages from multiple first selected voltages and multiple first unselected voltages, respectively, for performing asynchronous multi-plane independent read operations on the multiple memory planes; a non-asynchronous multi-plane independent read voltage selection module, which is used to select one of the voltages from multiple second selected voltages and multiple second unselected voltages, for performing non-asynchronous multi-plane independent read operations on the multiple memory planes; and multiple global word line voltage selection modules, which are used to select one of the voltages output by the corresponding asynchronous multi-plane independent read voltage selection module and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and output it to the corresponding global word line.

Description

Background Art

[0001] The present disclosure relates to the field of memory technology, and more particularly, to a peripheral circuit for a memory cell array and a memory device.

[0002] In recent years, in order to further increase the bit density of flash memory and reduce its cost, a 3D NAND flash memory including a memory cell array and peripheral circuits has been developed, wherein the memory cell array includes a plurality of memory planes.

[0003] In 3D NAND flash memory, parallel operations are often performed on multiple planes of the memory cell array to increase speed. For example, synchronous multi-plane independent read (SMPI) and asynchronous multi-plane independent read (AMPI) operations are often performed on multiple planes of the memory cell array to increase read speed. Furthermore, erase and program operations can also be performed simultaneously on multiple planes of the memory cell array.

[0004] For synchronous multi-plane independent read, erase, and program operations on multiple memory planes, since the same page on different memory planes is read, erased, and programmed simultaneously, only an appropriate global word line voltage needs to be selected to drive the same word line in all memory planes. However, for asynchronous multi-plane independent read operations on multiple memory planes, since different pages on different memory planes are read simultaneously, different global word line voltages need to be selected for different word lines in different memory planes.

[0005] In existing peripheral circuit structures, to select different pages in different memory planes, a multiplexer (MUX) first selects appropriate global wordline voltages (including selected and unselected voltages) for different wordlines in different memory planes and then outputs them to the global wordlines of the corresponding memory planes. If a memory cell array includes multiple memory planes, the multiplexer used to select appropriate global wordline voltages for different wordlines in different memory planes would occupy excessive area, resulting in an excessively large peripheral circuit area and hindering the miniaturization of memory devices. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a peripheral circuit for a memory cell array is provided, wherein the memory cell array includes multiple memory planes, and the peripheral circuit includes: multiple global word lines; multiple asynchronous multi-plane independent (AMPI) read voltage selection modules, which are used to select one of the voltages from multiple first selected voltages and multiple first unselected voltages, respectively, for performing asynchronous multi-plane independent read operations of the multiple memory planes; a non-asynchronous multi-plane independent read voltage selection module, which is used to select one of the voltages from multiple second selected voltages and multiple second unselected voltages, for performing non-asynchronous multi-plane independent read operations of the multiple memory planes; and multiple global word line voltage selection modules, which are used to select one of the voltages output by the corresponding asynchronous multi-plane independent read voltage selection module and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and output it to the corresponding global word line.

[0007] In some embodiments, the asynchronous multi-plane independent (AMPI) read voltage selection module and the non-asynchronous multi-plane independent read voltage selection module are multiplexers (MUXs).

[0008] In some embodiments, the global word line voltage selection module is a two-to-one multiplexer (MUX).

[0009] In some embodiments, the peripheral circuit further includes a plurality of local word line voltage selection modules for selecting one voltage from the voltage output by the corresponding global word line voltage selection module and a plurality of unselected voltages and outputting it to the corresponding local word line in the corresponding memory plane.

[0010] In some embodiments, the local word line voltage selection module is a multiplexer (MUX)

[0011] In some embodiments, the non-asynchronous multi-plane independent read operation includes a program operation or an erase operation.

[0012] In some embodiments, the plurality of second selected voltages includes the plurality of first selected voltages and the plurality of second unselected voltages includes the plurality of first unselected voltages, and wherein the non-asynchronous multi-plane independent read operation further includes a synchronous multi-plane independent (SMPI) read operation.

[0013] According to an embodiment of the present disclosure, a memory device is provided, including: a memory cell array including a plurality of memory planes; and a peripheral circuit according to the present disclosure.

[0014] According to an embodiment of the present disclosure, a memory system is provided, including: the memory device according to the present disclosure, the memory device being configured to store data; and a memory controller coupled to the memory device and configured to control the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the following detailed description, serve to further explain the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0016] Figure 1 shows a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure;

[0017] Figure 2 shows a schematic diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure;

[0018] Figure 3 shows a schematic diagram of an exemplary solid-state drive (SSD) having a storage device according to some aspects of the present disclosure;

[0019] Figure 4 shows a block diagram of a memory device including a memory cell array according to some aspects of the present disclosure;

[0020] Figure 5 shows a schematic circuit diagram of an exemplary memory device including peripheral circuits according to some aspects of the present disclosure;

[0021] Figure 6 shows a schematic block diagram of an exemplary memory device having multiple memory planes according to some aspects of the present disclosure;

[0022] Figure 7 shows a perspective view of a portion of a three-dimensional memory cell array according to some aspects of the present disclosure;

[0023] Figure 8 A schematic structural diagram of a peripheral circuit for a memory cell array including multiple memory planes according to an embodiment of the present disclosure is shown; and

[0024] Figure 9 A schematic structural diagram of a peripheral circuit for a memory cell array including multiple memory planes according to yet another embodiment of the present disclosure is shown.

[0025] Various aspects of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and are not intended to limit the scope of protection, applicability, or examples set forth in the claims. The functions and arrangements of the elements discussed may be changed without departing from the scope of protection of this specification. Various examples may omit, replace, or add various processes or components as needed. For example, the described method may be performed in an order different from the order described, and various steps may be added, omitted, or combined. In addition, features described relative to some examples may also be combined in other examples.

[0027] It should be noted that references to "one embodiment," "an embodiment," "some embodiments," etc. in the specification indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, such phraseology does not necessarily refer to the same embodiment. Furthermore, when specific features, structures, or characteristics are described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such features, structures, or characteristics in conjunction with other embodiments, whether explicitly described or not.

[0028] The embodiments of the present invention may be described with reference to the accompanying drawings. Unless otherwise specified, the dimensions of the accompanying drawings are intended to simplify the illustrations and are not intended to be a description of relative dimensions. For example, the various lengths / widths / heights of elements in the drawings may not be drawn to scale unless otherwise indicated.

[0029] Embodiments of a peripheral circuit for a memory cell array and a memory device according to the present disclosure will now be described with reference to the accompanying drawings.

[0030] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 1 As shown in FIG, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). Host 108 may be configured to send data to or receive data from memory device 104.

[0031] The memory device 104 may include phase-change memory (RRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), NAND flash memory, NOR flash memory, perpendicular NAND flash memory, spin transfer torque memory (STT-RAM), and the like. In some embodiments, a memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. In some embodiments, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 106 may be configured to control operations of the memory device 104, such as read operations, erase operations, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, wear leveling, etc. Any other suitable functions may also be performed by the memory controller 106, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, etc.

[0032] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of electronic devices, for example, included in the same package (e.g., a universal flash memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2In one example shown in FIG, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may further include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 3 In one example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 306. The SSD 306 may also include a processor that interfaces the SSD 306 with a host (e.g., Figure 1 An SSD connector 308 coupled to the host 108).

[0033] Figure 4 FIG. 4 is a block diagram of a memory device 400 including a memory cell array according to some aspects of the present disclosure. Figure 4 , the memory device 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, a control logic unit 412, a register 414 and a data input / output circuit 416. It should be understood that in some examples, the memory device 400 may also include Figure 4 Additional peripheral circuits not shown.

[0034] The page buffer 404 can be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to control signals from the control logic unit 412. In one example, the page buffer 404 can store data (write data) to be programmed into a selected page of the memory cell array 401. In another example, the page buffer 404 can output the read data during a program verification operation to ensure that the data has been correctly programmed into the corresponding memory cells coupled to the selected word line of the memory cell array 401. The column decoder 406 can operate in response to control signals provided by the control logic unit 412 to select one or more NAND memory strings in the memory cell array 401. The row decoder 408 can operate in response to control signals provided by the control logic unit 412 and select / deselect selected rows of the memory cell array 401. The row decoder 408 can also be configured to supply voltages generated by the voltage generator 410 to selected word lines and unselected word lines of the memory cell array 401. As described in detail below, the row decoder 408 is configured to perform an erase operation on memory cells coupled to one or more selected word lines in the memory cell array 401. The voltage generator 410 can use an external power supply voltage or an internal power supply voltage to generate various voltages required by the memory device, such as a program voltage, a read voltage, a pass voltage, a verification voltage, a bit line voltage, etc., and combinations thereof.

[0035] The control logic unit 412 can be coupled to the voltage generator 410, the page buffer 404, the column decoder 406, the row decoder 408, and the data input / output circuit 416, and is configured to control the operation of each peripheral circuit. The control logic unit 412 can generate an operation signal in response to a command or control signal from the memory controller. The register 414 can be coupled to the control logic unit 412 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The data input / output circuit 416 can be coupled to the control logic unit 412 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 412, as well as buffer status information received from the control logic unit 412 and relay them to the host. The data input / output circuit 416 may also be coupled to the column decoder 406 and function as a data input / output interface and a data buffer to buffer data and relay it to or from the memory cell array 401 .

[0036] Figure 5A schematic circuit diagram of an exemplary memory device 500 including peripheral circuitry according to some aspects of the present disclosure is shown. The memory device 500 includes a memory cell array 501 and peripheral circuitry 502 coupled to the memory cell array 501. The memory cell array 501 can be a NAND flash memory cell array, wherein the memory cells 506 are provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 is capable of holding a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 506. Each memory cell 506 can be a "floating gate" type memory cell including a floating gate transistor, or can be a "charge trap" type memory cell including a charge trapping transistor.

[0037] In some embodiments, each memory cell 506 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, the first memory state "0" can correspond to a first range of voltages, and the second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 506 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed from an erased state to assume one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used as the erased state.

[0038] like Figure 5As shown in FIG, each NAND memory string 508 may include at least one source select gate (SSG) 510 located at its source end and at least one drain select gate (DSG) 512 located at its drain end. The SSG 510 and the DSG 512 can be configured to activate the selected NAND memory string 508 during read and program operations. In some embodiments, the SSGs 510 of the NAND memory strings 508 within the same block 504 are coupled to, for example, ground via a common source line (SL) 514 (e.g., a common SL). According to some embodiments, the DSG 512 of each NAND memory string 508 is coupled to a corresponding bit line 516, and data can be read from the bit line 516 via an output bus (not shown). In some embodiments, each NAND memory string 508 is configured to be selected or deselected by applying a select voltage (e.g., exceeding the threshold voltage of a transistor having the DSG 512) or a deselect voltage (e.g., 0V) to a corresponding DSG 512 via one or more DSG lines 513 and / or by applying a select voltage (e.g., exceeding the threshold voltage of a transistor having the SSG 510) or a deselect voltage (e.g., 0V) to a corresponding SSG 510 via one or more SSG lines 515.

[0039] like Figure 5 As shown in FIG, NAND memory strings 508 can be organized into a plurality of blocks 504, each of which can have a common source line 514. Memory cells 506 in the same row of adjacent NAND memory strings 508 can be coupled via word lines 518. A row of memory cells 506 can be selected or deselected by applying a voltage to the word lines, which is affected by read and program operations. In some embodiments, each word line 518 is coupled to a page 520 of memory cells 506, which is the basic unit of data for programming operations. The size of a page 520, measured in bits, can correspond to the number of NAND memory strings 508 coupled by word lines 518 in a block 504.

[0040] The peripheral circuitry 502 may be coupled to the memory cell array 501 via bit lines 516, word lines 518, source lines 514, SSG lines 515, and DSG lines 513. The peripheral circuitry 502 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 501 by applying a voltage signal and / or a current signal to and sensing a voltage signal and / or a current signal from each target memory cell 506 via the bit lines 516, word lines 518, source lines 514, SSG lines 515, and DSG lines 513, thereby facilitating the operation.

[0041] Figure 6 1 is a schematic block diagram of an exemplary memory device 600 having multiple memory planes according to some aspects of the present disclosure. Figure 6 As shown in FIG, in some embodiments, a memory cell array 601 is arranged according to multiple memory planes 602. Each memory plane 602 is coupled to a word line voltage selection module 603 (including a global word line voltage selection module and a local word line voltage selection module) via a word line to select an appropriate word line voltage for the word line in the memory plane 602. The word line voltage selection module 603 enables the peripheral circuitry for the memory cell array 601 to control the operation of the multiple memory planes 602 in parallel, either synchronously or asynchronously, to improve the operating speed of the memory device 600. It should be understood that as the number of memory planes increases, the number of word line voltage selection modules in the peripheral circuitry for selecting appropriate word line voltages for the word lines in the corresponding memory planes also increases. Therefore, if the area occupied by the word line voltage selection modules for selecting appropriate word line voltages for the word lines in the corresponding memory planes does not decrease, the total area of ​​the peripheral circuitry for the memory cell array including multiple memory planes will continue to increase.

[0042] Figure 7 A perspective view of a portion of an exemplary three-dimensional memory cell array according to an embodiment of the present disclosure is shown. The memory cell array 700 includes a substrate 730 and a memory stack structure 735 above the substrate 730. The memory stack structure 735 includes alternating gate conductive layers and interlayer dielectric layers. The substrate 730 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. The gate conductive layer may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer includes a doped polysilicon layer. The gate conductive layer may include a plurality of word lines 733, at least one source select line 732, and at least one drain select line 734.

[0043] like Figure 7 As shown, the memory cell array 700 includes a plurality of channel structures 712 extending vertically through a memory stack structure 735. In some embodiments, the channel structure 712 includes a memory film 737 and a channel 738. Figure 7 As shown in FIG, according to some embodiments, a well 744 (eg, a P-well and / or an N-well) is formed in the substrate 730, and the source terminal of the memory cell array is in contact with the well 744. It should be understood that although Figure 7Not shown, but additional features of the memory cell array 700 may be formed, including but not limited to gate line slits / source contacts, local contacts, interconnect layers, etc.

[0044] Figure 8 FIG. 8 is a schematic structural diagram of a peripheral circuit 800 for a memory cell array 801 including multiple memory planes according to an embodiment of the present disclosure. Figure 8 As shown in FIG, the memory cell array 801 includes a memory plane 1, a memory plane 2, ..., a memory plane m (m is an integer at least greater than or equal to 2), and each memory plane may include multiple local word lines LWL. For simplicity, only one local word line LWL in each memory plane is shown.

[0045] like Figure 8 As shown in FIG, the peripheral circuit 500 includes a plurality of global word lines GWL, a plurality of global word line voltage selection modules (e.g., global word line voltage selection module 1, global word line voltage selection module 2, ..., global word line voltage selection module m) corresponding to the respective global word lines GWL, and a plurality of local word line voltage selection modules corresponding to the respective global word lines GWL. Each global word line voltage selection module in the peripheral circuit 800 can select different word line voltages (including selected voltages and unselected voltages) to select or unselect memory cells coupled to different word lines in different memory planes. For example, in one embodiment, global word line voltage selection module 1 selects a word line voltage V1 that can be used to select or unselect memory cells coupled to word line 1 in memory plane 1, global word line voltage selection module 2 selects a word line voltage V2 that can be used to select or unselect memory cells coupled to word line 2 in memory plane 2, ..., and global word line voltage selection module m selects a word line voltage Vm that can be used to select or unselect memory cells coupled to word line m in memory plane m. Each global word line voltage selection module then outputs the word line voltages selected for different word lines in different memory planes to the corresponding global word line GWL. By utilizing the different word line voltages selected for different word lines in different memory planes by each global word line voltage selection module, different pages in each memory plane of the memory cell array 801 can be simultaneously selected, thereby enabling asynchronous multi-plane independent reading of multiple memory planes in the memory cell array 801.

[0046] In addition, each global word line voltage selection module in the peripheral circuit 800 can also select the same word line voltage (including selected voltage and unselected voltage) to select or unselect memory cells coupled to the same word line in different memory planes. In one embodiment, global word line voltage selection module 1, global word line voltage selection module 2, ..., global word line voltage selection module m each selects a word line voltage that can be used to select or unselect memory cells coupled to a certain same word line in each memory plane (for example, word line 1 in each memory plane). Then, each global word line voltage selection module outputs the selected same word line voltage to the corresponding global word line GWL. In another embodiment, each global word line voltage selection module in the peripheral circuit 800 can also select the same word line voltage (including selected voltage and unselected voltage) for erase operations and program operations on multiple memory planes. When each global word line voltage selection module selects the same word line voltage, the same page in each storage plane of the memory cell array 801 can be selected simultaneously, thereby enabling synchronous multi-plane independent reading, erasing and programming operations of multiple storage planes of the memory cell array 801.

[0047] like Figure 8 As shown in , the inputs of each global word line voltage selection module include multiple selected voltages and multiple unselected voltages, wherein the multiple selected voltages include multiple selected voltages for biasing the storage cells coupled to each word line in each storage plane so as to enable reading operations thereon and multiple selected voltages for performing erasing operations and programming operations on multiple storage planes; and the multiple unselected voltages include multiple unselected voltages for turning on the storage cells coupled to each word line in each storage plane so as not to perform reading operations thereon and multiple unselected voltages for not performing erasing operations and programming operations on multiple storage planes. For example, in one embodiment, assuming that there are four selected voltages for biasing the memory cells coupled to each word line in each memory plane so that a read operation can be performed on them, and four selected voltages for performing erase operations and programming operations on multiple memory planes; and assuming that there are three unselected voltages for turning on the memory cells coupled to each word line in each memory plane so that a read operation is not performed on them, and three unselected voltages for not performing erase operations and programming operations on multiple memory planes, then each global word line voltage selection module includes 14 input voltages (including the above-mentioned selected voltages and unselected voltages), and before each erase, program, or read operation is performed on the selected memory cells in each memory plane, each global word line voltage selection module needs to select one voltage from the 14 input voltages and output it to the corresponding global word line GWL. For those skilled in the art, the number of the above-mentioned selected voltages and unselected voltages is only an example, and the present disclosure is not limited thereto.

[0048] In addition, if Figure 8 As shown in FIG, a local word line voltage selection module is further connected between each global word line GWL and a local word line LWL on the corresponding memory plane. The module selects a voltage from the voltage output by the global word line voltage selection module and multiple unselected voltages and outputs it to the corresponding local word line LWL. It will be apparent to those skilled in the art that the correspondence between global word lines GWL and local word lines LWL can be set based on actual needs. For example, one global word line GWL can correspond to one local word line LWL in each memory plane, or it can correspond to multiple local word lines LWL in each memory plane.

[0049] In practical applications, the global word line voltage selection module and the local word line voltage selection module may be multiplexers (MUXs). As described above, when each global word line voltage selection module includes 14 input voltages, the global word line voltage selection module may be a 14-to-1 multiplexer (MUX).

[0050] Figure 9 FIG. 1 shows a schematic structural diagram of a peripheral circuit 900 for a memory cell array 901 including multiple memory planes according to another embodiment of the present disclosure. Figure 9 As shown in FIG, the memory cell array 901 includes a memory plane 1, a memory plane 2, ..., a memory plane m (m is an integer at least greater than or equal to 2), and each memory plane may include multiple local word lines LWL. For simplicity, only one local word line LWL in each memory plane is shown.

[0051] like Figure 9 As shown in FIG, the peripheral circuit 900 includes a plurality of global word lines GWL, a plurality of global word line voltage selection modules (e.g., global word line voltage selection module 1, global word line voltage selection module 2, ..., global word line voltage selection module m) corresponding to the respective global word lines GWL, and a plurality of local word line voltage selection modules corresponding to the respective global word lines GWL. Figure 8 The peripheral circuit 800 shown in FIG. 8 is different in that the peripheral circuit 900 further includes a plurality of asynchronous multi-plane independent (AMPI) read voltage selection modules corresponding to the corresponding global word line voltage selection modules and one non-asynchronous multi-plane independent (AMPI) read voltage selection module.

[0052] The multiple asynchronous multi-plane independent (AMPI) read voltage selection modules of the peripheral circuit 900 can respectively select different word line voltages (including selected voltages and unselected voltages) to select or unselect memory cells coupled to different word lines in different memory planes. For example, in one embodiment, asynchronous multi-plane independent (AMPI) read voltage selection module 1 selects word line voltage V1 that can be used to select or unselect memory cells coupled to word line 1 in memory plane 1, asynchronous multi-plane independent (AMPI) read voltage selection module 2 selects word line voltage V2 that can be used to select or unselect memory cells coupled to word line 2 in memory plane 2, ..., and asynchronous multi-plane independent (AMPI) read voltage selection module m selects word line voltage Vm that can be used to select or unselect memory cells coupled to word line m in memory plane m. Then, each asynchronous multi-plane independent (AMPI) read voltage selection module outputs the word line voltages selected for different word lines in different memory planes to the corresponding global word line voltage selection module. For example, in one embodiment, the word line voltage V1 selected by the asynchronous multi-plane independent (AMPI) read voltage selection module 1 is output to the global word line voltage selection module 1, the word line voltage V2 selected by the asynchronous multi-plane independent (AMPI) read voltage selection module 2 is output to the global word line voltage selection module 2,..., the word line voltage Vm selected by the asynchronous multi-plane independent (AMPI) read voltage selection module m is output to the global word line voltage selection module m.

[0053] The non-asynchronous multi-plane independent (AMPI) read voltage selection module of the peripheral circuit 900 can select a voltage from a plurality of input voltages (including selected voltages and unselected voltages) for performing erase operations and programming operations on the plurality of memory planes, or for not performing erase operations and programming operations on the plurality of memory planes. For example, in one embodiment, the non-asynchronous multi-plane independent (AMPI) read voltage selection module selects a voltage that can be used for erase operations on the plurality of memory planes and then outputs the selected voltage to the corresponding global word line voltage selection module. In another embodiment, the non-asynchronous multi-plane independent (AMPI) read voltage selection module selects a voltage that can be used for programming operations on the plurality of memory planes and then outputs the selected voltage to the corresponding global word line voltage selection module.

[0054] like Figure 9As shown in , each global word line voltage selection module selects one voltage from the voltage output by the corresponding asynchronous multi-plane independent read voltage selection module and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and outputs it to the corresponding global word line. Specifically, global word line voltage selection module 1 selects one voltage from the voltage output by the asynchronous multi-plane independent read voltage selection module 1 and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and outputs it to global word line GWL1. Global word line voltage selection module 2 selects one voltage from the voltage output by the asynchronous multi-plane independent read voltage selection module 2 and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and outputs it to global word line GWL2. ... Global word line voltage selection module m selects one voltage from the voltage output by the asynchronous multi-plane independent read voltage selection module m and the voltage output by the non-asynchronous multi-plane independent read voltage selection module, and outputs it to global word line GWLm.

[0055] When each global word line voltage selection module respectively selects the voltage output by the corresponding asynchronous multi-plane independent read voltage selection module and outputs it to the corresponding global word line, different pages in each storage plane of the memory cell array 901 can be selected at the same time, thereby realizing asynchronous multi-plane independent reading of multiple storage planes of the memory cell array 901; when each global word line voltage selection module selects the voltage output by the non-asynchronous multi-plane independent read voltage selection module and outputs it to the corresponding global word line, it can realize the erase operation and programming operation of multiple storage planes of the memory cell array 901.

[0056] like Figure 9As shown in , the inputs of each asynchronous multi-plane independent read voltage selection module include multiple selected voltages and multiple unselected voltages. For example, in one embodiment, the multiple selected voltages include multiple selected voltages for biasing the memory cells coupled to each word line in each memory plane so that a read operation can be performed on them; and the multiple unselected voltages include multiple unselected voltages for turning on the memory cells coupled to each word line in each memory plane so that a read operation is not performed on them. For example, in one embodiment, assuming that there are four selected voltages for biasing the memory cells coupled to each word line in each memory plane so that a read operation can be performed on them; and assuming that there are three unselected voltages for turning on the memory cells coupled to each word line in each memory plane so that a read operation is not performed on them, then each asynchronous multi-plane independent read voltage selection module includes seven input voltages (including the above-mentioned selected voltages and unselected voltages). In actual applications, the asynchronous multi-plane independent read voltage selection module can be a multiplexer (MUX). As described above, when each asynchronous multi-plane independent read voltage selection module includes seven input voltages, each asynchronous multi-plane independent read voltage selection module can be a 7-to-1 multiplexer (MUX). For those skilled in the art, the number of selected voltages and unselected voltages described above is merely an example, and the present disclosure is not limited thereto.

[0057] like Figure 9 As shown in , the inputs of the non-asynchronous multi-plane independent read voltage selection module also include multiple selected voltages and multiple unselected voltages, wherein the multiple selected voltages include multiple selected voltages for performing erase operations or programming operations on multiple memory planes; and the multiple unselected voltages include multiple unselected voltages for not performing erase operations or programming operations on multiple memory planes. For example, in one embodiment, assuming that the multiple selected voltages for performing erase operations or programming operations on multiple memory planes are four, and assuming that the multiple unselected voltages for not performing erase operations or programming operations on multiple memory planes are three, the non-asynchronous multi-plane independent read voltage selection module also includes seven input voltages (including the aforementioned selected voltages and unselected voltages). In actual applications, the non-asynchronous multi-plane independent read voltage selection module can be a multiplexer (MUX). As described above, when the non-asynchronous multi-plane independent read voltage selection module includes seven input voltages, the non-asynchronous multi-plane independent read voltage selection module can be a 7-to-1 multiplexer (MUX). For those skilled in the art, the number of selected voltages and unselected voltages described above is merely an example, and the present disclosure is not limited thereto.

[0058] use Figure 9The peripheral circuit 900 shown in FIG. 1 selects a voltage from the outputs of the corresponding asynchronous multi-plane independent read voltage selection module and the non-asynchronous multi-plane independent read voltage selection module and outputs it to the corresponding global word line before each erase, program, or read operation is performed on the selected memory cells in each memory plane. This enables asynchronous multi-plane independent read, erase, and program operations for the multiple memory planes of the memory cell array 901. Furthermore, when the inputs of the non-asynchronous multi-plane independent read voltage selection module also include the inputs of the asynchronous multi-plane independent read voltage selection modules, the peripheral circuit 900 can also enable synchronous multi-plane independent read operations for the multiple memory planes of the memory cell array 901.

[0059] Likewise, if Figure 9 As shown in FIG, a local word line voltage selection module is further connected between each global word line GWL and a local word line LWL on the corresponding memory plane. The module selects a voltage from the voltage output by the global word line voltage selection module and multiple unselected voltages and outputs it to the corresponding local word line LWL. It will be apparent to those skilled in the art that the correspondence between global word lines GWL and local word lines LWL can be set based on actual needs. For example, one global word line GWL can correspond to one local word line LWL in each memory plane, or it can correspond to multiple local word lines LWL in each memory plane.

[0060] In practical applications, the asynchronous multi-plane independent read voltage selection module, the non-asynchronous multi-plane independent read voltage selection module, the global word line voltage selection module, and the local word line voltage selection module may be multiplexers (MUX). Figure 9 As shown in the figure, in the case where each global word line voltage selection module is used to select one of the voltages output from the corresponding asynchronous multi-plane independent read voltage selection module and the voltage output from the non-asynchronous multi-plane independent read voltage selection module and output it to the corresponding global word line, each global word line voltage selection module is a 2-to-1 multiplexer (MUX).

[0061] Assuming that there are four selected voltages for biasing the memory cells coupled to each word line in each memory plane so as to enable a read operation thereon, and three unselected voltages for turning on the memory cells coupled to each word line in each memory plane so as not to perform a read operation thereon, and assuming that there are four selected voltages for performing an erase operation or a program operation on the multiple memory planes, and three unselected voltages for not performing an erase operation or a program operation on the multiple memory planes, Figure 8One of the 14-to-1 multiplexers (MUX) serving as a global word line voltage selection module can be replaced by a 7-to-1 multiplexer (MUX) serving as an asynchronous multi-plane independent read voltage selection module and a 2-to-1 multiplexer (MUX) serving as a global word line voltage selection module, and a 7-to-1 multiplexer (MUX) shared by multiple global word line voltage selection modules and serving as a non-asynchronous multi-plane independent read voltage selection module can be added to achieve asynchronous multi-plane independent read, erase, and program operations for multiple storage planes of the memory cell array 901. In the case where the memory cell array 901 includes m storage planes, Figure 8 Compared with the peripheral circuit 800 shown in Figure 9 The area occupied by the multiplexer in the peripheral circuit 900 shown in FIG. 1 is greatly reduced, thereby greatly reducing the area occupied by the peripheral circuit and facilitating the miniaturization of the memory device.

[0062] According to an embodiment of the present disclosure, a corresponding global word line voltage selection module, a corresponding asynchronous multi-plane independent read voltage selection module, and a non-asynchronous multi-plane independent read voltage selection module are provided before the corresponding global word line of the memory cell in the NAND memory string in the corresponding memory plane, thereby significantly reducing the area occupied by the multiplexer in the peripheral circuit of the memory cell array. It will be apparent to those skilled in the art that the configuration of providing the corresponding global word line voltage selection module, the corresponding asynchronous multi-plane independent read voltage selection module, and the non-asynchronous multi-plane independent read voltage selection module before the corresponding global word line in the embodiment of the present disclosure is also applicable to the word lines coupled to the top select gate (TSG), the bottom select gate (BSG), and the dummy memory cell. In other words, providing the corresponding global word line voltage selection module, the corresponding asynchronous multi-plane independent read voltage selection module, and the non-asynchronous multi-plane independent read voltage selection module before the corresponding word line of the top select gate (TSG), the bottom select gate (BSG), and the dummy memory cell also significantly reduces the area occupied by the multiplexer in the peripheral circuit of the memory cell array.

[0063] It should be noted that not all units in the above system structure diagrams are required, and some units may be omitted according to actual needs. The device structures described in the above embodiments can be physical structures or logical structures. That is, some units may be implemented by the same physical entity, or some units may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0064] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0065] The foregoing description of the present disclosure is provided to enable any person skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to be consistent with the widest range of principles and novel features disclosed herein.

Claims

1. A peripheral circuit for a memory cell array, wherein the memory cell array includes a plurality of memory planes, the peripheral circuit comprising: multiple global word lines; a plurality of asynchronous multi-plane independent (AMPI) read voltage selection modules, configured to select one voltage from a plurality of first selected voltages and a plurality of first unselected voltages, respectively, for performing asynchronous multi-plane independent read operations on the plurality of memory planes; a non-asynchronous multi-plane independent read voltage selection module, configured to select one voltage from a plurality of second selected voltages and a plurality of second unselected voltages, for performing a non-asynchronous multi-plane independent read operation on the plurality of storage planes; as well as A plurality of global word line voltage selection modules are used to select one voltage from the voltage output by the corresponding asynchronous multi-plane independent read voltage selection module and the voltage output by the non-asynchronous multi-plane independent read voltage selection module and output it to the corresponding global word line.

2. The peripheral circuit according to claim 1, wherein The asynchronous multi-plane independent (AMPI) read voltage selection module and the non-asynchronous multi-plane independent read voltage selection module are both multiplexers (MUX).

3. The peripheral circuit according to claim 1, wherein: The global word line voltage selection module is a two-to-one multiplexer (MUX).

4. The peripheral circuit according to claim 1 further comprises a plurality of local word line voltage selection modules for selecting a voltage outputted by the corresponding global word line voltage selection module and a plurality of unselected voltages and outputting the voltage to the corresponding local word line in the corresponding memory plane.

5. The peripheral circuit according to claim 4, wherein: The local word line voltage selection module is a multiplexer (MUX).

6. The peripheral circuit according to claim 1, wherein The non-asynchronous multi-plane independent read operation includes a program operation or an erase operation.

7. The peripheral circuit according to claim 6, wherein: The plurality of second selected voltages includes the plurality of first selected voltages and the plurality of second unselected voltages includes the plurality of first unselected voltages, and wherein the non-asynchronous multi-plane independent read operation further includes a synchronous multi-plane independent (SMPI) read operation.

8. A storage device comprising: A memory cell array, the memory cell array comprising a plurality of memory planes; as well as The peripheral circuit according to any one of claims 1 to 7.

9. A storage system comprising: The memory device according to claim 8, wherein the memory device is configured to store data; as well as A memory controller is coupled to the memory device and configured to control the memory device.

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