A control method and circuit for an isolation converter

Abstract

The present invention provides a control method and circuit for an isolated converter. The isolated converter includes a primary-side controller, a secondary-side controller, and a magnetic isolation coupling device. The implementation scheme is as follows: the secondary-side controller modulates an output voltage feedback signal into a drive signal whose frequency or duty cycle varies with the load, and then transmits the signal to the primary-side controller via the magnetic isolation coupling device. After receiving the secondary-side modulated drive signal, the primary-side controller supplies power to its power input terminal via a bridge rectifier. Simultaneously, the received secondary-side modulated signal is demodulated into a pulse signal and a voltage signal. The pulse signal is used to stop the oscillator of the primary-side controller. The voltage signal is used to generate a drive signal to control a main power switch. The frequency or duty cycle of the drive signal is adjusted in combination with a peak current sampling signal. The present invention requires only a single magnetic isolation coupling device and can achieve both magnetic isolation feedback and steady-state power supply to the primary side, achieving two goals at once.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a control method and circuit for an isolation converter, which are used for controlling a main power switch tube in the isolation converter. Background Art

[0002] Switching power supplies are widely used in the industrial sector due to their high efficiency and ability to boost and buck voltages. Switching power supplies require sensing output voltage or current information and feeding it back to the control circuit to control the on / off switching of the power transistors, achieving energy transfer. Feedback paths are categorized as either isolated or non-isolated depending on whether safety regulations are met. Isolated feedback utilizes isolation devices to disconnect the feedback path to meet safety regulations. Common isolation methods for isolated feedback include magnetic, optocoupler, and capacitive. Optocoupler isolation consumes relatively high power, is slow, has a short lifespan, and exhibits significant performance degradation under high temperatures and high radiation. Magnetic or capacitive isolation utilizes transient magnetic or electric fields to discretely feed output information back to the control circuit. These methods offer low power consumption, high speed, long lifespan, and suitability for extreme environments. Capacitive isolation, on the other hand, requires a compromise between isolation distance and capacitance value, leading to increasing interest in magnetically isolated feedback.

[0003] In magnetically isolated feedback applications, existing technologies chop the secondary-side feedback signal from the isolated power supply before transmitting it to the primary-side controller via a magnetic isolation transformer, such as the Texas Instruments (TI) UC1901 chip. In this technology, the magnetic isolation transformer actually converts the power of the secondary-side feedback signal to the primary side. This makes it difficult to make the transformer smaller, and the transformer continuously transmits square wave signals, resulting in high power consumption.

[0004] In comparison, a Chinese patent 201410085973.X published by Power Integrations (PI) uses a secondary-side PSM (Peripheral Span Modulation) to determine whether to send a power tube turn-on signal to the primary side based on the comparison between the output voltage and the reference. The technology uses a state machine on the primary side to select the current limit point to shut down the power tube. This technology intermittently sends narrow pulses from the secondary side to the primary side to turn on the power tube, significantly reducing the size of the magnetic isolation transformer and reducing power consumption. The secondary-side control method also facilitates the implementation of synchronous rectification. Furthermore, this technology integrates the primary and secondary side chips and the magnetic isolation transformer into a single package, improving the power density of the power supply.

[0005] However, the above-mentioned existing technologies only implement magnetically isolated feedback control. The magnetic isolation transformer is only used for signal transmission, not energy transmission. In other words, the primary-side controller still needs to be powered by an auxiliary winding in the steady state, which increases the size and manufacturing cost of the main power transformer. Therefore, there is an urgent need for a magnetically isolated feedback technology that can not only achieve primary-to-secondary control and voltage regulation through magnetically isolated signal transmission, but also transfer energy to the primary through magnetic isolation, thus realizing primary-side power supply without the need for an auxiliary winding. Summary of the Invention

[0006] In view of the shortcomings and limitations of the above-mentioned prior art, the first technical problem to be solved by the present invention is: to provide a control method for an isolated converter, which is used to control the main power switch tube in the isolated converter, and can realize primary-secondary side control and voltage stabilization through magnetic isolation signal transmission, and can also realize primary side power supply by transferring energy to the primary side through magnetic isolation, without the need for auxiliary winding.

[0007] Correspondingly, the second technical problem to be solved by the present invention is to provide a power supply and feedback control circuit using the above method.

[0008] The technical solution of the present invention to solve the above-mentioned first technical problem is:

[0009] A control method for an isolation converter, wherein the isolation converter includes a main power switch tube, a primary side controller, and a secondary side controller, is characterized by comprising the following steps:

[0010] The output voltage feedback and loop compensation step performs loop compensation on the output voltage feedback signal to generate a voltage signal VEA that can reflect load changes;

[0011] A frequency conversion or duty cycle control step, wherein the voltage signal VEA generates two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 whose frequencies and duty cycles vary with the voltage signal VEA; or the voltage signal VEA generates a low-voltage drive signal V_pwm whose frequency is fixed but whose duty cycle varies with the voltage signal VEA;

[0012] A modulation signal driving step, generating two quasi-complementary driving signals TS1 and TS2 with driving capability from the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm;

[0013] A magnetic isolation transmission step is performed to isolate and transmit the drive signals TS1 and TS2 and generate drive signals TR1 and TR2 accordingly;

[0014] The primary side power supply and receiving demodulation step supplies power to the primary side controller through bridge rectification of the drive signals TR1 and TR2, and demodulates either of the drive signals TR1 and TR2 into a primary side inductor current modulation voltage signal VCS_Lim and a narrow pulse signal Tpulse_H;

[0015] The main power switch control step includes: before the output voltage is established, the oscillator in the primary-side controller generates a control signal to control the main power switch to be turned on and off; after the output voltage is established, the narrow pulse signal Tpulse_H controls the oscillator in the primary-side controller to stop working, and the primary-side inductor current modulation voltage signal VCS_Lim generates a control signal. The frequency or duty cycle of the control signal is adjusted in combination with the main power switch source peak current sampling signal to control the main power switch to be turned on and off;

[0016] From the output voltage feedback and loop compensation steps to the main power switch tube control step, this cycle is repeated to achieve closed-loop control and energy transmission.

[0017] Furthermore, in the output voltage feedback and loop compensation step, the feedback signal of the output voltage is compared with the first reference voltage signal VREF1 through the error amplifier, and by setting the gain and bandwidth of the error amplifier and combining loop compensation, a voltage signal VEA that can reflect load changes is generated.

[0018] Furthermore, the isolation converter further comprises a synchronous rectifier tube, and in the frequency conversion or duty cycle control step, a signal for controlling the shutdown of the synchronous rectifier tube is also generated simultaneously.

[0019] Furthermore, in the frequency conversion or duty cycle control step, the voltage signal VEA and the second reference voltage signal VREF2 output a current signal that varies with the voltage signal VEA through a transconductance amplifier. This current signal then outputs a frequency signal that varies with the voltage signal VEA through an oscillator. Then, through dead time control, two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 are generated, whose duty cycles vary with the voltage signal VEA.

[0020] Furthermore, in the frequency conversion or duty cycle control step, the voltage signal VEA and the signal generated by the triangle wave generator are output through the comparator CMP as a low voltage driving signal V_pwm with a fixed frequency but a duty cycle that varies with the voltage signal VEA.

[0021] Furthermore, in the frequency conversion or duty cycle control step, the higher the level of the voltage signal VEA is, the greater the duty cycle of the low-voltage driving signals Ton_H1 and Ton_H2 , or the low-voltage driving signal V_pwm.

[0022] Furthermore, in the modulation signal driving step, the low-voltage driving signals Ton_H1 and Ton_H2 are converted into two quasi-complementary NMOS tube driving signals and two quasi-complementary PMOS tube driving signals through an inverter chain and a totem pole driving structure, and then two quasi-complementary driving signals TS1 and TS2 with driving capability are generated through a built-in full-bridge power tube.

[0023] Furthermore, in the modulation signal driving step, the low voltage driving signal V_pwm generates two quasi-complementary driving signals TS1 and TS2 with driving capability through a cross-coupled oscillator.

[0024] Furthermore, the smaller the duty cycle of the driving signals TR1 and TR2 or the lower the frequency, the smaller the level of the primary inductor current modulation voltage signal VCS_Lim, and the smaller the duty cycle of the control signal generated by the primary inductor current modulation voltage signal VCS_Lim.

[0025] Accordingly, the technical solution of the present invention to solve the second technical problem is:

[0026] A control circuit for an isolation converter, comprising a main power switch, a primary-side controller, and a secondary-side controller, is characterized in that it includes the following units:

[0027] The error amplifier and compensation unit is used to perform loop compensation on the feedback signal of the output voltage to generate a voltage signal VEA that can reflect load changes;

[0028] A PFM or PWM unit is configured to generate, from the voltage signal VEA, two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 whose frequencies and duty cycles vary with the voltage signal VEA; or to generate, from the voltage signal VEA, a low-voltage drive signal V_pwm whose frequency is fixed but whose duty cycle varies with the voltage signal VEA;

[0029] A modulation signal driving unit, configured to generate two quasi-complementary driving signals TS1 and TS2 with driving capability from the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm;

[0030] A magnetic isolation transmission unit, configured to isolate and transmit the drive signals TS1 and TS2 and generate corresponding drive signals TR1 and TR2;

[0031] The primary side power supply and receiving demodulation unit is used to power the primary side controller through the bridge rectification of the driving signals TR1 and TR2, and at the same time demodulate any one of the driving signals TR1 and TR2 into the primary side inductor current modulation voltage signal VCS_Lim and the narrow pulse signal Tpulse_H;

[0032] The main power switch control unit is used to generate a control signal through the oscillator in the primary-side controller before the output voltage is established, so as to realize the control of turning on and off the main power switch. After the output voltage is established, the narrow pulse signal Tpulse_H controls the oscillator in the primary-side controller to stop working, and the primary-side inductor current modulation voltage signal VCS_Lim and the main power switch source peak current sampling signal jointly generate a control signal to realize the control of turning on and off the main power switch.

[0033] As a specific embodiment of the error amplifier & compensation unit, it is characterized by: including an error amplifier EA and a built-in compensation network; the non-phase input terminal of the error amplifier EA is used to input the first reference voltage signal VREF1, its negative input terminal is simultaneously connected to the VFB pin of the secondary-side controller and the output terminal of the built-in compensation network, its output terminal is connected to the input terminal of the built-in compensation network, and serves as the output terminal of the error amplifier & compensation unit 201, outputting the voltage signal VEA.

[0034] Furthermore, the isolation converter also includes a synchronous rectifier tube, and a signal for controlling the shutdown of the synchronous rectifier tube is also generated in the frequency conversion or duty cycle control unit to realize the control of the opening and closing of the synchronous rectifier tube.

[0035] As a specific embodiment of the PFM or PWM unit, it is characterized by: including a transconductance amplifier OTA, an oscillator OSC, a dead time control 1, a dead time control 2, a NAND gate nand1, a NAND gate nand2, a NOT gate not1 and a NOT gate not2; the first input end of the transconductance amplifier OTA is used to input a voltage signal VEA, the second input end thereof is used to input a second reference voltage signal VREF2, the first output end thereof outputs a current signal IOTA1 to the first input end of the oscillator OSC, the second output end thereof outputs a current signal IOTA2 to the first input end of the dead time control 1, and the third output end thereof outputs a current signal IOTA3 to the first input end of the dead time control 2; the second input end of the oscillator OSC inputs the third reference voltage signal VREF3, and the first output end CL K is simultaneously connected to the second input terminal of dead time control 1 and the first input terminal of NAND gate nand2, and its second output terminal CLK_ is simultaneously connected to the second input terminal of dead time control 2 and the first input terminal of NAND gate nand1; the output terminal of dead time control 1 is connected to the second input terminal of NAND gate nand1; the output terminal of dead time control 2 is connected to the second input terminal of NAND gate nand2; the output terminal of NAND gate nand1 is connected to the input terminal of NAND gate not1; the output terminal of NAND gate nand2 is connected to the input terminal of NAND gate not2; the output terminal of NAND gate not1 serves as the first output terminal of PFM or PWM unit 202, outputting signal Ton_H1; the output terminal of NAND gate not2 serves as the second output terminal of PFM or PWM unit 202, outputting signal Ton_H2.

[0036] As a specific embodiment of the oscillator OSC, it is characterized by comprising a bias current source IB1, a capacitor C3, an NMOS transistor NM1, a comparator CMP1, a latch LATH1, a D flip-flop DFF1, a NOT gate not3 and a NAND gate nand3; the current input end of the bias current source IB1 is used to connect to the low-voltage power supply VCC; the positive phase input end of the comparator CMP1 serves as the second input end of the oscillator OSC, and the negative phase input end thereof is simultaneously connected to the current output end of the bias current source IB1, one end of the capacitor C3 and the drain of the NMOS transistor NM1, and serves as the first input end of the oscillator OSC, and the output end thereof is connected to the input end of the latch LATH1; the other end of the capacitor C3 is simultaneously connected to the NMOS transistor N The source of M1 is connected to the GNDS pin of the secondary-side controller; the gate of the NMOS transistor NM1 is connected to the output of the NAND gate nand3; the first input of the NAND gate nand3 is simultaneously connected to the output of the latch LATH1 and the second input CP_L of the D-type flip-flop DFF1, and its second input is connected to the third input Clr_L of the D-type flip-flop DFF1, and its second input also simultaneously inputs the low-voltage initialization signal ENP_lv; the first input D of the D-type flip-flop DFF1 is connected to its second output Q, and its first output Q is connected to the input of the NAND gate not3 and serves as the first output CLK of the oscillator OSC, and the output of the NAND gate not3 serves as the second output CLK_ of the oscillator OSC.

[0037] As a specific implementation of the dead time control 1, it is characterized by comprising a bias current source IB2, a capacitor C4, a PMOS transistor PM1, NMOS transistors NM2 and NM3, a Schmitt trigger Smt, and inverters not4 and not5; the input end of the Schmitt trigger Smt is simultaneously connected to the drain of the PMOS transistor PM1, the drain of the NMOS transistor NM2, the drain of the NMOS transistor NM3, and one end of the capacitor C4; the source of the PMOS transistor PM1 is connected to the current output end of the bias current source IB2 and serves as the first input end of the dead time control 1; the bias current source IB2 The current input terminal is used to connect to the low-voltage power supply VCC; the gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM2 and serves as the second input terminal of the dead time control 1; the source of the NMOS transistor NM2 is simultaneously connected to the other end of the capacitor C4, the source of the NMOS transistor NM3, and the GNDS pin; the gate of the NMOS transistor NM3 is connected to the output terminal of the NOT gate not5; the input terminal of the NOT gate not5 is used to input the low-voltage initialization signal ENP_lv; the output terminal of the Schmitt trigger Smt is connected to the input terminal of the NOT gate not4, and the output terminal of the NOT gate not4 serves as the output terminal of the dead time control 1.

[0038] As a specific embodiment of the PFM or PWM unit, it is characterized by including a comparator CMP, a triangular wave generator and an NMOS transistor NM8; the negative phase input terminal of the comparator CMP is used to input the voltage signal VEA, the positive phase input terminal of the comparator CMP is connected to the output terminal of the triangular wave generator, the output terminal of the comparator CMP is connected to the gate of the NMOS transistor NM8, the source of the NMOS transistor NM8 is connected to the GNDS pin, and the drain of the NMOS transistor NM8 is the output terminal of the PFM or PWM unit, and the output signal is a low-voltage drive V_pwm.

[0039] Preferably, for the PFM or PWM unit, the higher the level of the voltage signal VEA is, the greater the duty cycle of the low-voltage driving signals Ton_H1 and Ton_H2 , or the low-voltage driving signal V_pwm.

[0040] As a specific embodiment of the modulation signal driving unit, it is characterized by comprising a latch LATH2, a latch LATH3, an inverter chain 1, an inverter chain 2, an inverter chain 3, an inverter chain 4, a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM4, an NMOS transistor NM5, a NOT gate not6, a NOT gate not7 and a full-bridge power transistor; an input end of the latch LATH2 serves as a first input end of the modulation signal driving unit to which a low-voltage driving signal Ton_H1 is input, and an output end thereof is connected to the input ends of both the inverter chain 1 and the inverter chain 2; an input end of the latch LATH3 serves as a second input end of the modulation signal driving unit to which a low-voltage driving signal Ton_H2 is input, and an output end thereof is connected to the input ends of both the inverter chain 3 and the inverter chain 4; an output end of the inverter chain 1 is connected to the gate of the PMOS transistor PM2; an output end of the inverter chain 2 is connected to the gate of the NMOS transistor NM4; and an output end of the inverter chain 3 is connected to the gate of the PMOS transistor PM3. The output end of the inverter chain 4 is connected to the gate of the NMOS transistor NM5; the source of the PMOS transistor PM2 is used to connect to the low-voltage power supply VCC, and its drain is simultaneously connected to the drain of the NMOS transistor NM4, the input end of the NOT gate not6 and the first input end of the full-bridge power transistor; the output end of the NOT gate not6 is connected to the second input end of the full-bridge power transistor; the source of the NMOS transistor NM4 is connected to the GNDS pin of the secondary-side controller; the source of the PMOS transistor PM3 is used to connect to the low-voltage power supply VCC, and its drain is simultaneously connected to the drain of the NMOS transistor NM5, the input end of the NOT gate not7 and the third input end of the full-bridge power transistor; the output end of the NOT gate not7 is connected to the fourth input end of the full-bridge power transistor; the source of the NMOS transistor NM5 is connected to the GNDS pin of the secondary-side controller; the first output end of the full-bridge power transistor serves as the first output end of the modulation signal driving unit to output the driving signal TS1, and the second output end of the full-bridge power transistor serves as the second output end of the modulation signal driving unit to output the driving signal TS2.

[0041] As a specific embodiment of the full-bridge power tube, it is characterized by: including a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM6 and an NMOS tube NM7; the gate of the PMOS tube PM4 is the second input terminal of the full-bridge power tube, and its source is simultaneously connected to the source of the PMOS tube PM5 and the Vp pin of the secondary-side controller; the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM6 and serves as the first output terminal of the modulation signal driving unit; the source of the NMOS tube NM6 is simultaneously connected to the source of the NMOS tube NM7 and the GNDS pin of the secondary-side controller; the gate of the NMOS tube NM6 is the first input terminal of the full-bridge power tube; the gate of the NMOS tube NM7 is the third input terminal of the full-bridge power tube; the drain of the NMOS tube NM7 is connected to the drain of the PMOS tube PM5 and serves as the second output terminal of the modulation signal driving unit; and the gate of the PMOS tube PM5 is the fourth input terminal of the full-bridge power tube.

[0042] As a specific embodiment of the modulation signal driving unit, it is characterized by: including a capacitor C6, an NMOS transistor NM9 and an NMOS transistor NM10; the source of the NMOS transistor NM9 is connected to the source of the NMOS transistor NM10, for inputting a low-voltage driving signal V_pwm; the gate of the NMOS transistor NM9 is simultaneously connected to one end of the capacitor C6 and the drain of the NMOS transistor NM10, and serves as the second output end of the modulation signal driving unit, for outputting the driving signal TS2; the gate of the NMOS transistor NM10 is simultaneously connected to the other end of the capacitor C6 and the drain of the NMOS transistor NM9, and serves as the first output end signal of the modulation signal driving unit, for outputting the driving signal TS1.

[0043] Furthermore, the smaller the duty cycle of the driving signals TR1 and TR2 or the lower the frequency, the smaller the level of the primary inductor current modulation voltage signal VCS_Lim, and the smaller the duty cycle of the control signal generated by the primary inductor current modulation voltage signal VCS_Lim.

[0044] As a specific embodiment of the magnetic isolation coupling device, it is characterized in that: the magnetic isolation coupling device is a small core transformer with two terminals on the primary and secondary sides, or a small core transformer with two terminals on the primary side and two terminals and a center tap on the secondary side.

[0045] As a specific embodiment of the power supply and demodulation circuit, it is characterized by: including a sampling signal generation, a full-bridge rectifier power supply unit, a PMOS transistor PM6, an NMOS transistor NM11, a bias current source IB3, a capacitor C5, a transmission gate Tri, a NOT gate not8, an operational amplifier AMP, a resistor R2 and a resistor R3; the source of the PMOS transistor PM6 is used to input a fourth reference voltage VREF4, the gate thereof is connected to the first output terminal generated by the sampling signal, and the drain thereof is simultaneously connected to one end of the capacitor C5, the current input terminal of the bias current source IB3 and the first input terminal of the transmission gate Tri; the other end of the capacitor C5 is simultaneously connected to the source of the NMOS transistor NM11 and the GNDP pin; the gate of the NMOS transistor NM11 is connected to the second output terminal generated by the sampling signal, and the drain thereof is connected to the current output terminal of the bias current source IB3; the second input terminal of the transmission gate Tri is simultaneously connected to the third output terminal generated by the sampling signal and the input terminal of the NOT gate not8, and the third input terminal of the transmission gate Tri is connected to the NOT gate not8. The output end of the transmission gate Tri is connected to the positive phase input end of the operational amplifier AMP; the negative phase input end of the operational amplifier AMP is connected to its output end, and is connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3, and this connection intersection serves as the third output end of the power supply and reception demodulation circuit unit, outputting the primary inductor current modulation voltage signal VCS_Lim; the other end of the resistor R3 is connected to the GNDP pin of the primary side controller; the input end generating the sampling signal is connected to the second input end of the full-bridge rectifier power supply unit, and serves as the second input end of the power supply and reception demodulation circuit unit, inputting the drive signal TR2; the first input end of the full-bridge rectifier power supply unit serves as the first input end of the power supply and reception demodulation circuit unit, inputting the drive signal TR1; the output end of the full-bridge rectifier power supply unit serves as the first output end of the power supply and reception demodulation circuit unit, and is used to connect to the VDD pin of the primary side controller.

[0046] As a specific embodiment of the full-bridge rectifier power supply unit, it is characterized in that: it includes a diode D2, a diode D3, a diode D4 and a diode D5; the cathode of the diode D2 and the cathode of the diode D3 are connected together, and this connection intersection serves as the output end of the full-bridge rectifier power supply unit, which is used to connect to the VDD pin of the primary side controller; the anode of the diode D2 and the cathode of the diode D4 are connected together, and this connection intersection serves as the first input end of the full-bridge rectifier power supply unit; the anode of the diode D4 is connected to the anode of the diode D5, and is used to connect to the GNDP pin of the primary side controller; the cathode of the diode D5 and the anode of the diode D3 are connected together, and this connection intersection serves as the second input end of the full-bridge rectifier power supply unit.

[0047] Preferably, the full-bridge rectifier power supply unit is implemented by an ESD diode of two signal receiving pins of the primary side controller, or by integrating a full-bridge power tube into the primary side controller.

[0048] Explanation of terminology:

[0049] Two quasi-complementary low-voltage drive signals: refers to the two low-voltage drive signals being between valid levels and being at invalid levels for a period of time.

[0050] The brief working principle of the present invention is as follows:

[0051] The secondary side controller modulates the output voltage feedback signal into drive signals TS1 and TS2 whose frequency or duty cycle varies with the load through the VFB pin, and then sends it to the primary side through the magnetic isolation coupling device. After receiving the drive signal modulated by the secondary side, the primary side controller supplies power to the power input terminal of the primary side controller through bridge rectification without the need for auxiliary winding; at the same time, the received secondary side modulated signal is demodulated into a narrow pulse signal Tpulse_H and an inductor current modulation voltage signal VCS_Lim. The demodulated narrow pulse signal Tpulse_H controls the oscillator of the primary side controller to stop. The secondary side takes over the work at this time. That is, the demodulated inductor current modulation voltage signal VCS_Lim represents the control timing of the secondary side. The demodulated inductor current modulation voltage signal VCS_Lim is combined with the primary side peak current sampling signal to adjust the driving frequency or duty cycle of the control signal output by the primary side controller. The control signal output by the primary side controller is then used to control the opening and closing of the main power tube, the excitation and demagnetization of the main power transformer, and the transmission of energy demand to the secondary side, thereby realizing continuous feedback of output voltage or load current information, primary side power supply and secondary side control.

[0052] The specific working principle and related analysis of the present invention will be described in detail in the specific implementation section below. The principles, functions and beneficial effects of each solution or technical feature are the same and will not be repeated here. The beneficial effects of the present invention are summarized as follows:

[0053] 1. The present invention requires only a single magnetic isolation coupling device, achieving both magnetic isolation feedback and primary-side steady-state power supply, achieving two goals at once. It eliminates the need for auxiliary windings and eliminates the problems of poor cross-regulation under varying loads and the difficulty in designing transformers with high leakage inductance requirements. This reduces the manufacturing cost and size of the main power transformer, while also conserving PCB space and facilitating system miniaturization.

[0054] 2. The high-frequency quasi-complementary transformer drive signals TR1 and TR2 of the present invention can reduce the inductance of the magnetic isolation coupling device and make it miniaturized. It can be a small core transformer, a small magnetic ring, or even a planar transformer, which is conducive to integration, reduces PCB board space, and has strong anti-interference ability.

[0055] 3. The high-frequency quasi-complementary transformer drive signals TR1 and TR2 of the present invention can adjust their frequency or duty cycle accordingly according to the change of the load, thereby ensuring good power supply stability of the primary-side controller VDD and high load regulation. It is also beneficial to improve the power supply rejection ratio of the LDO inside the primary-side controller, making the modules inside the primary-side controller work more reliably.

[0056] 4. The power consumption of the primary side controller of the present invention is usually at the level of hundreds of uA or several mA, which is equivalent to a low load demand for the secondary side controller, so that the area of ​​the secondary side integrated full-bridge power tube can be reduced, saving the cost of the secondary side controller.

[0057] 5. The primary-side controller of the present invention can utilize the ESD discharge diodes inside the two receiving signal pins to realize full-bridge rectification, thereby achieving both ESD discharge and full-bridge rectification functions, killing two birds with one stone, reducing the area of ​​the controller and saving costs.

[0058] 6. The present invention can realize the synchronization of the primary side main power tube and the secondary side synchronous rectifier tube while realizing the primary side power supply. In particular, in CCM mode, the secondary side controller sends the modulated drive signal and turns off the synchronous rectifier tube at the same time, thereby improving the robustness of the synchronous rectification control.

[0059] 7. The present invention is not limited to topology applications and can be forward, flyback, full-bridge or push-pull topologies, etc., with a more flexible application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A typical circuit application block diagram of the present invention in an isolation converter application is included;

[0061] Figure 2 This is a principle block diagram of an embodiment of the error amplifier and compensation unit in the secondary-side controller of the first embodiment of the present invention;

[0062] Figure 3 1 is a schematic circuit diagram of a PFM or PWM unit in a secondary-side controller according to a first embodiment of the present invention;

[0063] Figure 4 for Figure 3 Schematic diagram of an embodiment of an oscillator OSC in a PFM or PWM unit;

[0064] Figure 5 for Figure 3 Schematic diagram of an embodiment of dead time control 1 in a PFM or PWM unit;

[0065] Figure 6 for Figure 3Schematic diagram of the curve showing the frequency and duty cycle of the high-frequency quasi-complementary signal output by the PFM or PWM unit as a function of VEA;

[0066] Figure 7 1 is a schematic circuit diagram of an embodiment of a modulation signal driving unit in a secondary-side controller according to a first embodiment of the present invention;

[0067] Figure 8 for Figure 7 Schematic diagram of the circuit embodiment of the full-bridge power tube in the modulation signal drive unit;

[0068] Figure 9 This is a circuit diagram of a magnetic isolation coupling device according to a first embodiment of the present invention;

[0069] Figure 10 Schematic diagram of typical signal waveforms of primary output ports TR1 and TR2 in the magnetic isolation coupling device of the present invention;

[0070] Figure 11 This is a circuit diagram of an embodiment of a power supply and receiving demodulation circuit in a primary-side controller according to the first embodiment of the present invention;

[0071] Figure 12 Schematic diagram of the relationship between the output primary-side inductor current modulation voltage signal VCS_Lim and the input signal TR1 or TR2 in the power supply and receiving demodulation circuit in the primary-side controller of the first embodiment of the present invention;

[0072] Figure 13 for Figure 11 A schematic diagram of an embodiment of a full-bridge rectifier power supply unit in a power supply and receiving demodulation circuit;

[0073] Figure 14 1 is a circuit diagram of a PFM or PWM unit in a secondary-side controller according to a second embodiment of the present invention;

[0074] Figure 15 This is a circuit diagram of another embodiment of the modulation signal driving unit in the secondary-side controller of the second embodiment of the present invention;

[0075] Figure 16 This is a circuit diagram of another embodiment of the magnetic isolation coupling device of the second embodiment of the present invention. DETAILED DESCRIPTION

[0076] The present invention can ensure the stability of the output voltage and realize steady-state power supply of the primary-side controller. Furthermore, the present invention can also turn off the synchronous rectifier tube while the secondary-side controller sends a modulated drive signal in CCM mode, thereby realizing synchronization between the primary-side main power tube and the secondary-side synchronous rectifier tube, and improving the robustness of the synchronous rectification control.

[0077] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0078] like Figure 1 FIG. 1 is a typical circuit diagram of an isolating converter including the application of the present invention. Figure 1 As shown, the circuit of the present invention includes a primary-side controller 10, a secondary-side controller 20 and a magnetic isolation coupling device 30. The primary-side controller 10 includes a VDD pin, a GNDP pin, a CS pin, a DRVP pin, a TR1 pin and a TR2 pin, a power supply and receiving demodulation circuit 101, a PWM control 102, an oscillator 103, and a drive circuit 104; the secondary-side controller 20 includes a VD pin, a Vp pin, a GNDS pin, a VFB pin, a DRVS pin, a TS1 pin and a TS2 pin, an error amplifier & compensation unit 201, a PFM or PWM unit 202, a modulation signal driving unit 203, a CCM synchronous shutdown control unit 204, a synchronous rectifier tube start-up and shutdown detection unit 205 and a synchronous rectifier tube drive control unit 206.

[0079] Figure 1 The isolated converter in the figure is a typical flyback converter topology. It should be noted that this is only an example. The power supply and feedback control circuit of the present invention can also be applied to other isolated converters, such as forward, flyback, full-bridge or push-pull topologies. Figure 1 The flyback converter includes the main power transformer T1, input voltage VIN, main power tube M1, secondary synchronous rectifier tube M2, current sampling resistor R1, output resistor R O , output voltage sampling resistors Rf1 and Rf2, output capacitor C O , input filter capacitor C1 and bypass capacitor C2.

[0080] The pins included in the primary side controller 10 are described in detail as follows. Other pins are not related to the present invention and are therefore not described here:

[0081] VDD pin: The power supply port of the primary-side controller, used to power the primary-side controller. Typically, a bypass capacitor is connected to the controller, combined with a startup circuit to provide power during the startup phase. In the present invention, power is supplied to the VDD pin by the power supply and receiving demodulation circuit during the steady-state phase.

[0082] GNDP pin: the ground of the primary side controller, used to connect the primary side ground of the isolation converter;

[0083] CS pin: current sampling input port, used to sample the peak voltage of the source when the primary main power tube M1 of the isolation converter is turned on;

[0084] DRVP pin: drive pin, used to output the duty cycle to realize the on / off control of the primary side main power tube M1 of the isolation converter;

[0085] TR1 pin and TR2 pin: Quasi-complementary signal receiving pins, used to receive the quasi-complementary signals generated by the two primary terminals of the magnetic isolation coupling device.

[0086] The pins included in the secondary side controller 20 are described in detail as follows. Other pins are not relevant to the present invention and are not described here.

[0087] VD pin: The start and shut-down detection pin of the synchronous rectifier tube M2 on the secondary side of the isolation converter is used to detect the drain voltage of the synchronous rectifier tube M2;

[0088] Vp pin: the power supply port of the secondary side controller, used to power the secondary side controller. Figure 1 This pin is connected to the output voltage Vo of the flyback converter to realize the output power supply;

[0089] GNDS pin: the ground of the secondary side controller, used to connect to the secondary side ground of the isolation converter;

[0090] VFB pin: output voltage sampling input port. In the present invention, this pin is connected to an external voltage divider resistor and is used to sample the voltage signal of the output voltage after voltage division.

[0091] DRVS pin: drive pin, used to output the duty cycle to turn on and off the main power tube;

[0092] TS1 and TS2 pins: Quasi-complementary signal sending pins, used to send two quasi-complementary signals to the two terminals on the secondary side of the magnetic isolation coupling device.

[0093] The connection relationship of the secondary side controller 20 and the functions of each unit circuit are as follows:

[0094] The error amplifier & compensation unit has its input connected to the VFB pin and its output connected to the input of the PFM or PWM unit. Its function is to perform loop compensation on the feedback signal obtained after the output voltage is sampled by the voltage divider resistor to generate a voltage signal VEA that can reflect the load change;

[0095] The PFM or PWM unit has a first output terminal connected to the first input terminal of the modulation signal driving unit, a second output terminal connected to the second input terminal of the modulation signal driving unit, and a third output terminal connected to the input terminal of the CCM synchronous shutdown control unit. The PFM or PWM unit is used to generate two quasi-complementary low-voltage driving signals Ton_H1 and Ton_H2 whose frequencies and duty cycles vary with the voltage signal VEA from the voltage signal VEA; or to generate one low-voltage driving signal V_pwm whose frequency is fixed but whose duty cycle varies with the voltage signal VEA from the voltage signal VEA;

[0096] The modulation signal driving unit has a first output terminal connected to the TS1 pin and a second output terminal connected to the TS2 pin. Its function is to generate two quasi-complementary driving signals TS1 and TS2 with driving capability from the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm, and send them to the magnetic isolation coupling device;

[0097] A CCM synchronous shutdown control unit, whose output terminal is connected to the first input terminal of the synchronous rectifier tube on-and-off detection unit, is used to generate a shutdown signal for the synchronous rectifier tube when the PFM or PWM unit generates the drive signals TS1 and TS2;

[0098] A synchronous rectifier on-and-off detection unit, wherein the second input terminal is connected to the VD pin, and the output terminal is connected to the input terminal of the synchronous rectifier drive control unit. The function of the unit is to detect whether the synchronous rectifier meets the on-and-off conditions and to perform related operations. Specifically, the synchronous rectifier can be turned on when the set on threshold is reached by detecting the drain voltage of the synchronous rectifier during the demagnetization stage of the main power transformer. In the DCM mode, the synchronous rectifier can be turned off when the set off threshold is reached by detecting the drain voltage of the synchronous rectifier during the demagnetization stage of the main power transformer. In the CCM mode, the synchronous rectifier can be turned off when the set off threshold is reached by detecting the drain voltage of the synchronous rectifier during the demagnetization stage of the main power transformer.

[0099] The synchronous rectifier drive control unit has its output connected to the DRVS pin. Its function is to enhance the driving capability of the output signal of the synchronous rectifier turn-on and turn-off detection unit to meet the driving capability requirements of the synchronous rectifier.

[0100] It should be noted that the above-mentioned CCM synchronous shutdown control unit, synchronous rectifier tube start-up and shutdown detection unit and synchronous rectifier tube drive control unit are designed for the isolation converter using a synchronous rectification scheme on the secondary side. If a diode rectification scheme is used, these three unit circuits do not need to be set.

[0101] The magnetic isolation coupling device 30 is used to receive the drive signals TS1 and TS2 generated by the secondary-side controller 20 , generate drive signals TR1 and TR2 accordingly after isolated transmission, and send the drive signals TR1 and TR2 to the primary-side controller 10 .

[0102] The connection relationship of the primary side controller 10 and the functions of each unit circuit are as follows:

[0103] A power supply and receiving demodulation circuit unit has a first input connected to the TR1 pin, a second input connected to the TR2 pin, a first output connected to the VDD pin, a second output connected to the input of the oscillator unit, and a third output connected to the first input of the PWM control unit. The power supply and receiving demodulation circuit unit is used to power the primary controller via bridge rectification of the drive signals TR1 and TR2, and to demodulate either of the drive signals TR1 and TR2 into a primary inductor current modulation voltage signal VCS_Lim and a narrow pulse signal Tpulse_H. The narrow pulse signal controls the primary oscillator to stop operation and the secondary side to take over, i.e., the secondary side controls the turning on of the primary controller. The primary inductor current modulation voltage signal VCS_Lim is used to generate a control signal output by the primary controller, and is combined with the main power switch tube source peak current sampling signal to adjust the frequency or duty cycle of the control signal output by the primary controller to control the turning on and off of the main power switch tube.

[0104] A PWM control unit, whose second input terminal is connected to the CS pin, and whose output terminal is connected to the first input terminal of the driving circuit unit, is used to realize PWM control of the primary side controller together with the peak current sampling signal received by the CS pin;

[0105] The oscillator unit has an output terminal connected to the second input terminal of the driving circuit unit. Its function is to control the primary side controller to continuously turn on and off the power tube before the secondary side output voltage is established, continuously excite and demagnetize the main power transformer, realize energy transfer to the secondary side, and make the secondary side output voltage continue to rise. After the secondary side output voltage is established, it stops working by supplying power and receiving the narrow pulse signal output by the demodulation circuit, and then the secondary side takes over.

[0106] The output end of the drive circuit is connected to the DRVP pin, which is used to enhance the driving capability so that the power tube can be turned on and off normally.

[0107] It should be noted that, in addition to Figure 1In addition to the circuits included, other auxiliary circuits are also included, such as a low-voltage power supply VCC generation circuit, a reference voltage generation circuit, and a low-voltage initialization signal generation circuit. In the present invention, the low-voltage power supply VCC can be obtained from the Vp pin through an LDO and is used to power the various sub-modules within the secondary-side controller 20. The reference voltage generation circuit can be obtained from a well-known bandgap reference circuit and is used to input a stable voltage reference signal to the modules within the secondary-side controller. The secondary-side controller 20 of the present invention needs to generate three reference voltage signals, namely a first reference voltage signal VREF1, a second reference voltage signal VREF2, and a third reference voltage signal VREF1. The low-voltage initialization signal generation circuit can be obtained by adding a delay to a well-known startup circuit. The low-voltage initialization signal ENP_lv generated by it is usually established with a delay after the power supply voltage VCC within the secondary-side controller is generated. It is used to initialize the corresponding logic units within the controller, such as the Schmitt trigger Smt and the D flip-flop DFF, to ensure that they are at a valid potential before the logic is activated. The primary-side controller 10 of the present invention also includes some other auxiliary circuits. For example, the primary-side controller 10 of the present invention needs to generate a fourth reference voltage signal VREF4 , so a reference voltage generating circuit needs to be designed.

[0108] The following describes in detail the specific embodiments of the main unit circuits in the secondary-side controller 20 and the primary-side controller 10 of the present invention through specific embodiments.

[0109] It should be noted that the present invention Figure 1 The CCM synchronous shutdown control unit, synchronous rectifier tube start-up and shutdown detection unit and synchronous rectifier tube drive control unit inside the secondary side controller 20, the PWM control unit, oscillator unit and drive circuit unit inside the primary side controller 10, as well as the error amplifier EA, built-in compensation network, transconductance amplifier OTA, inverter chain, sampling signal generation, bias current source, etc. described in the specific embodiments of each unit circuit below, these circuits have many well-known circuit structures. Since they are not the innovation of the present invention, they will not be explained in this article through specific embodiments.

[0110] First embodiment

[0111] like Figure 2 FIG. 1 is a schematic circuit diagram of an embodiment of the error amplifier and compensation unit 201 in the secondary-side controller 20 according to the first embodiment of the present invention. Figure 2The error amplifier and compensation unit 201 includes an error amplifier EA and a built-in compensation network, which is used to compensate for loop stability. The error amplifier EA's non-inverting input receives a first reference voltage signal, VREF1. Its negative input is connected to both the VFB pin and the output of the built-in compensation network. Its output is connected to the input of the built-in compensation network and serves as the output of the error amplifier and compensation unit 201, outputting a voltage signal, VEA.

[0112] Combine Figure 1 ,right Figure 2 The working principle of the error amplifier & compensation unit 201 embodiment is described as follows:

[0113] The output voltage Vo is divided by the voltage-divider resistors Rf1 and Rf2, and the resulting voltage signal is input to the negative input of the error amplifier EA via the VFB pin. The positive input of the error amplifier is connected to the first reference voltage signal VREF1. By properly setting the gain, output swing, and bandwidth of the error amplifier EA, and using a built-in loop compensation network, the system's requirements for stability and dynamic response can be met. Assuming the gain of the error amplifier is Av, the absolute value of the output voltage signal VEA of the error amplifier EA can be expressed as:

[0114]

[0115] where |V EA | is the absolute value of the output voltage signal VEA of the error amplifier EA, Av is the gain of the error amplifier, VREF1 is the first reference voltage signal, Vo is the output voltage of the isolation converter, Rf1 is the resistance value of the voltage divider resistor Rf1, and Rf2 is the resistance value of the voltage divider resistor Rf2.

[0116] It can be seen from formula (1) that the higher the output voltage is than the steady-state value, the smaller the absolute value of the EA output voltage VEA is; the lower the output voltage is than the steady-state value, the larger the absolute value of the EA output voltage VEA is.

[0117] like Figure 3The figure shows a circuit schematic diagram of an embodiment of the PFM or PWM unit 202 in the secondary-side controller 20 of the first embodiment of the present invention. The PFM or PWM unit 202 includes a transconductance amplifier OTA, an oscillator OSC2021, a dead time control 12022, a dead time control 2, a NAND gate nand1, a NAND gate nand2, a NOT gate not1, and a NOT gate not2. The first input of the transconductance amplifier OTA is connected to the output of the error amplifier and compensation unit 201, the second input of the transconductance amplifier OTA inputs the second reference voltage signal VREF2, the first output of the transconductance amplifier OTA outputs a current signal IOTA1 to the first input of the oscillator OSC2021, the second output of the transconductance amplifier OTA outputs a current signal IOTA2 to the first input of the dead time control 12022, and the third output of the transconductance amplifier OTA outputs a current signal IOTA3 to the first input of the dead time control 2. The second input of the oscillator OSC2021 inputs the third reference voltage signal VREF3, the first output of the transconductance amplifier OTA CLK is connected to both the second input of the dead time control 12022 and the first input of the NAND gate nand2, and the third output of the transconductance amplifier OTA outputs a current signal IOTA3 to the first input of the dead time control 2. The second output terminal CLK_ is simultaneously connected to the second input terminal of the dead time control 2 and the first input terminal of the NAND gate nand1; the output terminal of the dead time control 12022 is connected to the second input terminal of the NAND gate nand1; the output terminal of the dead time control 2 is connected to the second input terminal of the NAND gate nand2; the output terminal of the NAND gate nand1 is connected to the input terminal of the NAND gate not1; the output terminal of the NAND gate nand2 is connected to the input terminal of the NAND gate not2; the output terminal of the NAND gate not1 serves as the first output terminal of the PFM or PWM unit 202, outputting the signal Ton_H1; the output terminal of the NAND gate not2 serves as the second output terminal of the PFM or PWM unit 202, outputting the signal Ton_H2.

[0118] Figure 3 The working principle of the embodiment of the PFM or PWM unit 202 is described as follows:

[0119] The output voltage signal VEA of the error amplifier & compensation unit 201 and the second reference voltage signal VREF2 generate a current signal that varies with the voltage signal VEA through the transconductance amplifier OTA. This current signal controls the oscillator OSC and the dead time control 12022 and the dead time control 2 to generate two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2, with a constant on-time Ton and an off-time Toff that varies with the voltage signal VEA. Typically, the higher the voltage of the voltage signal VEA, the shorter the off-time Toff, that is, the larger the duty cycle D of Ton_H1 and Ton_H2, and the higher the frequency fs. Combined with Figure 2It can be shown that the higher the output voltage is than the steady-state value, the smaller the frequency fs and duty cycle D of Ton_H1 and Ton_H2 are; the lower the output voltage is than the steady-state value, the larger the frequency fs and duty cycle D of Ton_H1 and Ton_H2 are.

[0120] like Figure 4 Shown Figure 3 Schematic diagram of an embodiment of the oscillator OSC2021 in the PFM or PWM unit 202. The oscillator OSC2021 includes a bias current source IB1, a capacitor C3, an NMOS transistor NM1, a comparator CMP1, a latch LATH1, a D flip-flop DFF1, a NOT gate not3, and a NAND gate nand3. The current input terminal of the bias current source IB1 is used to connect to the low-voltage power supply VCC; the non-inverting input terminal of the comparator CMP1 serves as the second input terminal of the oscillator OSC2021, for inputting the third reference voltage signal VREF3, and the negative input terminal of the comparator CMP1 is simultaneously connected to the current output terminal of the bias current source IB1, one end of the capacitor C3, and the drain of the NMOS transistor NM1, and serves as the first input terminal of the oscillator OSC2021, and the output terminal of the oscillator OSC2021 is connected to the input terminal of the latch LATH1; the other end of the capacitor C3 is simultaneously connected to the source of the NMOS transistor NM1 and the GNDS pin; the gate of the NMOS transistor NM1 is connected to the output terminal of the NAND gate nand3; the first input terminal of the NAND gate nand3 is simultaneously connected to the output terminal of the latch LATH1 and the second input terminal CP_L of the D-type flip-flop DFF1, and the second input terminal of the NAND gate nand3 is connected to the third input terminal Clr_L of the D-type flip-flop DFF1. The low-voltage initialization signal ENP_lv is also input to the second input terminal of the NAND gate nand3; the first input terminal D of the D-type flip-flop DFF1 and its second output terminal The first output terminal Q is connected to the input terminal of the NOT gate not3 and serves as the first output terminal CLK of the oscillator OSC2021 . The output terminal of the NOT gate not3 serves as the second output terminal CLK_ of the oscillator OSC2021 .

[0121] Combine Figure 4 The working principle of the oscillator OSC2021 embodiment of the present invention is described as follows:

[0122] The on-time Ton1 of the second input terminal CP_L of the D flip-flop DFF1 can be explained by the principle of capacitor charging and discharging. The current signal IOTA1 output from the first output terminal of the transconductance amplifier OTA and the bias current source IB1 together charge the capacitor C3. When the node voltage signal Vtri1 at the negative input terminal of the comparator CMP1 reaches the third reference voltage VREF3 input at the positive input terminal, the comparator CMP1 flips to a low level, and then generates a high level through the NAND gate nand3, turning on the NMOS tube NM1, discharging the capacitor C3, and ending the on-time. The on-time Ton1 can be expressed by formula (2):

[0123]

[0124] Its T on1 is the on-time Ton1 of the second input terminal CP_L of the D flip-flop DFF1, C3 is the capacitance of the capacitor C3, VREF3 is the third reference voltage signal, IB1 is the current signal output by the current output terminal of the bias current source IB1, and IOTA1 is the current signal output by the first output terminal of the transconductance amplifier OTA.

[0125] By properly setting the width-to-length ratio of the NMOS transistor NM1, the discharge time can be very short. This means that the signal inputted by CP_L at the second input terminal of the D-type flip-flop DFF1 is a square wave signal with a duty cycle close to 100%. This signal then passes through the D-type flip-flop DFF1 to form a divide-by-two circuit, generating a square wave signal CLK with a duty cycle close to 50%. The square wave signal CLK then passes through the NOT gate to generate an inverted square wave signal CLK_. The final frequency of CLK or CLK_ can be approximately expressed as follows:

[0126]

[0127] From formula (3), we can see that the larger the current signal IOTA1 is, the higher the frequency of the square wave signal CLK or CLK_ is. Figure 2 and Figure 3 , which shows that the lower the output voltage is than the steady-state value, the larger the voltage signal VEA is, the larger the current signal IOTA1 is, and the lower the low-voltage drive signal frequency f output by the oscillator OSC is. CLK The higher the output voltage is compared to the steady-state value, the smaller the voltage signal VEA is, the smaller the current signal IOTA1 is, and the lower the low-voltage drive signal frequency fCLK output by the oscillator OSC is. In addition, the frequency fCLK is in the MHz level. When the voltage signal VEA is reduced, the frequency fCLK can be reduced to the 100 kHz level.

[0128] like Figure 5 Shown Figure 3Schematic diagram of an embodiment of the dead time control 12022 in the PFM or PWM unit 202. The dead time control 12022 includes a bias current source IB2, a capacitor C4, a PMOS transistor PM1, NMOS transistors NM2 and NM3, a Schmitt trigger Smt, and inverters not4 and not5. The input end of the Schmitt trigger Smt is simultaneously connected to the drain of the PMOS transistor PM1, the drain of the NMOS transistor NM2, the drain of the NMOS transistor NM3, and one end of the capacitor C4; the source of the PMOS transistor PM1 is connected to the current output end of the bias current source IB2 and serves as the first input end of the dead time control 12022, inputting the current signal Iin1 (the current signal Iin1 is also the current signal IOTA2 output by the second output end of the transconductance amplifier); the current input end of the bias current source IB2 is used to connect to the low voltage power supply VCC; the gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM2 and serves as the dead time control 12 The second input terminal of 022 receives the square wave signal Vin1 (the square wave signal Vin1 is also the square wave signal CLK output by the first output terminal of oscillator OSC2021); the source of NMOS transistor NM2 is simultaneously connected to the other end of capacitor C4, the source of NMOS transistor NM3, and the GNDS pin; the gate of NMOS transistor NM3 is connected to the output terminal of NOT gate not5; the input terminal of NOT gate not5 is used to input the low-voltage initialization signal ENP_lv; the output terminal of Schmitt trigger Smt is connected to the input terminal of NOT gate not4, and the output terminal of NOT gate not4 serves as the output terminal of dead time control 12022, outputting the square wave signal Vo1.

[0129] Combine Figure 5 The working principle of the dead time control embodiment 12022 of the present invention is described as follows:

[0130] Based on the principle of capacitor charging and discharging, when the input square wave signal Vin1 is at a low level, the PMOS transistor PM1 is turned on and the NMOS transistor NM2 is turned off. Then the current signal Iin1 and the bias current source IB2 together charge the capacitor C4. When the node voltage signal Vtri2 at the input end of the Schmitt trigger Smt reaches the flip threshold Vth of the Schmitt Smt, the Schmitt Smt flips to a low level, and then the square wave signal Vo1 generated by the NOT gate not4 is at a high level. The delay from the low level of Vin1 to the high level of Vo1 can be expressed by formula (4):

[0131]

[0132] Where T DTis the duration from the second input terminal of the dead time control 1 inputting a low level to the output terminal outputting a high level, C4 is the capacitance of the capacitor C4, Vth is the flip threshold of the Schmitt transistor Smt, IB2 is the current signal output by the current output terminal of the bias current source IB2, and IOTA2 is the current signal output by the second output terminal of the transconductance amplifier OTA.

[0133] Combine Figure 3 , Figure 4 and Figure 5 , it can be seen that the frequency fs and duty cycle D of the final two quasi-complementary drive signals Ton_H1 and Ton_H2 can be expressed by formula (5) and formula (6):

[0134]

[0135]

[0136] Where T ON1 The time when the driving signal Ton_H1 or Ton_H2 is at a high level.

[0137] The magnitude of the current signal IOTA1 is determined by the transconductance gm of the transconductance amplifier OTA, which can be expressed by formula (7):

[0138] IOTA=gm×(VEA-VREF2) (7)

[0139] Wherein IOTA is the output current of the transconductance amplifier OTA, and gm is the transconductance of the transconductance amplifier OTA.

[0140] The current signals IOTA2 and IOTA3 can be obtained by the current mirror image inside the transconductance amplifier OTA, and their values ​​are equal, that is, IOTA2=IOTA3.

[0141] The relationship curve between frequency fs and duty cycle D as voltage signal VEA changes is as follows: Figure 6 As shown, combined with formulas (5), (6) and (7), it can be seen that the frequencies and duty cycles of the two complementary drive signals Ton_H1 and Ton_H2 are higher when the output voltage is lower than the steady-state value; and are lower when the output voltage is higher than the steady-state value.

[0142] like Figure 7FIG2 is a schematic circuit diagram of a modulation signal driving unit 203 in a secondary-side controller 20 according to a first embodiment of the present invention. The modulation signal driving unit 203 includes latches LATH2 and LATH3, inverter chain 1, inverter chain 2, inverter chain 3, inverter chain 4, PMOS transistors PM2 and PM3, NMOS transistors NM4 and NMOS transistors NM5, NOT gates not6 and not gates not7, and a full-bridge power transistor 2031. The input end of latch LATH2 serves as the first input end of the modulation signal driving unit 203, inputting the low-voltage driving signal Ton_H1, and the output end of latch LATH2 is simultaneously connected to the input ends of inverter chain 1 and inverter chain 2. The input end of latch LATH3 serves as the second input end of the modulation signal driving unit 203, inputting the low-voltage driving signal Ton_H2, and the output end of latch LATH3 is simultaneously connected to the input ends of inverter chain 3 and inverter chain 4. The output end of inverter chain 1 is connected to the gate of PMOS transistor PM2; the output end of inverter chain 2 is connected to the gate of NMOS transistor NM4; the output end of inverter chain 3 is connected to the gate of PMOS transistor PM3; the output end of inverter chain 4 is connected to the gate of NMOS transistor NM5; the source of PMOS transistor PM2 is used to connect to the low-voltage power supply VCC, and its drain is simultaneously connected to the gate of NMOS transistor NM4. The drain, the input end of the NOT gate not6 and the first input end of the full-bridge power tube 2031 are connected; the output end of the NOT gate not6 is connected to the second input end of the full-bridge power tube 2031; the source of the NMOS tube NM4 is connected to the GNDS pin; the source of the PMOS tube PM3 is used to connect to the low-voltage power supply VCC, and its drain is also connected to the drain of the NMOS tube NM5, the input end of the NOT gate not7 and the third input end of the full-bridge power tube 2031; the output end of the NOT gate not7 is connected to the fourth input end of the full-bridge power tube; the source of the NMOS tube NM5 is connected to the GNDS pin; the first output end of the full-bridge power tube 2031 serves as the first output end of the modulation signal driving unit 203 to output the signal TS1, and the second output end of the full-bridge power tube 2031 serves as the second output end of the modulation signal driving unit 203 to output the signal TS2.

[0143] Combine Figure 7 The working principle of the modulation signal driving unit 203 embodiment of the present invention is described as follows:

[0144] The two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2, respectively, pass through an inverter chain and a totem-pole drive structure to generate two N-transistor drive signals Drv_N1 and Drv_N2 with certain drive capabilities for the first / third input terminals of the full-bridge power transistors. Furthermore, two P-transistor drive signals Drv_P1 and Drv_P2 are generated for the second / fourth input terminals of the full-bridge power transistors through a NOT gate. These four drive signals then pass through the full-bridge power transistor 2031 to generate the final modulated two quasi-complementary modulation signals TS1 and TS2 with certain drive capabilities.

[0145] like Figure 8 Shown Figure 7 Schematic diagram of a circuit embodiment of the full-bridge power transistor 2031 in the modulation signal driving unit 203. The full-bridge power transistor 2031 includes a PMOS transistor PM4, a PMOS transistor PM5, an NMOS transistor NM6, and an NMOS transistor NM7. The gate of the PMOS transistor PM4 serves as the second input terminal of the full-bridge power transistor 2031, and its source is simultaneously connected to the source of the PMOS transistor PM5 and the Vp pin; the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM6 and serves as the first output terminal of the modulation signal driving unit 203; the source of the NMOS transistor NM6 is simultaneously connected to the source of the NMOS transistor NM7 and the GNDS pin; the gate of the NMOS transistor NM6 serves as the first input terminal of the full-bridge power transistor 2031; the gate of the NMOS transistor NM7 serves as the third input terminal of the full-bridge power transistor 2031; the drain of the NMOS transistor NM7 is connected to the drain of the PMOS transistor PM5 and serves as the second output terminal of the modulation signal driving unit 203; and the gate of the PMOS transistor PM5 serves as the fourth input terminal of the full-bridge power transistor 2031.

[0146] Combine Figure 8 The working principle of the full-bridge power tube 2031 embodiment of the present invention is described as follows:

[0147] When the drive signal Drv_P1 is at a low level and the drive signal Drv_N2 is at a high level, the drive signal Drv_P2 is at a high level and the drive signal Drv_N1 is at a low level. One bridge arm formed by the PMOS transistor PM4 and the NMOS transistor NM7 is turned on, and another bridge arm formed by the PMOS transistor PM5 and the NMOS transistor NM6 is turned off. Similarly, when the drive signal Drv_P1 is at a high level and the drive signal Drv_N2 is at a low level, the drive signal Drv_P2 is at a low level and the drive signal Drv_N1 is at a high level. One bridge arm formed by the PMOS transistor PM4 and the NMOS transistor NM7 is turned off, and another bridge arm formed by the PMOS transistor PM5 and the NMOS transistor NM6 is turned on, and the process alternates in this way.

[0148] like Figure 9 The following is a schematic circuit diagram of a magnetic isolation coupling device 30 according to a first embodiment of the present invention. The magnetic isolation coupling device 30 includes a small core transformer. The two primary terminals of the small core transformer serve as the first and second output terminals of the magnetic isolation coupling device, respectively. The two secondary terminals of the small core transformer are connected to the first and second output terminals of the modulation signal driving unit 203, respectively.

[0149] like Figure 10The following is a typical waveform diagram of the output signals TR1 and TR2 of the two primary terminals of the magnetic isolation coupling device 30 of the present invention. TR1 and TR2 are quasi-complementary waveforms with a duty cycle close to 50%. There is a common time for TR1 off and TR2 off, namely the dead time t DT Dead time t DT The purpose of this setting is to prevent a large current path from the power supply to the ground caused by the common bridge arm, which may cause damage to the controller.

[0150] The magnetic isolation coupling device 30 of this embodiment may also be a small magnetic ring transformer or a planar transformer. Furthermore, the power supply level requirement of the primary controller may be achieved by setting the inductance and the primary-to-secondary turns ratio.

[0151] like Figure 11 FIG. 1 is a circuit diagram of an embodiment of the power supply and receiving demodulation circuit unit 101 in the primary side controller 10 according to the first embodiment of the present invention. Figure 11The power supply and receiving demodulation circuit unit 101 includes a sampling signal generation unit, a full-bridge rectifier power supply unit 1011, a PMOS transistor PM6, an NMOS transistor NM11, a bias current source IB3, a capacitor C5, a transmission gate Tri, a NOT gate not8, an operational amplifier AMP, resistors R2 and R3; the sampling signal generation unit generates gate control signals for the PMOS transistor PM6 and the NMOS transistor NM11, as well as a narrow pulse signal Tpulse_H, based on the received drive signal TR1 or TR2. The source of the PMOS transistor PM6 is used to input the fourth reference voltage VREF4, the gate thereof is connected to the first output terminal generated by the sampling signal, and the drain thereof is simultaneously connected to one end of the capacitor C5, the current input terminal of the bias current source IB3, and the first input terminal of the transmission gate Tri; the other end of the capacitor C5 is simultaneously connected to the source of the NMOS transistor NM11 and the GNDP pin; the gate of the NMOS transistor NM11 is connected to the second output terminal generated by the sampling signal, and the drain thereof is connected to the current output terminal of the bias current source IB3; the second input terminal of the transmission gate Tri is simultaneously connected to the third output terminal generated by the sampling signal and the input terminal of the NOT gate not8, and the third input terminal of the transmission gate Tri is connected to the output terminal of the NOT gate not8, serving as the second output terminal of the power supply and receiving demodulation circuit unit 101, outputting the narrow pulse signal Tpulse_H; the output terminal of the transmission gate Tri is connected to the operational amplifier AMP The positive phase input terminal of the operational amplifier AMP is connected to its output terminal, and is connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3, and this connection intersection serves as the third output terminal of the power supply and reception demodulation circuit unit 101, outputting the primary inductor current modulation voltage signal VCS_Lim; the other end of the resistor R3 is connected to the GNDP pin; the input terminal generated by the sampling signal is connected to the second input terminal of the full-bridge rectifier power supply unit 1011, and serves as the second input terminal of the power supply and reception demodulation circuit unit 101, inputting the drive signal TR2; the first input terminal of the full-bridge rectifier power supply unit 1011 serves as the first input terminal of the power supply and reception demodulation circuit unit 101, inputting the drive signal TR1; the output terminal of the full-bridge rectifier power supply unit 1011 serves as the first output terminal of the power supply and reception demodulation circuit unit 101, and is used to connect to the VDD pin.

[0152] Combine Figure 11 The working principle of the embodiment of the power supply and receiving demodulation circuit unit 101 of the present invention is described as follows:

[0153] The secondary-side controller 20 sends the modulated two-way quasi-complementary signals TS1 and TS2 to the primary-side controller 10 through the magnetic isolation coupling device 30. The duty cycle and frequency of the two-way quasi-complementary drive signals TR1 and TR2 received by the primary-side controller 10 are consistent with the transmitted signals TS1 and TS2. Therefore, the duty cycle and frequency of the drive signals TR1 and TR2 represent the magnitude of the output compensation voltage signal VEA of the error amplifier & compensation unit 201 in the secondary-side controller 20, and the magnitude of the voltage signal VEA represents the magnitude of the flyback converter load; therefore, the primary-side controller 10 demodulates the time when either of the two received quasi-complementary drive signals TR1 and TR2 is at a low level into a voltage signal ( Figure 11 (where TR2 is the drive signal), which can be used to modulate the primary inductor current of the converter. The sampling signal generation circuit generates a first output signal and a second output signal based on the low level of the drive signal TR2. The first output signal turns off the PMOS transistor PM6, while the second output signal turns on the NMOS transistor NM11, discharging the capacitor C5 via the current of the bias current source IB3. When the drive signal TR2 flips to a high level, the NMOS transistor NM11 is turned off, stopping the discharge of the capacitor C5. At this time, the voltage V C5 It can be expressed as:

[0154]

[0155] Where, T C As mentioned above, this is the time for TR2 to maintain a low level. The third output terminal of the sampling signal generating circuit generates a signal Tpulse_L, which generates a signal Tpulse_H through the NOT gate not8. These two control signals are narrow pulse signals that control the transmission gate Tri to be turned on, sampling the voltage of the capacitor C5 to the positive input terminal of the operational amplifier AMP. The negative input terminal of the operational amplifier AMP is connected to its own output terminal to form a buffer. Then, the output voltage of the operational amplifier AMP is equal to the voltage stored at the positive input terminal. After this output voltage is divided by resistors R2 and R3, the primary inductor current modulation voltage signal VCS_Lim is obtained, which is expressed by formula (9):

[0156]

[0157] Combined with formula (4) and formula (7), the output current IOTA of the transconductance amplifier OTA and the low level time T of the secondary-side modulated drive signal TS1 or TS2 are DT Substituting into formula (9) we can get:

[0158]

[0159] like Figure 12FIG. 1 is a diagram showing the relationship between the primary-side inductor current modulation voltage signal VCS_Lim output from the power supply and receiving demodulation circuit 101 in the primary-side controller 10 of the present invention and the duty cycle of the input drive signal TR1 or TR2. Combining this with formula (10), it can be seen that the longer the low-level time of the drive signal TR1 or TR2, that is, the smaller the duty cycle, the smaller the primary-side inductor current modulation voltage signal VCS_Lim generated.

[0160] Figure 13 for Figure 11 A circuit schematic diagram of an embodiment of the full-bridge rectifier power supply unit 1011 in the power supply and receiving demodulation circuit unit 101. Figure 13 The full-bridge rectifier power supply unit 1011 includes a diode D2, a diode D3, a diode D4 and a diode D5; the cathode of the diode D2 and the cathode of the diode D3 are connected together, and this connection intersection serves as the output end of the full-bridge rectifier power supply unit 1011, which is used to connect to the VDD pin; the anode of the diode D2 and the cathode of the diode D4 are connected together, and this connection intersection serves as the first input end of the full-bridge rectifier power supply unit 1011; the anode of the diode D4 is connected to the anode of the diode D5 and is connected to the GNDP pin; the cathode of the diode D5 and the anode of the diode D3 are connected together, and this connection intersection serves as the second input end of the full-bridge rectifier power supply unit 1011.

[0161] It should be noted that the full-bridge rectifier power supply unit can be implemented by the ESD diodes of the two signal receiving pins of the primary side controller 10, or by integrating the full-bridge power tube into the primary side controller.

[0162] Combine Figure 1 、 Figure 10 and Figure 13 It can be seen that in the selected switching cycle Tsw, the full-bridge power tube 2031 inside the secondary controller 20 is turned on alternately, that is, TS1 and TS2 present quasi-complementary waveforms. ON That is, during the period between TS1 off and TS2 on, the potential of the same-name terminals of the magnetic isolation coupling device 30 winding becomes positive relative to the non-same-name terminals. When the converter's output voltage Vo is applied to the secondary side of the magnetic isolation coupling device via the Vp pin, the reflected load current plus the excitation current of the secondary side of the magnetic isolation coupling device 30 will flow through the full-bridge rectifier power supply unit 1011 within the primary controller 10. This turns on diodes D2 and D5, and turns off diodes D3 and D4, supplying power to the VDD pin. During the dead zone T DT During the period TS1off and TS2off, all power transistors in the full-bridge power transistor 2031 of the secondary controller 20 are turned off. ONDuring this period (TS1 on and TS2 off), the polarity of the winding's dotted ends becomes negative relative to the non-dotted ends. When the output voltage Vo is applied to the secondary side of the magnetic isolation coupling device via the Vp pin, the reflected load current plus the excitation current of the secondary side of the magnetic isolation coupling device 30 flows through the full-bridge rectifier power supply unit 1011 within the primary controller 10. This turns off diodes D2 and D5, while diodes D3 and D4 conduct, re-energizing the VDD pin. This alternating cycle ensures a stable power supply to the VDD pin of the primary controller 10.

[0163] According to the volt-second balance principle of inductance, the output voltage of the primary side of the magnetic isolation coupling device is equal to the voltage V VDD , which can be expressed by formula (11):

[0164]

[0165] in is the turns ratio of the primary coil and the secondary coil of the magnetic isolation coupling device 30; V VP is the voltage of the Vp pin, which is equal to the voltage of the output Vo; V MOS is the conduction voltage drop of the internal full-bridge power tube 2031 of the secondary side controller 20, V NP(DCR) is the voltage drop across the DC resistance of the primary coil of the magnetic isolation coupling device 30, D is the duty cycle of the secondary controller 20 outputting the quasi-complementary signal TS1 or TS2, V Diode is the voltage drop of the output rectifier diode in the full-bridge rectifier power supply unit 1011 in the primary side controller 10, V NS(DCR) is the voltage drop across the DC resistance of the secondary coil of the magnetic isolation coupling device 30 .

[0166] Second embodiment

[0167] The difference between this embodiment and the first embodiment is that this embodiment adopts fixed frequency control, and the PFM or PWM unit, modulation signal driving unit and magnetic isolation coupling device therein are different from those of the first embodiment, which are explained as follows with reference to the accompanying drawings.

[0168] like Figure 14 FIG. 2 is a circuit diagram of another embodiment of the PFM or PWM unit 202_2 in the secondary-side controller 20 according to the second embodiment of the present invention. Figure 14The PFM or PWM unit 202_2 includes a comparator CMP, a triangle wave generator, and an NMOS transistor NM8. The negative input of the comparator CMP serves as the input of the PFM or PWM unit 202_2. The positive input of the comparator CMP is connected to the output of the triangle wave generator. The output of the comparator CMP is connected to the gate of the NMOS transistor NM8. The source of the NMOS transistor NM8 is connected to the GNDS pin. The drain of the NMOS transistor NM8 serves as the output of the PFM or PWM unit 202_2, outputting a low-voltage drive signal V_pwm.

[0169] and Figure 3 The difference between the PFM or PWM unit 202 of the embodiment is that this embodiment only generates one low-voltage drive signal V_pwm, the frequency of which is determined by the triangular wave generator, that is, the low-voltage drive signal V_pwm is fixed, and its duty cycle is determined by the signal PWM output from the output terminal of the comparator CMP, that is, the comparator CMP compares the voltage signal VEA output by the error amplifier EA with the signal output by the triangular wave generator, and outputs a PWM signal to control the on and off of the NMOS tube NM8, that is, the voltage signal VEA determines the duty cycle of the output signal V_pwm, so the duty cycle of the low-voltage drive signal V_pwm changes with the load. Figure 3 Similarly, the heavier the load, the lower the output voltage is than the steady-state value, the higher the level of the voltage signal VEA, the longer the on-time of the signal PWM outputted from the output terminal of the comparator CMP, and the greater the duty cycle of the low-voltage drive signal V_pwm.

[0170] like Figure 15 The schematic diagram shows another circuit diagram of the modulation signal driving unit 203_2 in the secondary-side controller 20 according to the second embodiment of the present invention. This circuit diagram is suitable for situations where the PFM or PWM unit 202 generates only one drive signal. The modulation signal driving unit 203_2 shown in the figure includes a capacitor C6, an NMOS transistor NM9, and an NMOS transistor NM10. The source of the NMOS transistor NM9 is connected to the source of the NMOS transistor NM10, for inputting the drive signal generated by the PFM or PWM unit 202. The gate of the NMOS transistor NM9 is connected to one end of the capacitor C6 and the drain of the NMOS transistor NM10, serving as the second output terminal of the modulation signal driving unit 203_2. The gate of the NMOS transistor NM10 is connected to the other end of the capacitor C6 and the drain of the NMOS transistor NM9, serving as the first output terminal signal of the modulation signal driving unit 203_2.

[0171] like Figure 15 As shown in the figure, this is an equivalent block diagram of a typical cross-coupled oscillator, which can achieve higher frequency resonant oscillation, further reduce the size of the small transformer, and is more conducive to transformer integration.

[0172] like Figure 16FIG. 1 is another circuit diagram of the magnetic isolation coupling device 30_2 according to the second embodiment of the present invention. Figure 9 The difference is that this small transformer is a small core transformer with a center tap on the secondary side. The specific connection relationship is: the two terminals of the secondary side of the small core transformer are connected to the first output terminal and the second output terminal of the modulation signal driving unit 203_2 respectively, and its center tap is connected to the Vp pin.

[0173] Combine Figure 15 and Figure 16 As shown, the working principle of this cross-coupled oscillator combined with a small transformer is briefly as follows:

[0174] The longer the V_pwm signal is low, the more pulse energy is transmitted from the Vp pin when the cross-coupled oscillator drives the small transformer, thereby meeting the higher power consumption requirement of the VDD pin in the primary-side controller 10. The shorter the V_pwm signal is low, the less pulse energy is transmitted from the Vp pin when the cross-coupled oscillator drives the small transformer, thereby meeting the low power consumption requirement of the VDD pin in the primary-side controller 10. When the V_pwm signal is high, the cross-coupled oscillator stops oscillating, and the power loss of the primary-side VDD pin is resisted by the bypass capacitor C2 connected to the VDD pin.

[0175] use Figure 15 、 16 The beneficial effects of the circuit are: the cross-coupled oscillator can more easily achieve ultra-high frequency, which is beneficial to energy transmission. At the same time, the duty cycle of the V_pwm signal can be controlled to meet the power consumption requirements of the primary side VDD pin under different loads, and the load regulation rate is higher. At the same time, the ultra-high frequency transformer can be further reduced, which is more conducive to integration, reduces PCB board space, and has strong anti-interference ability.

[0176] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be construed as limiting the present invention. It should be recognized that the present invention is applicable to a wider range of applications. Based on the above disclosure, utilizing common technical knowledge and conventional means in the art, and without departing from the basic technical concept of the present invention, the present invention may be modified, replaced, or altered in various other forms, all of which fall within the scope of protection of the present invention.

Claims

1. A control method for an isolation converter, wherein the isolation converter comprises a main power switch tube, a primary side controller and a secondary side controller, characterized in that: The steps include: The output voltage feedback and loop compensation step performs loop compensation on the output voltage feedback signal to generate a voltage signal VEA that can reflect load changes; A frequency conversion or duty cycle control step, wherein the voltage signal VEA generates two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 whose frequencies and duty cycles vary with the voltage signal VEA; or the voltage signal VEA generates a low-voltage drive signal V_pwm whose frequency is fixed but whose duty cycle varies with the voltage signal VEA; A modulation signal driving step, generating two quasi-complementary driving signals TS1 and TS2 with driving capability from the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm; A magnetic isolation transmission step is performed to isolate and transmit the drive signals TS1 and TS2 and generate drive signals TR1 and TR2 accordingly; The primary side power supply and receiving demodulation step supplies power to the primary side controller through bridge rectification of the drive signals TR1 and TR2, and demodulates either of the drive signals TR1 and TR2 into a primary side inductor current modulation voltage signal VCS_Lim and a narrow pulse signal Tpulse_H; The main power switch control step includes: before the output voltage is established, the oscillator in the primary-side controller generates a control signal to control the main power switch to be turned on and off; after the output voltage is established, the narrow pulse signal Tpulse_H controls the oscillator in the primary-side controller to stop working, and the primary-side inductor current modulation voltage signal VCS_Lim generates a control signal. The frequency or duty cycle of the control signal is adjusted in combination with the main power switch source peak current sampling signal to control the main power switch to be turned on and off; From the output voltage feedback and loop compensation steps to the main power switch tube control step, this cycle is repeated to achieve closed-loop control and energy transmission; When the modulation signal driving step generates two quasi-complementary drive signals TS1 and TS2 with driving capability from the low-voltage drive signals Ton_H1 and Ton_H2, in the modulation signal driving step, the low-voltage drive signals Ton_H1 and Ton_H2 are used to generate two quasi-complementary NMOS tube drive signals and two quasi-complementary PMOS tube drive signals through an inverter chain and a totem pole drive structure, and then the two quasi-complementary drive signals TS1 and TS2 with driving capability are generated through a built-in full-bridge power tube; when the modulation signal driving step generates two quasi-complementary drive signals TS1 and TS2 with driving capability from the low-voltage drive signal V_pwm, in the modulation signal driving step, the low-voltage drive signal V_pwm is used to generate two quasi-complementary drive signals TS1 and TS2 with driving capability through a cross-coupled oscillator.

2. The control method of the isolation converter according to claim 1, wherein: In the output voltage feedback and loop compensation step, the feedback signal of the output voltage is compared with the first reference voltage signal VREF1 through the error amplifier, and by setting the gain and bandwidth of the error amplifier and combining loop compensation, a voltage signal VEA that can reflect load changes is generated.

3. The control method of the isolation converter according to claim 1, wherein: The isolation converter further comprises a synchronous rectifier tube, and in the frequency conversion or duty cycle control step, a signal for controlling the shutdown of the synchronous rectifier tube is also generated simultaneously.

4. The control method of the isolation converter according to claim 1, wherein: In the frequency conversion or duty cycle control step, the voltage signal VEA and the second reference voltage signal VREF2 output a current signal that varies with the voltage signal VEA through a transconductance amplifier. This current signal then outputs a frequency signal that varies with the voltage signal VEA through an oscillator. Then, through dead-time control, two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 are generated, whose duty cycles vary with the voltage signal VEA.

5. The control method of the isolation converter according to claim 1, wherein: In the frequency conversion or duty cycle control step, the voltage signal VEA and the signal generated by the triangle wave generator are output through the comparator CMP as a low voltage driving signal V_pwm with a fixed frequency but a duty cycle that varies with the voltage signal VEA.

6. The control method of the isolation converter according to claim 1, wherein: In the frequency conversion or duty cycle control step, the higher the level of the voltage signal VEA is, the greater the duty cycle of the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm is.

7. The control method of the isolation converter according to claim 1, wherein: The smaller the duty cycle of the driving signals TR1 and TR2 or the lower the frequency, the smaller the level of the primary inductor current modulation voltage signal VCS_Lim, and the smaller the duty cycle of the control signal generated by the primary inductor current modulation voltage signal VCS_Lim.

8. A control circuit for an isolation converter, comprising a main power switch, a primary side controller, and a secondary side controller, characterized in that: Includes the following units: The error amplifier and compensation unit is used to perform loop compensation on the feedback signal of the output voltage to generate a voltage signal VEA that can reflect load changes; A PFM or PWM unit is configured to generate, from the voltage signal VEA, two quasi-complementary low-voltage drive signals Ton_H1 and Ton_H2 whose frequencies and duty cycles vary with the voltage signal VEA; or to generate, from the voltage signal VEA, a low-voltage drive signal V_pwm whose frequency is fixed but whose duty cycle varies with the voltage signal VEA; A modulation signal driving unit, configured to generate two quasi-complementary driving signals TS1 and TS2 with driving capability from the low-voltage driving signals Ton_H1 and Ton_H2 or the low-voltage driving signal V_pwm; A magnetic isolation transmission unit, configured to isolate and transmit the drive signals TS1 and TS2 and generate corresponding drive signals TR1 and TR2; The primary side power supply and receiving demodulation unit is used to power the primary side controller through the bridge rectification of the driving signals TR1 and TR2, and at the same time demodulate any one of the driving signals TR1 and TR2 into the primary side inductor current modulation voltage signal VCS_Lim and the narrow pulse signal Tpulse_H; The main power switch control unit is used to generate a control signal through the oscillator in the primary-side controller before the output voltage is established to control the on and off of the main power switch. After the output voltage is established, the narrow pulse signal Tpulse_H controls the oscillator in the primary-side controller to stop working, and the primary-side inductor current modulation voltage signal VCS_Lim and the main power switch source peak current sampling signal jointly generate a control signal to control the on and off of the main power switch. Among them, when the modulation signal driving unit is used to generate two quasi-complementary driving signals TS1 and TS2 with driving capabilities from the low-voltage driving signals Ton_H1 and Ton_H2, the modulation signal driving unit includes a latch LATH2, a latch LATH3, an inverter chain 1, an inverter chain 2, an inverter chain 3, an inverter chain 4, a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM4, an NMOS transistor NM5, a NOT gate not6, a NOT gate not7 and a full-bridge power tube; the input end of the latch LATH2 serves as the first input end of the modulation signal driving unit to input the low-voltage driving signal Ton_H1, and its output end is simultaneously connected to the input ends of the inverter chain 1 and the inverter chain 2; the latch LATH2 is connected to the input end of the inverter chain 1 and the inverter chain 2; The input end of the LATH3 is used as the second input end of the modulation signal driving unit to input the low-voltage driving signal Ton_H2, and its output end is connected to the input ends of the inverter chain 3 and the inverter chain 4 at the same time; the output end of the inverter chain 1 is connected to the gate of the PMOS tube PM2; the output end of the inverter chain 2 is connected to the gate of the NMOS tube NM4; the output end of the inverter chain 3 is connected to the gate of the PMOS tube PM3; the output end of the inverter chain 4 is connected to the gate of the NMOS tube NM5; the source of the PMOS tube PM2 is used to connect to the low-voltage power supply VCC, and its drain is simultaneously connected to the drain of the NMOS tube NM4, the input end of the NOT gate not6 and the first input end of the full-bridge power tube; the output end of the NOT gate not6 is connected to the full-bridge power tube The second input terminal of the NMOS tube NM4 is connected to the GNDS pin of the secondary side controller; the source of the PMOS tube PM3 is used to connect to the low-voltage power supply VCC, and its drain is connected to the drain of the NMOS tube NM5, the input terminal of the NOT gate not7 and the third input terminal of the full-bridge power tube; the output terminal of the NOT gate not7 is connected to the fourth input terminal of the full-bridge power tube; the source of the NMOS tube NM5 is connected to the GNDS pin of the secondary side controller; the first output terminal of the full-bridge power tube serves as the first output terminal of the modulation signal driving unit to output the driving signal TS1, and the second output terminal of the full-bridge power tube serves as the second output terminal of the modulation signal driving unit to output the driving signal TS2; when the modulation signal driving unit is used to generate a low-voltage driving signal V_pw When generating two quasi-complementary drive signals TS1 and TS2 with drive capability, the modulation signal driving unit includes a capacitor C6, an NMOS transistor NM9, and an NMOS transistor NM10; the source of the NMOS transistor NM9 is connected to the source of the NMOS transistor NM10 for inputting the low-voltage drive signal V_pwm; the gate of the NMOS transistor NM9 is connected to one end of the capacitor C6 and the drain of the NMOS transistor NM10, and serves as the second output end of the modulation signal driving unit for outputting the drive signal TS2; the gate of the NMOS transistor NM10 is connected to the other end of the capacitor C6 and the drain of the NMOS transistor NM9, and serves as the first output end signal of the modulation signal driving unit for outputting the drive signal TS1.

9. The control circuit of the isolation converter according to claim 8, wherein: The error amplifier & compensation unit includes an error amplifier EA and a built-in compensation network; the positive input terminal of the error amplifier EA is used to input the first reference voltage signal VREF1, and its negative input terminal is connected to the VFB pin of the secondary side controller and the output terminal of the built-in compensation network at the same time. Its output terminal is connected to the input terminal of the built-in compensation network and serves as the output terminal of the error amplifier & compensation unit 201, outputting the voltage signal VEA.

10. The control circuit of the isolation converter according to claim 8, wherein: The isolation converter also includes a synchronous rectifier tube. In the frequency conversion or duty cycle control unit, a signal for controlling the shutdown of the synchronous rectifier tube is also generated to realize the control of the opening and closing of the synchronous rectifier tube.

11. The control circuit of the isolation converter according to claim 8, wherein: The PFM or PWM unit includes a transconductance amplifier OTA, an oscillator OSC, a dead time control 1, a dead time control 2, a NAND gate nand1, a NAND gate nand2, a NOT gate not1 and a NOT gate not2; the first input terminal of the transconductance amplifier OTA is used to input a voltage signal VEA, the second input terminal thereof is used to input a second reference voltage signal VREF2, the first output terminal thereof outputs a current signal IOTA1 to the first input terminal of the oscillator OSC, the second output terminal thereof outputs a current signal IOTA2 to the first input terminal of the dead time control 1, and the third output terminal thereof outputs a current signal IOTA3 to the first input terminal of the dead time control 2; the second input terminal of the oscillator OSC inputs the third reference voltage signal VREF3, the first output terminal CLK thereof is simultaneously connected to the dead time control 2. The second input terminal of dead time control 1 is connected to the first input terminal of NAND gate nand2, and its second output terminal CLK_ is simultaneously connected to the second input terminal of dead time control 2 and the first input terminal of NAND gate nand1; the output terminal of dead time control 2 is connected to the second input terminal of NAND gate nand1; the output terminal of dead time control 2 is connected to the second input terminal of NAND gate nand2; the output terminal of NAND gate nand1 is connected to the input terminal of NAND gate not1; the output terminal of NAND gate nand2 is connected to the input terminal of NAND gate not2; the output terminal of NAND gate not1 serves as the first output terminal of PFM or PWM unit 202, outputting signal Ton_H1; the output terminal of NAND gate not2 serves as the second output terminal of PFM or PWM unit 202, outputting signal Ton_H2.

12. The control circuit of the isolation converter according to claim 11, wherein: The oscillator OSC includes a bias current source IB1, a capacitor C3, an NMOS transistor NM1, a comparator CMP1, a latch LATH1, a D flip-flop DFF1, a NOT gate not3 and a NAND gate nand3; the current input end of the bias current source IB1 is used to connect to the low-voltage power supply VCC; the positive input end of the comparator CMP1 serves as the second input end of the oscillator OSC, and its negative input end is simultaneously connected to the current output end of the bias current source IB1, one end of the capacitor C3 and the drain of the NMOS transistor NM1, and serves as the first input end of the oscillator OSC, and its output end is connected to the latch LATH1. The input terminal of TH1 is connected; the other end of the capacitor C3 is connected to the source of the NMOS transistor NM1 and the GNDS pin of the secondary side controller; the gate of the NMOS transistor NM1 is connected to the output terminal of the NAND gate nand3; the first input terminal of the NAND gate nand3 is connected to the output terminal of the latch LATH1 and the second input terminal CP_L of the D flip-flop DFF1, and the second input terminal is connected to the third input terminal Clr_L of the D flip-flop DFF1, and the second input terminal also inputs the low voltage initialization signal ENP_lv; the first input terminal D of the D flip-flop DFF1 and its second output terminal The first output terminal Q is connected to the input terminal of the NOT gate not3 and serves as the first output terminal CLK of the oscillator OSC. The output terminal of the NOT gate not3 serves as the second output terminal CLK_ of the oscillator OSC.

13. The control circuit of the isolation converter according to claim 11, wherein: Dead time control 1 includes a bias current source IB2, a capacitor C4, a PMOS transistor PM1, NMOS transistors NM2 and NM3, a Schmitt trigger Smt, and inverters not4 and not5. The input end of the Schmitt trigger Smt is simultaneously connected to the drain of the PMOS transistor PM1, the drain of the NMOS transistor NM2, the drain of the NMOS transistor NM3, and one end of the capacitor C4. The source of the PMOS transistor PM1 is connected to the current output end of the bias current source IB2 and serves as the first input end of the dead time control 1. The current input end of the bias current source IB2 is used to connect to the low-voltage power supply VCC. The gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM2 and serves as the second input terminal of the dead time control 1; the source of the NMOS transistor NM2 is simultaneously connected to the other end of the capacitor C4, the source of the NMOS transistor NM3, and the GNDS pin; the gate of the NMOS transistor NM3 is connected to the output terminal of the NOT gate not5; the input terminal of the NOT gate not5 is used to input the low-voltage initialization signal ENP_lv; the output terminal of the Schmitt trigger Smt is connected to the input terminal of the NOT gate not4, and the output terminal of the NOT gate not4 serves as the output terminal of the dead time control 1.

14. The control circuit of the isolation converter according to claim 8, wherein: The PFM or PWM unit includes a comparator CMP, a triangular wave generator and an NMOS transistor NM8; the negative phase input terminal of the comparator CMP is used to input the voltage signal VEA, the positive phase input terminal of the comparator CMP is connected to the output terminal of the triangular wave generator, the output terminal of the comparator CMP is connected to the gate of the NMOS transistor NM8, the source of the NMOS transistor NM8 is connected to the GNDS pin, and the drain of the NMOS transistor NM8 is the output terminal of the PFM or PWM unit, and the output signal is a low-voltage drive V_pwm.

15. The control circuit of the isolation converter according to claim 8, wherein: For the PFM or PWM unit, the higher the level of the voltage signal VEA is, the greater the duty cycle of the low-voltage driving signals Ton_H1 and Ton_H2 , or the low-voltage driving signal V_pwm.

16. The control circuit of the isolation converter according to claim 8, wherein: The full-bridge power transistors include a PMOS transistor PM4, a PMOS transistor PM5, an NMOS transistor NM6, and an NMOS transistor NM7; the gate of the PMOS transistor PM4 serves as the second input terminal of the full-bridge power transistor, and its source is simultaneously connected to the source of the PMOS transistor PM5 and the Vp pin of the secondary-side controller; the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM6 and serves as the first output terminal of the modulation signal driving unit; the source of the NMOS transistor NM6 is simultaneously connected to the source of the NMOS transistor NM7 and the GNDS pin of the secondary-side controller; the gate of the NMOS transistor NM6 serves as the first input terminal of the full-bridge power transistor; the gate of the NMOS transistor NM7 serves as the third input terminal of the full-bridge power transistor; the drain of the NMOS transistor NM7 is connected to the drain of the PMOS transistor PM5 and serves as the second output terminal of the modulation signal driving unit; and the gate of the PMOS transistor PM5 serves as the fourth input terminal of the full-bridge power transistor.

17. The control circuit of the isolation converter according to claim 8, wherein: The smaller the duty cycle of the driving signals TR1 and TR2 or the lower the frequency, the smaller the level of the primary inductor current modulation voltage signal VCS_Lim, and the smaller the duty cycle of the control signal generated by the primary inductor current modulation voltage signal VCS_Lim.

18. The control circuit of the isolation converter according to claim 8, wherein: The magnetic isolation coupling device is a small core transformer with two terminals on the primary side and two terminals on the secondary side, or a small core transformer with two terminals on the primary side and two terminals and a center tap on the secondary side.

19. The control circuit of the isolation converter according to claim 8, wherein: The power supply and receiving demodulation circuit includes a sampling signal generation, a full-bridge rectifier power supply unit, a PMOS transistor PM6, an NMOS transistor NM11, a bias current source IB3, a capacitor C5, a transmission gate Tri, a non-gate not8, an operational amplifier AMP, a resistor R2, and a resistor R3; the source of the PMOS transistor PM6 is used to input a fourth reference voltage VREF4, the gate thereof is connected to the first output terminal generated by the sampling signal, and the drain thereof is simultaneously connected to one end of the capacitor C5, the current input terminal of the bias current source IB3, and the first input terminal of the transmission gate Tri; the other end of the capacitor C5 is simultaneously connected to the source of the NMOS transistor NM11 and the GNDP pin; the gate of the NMOS transistor NM11 is connected to the second output terminal generated by the sampling signal, and the drain thereof is connected to the current output terminal of the bias current source IB3; the second input terminal of the transmission gate Tri is simultaneously connected to the second output terminal generated by the sampling signal The three output terminals are connected to the input terminals of the NOT gate not8, the third input terminal of the transmission gate Tri is connected to the output terminal of the NOT gate not8, serving as the second output terminal of the power supply and receiving demodulation circuit unit, outputting a narrow pulse signal Tpulse_H; the output terminal of the transmission gate Tri is connected to the positive phase input terminal of the operational amplifier AMP; the negative phase input terminal of the operational amplifier AMP and its output terminal are connected together, and connected to one end of the resistor R2; the other end of the resistor R2 is connected to one end of the resistor R3, and the intersection of these connections serves as the third output terminal of the power supply and receiving demodulation circuit unit, outputting the primary inductor current modulation voltage signal VCS_Lim; the other end of the resistor R3 is connected to the GNDP pin of the primary controller; the input terminal generating the sampling signal is connected to the second input terminal of the full-bridge rectifier power supply unit, and serves as the second input terminal of the power supply and receiving demodulation circuit unit, inputting the drive signal TR2; The first input end of the full-bridge rectifier power supply unit serves as the first input end of the power supply and receiving demodulation circuit unit, and inputs the driving signal TR1; the output end of the full-bridge rectifier power supply unit serves as the first output end of the power supply and receiving demodulation circuit unit, and is used to connect to the VDD pin of the primary side controller.

20. The control circuit of the isolation converter according to claim 8, wherein: The full-bridge rectifier power supply unit includes a diode D2, a diode D3, a diode D4 and a diode D5; the cathode of diode D2 and the cathode of diode D3 are connected together, and this connection intersection serves as the output end of the full-bridge rectifier power supply unit, which is used to connect to the VDD pin of the primary side controller; the anode of diode D2 and the cathode of diode D4 are connected together, and this connection intersection serves as the first input end of the full-bridge rectifier power supply unit; the anode of diode D4 is connected to the anode of diode D5 and is used to connect to the GNDP pin of the primary side controller; the cathode of diode D5 and the anode of diode D3 are connected together, and this connection intersection serves as the second input end of the full-bridge rectifier power supply unit.

21. The control circuit of the isolation converter according to claim 8, wherein: The full-bridge rectifier power supply unit is realized by the ESD diodes of the two signal receiving pins of the primary side controller, or by integrating the full-bridge power tube into the primary side controller.

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