Asymmetric half-bridge flyback converter and design method thereof

Abstract

The present invention discloses an asymmetric half-bridge flyback converter and a design method thereof, including the design of a main power circuit and a control circuit, and the derivation of the voltage fluctuation and resonance time on the resonant capacitor. The main power circuit includes the design of a planar transformer: the PPPSSS winding method is adopted to use one turn of the primary side as a shielding layer to greatly reduce the coupling capacitance of the primary and secondary sides, and no additional series resonant inductor is required to reduce losses. According to the derivation of the voltage fluctuation of the resonant capacitor, a reasonable resonant capacitor capacitance can be designed, and according to the derivation of the resonant time, a suitable resonant time can be obtained to achieve zero current shutdown of the secondary synchronous rectifier tube, while reducing the current circulation in the resonant cavity to improve efficiency. The present invention can realize soft switching of all switch tubes within a wide input voltage, output voltage and power range to achieve high efficiency.

Description

Technical Field

[0001] The present invention relates to the DC-DC converter technology of power conversion devices, and particularly to an asymmetric half-bridge flyback converter and its design method. Background Art

[0002] With the wide use of portable electronic devices, electronic device charging adapters have become necessities. With the development of fields such as mobile phone fast charging in recent years, higher requirements are put forward for the power and volume of the power system, requiring the charging device to have a fast charging speed and a small volume. At the same time, with the increase in the power of the charging device, the grid's EMI requirements for the converter are also increasing day by day, requiring compliance with the national set standards.

[0003] For small and medium-power switch-mode power supplies required for mobile electronic devices such as mobile phone fast charging, their losses are dissipated in the form of heat. Therefore, the requirements for the converter can be summarized as the requirements for high efficiency and high power density of the converter. Currently, two commonly used simple and practical switch-mode power supply topologies can both achieve the required power requirements. One is the forward converter, and the other is the flyback converter. The energy of the forward converter can be directly transferred to the transformer without using the transformer to store energy. Therefore, the transformer has a higher magnetizing inductance and no air gap, which can improve the utilization rate of the transformer; the secondary output of the transformer is filtered by LC, which can ensure that while reducing the output voltage ripple, the peak current on the transistor is reduced, thereby reducing the voltage stress. Compared with the forward converter, the flyback transformer is mainly used to store energy during the operation of the circuit, and its application in high-power occasions is limited. At the same time, the converter secondary side does not require a filter inductor, and it has an absolute advantage in dealing with wide input voltage range, wide output voltage range, and high gain requirements. Therefore, the flyback converter is an optimal choice in low-power occasions.

[0004] The flyback converter also has many problems in practical applications. One is that since the conventional flyback circuit operates in the hard-switching mode, high efficiency cannot be achieved. The other is that for the consideration of reducing cost and volume, the transformer needs to have an air gap to prevent magnetic flux saturation, but this measure leads to an increase in the leakage inductance of the transformer, increasing power loss and MOS tube voltage stress, and reducing the efficiency of the converter and the stability of the circuit. In addition, the resonant peak voltage caused by the secondary winding of the converter will affect the working efficiency of the switch-mode power supply transformer. [3] . In the hard-switching mode, the EMI performance of the converter will deteriorate, which also limits the use of the flyback converter in some application scenarios. In response to the above three major problems of the flyback converter, scholars have conducted a large number of studies on the flyback converter.

[0005] To reduce the voltage stress and voltage spikes of flyback converters, a passive RCD snubber circuit is often used in the quasi-resonant circuit (QR) to consume the remaining energy in the leakage inductance, which limits the efficiency improvement of flyback converters. The active-clamped flyback circuit (ACF) can effectively utilize the energy in the leakage inductance through the clamping capacitor, but the problem of high voltage stress on its switching transistors still restricts the development and application of flyback converters. Summary of the Invention

[0006] The object of the present invention is to address the deficiencies of the above background technology and provide an asymmetric half-bridge flyback converter and its design method, enabling the converter to meet the requirements of wide input and wide output (input 90VAC - 220VAC, output 5V - 15V, 5A), with as high an efficiency as possible and as large a power density as possible.

[0007] The present invention adopts the following technical solutions to achieve the above object:

[0008] An asymmetric half-bridge flyback converter includes a main power circuit. The main power circuit includes V B which is the bus voltage of the AC input voltage after passing through a rectifier bridge and an input filter capacitor, S 1 , S 2 as the primary switching transistors, using GaN devices. Since GaN devices do not have body diodes but have a third quadrant, the diodes connected in parallel with S 1 , S 2 in the schematic diagram are used to represent its third quadrant for describing the freewheeling process. The transformer model can be equivalent to a leakage inductance of L r , an exciting inductance of L m and an ideal transformer with a turns ratio of n:1, C r as the resonant capacitor, Q 1 as the secondary synchronous rectifier transistor, C o as the output capacitor, and R o as the load.

[0009] A design method for an asymmetric half-bridge flyback converter, used for the above-mentioned asymmetric half-bridge flyback converter, includes the following steps:

[0010] Step A: Analyze the leakage inductance current i Lr and the voltage v Cr across the resonant capacitor in each mode according to the converter operating modes;

[0011] Step B: Obtain the duty cycle of the upper transistor S 1 as

[0012] according to the volt-second balance of the exciting inductance; Step C: The output current can be obtained according to the input power integration Lmmax where ILmmin They are the positive and negative peak currents of the exciting inductance respectively. The specific calculation is as follows where t off is the turn-off time of the upper switch;

[0013] Step D: The secondary current can be approximately regarded as a half sine wave. The average value of the secondary current in one cycle is equal to the output current I o The peak current of the secondary side can be obtained

[0014] Step E: The value of the input capacitor C in depends on the minimum effective value V of the AC voltage inrms_min and the minimum capacitor voltage V B_min . The value of the input filter capacitor is

[0015] Step F: According to the maximum duty cycle set for the upper switch, the maximum turns ratio can be obtained According to the breakdown voltage of the secondary synchronous rectifier tube Q 1 the minimum turns ratio can be obtained Thus, the turns ratio n of the transformer is obtained;

[0016] Step G: Conduct the transformer design. According to the effective area A of the magnetic core e and the magnetic flux density variable ΔB, the number of turns of the secondary side of the transformer can be obtained Thus, the number of turns N of the primary side of the transformer is obtained p and the size δ of the magnetic core air gap;

[0017] Step H: Since the secondary current is approximately a half sine wave, the intersection points of its waveform with that of I o in the waveform are t A1 and t A2 . According to the requirement of the output voltage ripple amplitude ΔU, the output capacitor is obtained

[0018] Preferably, the valley value of the voltage fluctuation on the resonant capacitor, that is Figure 1 the voltage value of the resonant capacitor at the moment t 1 in is

[0019]

[0020] In the formula

[0021] The peak value of the voltage fluctuation on the resonant capacitor, that is Figure 1 the voltage value of the resonant capacitor at the moment t 5 in is

[0022]

[0023] In the formula

[0024]

[0025] Preferably, the turn-on time t of the lower switch when the upper switch is turned off off (ignoring the dead time) should be as close as possible to the resonance time to reduce the circulating current in the resonance cavity and enable zero-current turn-off of the secondary synchronous rectifier. The resonance time is

[0026]

[0027] In the formula

[0028] Preferably, a planar transformer design is adopted. The PPPSSS winding method is used to design a single turn of the primary coil into a shielding layer, which is at the same potential as the positive electrode of the resonance capacitor C r so that the coupling capacitors between the primary and secondary sides are coupled to a potential with very little fluctuation, effectively reducing the common-mode noise, and there is no need to additionally connect a series resonance inductor to reduce the loss.

[0029] Preferably, for the upper switch of the primary switch tube, GS-065-011-1-L of GaN System is selected; for the lower switch, GS66508B of GaNSystems is selected; for the secondary synchronous rectifier, BSC093N15NS5 of Infineon is selected; and for the magnetic core, PC95EL25X8.6-Z of TDK is selected. The control chip adopts the XDPS2201 chip of Infineon.

[0030] Compared with the prior art, the present invention adopting the above technical solutions has the following beneficial effects:

[0031] 1. The present invention provides an asymmetric half-bridge flyback converter and its design method. By randomly selecting a frequency within the range of two switching frequency changes in each control cycle to randomize the switching frequency, it is possible to improve the harmonic dispersion effect of the random SVPWM method and further suppress electromagnetic interference in the case of a relatively narrow switching frequency change range.

[0032] 2. The present invention provides an asymmetric half-bridge flyback converter and its design method. It can achieve zero-voltage switching (ZVS) of the primary switch tube and zero-current switching (ZCS) of the secondary synchronous rectifier within a wide range of input voltage, output voltage, and output power.

[0033] 3. The present invention provides an asymmetric half-bridge flyback converter and its design method, and proposes a new magnetic shielding technology method for the planar transformer design of the asymmetric half-bridge flyback converter. By using a single turn of the primary winding as a shielding layer to greatly reduce the coupling capacitance between the primary and secondary sides, the converter meets the requirements of EN55022B.

[0034] 4. The present invention provides an asymmetric half-bridge flyback converter and its design method, which reduces the AC impedance of the transformer by adopting a mixed copper thickness method, thereby improving the efficiency and power density of the converter. Brief Description of the Drawings

[0035] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 are the key waveforms of the converter in a switching cycle;

[0037] Figure 2 is the main circuit of the asymmetric half-bridge flyback converter;

[0038] Figure 3 is the working mode diagram of the converter;

[0039] Figure 4 is the schematic diagram of the PPPSSS winding method;

[0040] Figure 5 is the cross-sectional view of the transformer winding;

[0041] Figure 6 is the spatial structure diagram of the transformer winding. Detailed Description of the Embodiments

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] 1. Working principle of the asymmetric half-bridge flyback converter:

[0044] Figure 1 shows the key waveforms of the converter in a switching cycle. From top to bottom, they are the driving signal of the upper switch, the driving signal of the lower switch, the resonant current and the magnetizing current, the secondary current, and the voltage at the midpoint of the half-bridge. Figure 2 is the main circuit of the asymmetric half-bridge flyback converter. Figure 3 shows the working mode diagram of the converter.

[0045] Mode 1: t 1 ~t 2 stage, S 1Turn on, S 2 Turn off. The current in the transformer increases, and the voltage across the resonant capacitor C r increases. Both devices can store energy. The secondary diode D 1 is reverse-biased, so no energy is transferred to the secondary side.

[0046] Mode 2: t 2 ~t 3 phase, the switching transistors S 1 and S 2 are both off. The primary current charges the parasitic capacitance of S 1 while discharging the parasitic capacitance of S 2 . At time t 3 , the charging and discharging processes of the parasitic capacitances of S 1 and S 2 end, and the voltage across S 2 drops to zero, providing a condition for the body diode of S 2 to turn on.

[0047] Mode 3: t 3 ~t 4 phase, the switching transistors S 1 and S 2 are both off. The body diode of S 2 clamps the voltage. The primary side of the transformer has the same voltage as the capacitor C r . The voltage across S 2 is the conduction voltage of the body diode.

[0048] Mode 4: t 4 ~t 5 phase, in the ZVS state, S 1 turns off and S 2 turns on. The secondary voltage is equal to the voltage across the capacitor C r divided by the turns ratio. Current starts to flow through Q 1 , and the energy in the capacitor and transformer is transferred to the output. Since the LC resonant cavity consists of L r (transformer leakage inductance) and the resonant capacitor, the secondary current is a sine wave determined by the resonant period of these two devices. The primary current is the sum of the magnetizing current and the secondary reflected current. The current in the resonant cavity is still positive and is mainly driven by the magnetizing inductance of the transformer T 1 , flowing into the resonant capacitor C r to further charge it.

[0049] Mode 5: t 5 ~t 6 phase is a continuation of the previous phase. S 1 turns off, S 2When it is turned on, energy is still transferred to the secondary side, but the directions of the resonant circuit current and voltage are reversed, and the voltage is provided by the resonant capacitor C. r The energy of the resonant capacitor is not only transferred to the secondary side, but also helps to reduce the magnetizing current of the transformer T 1 from positive to negative when S 2 is turned on.

[0050] Mode 6: from t 6 to t 7 During this stage, the secondary current finally drops to zero, and the primary current continues to decrease after resonating to zero. In order to provide enough negative current for the body diode of S 1 to turn on, so as to achieve ZVS (Zero Voltage Switching) of S 1

[0051] Mode 7: from t 7 to t 8 During this stage, both switches S 1 and S 2 are off. The primary current charges the parasitic capacitance of S 2 while discharging the parasitic capacitance of S 1 . At the moment of t 8 , the charging and discharging processes of the parasitic capacitances of S 2 and S 1 end, and the voltage across S 1 drops to zero, providing conditions for the body diode of S 1 to turn on.

[0052] Mode 8: from t 8 to t 9 During this stage, both switches S 1 and S 2 are off. The body diode of S 1 conducts, providing conditions for ZVS of S 1 .

[0053] Mode 9: from t 9 to t 10 During this stage, similar to the first stage, under ZVS conditions, S 1 turns on and S 2 turns off, but the current in the transformer resonant cavity is still negative, which means that the excess energy in the resonant cavity will be sent back to the input terminal.

[0054] 2. Circuit parameter design:

[0055] Step A: Analyze the equations of the leakage inductance current i Lr and the voltage v Cr across the resonant capacitor in each mode according to the working modes of the converter.

[0056] ​Step B: Obtain the upper switch S according to the volt-second balance of the excitation inductance 1 The duty cycle is

[0057] Step C: The output current can be obtained by integrating the input power where I Lmmax and I Lmmin are the positive and negative peak currents of the excitation inductance respectively. The specific calculation is where t off is the turn-off time of the upper switch

[0058] Step D: The secondary current can be approximately regarded as a half sine wave. The average value of the secondary current in one cycle is equal to the output current I o The peak value of the secondary current can be obtained

[0059] Step E: The size of the input capacitor C in depends on the minimum effective value V of the AC voltage inrms_min and the minimum capacitor voltage V B_min . The value of the input filter capacitor is

[0060] Step F: The maximum turns ratio can be obtained according to the maximum duty cycle set for the upper switch According to the withstand voltage of the secondary synchronous rectifier tube Q 1 the minimum turns ratio can be obtained Thus, the transformer turns ratio n is obtained

[0061] Step G: Conduct transformer design. According to the effective area A of the magnetic core e and the magnetic flux density variable ΔB, the number of secondary turns of the transformer can be obtained Thus, the number of primary turns N of the transformer is obtained p and the size of the magnetic core air gap δ

[0062] Step H: Since the secondary current is approximately a half sine wave, the intersection points of its waveform with I o in the waveform are t A1 and t A2 . According to the requirement of the output voltage ripple amplitude ΔU, the output capacitor is obtained

[0063] 3. Reference for the voltage fluctuation value on the resonant capacitor

[0064] The valley value of the voltage fluctuation on the resonant capacitor is Figure 1 where the resonant capacitor voltage value at the moment t 1 is

[0065]

[0066] In the formula

[0067] The peak value of the voltage fluctuation on the resonant capacitor, i.e., Figure 1 in which t 5 the voltage value of the resonant capacitor at the moment is

[0068]

[0069] In the formula

[0070]

[0071] 4. Design of the turn-on time of the lower switch:

[0072] The turn-off of the upper switch, i.e., the turn-on time t of the lower switch off (ignoring the dead time) should be as close as possible to the resonant time to reduce the circulating current in the resonant cavity and make the synchronous rectifier diode on the secondary side turn off with zero current. The resonant time is

[0073]

[0074] In the formula

[0075] 5. Design of the planar transformer:

[0076] To improve the power density, the planar transformer design is adopted. There are mainly two winding methods for the planar transformer on the six-layer board, namely the PPPSSS winding method and the PSPSPS winding method. The cross-sectional view and the spatial structure diagram of the transformer with the PSPSPS winding method are respectively as Figure 5 (a) and Figure 6 (a) shown. This winding method will cause multiple coupling capacitors C PS to exist between the primary and secondary sides. The common-mode noise is transmitted through C PS , so the common-mode noise of this winding method is relatively large. The schematic diagram of the PPPSSS winding method is as Figure 4 shown. The cross-sectional view and the spatial structure diagram of the transformer winding are respectively as Figure 5 (b) and Figure 6 (b) shown. This winding method uses a single turn of the primary coil to design it into a shielding layer, which is at the same potential as the positive electrode of the resonant capacitor C r , so that the coupling capacitors between the primary and secondary sides are all coupled to a potential with very small fluctuations, which can effectively reduce the common-mode noise.

[0077] With the excitation inductance of 55 μH, the parameters of the two winding methods with the same inductance value are measured by LCR, as shown in Table 1. Through measurement, the primary-secondary coupling capacitance of the PPPSSS winding method is much smaller than that of the PSPSPS winding method, and the inductance impedance and the AC impedance do not change much. Therefore, the common-mode noise can be effectively reduced without affecting the efficiency. At the same time, the leakage inductance is increased to avoid an additional series resonant inductor to improve the efficiency and increase the power density.

[0078]

[0079] Table 1

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A design method for an asymmetric half-bridge flyback converter, characterized in that: The following steps are involved: Step A: Analyze the leakage inductance current i in each mode according to the converter operating mode Lr The voltage across the resonant capacitor v Cr equation; Step B: According to the excitation inductance volt-second balance, the duty cycle of the upper tube S1 is obtained as Step C: Output current can be obtained by integrating the input power Among them I Lmmax with I Lmmin are respectively the positive and negative peak currents of the excitation inductance; the specific calculation is: where t off is the upper tube shut-off time; Step D: The secondary current can be approximately regarded as a half sine wave. The average value of the secondary current in one cycle is equal to the output current I o The secondary side peak current can be obtained Step E: Input Capacitor C in The size depends on the minimum effective value of the AC voltage V inrms_min and the minimum capacitor voltage V B_min The input filter capacitor value is Step F: Set the maximum duty cycle according to the upper tube to get the maximum turns ratio The minimum turns ratio can be obtained based on the withstand voltage of the secondary synchronous rectifier Q1. From this, the transformer turns ratio n is obtained; Step G: Design the transformer according to the effective area A of the core e The number of turns on the secondary side of the transformer can be obtained by using the magnetic flux density variable ΔB From this, we can get the number of turns N of the primary side of the transformer p and the core air gap size δ; Step H: Since the secondary current is approximately a half sine wave, its waveform is similar to I o The intersection point of on the waveform is t A1 and t A2 , according to the output voltage ripple amplitude ΔU requirement, the output capacitance is obtained 2. The design method of an asymmetric half-bridge flyback converter according to claim 1, characterized in that: The voltage fluctuation valley value on the resonant capacitor is In the formula The peak value of the voltage fluctuation on the resonant capacitor is In the formula 3. The design method of an asymmetric half-bridge flyback converter according to claim 1, characterized in that: The time t when the upper tube is turned off and the lower tube is turned on off It needs to match the resonance time to reduce the circulating current in the resonant cavity and make the secondary synchronous rectifier tube turn off with zero current. The resonance time is In the formula 4. The design method of an asymmetric half-bridge flyback converter according to claim 1, characterized in that: The planar transformer design is adopted, and the PPPSSS winding method is used to use a single turn of the primary coil to design it into a shielding layer, which is connected to the resonant capacitor C r The positive electrodes have the same potential, so that the coupling capacitors between the primary and secondary sides are coupled to a potential with very small fluctuations, which can effectively reduce common-mode noise. At the same time, there is no need for additional series resonant inductors to reduce losses.

5. The design method of an asymmetric half-bridge flyback converter according to claim 1, characterized in that: The upper switch tube of the primary side uses GaN System's GS-065-011-1-L, the lower switch tube uses GaN Systems' GS66508B, the secondary side synchronous rectifier tube uses Infineon's BSC093N15NS5, the magnetic core uses TDK's PC95EL25X8.6-Z; the control chip uses Infineon's XDPS2201 chip.

6. An asymmetric half-bridge flyback converter, applicable to the design method of an asymmetric half-bridge flyback converter according to any one of claims 1 to 5, characterized in that: The main power circuit includes a V B is the bus voltage of the AC input voltage after passing through the rectifier bridge and the input filter capacitor. S1 and S2 are primary switch tubes. The transformer model can be equivalent to the leakage inductance L r , the excitation inductance is L m Compared with an ideal transformer with a turns ratio of n:1, C r is the resonant capacitor, Q1 is the secondary synchronous rectifier, C o is the output capacitor, R o For load.

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