A universal verification component and feedback control method based on UVM

Abstract

The invention discloses a UVM-based universal verification component and feedback control method. Based on UVM, the existing proxy verification component is improved, modeling is performed at the bus protocol layer, and the universal verification component structure is realized. The core of the universal verification component design of the invention is the feedback control logic jointly constructed by a transaction monitor, a protocol manager, a virtual sequence arbitrator and a virtual sequence. The feedback control method is divided into two paths: one is a control of blocking the sending of a virtual sequence through a legality check constructed by a protocol manager and a virtual sequence arbitrator; the other is a protocol handshake process jointly constructed by a transaction monitor and a virtual sequence arbitrator. The purpose is to control the simulation of bus protocol behavior in the universal verification component, to provide a more flexible way for constructing verification scenarios for test cases, to save development time for the verification platform, and to improve the efficiency and completeness of verification.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and in particular relates to a UVM-based universal verification component and a feedback control method. Background Art

[0002] With the development of the mobile Internet era, in order to meet the diverse market needs, integrating different types of IP cores and designing based on SOC development platforms has become the mainstream of chip design today. The increase in SOC integration also makes functional verification, an important part of the chip development process, face many challenges.

[0003] Simulation verification is the mainstream technology for current chip function verification. Its basic steps are to drive the input signal of the design under test through the verification platform, sample the output signal of the design under test to compare with the expected value, and finally verify the correctness of the function of the design under test. In this process, the development and debugging of the verification platform consumes a lot of time and energy of the verification personnel.

[0004] The existing verification strategy is to develop a UVM-based verification platform through the advantages of UVM (Universal Verification Methodology) verification methodology in standardization, automation and reusability, and reuse it in the verification of the design to be tested at different levels or projects to shorten the verification time.

[0005] The problems in the existing technical solutions are:

[0006] 1. In the verification of bus bridge interfaces, since this type of interface usually implements the switching from one protocol to another, this requires the verifier to have a thorough understanding of various bus protocols on the market in order to efficiently complete the implementation of the proxy verification component. In the end, it is only a bus interface verification for switching between two specific protocols (such as ICB protocol to SPI protocol), and the scenarios that can be reused in the future are limited.

[0007] 2. Verification of complex bus interfaces. This type of interface is characterized by a large number of signal types, including information such as upstream request entry release tags, and a set of processes from request initiation to completion. A typical scenario is that the verification platform needs to simulate that the upstream entry is full and cannot send new requests, and at the same time needs to monitor the downstream release signal and wait for the release entry to drive new requests. The current solution mostly uses test cases and agents to complete this feedback control, which is not flexible enough in control. Summary of the invention

[0008] The present invention provides a UVM-based universal verification component and a feedback control method to solve one or more technical problems existing in the prior art.

[0009] The present invention designs a universal verification component based on UVM verification methodology and SystemVerilog language. The verification component simulates a bus protocol layer, and according to the driving, sampling and coverage collection functions in different modes configured in the top layer of a verification platform, the verification component can be reused in any verification platform with the protocol interface module at the granularity of a set of bus protocols, and has more flexible reusability.

[0010] The technical solution of the present invention is as follows:

[0011] A UVM-based universal verification component includes: a protocol transaction package, a transaction driver, a sequence generator, a protocol agent, a transaction monitor, a coverage collector, a component configurator, a virtual sequence arbitrator, a protocol manager, a virtual sequence, a component interface and a component top layer, wherein:

[0012] The protocol transaction packet encapsulates the input signals and output signals that the bus module usually has, including five input variables and three output variables, the five input variables are request flag, request preparation, request command, request address and request data, and the three output variables are response flag, response preparation and response data; wherein the input variables are all random variables and can be randomized;

[0013] The transaction driver obtains the protocol transaction packet through the sequencer, and can drive the interface module to be tested through the component interface according to a specific protocol mode set by the component configurator;

[0014] The sequence generator acts as a bridge between the sequence arbitrator and the transaction driver, transmitting the protocol transaction packet and the response return information;

[0015] The protocol agent instantiates a connection sequence initiator and a transaction driver, and passes a component configurator pointer, representing a bus protocol standard of minimum granularity;

[0016] The transaction monitor samples the protocol transaction packet through the component interface and transmits it to the coverage collector, the virtual sequence arbiter and other components in the verification platform through the UVM port;

[0017] The coverage collector sets a functional coverage group, which is triggered by the transaction monitor when the transaction is valid, and collects and performs functional coverage statistics through sampling functions;

[0018] The component configurator is controlled by the top layer of the verification platform and determines the driving sampling mode and feedback control path of the universal verification component;

[0019] The virtual sequence arbitration is a sequence transmission and feedback control node of the general verification component, in which the protocol manager is instantiated, which has a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations inside the general verification component, and provides accessible variables and queues for use by test cases of the verification platform;

[0020] The protocol manager is responsible for registering the transaction requests initiated by the general verification component and allocating corresponding entries. When the entry is full, all subsequent transaction requests are blocked. When a release signal from the bus is obtained through the virtual sequence arbiter, the request corresponding to the entry number is released, and a new transaction request is run to occupy the entry.

[0021] The virtual sequence is a window for the test case to send a transaction request. A single test case can construct a functional scenario corresponding to the bus protocol according to multiple sets of virtual sequences provided by different general verification components;

[0022] The verification interface is used to realize the communication between the general verification component and the bus module to be tested. The verification platform needs to implement the corresponding binding function, and the interaction data can be obtained through the pointer object;

[0023] The top level of the component encapsulates all subcomponents of the general verification component, is the minimum level for instantiation and reuse of the verification platform, and is managed by a higher level verification environment component;

[0024] Two feedback paths consisting of a protocol manager, a virtual sequence arbitrator, and a transaction monitor are used to encapsulate functional scenarios that were originally managed by test cases into a common verification component to independently implement hierarchical management;

[0025] Among them, the feedback path one is composed of a virtual sequence, a virtual sequence arbitrator and a protocol manager. The virtual sequence is called by the test case written by the verification personnel, and the control functions including blocking control, flow control and conditional control are integrated internally (the control function is a known function, not designed by the present invention); the virtual sequence arbitrator integrates the real-time state of the current bus signal to provide the conditional variable for arbitration; the protocol manager records the transaction previously initiated by the virtual sequence, and integrates the conditional function (the conditional function is a known function, not designed by the present invention) to provide the conditional judgment for arbitration; the feedback path one will affect the validity and priority of the test case in the simulation timeline, and provide a new support method for the generation and control of incentives;

[0026] Among them, feedback path two is composed of a virtual sequence arbitrator, a transaction monitor and a protocol manager. The transaction monitor integrates a sampling function to provide real-time bus signals to assign values ​​to conditional variables in the virtual sequence arbitrator, and completes handshakes with requests in the protocol manager through configuration (the sampling function is a known function, not designed by the present invention), thereby affecting the conditional judgment logic in the feedback path one.

[0027] The UVM-based feedback control method specifically comprises the following steps:

[0028] Step 1, instantiate the universal verification component in the top layer of the verification platform, use the universal interface to bind with the interface module to be tested, use the UVM port to be connected with other verification components, and control the component configurator according to the register value of the module to be tested, complete the virtual sequence creation, and finally start the verification platform;

[0029] Step 2: The virtual sequence sends a protocol transaction packet with access request information to the sequence arbiter. The sequence arbiter queries the protocol manager entry and finds that it is not empty. It allocates a new entry and sends the protocol transaction packet to the transaction driver via the sequence generator. The transaction driver transmits a timing signal that complies with the bus protocol specification according to the working mode set by the current component configurator, and finally drives the interface module to be tested by the component interface.

[0030] Step 3: Subsequent consecutive access requests are created through the virtual sequence. The sequence arbiter queries the protocol manager and the entry is full, so no new entry can be allocated. It will block the protocol transaction packets generated by all subsequent access requests until the receiving port obtains the completion response delivered by the transaction monitor.

[0031] Step 4: The transaction monitor accesses the bus signal of the interface module to be tested in each clock cycle. When a transaction completion response is observed, the coverage collector is triggered to collect the functional coverage, and the response is sent to the sequence arbiter and other components of the verification platform through the UVM port. After the sequence arbiter receives the completion response, it releases the corresponding entry space and reprocesses the previously blocked access request;

[0032] Furthermore, in the step 1, the verification platform sets the component configurator in the verification component during the simulation initialization process;

[0033] Furthermore, in step 3, the virtual sequence arbiter queries the protocol manager before transmitting the protocol transaction packet, and allocates a free entry in the protocol manager according to the bus transaction ID number.

[0034] Furthermore, in step 4, the transaction monitor sends the sampled protocol transaction packet to the virtual sequence arbiter for completing the bus request handshake process;

[0035] The present invention has the following technical features:

[0036] 1. Compared with the traditional method of improving verification efficiency by building a verification platform and reusing it, the universal verification component of the present invention uses the bus protocol layer as the granularity, has a clearer hierarchical structure, and is more reusable. It can be flexibly reused in verification platforms that need to verify multiple bus protocols;

[0037] 2. The feedback control method proposed by the present invention based on the universal verification component separates the bus protocol control from the test case. The feedback control method implemented by the universal verification component does not require the intervention of the test case, and can automatically complete a whole set of bus protocol handshake behaviors. The verification personnel do not need to pay attention to the bus behavior and can complete the writing of the test case independently, which greatly improves the verification efficiency. At the same time, the virtual arbitrator provides functions for external access to provide users with the flexibility of customized scenario verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The structural diagram of the universal verification component of the present invention is

[0039] Figure 2 Flow chart of the feedback control method of the present invention

[0040] Figure 3 This is an example diagram of the reuse of the universal verification component of the present invention.

[0041] Figure 4 An extended schematic diagram of the universal verification component of the present invention DETAILED DESCRIPTION

[0042] The present invention provides a universal verification component based on UVM, such as Figure 1 As shown, the universal verification component is composed of multiple UVM components, and the UVM components include: protocol transaction package, transaction driver, sequencer, protocol agent, transaction monitor, coverage collector, component configurator, virtual sequence arbitrator, protocol manager, virtual sequence, component interface and component top layer. The UVM components are connected through instantiation and UVM ports to form a structural hierarchy relationship. The specific functions of each module are as follows:

[0043] The protocol transaction packet is derived from the uvm_sequence_item class, which is a class that encapsulates all information of the request flag, request preparation, request command, request address, request data and response flag, response preparation, and response data in the bus protocol, with a total of 5 input variables and 3 output variables, wherein the input variables are all random variables and can be randomized;

[0044] The transaction driver is derived from the uvm_driver class, obtains the protocol transaction package from the sequencer through the get_next_item() function, and can drive the interface module to be tested through the component interface in the run_phase() task according to the component configurator get() function according to a specific protocol mode;

[0045] The sequencer is derived from the uvm_sequencer class, and serves as a bridge between the sequence arbitrator and the transaction driver, passing the protocol transaction packet and the response return information through the start() function;

[0046] The protocol agent is derived from the uvm_agent class, instantiated and connected to the sequence initiator and the transaction driver through the connect() function, and passed the component configurator pointer;

[0047] The transaction monitor is derived from the uvm_monitor class, samples the protocol transaction packet through the component interface in the run_phase() task, and passes it to the coverage collector, the virtual sequence arbiter and other components in the verification platform through the analysis_port port;

[0048] The coverage collector is derived from the uvm_subscriber class, sets the function coverage group through the covergroup method, is triggered by the transaction monitor when the transaction is valid, and collects and performs function coverage statistics through the sample() function;

[0049] The component configurator is derived from the uvm_object class, controlled by the top level of the verification platform, and has built-in set() and get() functions for other component configurations to obtain internal variables;

[0050] The virtual sequence arbitration is derived from the uvm_virtual_sequencer class, which is the sequence sending and feedback control node of the general verification component, in which the protocol manager is instantiated, which has a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations inside the general verification component, and provides an access() function for the test case access of the verification platform;

[0051] The protocol manager is derived from the uvm_object class, is responsible for registering the transaction requests initiated by the general verification component and allocating corresponding entries, provides allocate() and release() functions for the virtual sequence arbiter to allocate and release entries, and also provides full and empty variables to indicate whether the protocol manager entries are empty or full;

[0052] The virtual sequence is derived from the uvm_sequence class, which is a window for the test case to send a transaction request, and has a built-in protocol transaction package for the test case to call to achieve the expected scenario;

[0053] The verification interface is of interface type, which is used to realize the communication between the general verification component and the bus module to be tested. The verification platform needs to implement the corresponding binding function, and the interaction data can be obtained through the pointer object;

[0054] The top level of the component is derived from the uvm_component class, which encapsulates all subcomponents of the general verification component, establishes the connection relationship between the internal components through the connect() function, and transmits the protocol transaction packets sampled by the transaction monitor to the verification platform through the analysis_export port;

[0055] Two feedback paths consisting of the protocol manager, virtual sequence arbitrator and transaction monitor are used to encapsulate the functional scenarios originally managed by test cases in the general verification component to independently realize hierarchical management;

[0056] Among them, the feedback path one is composed of a virtual sequence, a virtual sequence arbitrator and a protocol manager. The virtual sequence is called by the test case written by the verification personnel, and the control functions including blocking control, flow control and conditional control are integrated internally (the control function is a known function, not designed by the present invention); the virtual sequence arbitrator integrates the real-time state of the current bus signal to provide the conditional variable for arbitration; the protocol manager records the transaction previously initiated by the virtual sequence, and integrates the conditional function (the conditional function is a known function, not designed by the present invention) to provide the conditional judgment for arbitration; the feedback path one will affect the validity and priority of the test case in the simulation timeline, and provide a new support method for the generation and control of incentives;

[0057] Among them, feedback path two is composed of a virtual sequence arbitrator, a transaction monitor and a protocol manager. The transaction monitor integrates a sampling function to provide real-time bus signals to assign values ​​to conditional variables in the virtual sequence arbitrator, and completes handshakes with requests in the protocol manager through configuration (the sampling function is a known function, not designed by the present invention), thereby affecting the conditional judgment logic in the feedback path one.

[0058] According to an embodiment of the present invention, a feedback control method based on UVM is provided, such as Figure 2 As shown, the following steps are included:

[0059] Step 1, instantiate the universal verification component in the top layer of the verification platform, use the universal interface to bind with the interface module to be tested, use the UVM port to be connected with other verification components, and control the component configurator according to the register value of the module to be tested, complete the virtual sequence creation, and finally start the verification platform;

[0060] Step 2: The virtual sequence sends a protocol transaction packet with access request information to the sequence arbiter. The sequence arbiter queries the protocol manager entry and finds that it is not empty. It allocates a new entry and sends the protocol transaction packet to the transaction driver via the sequence generator. The transaction driver transmits a timing signal that complies with the bus protocol specification according to the working mode set by the current component configurator, and finally drives the interface module to be tested by the component interface.

[0061] Step 3: Multiple consecutive access requests are created through the virtual sequence. The sequence arbiter queries the protocol manager and the entry is full. No new entry can be allocated. All subsequent protocol transaction packets generated by access requests will be blocked until the receiving port obtains the completion response delivered by the transaction monitor.

[0062] Step 4: The transaction monitor accesses the bus signal of the interface module to be tested in each clock cycle. When a transaction completion response is observed, the coverage collector is triggered to collect the functional coverage, and the response is sent to the sequence arbiter and other components of the verification platform through the UVM port. After the sequence arbiter receives the completion response, it releases the corresponding entry space and reprocesses the previously blocked access request;

[0063] In this embodiment, the verification platform in step 1 sets the component configurator in the verification component during the simulation initialization process;

[0064] In this embodiment, the virtual sequence arbiter in step 3 queries the protocol manager before transmitting the protocol transaction packet, and allocates a free entry in the protocol manager according to the bus transaction ID number.

[0065] In this embodiment, the transaction monitor in step 4 sends the sampled protocol transaction packet to the virtual sequence arbiter to complete the bus request handshake process;

[0066] Figure 3 An example diagram of the reuse of the universal verification components of the present invention is given. Assuming that universal verification components for the ICB bus protocol, the SPI bus protocol, and the AXI bus protocol have been developed, due to the independence of component packaging, these three sets of universal verification components can be combined in pairs and used in the verification platform of six sets of bus bridge modules. This method reduces the overhead of repeated development of the verification platform;

[0067] Figure 4 An example diagram of the expansion of the universal verification component of the present invention is given. It is assumed that a universal verification component based on the AXI bus protocol has been developed. Because the project requires the universal verification component to be expanded to support the ACE bus protocol, and due to the similarity between the AXI protocol and the ACE protocol, the ACE protocol agent, ACE protocol manager, ACE transaction monitor and ACE virtual sequence can be expanded on the basis of the original universal verification component. This approach reduces the overhead of additional expansion of the verification component.

[0068] The present invention has the following technical features:

[0069] 1. Compared with the traditional method of improving verification efficiency by building a verification platform and reusing it, the universal verification component of the present invention uses the bus protocol layer as the granularity, has a clearer hierarchical structure, and is more reusable. It can be flexibly reused in verification platforms that need to verify multiple bus protocols;

[0070] 2. The feedback control method proposed based on the universal verification component of the present invention separates the bus protocol control from the test case. The feedback control method implemented by the universal verification component does not require the intervention of the test case, and can automatically complete a whole set of bus protocol handshake behaviors. The verification personnel can complete the writing of test cases independently without paying attention to the bus behavior, which greatly improves the verification efficiency. At the same time, the virtual arbitrator provides functions for external access to provide users with the flexibility of customized scenario verification.

Claims

1. A UVM-based universal verification component, characterized in that: include: A protocol transaction package, a transaction driver, a sequencer, a protocol agent, a transaction monitor, a coverage collector, a component configurator, a virtual sequence arbitrator, a protocol manager, a virtual sequence, a component interface, and a component top layer, wherein: The protocol transaction packet encapsulates the input signals and output signals that the bus module usually has, including five input variables and three output variables, the five input variables are request flag, request preparation, request command, request address and request data, and the three output variables are response flag, response preparation and response data; wherein the input variables are all random variables and can be randomized; The transaction driver obtains the protocol transaction packet through the sequencer, and can drive the interface module to be tested through the component interface according to a specific protocol mode set by the component configurator; The sequence generator acts as a bridge between the sequence arbitrator and the transaction driver, transmitting the protocol transaction packet and the response return information; The protocol agent instantiates the connection sequencer and the transaction driver, the pointer of the external parameter is passed via the component configurator, and the protocol agent represents a single bus protocol standard; The transaction monitor samples the protocol transaction packet through the component interface and transmits it to the coverage collector, the virtual sequence arbiter and other components in the verification platform through the UVM port; The coverage collector sets a functional coverage group, which is triggered by the transaction monitor when the transaction is valid, and collects and performs functional coverage statistics through sampling functions; The component configurator is controlled by the top layer of the verification platform and determines the drive sampling mode and feedback control path executed by the general verification component; The virtual sequence arbitrator is a sequence sending and feedback control node of the general verification component, in which the protocol manager is instantiated, which has a sequence generator pointer object and a transaction monitor receiving port, controls all sequence transmission, transaction registration and release operations inside the general verification component, and provides accessible variables and queues for use by test cases of the verification platform; The protocol manager is responsible for registering the transaction requests initiated by the general verification component and allocating corresponding entries. When the entry is full, all subsequent transaction requests are blocked. When a release signal from the bus is obtained through the virtual sequence arbiter, the request corresponding to the entry number is released to allow the allocation of new entries. The virtual sequence is a window for the test case to send a transaction request. A single test case can construct a functional scenario corresponding to the bus protocol according to multiple sets of virtual sequences provided by different general verification components; The component interface is used to realize the communication between the general verification component and the bus module to be tested. The verification platform needs to implement the corresponding binding function, and the interaction data can be obtained through the pointer object; The top level of the component encapsulates all subcomponents in the general verification component, is the minimum level for instantiation and reuse of the verification platform, and is managed by a higher level verification environment component.

2. A UVM-based universal verification component as claimed in claim 1, characterized in that, Two feedback paths consisting of a protocol manager, a virtual sequence arbitrator, and a transaction monitor are used to encapsulate functional scenarios that were originally managed by test cases into a common verification component to independently implement hierarchical management; Among them, the feedback path 1 is composed of a virtual sequence, a virtual sequence arbitrator and a protocol manager. The virtual sequence is called by the test case written by the verification personnel, and the control functions including blocking control, flow control and conditional control are integrated internally; the virtual sequence arbitrator integrates the real-time status of the current bus signal to provide the conditional variables for arbitration; the protocol manager records the transactions previously initiated by the virtual sequence and integrates the conditional function to provide the conditional judgment for arbitration; the feedback path 1 will affect the validity and priority of the test case in the simulation timeline, and provide a new support method for the generation and control of incentives; Among them, feedback path two is composed of a virtual sequence arbitrator, a transaction monitor and a protocol manager. The transaction monitor integrates a sampling function, provides real-time bus signals to assign values ​​to conditional variables in the virtual sequence arbitrator, and completes handshakes with requests in the protocol manager through configuration, thereby affecting the conditional judgment logic in the feedback path one.

3. A feedback control method for the UVM of the universal verification component based on UVM as claimed in claim 1, characterized in that, The following steps are involved: Step 1, instantiate the universal verification component in the top layer of the verification platform, use the component interface to bind with the interface module to be tested, use the UVM port to be connected with other verification components, and control the component configurator according to the register value of the module to be tested, complete the virtual sequence creation, and finally start the verification platform; Step 2, the virtual sequence sends a protocol transaction packet with access request information to the virtual sequence arbiter. The virtual sequence arbiter queries the protocol manager entry and finds that it is not empty. It allocates a new entry and sends the protocol transaction packet to the transaction driver via the sequence generator. The transaction driver transmits a timing signal that complies with the bus protocol specification according to the working mode set by the current component configurator, and finally drives the interface module to be tested by the component interface. Step 3: Subsequent consecutive access requests are created through the virtual sequence. The virtual sequence arbiter queries the protocol manager and the entries are full, so no new entries can be allocated. The protocol transaction packets generated by all subsequent access requests are blocked until the receiving port obtains the completion response delivered by the transaction monitor. Step 4: The transaction monitor obtains the bus signal of the interface module under test in each clock cycle. When a transaction completion response is observed, the coverage collector is triggered to collect functional coverage. At the same time, the response is sent to the virtual sequence arbiter and other components of the verification platform through the UVM port. After receiving the completion response, the virtual sequence arbiter releases the corresponding entry space and reprocesses the previously blocked access request.

4. The feedback control method of UVM as claimed in claim 3, characterized in that, In step 1, the verification platform sets the component configurator in the verification component during the simulation initialization process.

5. The feedback control method of UVM as claimed in claim 3, characterized in that, In step 3, the virtual sequence arbiter queries the protocol manager before transmitting the protocol transaction packet, and allocates a free entry in the protocol manager according to the bus transaction ID number.

6. The feedback control method of UVM as claimed in claim 3, characterized in that, In step 4, the transaction monitor sends the sampled protocol transaction packet to the virtual sequence arbiter to complete the bus request handshake process.

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