Pixel and light-emitting display device including the same

Abstract

A pixel and a light-emitting display device including the pixel are provided. The pixel includes: a light-emitting diode including an anode electrode and a cathode electrode; a driving transistor including an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node; a switching transistor that applies a data signal to the first node in response to a scan signal in a second period; a first initialization transistor that applies a first initialization voltage to the second node in response to an initialization control signal in the first period; and a second initialization transistor that applies a second initialization voltage having a voltage level different from the first initialization voltage to the anode electrode in response to the initialization control signal in the first period. The first initialization transistor and the second initialization transistor are configured to be turned on substantially simultaneously in the first period.

Description

[0001] This application is a divisional application of application No. 201910035672.9, entitled “Pixel and organic light-emitting display device including the pixel”, filed with the State Intellectual Property Office of China on January 15, 2019. Technical Field

[0002] One or more exemplary embodiments relate generally to a display device, and more particularly, to a pixel and an organic light emitting display device including the pixel. Background Art

[0003] Typically, an organic light-emitting display device includes multiple pixels. Each pixel typically includes an organic light-emitting diode (OLED) and a circuit unit that controls the OLED. The circuit unit may include at least a switching transistor, a drive transistor, and a storage capacitor. The OLED includes an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode and cathode electrodes. When a voltage higher than the threshold voltage of the organic light-emitting layer is applied between the anode and cathode electrodes, the OLED emits light.

[0004] The above information disclosed in this section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0005] Some exemplary embodiments provide a pixel capable of improving display quality of a display device.

[0006] Some exemplary embodiments provide a display device including pixels capable of improving display quality of the display device.

[0007] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

[0008] According to some exemplary embodiments, a pixel includes: a light emitting diode including an anode electrode and a cathode electrode, the cathode electrode being configured to receive a second driving voltage; a driving transistor including an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node; a switching transistor configured to apply a data signal to the first node in response to a scan signal received in a second period; a first initialization transistor configured to apply a first initialization voltage to the second node in response to an initialization control signal received in a first period; and a second initialization transistor configured to apply a second initialization voltage having a voltage level different from the first initialization voltage to the anode electrode in response to an initialization control signal received in the first period, wherein the first initialization transistor and the second initialization transistor are configured to be simultaneously turned on in the first period, the second driving voltage has a voltage level lower than the second initialization voltage, and a potential difference between the second driving voltage and the second initialization voltage is smaller than a threshold voltage of the light emitting diode.

[0009] According to some exemplary embodiments, a pixel includes an organic light-emitting diode, a driving transistor, a switching transistor, a first initialization transistor, a second initialization transistor, and a conduction bias transistor. The organic light-emitting diode includes an anode electrode and a cathode electrode. The driving transistor includes an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node. The switching transistor is configured to apply a data signal to the first node in response to a scan signal received during a second period. The first initialization transistor is configured to apply a first initialization voltage to the second node in response to an initialization control signal received during a first period. The second initialization transistor is configured to apply a second initialization voltage to the anode electrode in response to an initialization control signal received during a first period, the second initialization voltage having a voltage level different from the first initialization voltage. The conduction bias transistor is configured to apply a first drive voltage to the first node in response to an on-bias control signal received during a first period.

[0010] In some exemplary embodiments, the first initialization transistor may include: a control electrode configured to receive an initialization control signal in a first time period; an input electrode configured to receive a first initialization voltage; and an output electrode connected to the second node, and the second initialization transistor may include: a control electrode configured to receive an initialization control signal in a first time period; an input electrode configured to receive a second initialization voltage; and an output electrode connected to the anode electrode.

[0011] In some exemplary embodiments, the second initialization voltage may have a lower voltage level than the first initialization voltage.

[0012] In some exemplary embodiments, the cathode electrode of the organic light emitting diode may be configured to receive a second driving voltage, and the second driving voltage may have a voltage level lower than the second initialization voltage.

[0013] In some exemplary embodiments, the second driving voltage may be in a range of approximately -9 volts to approximately -11 volts.

[0014] In some exemplary embodiments, a potential difference between the second driving voltage and the second initialization voltage may be less than a threshold voltage of the organic light emitting diode.

[0015] In some exemplary embodiments, the potential difference may be in a range of approximately 0.5 volts to approximately 0.6 volts.

[0016] In some exemplary embodiments, the switching transistor may include a control electrode configured to receive a scan signal in the second period, an input electrode configured to receive a data signal, and an output electrode connected to the first node.

[0017] In some exemplary embodiments, the on-bias transistor may include: a control electrode configured to receive an on-bias control signal in a first period; an input electrode configured to receive a first driving voltage; and an output electrode connected to the first node.

[0018] In some example embodiments, in the first period, the initialization control signal and the on-bias control signal may be configured to turn on the first initialization transistor and the on-bias transistor simultaneously.

[0019] In some exemplary embodiments, the first initialization voltage may have a voltage level lower than a threshold voltage of the driving transistor.

[0020] In some exemplary embodiments, the pixel may further include a first control transistor, the first control transistor including: a control electrode configured to receive a scan signal; an input electrode connected to the second node; and an output electrode connected to the output electrode of the driving transistor, wherein the first control transistor is turned on in response to the scan signal received in the second period.

[0021] In some exemplary embodiments, the pixel may further include a second control transistor and a third control transistor, the second control transistor including: a control electrode configured to receive a light-emitting control signal; an input electrode connected to a third node; and an output electrode connected to an anode electrode of the organic light-emitting diode, wherein the second control transistor is configured to be turned on in response to the light-emitting control signal received in a light-emitting stage, and the third control transistor includes: a control electrode configured to receive a light-emitting control signal; an input electrode configured to receive a first driving voltage; and an output electrode connected to the first node.

[0022] In some exemplary embodiments, the pixel may further include a storage capacitor connected between the second node and a node configured to receive the first driving voltage.

[0023] In some exemplary embodiments, the pixel may further include a first auxiliary electrode facing the control electrode of the driving transistor, and the first auxiliary electrode may be configured to receive the first driving voltage.

[0024] In some exemplary embodiments, the first auxiliary electrode may also face the input electrode of the driving transistor.

[0025] According to some exemplary embodiments, a pixel includes an organic light-emitting diode, a driving transistor, a switching transistor, a first initialization transistor, a second initialization transistor, and a conduction bias transistor. The organic light-emitting diode includes an anode electrode and a cathode electrode. The driving transistor includes an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node. The switching transistor is configured to apply a data signal to the first node in response to a scan signal received during a second period. The first initialization transistor is configured to apply a first initialization voltage to the second node in response to a first initialization control signal received during a first period. The second initialization transistor is configured to apply a second initialization voltage to the anode electrode in response to a second initialization control signal received, the second initialization voltage having a voltage level different from the first initialization voltage. The conduction bias transistor is configured to apply a first drive voltage to the first node in response to a conduction bias control signal received during a first period.

[0026] In some example embodiments, the first initialization control signal may be configured to turn on the first initialization transistor in a first period, and the second initialization control signal may be configured to turn on the second initialization transistor in a second period.

[0027] In some example embodiments, during the first period, the first initialization control signal and the on-bias control signal may be configured to respectively turn on the first initialization transistor and the on-bias transistor substantially simultaneously.

[0028] According to some exemplary embodiments, an organic light-emitting display device includes a scan driver, a data driver, pixels, and an initialization voltage generator. The scan driver is configured to apply scan signals to scan lines extending in a first direction and arranged in a second direction intersecting the first direction. The data driver is configured to apply data signals to data lines insulated from the scan lines. At least one of the pixels includes an organic light-emitting diode (OLED) having an anode electrode and a cathode electrode, and a circuit configured to control the light-emitting operation of the OLED. The initialization voltage generator is configured to generate a first initialization voltage and a second initialization voltage, and apply the first and second initialization voltages to the at least one pixel. The circuit includes a drive transistor, a switching transistor, a first initialization transistor, a second initialization transistor, and a conduction bias transistor. The drive transistor includes an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node. The switching transistor is configured to apply a data signal from among the data signals to the first node in response to a scan signal from among the scan signals received during a second period. The first initialization transistor is configured to apply the first initialization voltage to the second node in response to an initialization control signal received during a first period. The second initialization transistor is configured to apply a second initialization voltage to the anode electrode in response to an initialization control signal received in the first period, the second initialization voltage having a voltage level different from the first initialization voltage. The on-bias transistor is configured to apply a first drive voltage to the first node in response to an on-bias control signal received in the first period.

[0029] According to some exemplary embodiments, during an initialization period preceding the light-emitting period, a first drive voltage may be applied to the input electrode of the drive transistor, thereby applying a constant on-bias voltage between the control electrode and the input electrode of the drive transistor. Consequently, degradation of display quality, which typically occurs when the potential difference between the control electrode and the input electrode of the drive transistor increases above a certain level, can be prevented. Furthermore, a second initialization voltage, different from the first initialization voltage, may be applied to the anode electrode of the organic light-emitting diode so that the second initialization voltage has a constant potential difference relative to the second drive voltage. Consequently, degradation of black grayscale characteristics can be prevented, and color bleed defects can be reduced.

[0030] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0032] Figure 1 is a block diagram illustrating an organic light emitting display device according to some exemplary embodiments.

[0033] Figure 2 is a diagram showing a method according to some exemplary embodiments Figure 1 FIG. 5 is a diagram showing the potentials of the first initialization voltage and the second initialization voltage.

[0034] Figure 3 is an equivalent circuit diagram of a pixel according to some example embodiments.

[0035] Figure 4 FIG. 1 is a diagram showing a method for driving a Figure 3 Waveform diagram of the pixel driving signal.

[0036] Figure 5 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG1 is an equivalent circuit diagram of the operation of a pixel during a first period.

[0037] Figure 6 is a diagram showing the Figure 5 1 is a waveform diagram of the waveform of the driving signal during the first period.

[0038] Figure 7 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the second period.

[0039] Figure 8 is a diagram showing the Figure 7 1 is a waveform diagram of the waveform of the driving signal during the second period of FIG.

[0040] Figure 9 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the third period.

[0041] Figure 10 is a diagram showing the Figure 9 3 is a waveform diagram of the waveform of the driving signal during the third period of time.

[0042] Figure 11 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG1 is an equivalent circuit diagram of the operation of a pixel during a first period.

[0043] Figure 12 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the second period.

[0044] Figure 13 is an equivalent circuit diagram of a pixel according to some example embodiments.

[0045] Figure 14 According to some exemplary embodiments Figure 13 The pixels include at least Figure 13 A cross-sectional view of part "I" in FIG.

[0046] Figure 15 is an equivalent circuit diagram illustrating a pixel according to some exemplary embodiments.

[0047] Figure 16 According to some exemplary embodiments Figure 15 The pixels include at least Figure 15 A cross-sectional view of part "II" in FIG. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or in the presence of one or more equivalent arrangements. In other cases, in order to avoid making the various exemplary embodiments unnecessarily obscure, well-known structures and devices are shown in block diagram form. In addition, the various exemplary embodiments may be different, but not necessarily mutually exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0049] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of different details of some exemplary embodiments. Therefore, unless otherwise specified, the various exemplified features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter, individually or collectively referred to as "elements") may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0050] In the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0051] When an element is referred to as being "on" another element, "connected to" or "bound to" another element, the element may be directly on the other element, directly connected to or directly bound to the other element, or there may be an intermediate element. However, when an element is referred to as being "directly on" another element, "directly connected to" or "directly bound to" another element, there is no intermediate element. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." and "directly between...", "adjacent to..." and "directly adjacent to...", "on..." and "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection and / or fluid connection. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two of X, Y and Z or more of them, such as, for example, XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be named the second element without departing from the disclosed teachings.

[0053] For descriptive purposes, spatially relative terms such as "under," "beneath," "under," "down," "over," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "under" or "beneath" other elements or features would then be positioned "over" the other elements or features. Thus, the exemplary term "under" can include both the orientations of "above" and "under." Furthermore, the device can be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0054] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their groups are used in this manual, the description indicates the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, so that they are used to explain the inherent deviations of the measured values, calculated values and / or values provided that will be recognized by those of ordinary skill in the art.

[0055] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic representations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the drawings due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of regions, but are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of the device, and as such, are not intended to be limiting.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Unless expressly defined as such herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0057] According to the practice in the art, some exemplary embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules, which may also be referred to as controllers, drivers, generators, etc. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc.), and these blocks, units and / or modules can be formed using semiconductor-based manufacturing technology or other manufacturing technology. For blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions. In addition, without departing from the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. In addition, without departing from the inventive concept, the blocks, units and / or modules of some exemplary embodiments can be physically combined into more complex blocks, units and / or modules.

[0058] Figure 1 is a block diagram illustrating an organic light emitting display device according to some exemplary embodiments. Figure 2 is a diagram showing a method according to some exemplary embodiments Figure 1 FIG. 5 is a diagram showing the potentials of the first initialization voltage and the second initialization voltage.

[0059] Reference Figure 1 , the organic light emitting display device includes a signal controller 100, a scan driver 200, a data driver 300, a driving voltage generator 400, an initialization voltage generator 500, and a display panel unit DP.

[0060] The signal controller 100 receives an input image signal (not shown) and converts the data format of the input image signal into a data format suitable for the interface between the signal controller 100 and the data driver 300 to generate image data RGB. The signal controller 100 outputs the image data RGB and various control signals DCS, SCS, and VCS.

[0061] The scan driver 200 receives a scan control signal SCS from the signal controller 100. The scan control signal SCS includes a vertical start signal that initiates the operation of the scan driver 200 and a clock signal that determines the output timing of the signals. The scan driver 200 generates a plurality of scan signals and sequentially outputs the scan signals to a plurality of scan lines SL1 to SLn, which will be described later. Furthermore, the scan driver 200 generates a plurality of light emission control signals in response to the scan control signal SCS and outputs the light emission control signals to a plurality of light emission lines EL1 to ELn, which will be described later.

[0062] exist Figure 1 In the embodiment, the scan signal and the light emission control signal are output from one scan driver 200, but the inventive concept is not limited thereto or thereby. For example, a plurality of scan drivers may be divided and output the scan signal, and other scan drivers may be divided and output the light emission control signal. According to some exemplary embodiments, the drive circuit that generates and outputs the scan signal and the drive circuit that generates and outputs the light emission control signal may be implemented separately from each other.

[0063] The data driver 300 receives a data control signal DCS and image data RGB from the signal controller 100. The data driver 300 converts the image data RGB into data signals and outputs the data signals to a plurality of data lines DL1 to DLm. The data signals correspond to analog voltages corresponding to grayscales of the image data RGB, respectively.

[0064] The driving voltage generator 400 receives a power voltage Vin from a power source (not shown). The driving voltage generator 400 converts the power voltage Vin to generate a first driving voltage ELVDD and a second driving voltage ELVSS having a lower level than the first driving voltage ELVDD.

[0065] The driving voltage generator 400 may include a DC to DC converter. The driving voltage generator 400 may include a boost converter that boosts the power supply voltage Vin to generate the first driving voltage ELVDD. In addition, the driving voltage generator 400 may include a buck converter that steps down the power supply voltage Vin to generate the second driving voltage ELVSS.

[0066] The driving voltage generator 400 receives the driving voltage control signal VCS from the signal controller 100. The driving voltage generator 400 generates the first driving voltage ELVDD having a determined level in response to the driving voltage control signal VCS. Figure 2As shown in , the first driving voltage ELVDD may be a positive voltage having a positive polarity with respect to 0 V, for example, a voltage in the range of about 4 V to about 5 V. For example, the first driving voltage ELVDD may have a voltage level of about 4.6 V.

[0067] The driving voltage generator 400 may generate a second driving voltage ELVSS having a certain voltage range in response to the driving voltage control signal VCS. The second driving voltage ELVSS may be a negative voltage, for example, a voltage in a range of approximately -9 volts to approximately -11 volts. For example, the second driving voltage ELVSS may have a voltage level of approximately -10 volts.

[0068] Refer again Figure 1 The initialization voltage generator 500 receives the first driving voltage ELVDD and the second driving voltage ELVSS from the driving voltage generator 400. The initialization voltage generator 500 generates the first initialization voltage Vint1 and the second initialization voltage Vint2 using the first driving voltage ELVDD and the second driving voltage ELVSS. The first initialization voltage Vint1 and the second initialization voltage Vint2 have different voltage levels from each other.

[0069] like Figure 2 As shown in FIG, the second initialization voltage Vint2 has a voltage level lower than the voltage level of the first initialization voltage Vint1. The second initialization voltage Vint2 has a constant potential difference Vd with respect to the second driving voltage ELVSS. As an example, the second initialization voltage Vint2 and the second driving voltage ELVSS maintain a potential difference Vd of approximately 0.5 volts to approximately 0.6 volts. As an example, when the second driving voltage ELVSS is in a range of approximately -9 volts to approximately -11 volts, the second initialization voltage Vint2 may be in a range of approximately -8.4 volts to approximately -10.5 volts. According to some exemplary embodiments, when the second driving voltage ELVSS has a voltage level of approximately -10 volts, the second initialization voltage Vint2 has a voltage level of approximately -9.5 volts.

[0070] The first initialization voltage Vint1 has a negative voltage and has a voltage level higher than the voltage level of the second initialization voltage Vint2. The first initialization voltage Vint1 can be set to a voltage level lower than the threshold voltage of the first transistor T1. As an example, the first initialization voltage Vint1 can be approximately -4.5 volts.

[0071] Refer again Figure 1The display panel unit DP includes scan lines SL1 to SLn, emission lines EL1 to ELn, data lines DL1 to DLm, and pixels PX. The scan lines SL1 to SLn extend in a first direction DR1 and are arranged in a second direction DR2 substantially perpendicular to the first direction DR1. Each emission line EL1 to ELn is arranged substantially parallel to a corresponding scan line among the scan lines SL1 to SLn. The data lines DL1 to DLm are insulated from the scan lines SL1 to SLn and intersect with the scan lines SL1 to SLn.

[0072] Each pixel PX is connected to a corresponding scan line among the scan lines SL1 to SLn, a corresponding light emitting line among the light emitting lines EL1 to ELn, and a corresponding data line among the data lines DL1 to DLm. Figure 1 Although schematically shown in FIG, each pixel PX may be connected to a plurality of scan lines among the scan lines SL1 to SLn. Figure 3 and 4 The structure is described in detail.

[0073] Each pixel PX includes an organic light-emitting diode (not shown) and a circuit (not shown) that controls light emission from the organic light-emitting diode. The circuit includes a plurality of thin-film transistors and a storage capacitor; however, exemplary embodiments are not limited thereto or thereby. The pixel PX includes a red pixel that emits red light, a green pixel that emits green light, and a blue pixel that emits blue light. The organic light-emitting diodes of the red pixels, the green pixels, and the blue pixels may include organic light-emitting layers formed of different materials.

[0074] Scan lines SL1 to SLn, emission lines EL1 to ELn, data lines DL1 to DLm, and pixels PX may be formed on a base substrate (not shown) through multiple photolithography processes and multiple deposition processes. Furthermore, a sealing layer (not shown) may be formed on the base substrate to protect the pixels PX.

[0075] The display panel unit DP receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD is applied to the pixel PX through the first voltage line PL1. The second driving voltage ELVSS is applied to the pixel PX through electrodes (not shown) formed on the display panel unit DP and power lines (not shown).

[0076] The display panel unit DP receives a first initialization voltage Vint1 and a second initialization voltage Vint2. The first initialization voltage Vint1 is applied to the pixel PX through the first initialization voltage line VIL1. The second initialization voltage Vint2 is applied to the pixel PX through the second initialization voltage line VIL2.

[0077] Figure 3 is an equivalent circuit diagram of a pixel according to some example embodiments. Figure 4 FIG. 1 is a diagram showing a method for driving a Figure 3 Waveform diagram of the pixel driving signal.

[0078] Figure 3 The scanning lines SL1 to SLn (see Figure 1 ) among the i-th scanning line (not shown), the light emitting lines EL1 to ELn (refer to Figure 1 ) among the i-th light emitting line (not shown) and the data lines DL1 to DLm (refer to Figure 1 ) is an equivalent circuit diagram of a pixel PXij of the j-th data line (not shown). Figure 1 Each pixel PX shown in FIG may have Figure 3 The circuit configuration of the equivalent circuit diagram of the pixel PXij shown in FIG. 1 is substantially the same as the circuit configuration; however, exemplary embodiments are not limited thereto or thereby.

[0079] The pixel PXij includes an organic light emitting diode ED and a circuit CP for controlling the organic light emitting diode ED. In some exemplary embodiments, the circuit CP includes eight transistors T1 to T8 and a storage capacitor Cst. In addition, each of the eight transistors T1 to T8 is a p-type transistor, but the configuration of the pixel is not limited to Figure 3 The structure shown in . Figure 3 The circuit CP shown in corresponds to only one example, and the configuration of the circuit CP may be modified.

[0080] Reference Figure 3 Circuit CP includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The first transistor T1 includes an input electrode connected to a first node N1, a control electrode connected to a second node N2, and an output electrode connected to a third node N3. The second transistor T2 is connected between the j-th data line and the first transistor T1, and the third transistor T3 is connected between the second node N2 and the third node N3. The fourth transistor T4 is connected between the third node N3 and the anode electrode of the organic light emitting diode ED. The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to a first voltage node VN1 to which the first driving voltage ELVDD is applied.

[0081] The fifth transistor T5 is connected between the first node N1 and the first voltage node VN1. The sixth transistor T6 is connected between the second node N2 and the first initialization node IN1 to which the first initialization voltage Vint1 is applied. The seventh transistor T7 is connected between the anode electrode of the organic light emitting diode ED and the second initialization node IN2 to which the second initialization voltage Vint2 is applied. The eighth transistor T8 is connected between the first voltage node VN1 and the first node N1.

[0082] More specifically, the first transistor T1 includes an input electrode connected to a first node N1 that receives a first drive voltage ELVDD via a fifth transistor T5; a control electrode connected to a second node N2; and an output electrode connected to a third node N3. The output electrode of the first transistor T1 applies the first drive voltage ELVDD to the anode electrode of the organic light emitting diode ED via a fourth transistor T4. The first transistor T1 controls the drive current applied to the organic light emitting diode ED in response to the potential of the second node N2. The first transistor T1 may be referred to as a "drive transistor."

[0083] The second transistor T2 includes an input electrode connected to the j-th data line; a control electrode connected to the i-th scan line; and an output electrode connected to the first node N1, thereby connecting to the input electrode of the first transistor T1. The second transistor T2 is turned on by the scan signal GSi applied to the i-th scan line and provides the data signal DSj applied to the j-th data line to the first node N1. The second transistor T2 can be referred to as a "switching transistor."

[0084] The third transistor T3 includes an input electrode connected to a third node N3, thereby connecting to the output electrode of the first transistor T1; a control electrode connected to the i-th scan line; and an output electrode connected to the second node N2. The third transistor T3 is turned on in response to a scan signal GSi applied to the i-th scan line. The third transistor T3 can be referred to as a "first control transistor." When the third transistor T3 is turned on, the first transistor T1 is connected in a diode configuration via the turned-on third transistor T3.

[0085] The fourth transistor T4 includes an input electrode connected to the third node N3, a control electrode connected to the i-th emission line, and an output electrode connected to the anode electrode of the organic light emitting diode ED. The fifth transistor T5 includes an input electrode connected to the first voltage node VN1, a control electrode connected to the i-th emission line, and an output electrode connected to the first node N1.

[0086] The fourth transistor T4 and the fifth transistor T5 are turned on or off in response to an emission control signal ESi provided via the i-th emission line. The operation of the fourth transistor T4 and the fifth transistor T5 establishes or blocks a current path between the first voltage node VN1 and the organic light-emitting diode ED. The fourth transistor T4 and the fifth transistor T5 may be referred to as a "second control transistor" and a "third control transistor," respectively. In some exemplary embodiments, the fifth transistor T5 may be omitted, and the input electrode of the first transistor T1 may be directly connected to the first voltage node VN1.

[0087] The sixth transistor T6 includes: an input electrode that receives a first initialization voltage Vint1; a control electrode that receives an initialization control signal; and an output electrode that is connected to the second node N2, thereby connecting to the control electrode of the first transistor T1. The sixth transistor T6 is turned on in response to the initialization control signal and provides the first initialization voltage Vint1 to the second node N2. In some exemplary embodiments, the initialization control signal may be the (i-1)th scan signal GS(i-1) of the (i-1)th scan line. For ease of description, the initialization control signal will be referred to as the initialization control signal GS(i-1) hereinafter. The second node N2 is initialized by the first initialization voltage Vint1. In this case, the sixth transistor T6 may be referred to as the "first initialization transistor."

[0088] The seventh transistor T7 includes an input electrode receiving a second initialization voltage Vint2; a control electrode receiving an initialization control signal GS(i-1); and an output electrode connected to the anode electrode of the organic light-emitting diode ED. The seventh transistor T7 is turned on in response to the initialization control signal GS(i-1) and supplies the second initialization voltage Vint2 to the anode electrode of the organic light-emitting diode ED. As a result, the anode electrode of the organic light-emitting diode ED is initialized by the second initialization voltage Vint2. That is, the anode electrode of the organic light-emitting diode ED is discharged to the second initialization voltage Vint2. The second initialization voltage Vint2 has a constant potential difference Vd relative to the second driving voltage ELVSS. The potential difference Vd between the second driving voltage ELVSS and the second initialization voltage Vint2 may be less than the threshold voltage of the organic light-emitting diode ED. The second initialization voltage Vint2 is determined by the voltage level of the second driving voltage ELVSS. The seventh transistor T7 may be referred to as a "second initialization transistor."

[0089] Although the configuration in which the sixth and seventh transistors T6 and T7 are substantially simultaneously turned on by the initialization control signal GS(i-1) has been described, exemplary embodiments are not limited thereto or thereby. For example, the sixth and seventh transistors T6 and T7 may be turned on at different periods.

[0090] The eighth transistor T8 includes an input electrode connected to the first voltage node VN1 to receive the first driving voltage ELVDD; a control electrode receiving an on-bias control signal; and an output electrode connected to the first node N1. The eighth transistor T8 is turned on in response to the on-bias control signal to apply the first driving voltage ELVDD to the first node N1. The eighth transistor T8 can be referred to as an "on-bias transistor."

[0091] According to some exemplary embodiments, the conduction bias control signal may be a scan signal GS(i-1) applied to the (i-1)th scan line. Therefore, the conduction bias control signal GS(i-1) may be a signal substantially identical to the initialization control signal GS(i-1). Therefore, the eighth transistor T8 may be turned on substantially simultaneously with the sixth transistor T6 and the seventh transistor T7. For example, the eighth transistor T8 is turned on during the initialization period in which the second node N2 is initialized to the first initialization voltage Vint1 by the sixth transistor T6, and therefore, the first drive voltage ELVDD may be applied to the first node N1. As an example, when the first initialization voltage Vint1 is approximately -4.5 volts and the first drive voltage ELVDD is approximately 4.6 volts (referring to Figure 2 ), during the initialization period, a potential of approximately 9.1 volts is formed between the input electrode and the control electrode of the first transistor T1. That is, since the potential of the first node N1 is reset to the first drive voltage ELVDD by the eighth transistor T8 during the initialization period, a constant on-bias voltage can be applied between the input electrode and the control electrode of the first transistor T1. Therefore, it is possible to prevent degradation of display quality caused by the potential difference between the control electrode and the input electrode of the first transistor T1 increasing to a certain level or more due to hysteresis.

[0092] The storage capacitor Cst is connected between the second node N2 and the first voltage node VN1 and is charged with a voltage corresponding to a voltage difference between the first driving voltage ELVDD and a voltage applied to the second node N2 .

[0093] Reference Figure 4 , the organic light emitting display device displays a unit image in each of the frame periods F(k-1), Fk, and F(k+1). Figure 1 Each pixel PX shown in FIG. 1 receives a corresponding data signal in each of the frame periods F(k−1), Fk, and F(k+1). Figure 4 Shown Figure 3Frame periods F(k-1), Fk and F(k+1) of the pixel PXij shown in FIG. Hereinafter, the driving signal for driving the pixel PX will be described focusing on the k-th frame period Fk. The k-th frame period Fk includes a scanning period Sk and a light emitting period Ek.

[0094] The initialization control signal GS(i-1) is activated in the scanning period Sk. In some exemplary embodiments, Figure 4 The signal shown in is activated at a low level. Figure 4 The low level of the signal shown in may be an on-voltage of a transistor to which the signal is applied.

[0095] The second node N2 is initialized to the first initialization voltage Vint1 by the initialization control signal GS(i-1). The initialization control signal GS(i-1) may be applied to the scan lines SL1 to SLn (refer to Figure 1 ). For example, the initialization control signal GS(i-1) may be the (i-1)th scan signal GS(i-1) applied to the (i-1)th scan line immediately preceding the i-th scan line. Furthermore, the anode electrode of the organic light emitting diode ED is initialized to the second initialization voltage Vint2 by the initialization control signal GS(i-1).

[0096] The characteristics of the black grayscale of the pixel and the degree of the color diffusion defect in the pixel may vary according to the second initialization voltage Vint2 applied to the anode electrode of the organic light emitting diode ED. That is, when the second initialization voltage Vint2 is set to exceed a constant potential difference Vd (refer to Figure 2 ) range (for example, exceeding the range of about 0.5 volts to about 0.6 volts), the characteristics of the black grayscale deteriorate and a color diffusion defect occurs. Therefore, the second initialization voltage Vint2 should be appropriately controlled according to the voltage level of the second driving voltage ELVSS.

[0097] The i-th scan signal GSi applied to the i-th scan line is activated during the scan period Sk. The second transistor T2 is turned on by the i-th scan signal GSi, and the data signal DSj applied to the j-th data line is applied to the first node N1. Then, during the light emission period Ek, a current path is formed between the first node N1 and the organic light emitting diode ED by the light emission control signal ESi. The light emission control signal ESi is low during the light emission period Ek. Therefore, the organic light emitting diode ED emits light during the light emission period Ek. The light emission control signal ESi is not activated during the scan period Sk. That is, the light emission control signal ESi is high during the scan period Sk.

[0098] Will refer to Figures 5 to 12 The operation of the pixel PXij is described in more detail.

[0099] Figure 5 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG1 is an equivalent circuit diagram of the operation of a pixel during a first period. Figure 6 is a diagram showing the Figure 5 1 is a waveform diagram of the waveform of the driving signal during the first period.

[0100] Reference Figure 5 and Figure 6 , the initialization control signal GS(i-1) activated in the first period 1H is applied to the sixth transistor T6. Therefore, the sixth transistor T6 is turned on, and the first initialization voltage Vint1 is applied to the second node N2 through the turned-on sixth transistor T6. The first initialization voltage Vint1 can be set to a voltage low enough to initialize the second node N2, for example, a voltage lower than the threshold voltage of the first transistor T1 than the data signal with the highest grayscale.

[0101] The initialization control signal GS(i-1) activated during the first period 1H is applied to the seventh transistor T7. Therefore, the seventh transistor T7 is turned on, and the second initialization voltage Vint2 is applied to the anode electrode of the organic light emitting diode ED through the turned-on seventh transistor T7. The second initialization voltage Vint2 can be set to a voltage having a constant potential difference Vd relative to the second driving voltage ELVSS. As an example, the potential difference Vd between the second initialization voltage Vint2 and the second driving voltage ELVSS (refer to Figure 2 ) may be maintained in a range of about 0.5 volts to about 0.6 volts. In some exemplary embodiments, when the second driving voltage ELVSS has a voltage level of about -10 volts, the second initialization voltage Vint2 may have a voltage level of about -9.5 volts.

[0102] During the first period 1H, the anode electrode of the organic light emitting diode ED is initialized to the second initialization voltage Vint2, and the second node N2 is initialized to the first initialization voltage Vint1. Therefore, during the first period 1H, the anode electrode of the organic light emitting diode ED and the second node N2 may have different potentials from each other.

[0103] During the first period 1H, the activated on-bias control signal GS(i-1) is applied to the eighth transistor T8. Thus, the eighth transistor T8 is turned on, and the first driving voltage ELVDD is applied to the first node N1 through the turned-on eighth transistor T8.

[0104] In some exemplary embodiments, the initialization control signal GS(i-1) and the conduction bias control signal GS(i-1) may be the scan signal GS(i-1) applied to the (i-1)th scan line. Therefore, during the first period 1H, the initialization control signal GS(i-1) and the conduction bias control signal GS(i-1) are activated substantially simultaneously. Therefore, the eighth transistor T8 may be turned on substantially simultaneously with the sixth transistor T6 and the seventh transistor T7. Due to the turned-on sixth transistor T6 and the eighth transistor T8, the second node N2 is initialized to the first initialization voltage Vint1 during the first period 1H, and the first drive voltage ELVDD is applied to the first node N1 during the first period 1H. Therefore, a potential difference corresponding to the difference between the first initialization voltage Vint1 and the first drive voltage ELVDD is formed between the input electrode and the control electrode of the first transistor T1. As an example, when the first initialization voltage Vint1 is approximately -4.5 volts and the first drive voltage ELVDD is approximately 4.6 volts (refer to Figure 2 ), a potential difference of approximately 9.1 volts is formed between the input electrode and the control electrode of the first transistor T1.

[0105] As described above, during the first period 1H, the potential of the first node N1 is reset to the first driving voltage ELVDD by the eighth transistor T8. Therefore, regardless of the data signal applied to the first node N1 in the previous frame period F(k-1), a constant on-bias voltage Vob (Vob=ELVDD-Vint1) can be applied between the input electrode and the control electrode of the first transistor T1.

[0106] Figure 7 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the second period. Figure 8 is a diagram showing the Figure 7 1 is a waveform diagram of the waveform of the driving signal during the second period of FIG.

[0107] Reference Figure 7 and Figure 8 The scan signal GSi activated during the second period 2H of the scan period Sk is applied to the i-th scan line. Therefore, the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 is connected in a diode configuration through the third transistor T3.

[0108] During the second period 2H, a data signal DSj is applied to the j-th data line. The data signal DSj is applied to the first node N1 via the second transistor T2. In this case, since the first transistor T1 has a diode configuration, a voltage corresponding to the voltage difference between the data signal DSj and the threshold voltage of the first transistor T1 is applied to the second node N2. The voltage applied to the second node N2 during the second period 2H is charged into the storage capacitor Cst. The voltage charged into the storage capacitor Cst serves as a driving voltage to drive the first transistor T1 during the period when the second transistor T2 and the third transistor T3 are turned off.

[0109] Figure 9 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the third period. Figure 10 is a diagram showing the Figure 9 3 is a waveform diagram of the waveform of the driving signal during the third period of time.

[0110] Reference Figure 9 and Figure 10 During the light-emission period Ek, the light-emission control signal ESi activated is applied to the i-th light-emission line. Therefore, the fifth transistor T5 and the fourth transistor T4 are turned on. A current path is formed between the first driving voltage ELVDD and the second driving voltage ELVSS via the fifth transistor T5, the first transistor T1, the fourth transistor T4, and the organic light-emitting diode ED.

[0111] The driving current flowing through the organic light emitting diode ED is controlled by the potential of the second node N2. During the second period 2H, the operation of the first transistor T1 is controlled according to the data signal DSj applied to the second node N2.

[0112] During the light emitting period Ek, the organic light emitting diode ED emits light with brightness corresponding to the data signal DSj.

[0113] Figure 11 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG1 is an equivalent circuit diagram of the operation of a pixel during a first period. Figure 12 is a diagram showing a method according to some exemplary embodiments Figure 3 1 is an equivalent circuit diagram of the operation of the pixel during the second period.

[0114] Reference Figure 6 and Figure 11, a first initialization control signal GS(i-1) is applied to the control electrode of the sixth transistor T6. During the first period 1H of the scan period Sk, the first initialization control signal GS(i-1) is activated. The sixth transistor T6 is turned on in response to the activated first initialization control signal GS(i-1), and the first initialization voltage Vint1 is applied to the second node N2 through the turned-on sixth transistor T6.

[0115] During the first period 1H, the activated on-bias control signal GS(i-1) is applied to the eighth transistor T8. Therefore, the eighth transistor T8 is turned on, and the first driving voltage ELVDD is applied to the first node N1 through the turned-on eighth transistor T8.

[0116] During the first period 1H, the conduction bias control signal GS(i-1) and the first initialization control signal GS(i-1) are activated substantially simultaneously. Therefore, the eighth transistor T8 can be turned on substantially simultaneously with the sixth transistor T6. During the first period 1H, the second node N2 is initialized to the first initialization voltage Vint1, and the first drive voltage ELVDD is applied to the first node N1 due to the turned-on eighth transistor T8. Therefore, during the first period 1H, a potential difference corresponding to the voltage difference between the first initialization voltage Vint1 and the first drive voltage ELVDD is formed between the input electrode and the control electrode of the first transistor T1.

[0117] Therefore, regardless of the data signal applied to the first node N1 in the previous frame period F(k-1), a constant on-bias voltage Vob (Vob=ELVDD-Vint1) may be applied between the input electrode and the control electrode of the first transistor T1 during the first period 1H.

[0118] The first initialization control signal GS(i-1) and the on-bias control signal GS(i-1) may be applied to the scan lines SL1 to SLn (refer to Figure 1 ), for example, the (i-1)th scan signal GS(i-1) is applied to the (i-1)th scan line set to be immediately before the i-th scan line.

[0119] Reference Figure 8 and Figure 12 The second initialization control signal GSi activated during a period different from the activated period of the first initialization control signal GS(i-1) is applied to the control electrode of the seventh transistor T7.

[0120] When the second initialization control signal GSi, which is activated during the second period 2H, is applied to the seventh transistor T7, the seventh transistor T7 is turned on. A second initialization voltage Vint2 is applied to the anode electrode of the organic light emitting diode ED through the turned-on seventh transistor T7. The second initialization voltage Vint2 can be set to a voltage having a constant potential difference Vd with respect to the second drive voltage ELVSS. During the second period 2H, the anode electrode of the organic light emitting diode ED is initialized to the second initialization voltage Vint2.

[0121] In some exemplary embodiments, the second initialization control signal GSi may be applied to the scan lines SL1 to SLn (refer to Figure 1 ). However, the second initialization control signal GSi is not limited to the scan signal applied to the i-th scan line. For example, the activation period of the second initialization control signal GSi should not be particularly limited as long as the potential of the anode electrode of the organic light emitting diode ED is released to the second initialization voltage Vint2 before the start of the light emission period Ek.

[0122] The scan signal GSi activated during the second period 2H is applied to the i-th scan line. Therefore, the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 is connected in a diode configuration through the third transistor T3.

[0123] During the second period 2H, a data signal DSj is applied to the j-th data line. The data signal DSj is applied to the first node N1 via the second transistor T2. In this case, since the first transistor T1 has a diode configuration, a voltage corresponding to the voltage difference between the data signal DSj and the threshold voltage of the first transistor T1 is applied to the second node N2. The voltage applied to the second node N2 during the second period 2H is charged into the storage capacitor Cst. The voltage charged into the storage capacitor Cst serves as a driving voltage to drive the first transistor T1 during the period when the second transistor T2 and the third transistor T3 are turned off.

[0124] Figure 13 is an equivalent circuit diagram of a pixel according to some example embodiments. Figure 14 According to some exemplary embodiments Figure 13 The pixels include at least Figure 13 A cross-sectional view of part "I" in FIG. Figure 13 In the figure, the same reference numerals denote Figure 3 , and therefore, detailed description of the same elements will be omitted.

[0125] Reference Figure 13Pixel PX_1ij further includes a first auxiliary electrode ML1 facing the control electrode of the first transistor T1. The first auxiliary electrode ML1 is connected to a first voltage node VN1 to receive the first drive voltage ELVDD. The first auxiliary electrode ML1 faces the control electrode of the first transistor T1 to form a sub-storage capacitor Ccst that increases the capacitance of the storage capacitor Cst.

[0126] When the capacitance of the storage capacitor Cst is insufficient, a mura phenomenon occurs in which the brightness and color of the image are uneven. As described above, when the sub-storage capacitor Ccst is formed using the first auxiliary electrode ML1, even if it is difficult to sufficiently ensure capacitance by using only the storage capacitor Cst due to lack of space, deterioration of display quality due to the mura phenomenon can be prevented.

[0127] Reference Figure 14 , the circuit device layer DP-CL, the display device layer DP-ED and the thin film encapsulation layer TFE are sequentially arranged on the base layer SUB.

[0128] The circuit device layer DP-CL includes at least one inorganic layer, at least one organic layer, and a circuit device. The circuit device layer DP-CL includes a buffer layer BFL as an inorganic layer, a first intermediate inorganic layer 10, a second intermediate inorganic layer 20, and an intermediate organic layer 30 as an organic layer.

[0129] The inorganic layer may include at least one of silicon nitride, silicon oxynitride, and silicon oxide. The organic layer may include at least one of an acryl resin, a methacryl resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a parylene resin. The circuit device includes a conductive pattern and / or a semiconductor pattern.

[0130] The buffer layer BFL improves the adhesion strength between the base layer SUB and the conductive pattern or semiconductor pattern. Although not shown separately, a barrier layer may be provided over the base layer SUB to prevent the intrusion of foreign matter. The buffer layer BFL and the barrier layer may be selectively provided or omitted.

[0131] In some exemplary embodiments, the first auxiliary electrode ML is disposed on the base layer SUB and covered by the buffer layer BFL.

[0132] A semiconductor pattern OSP1 of the first transistor T1 (hereinafter, referred to as "first semiconductor pattern OSP1") and a semiconductor pattern OSP2 of the second transistor T2 (hereinafter, referred to as "second semiconductor pattern OSP2") are disposed on the buffer layer BFL. The first semiconductor pattern OSP1 and the second semiconductor pattern OSP2 may include amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor.

[0133] The first intermediate inorganic layer 10 is provided on the first semiconductor pattern OSP1 and the second semiconductor pattern OSP2. The control electrode GE1 of the first transistor T1 (hereinafter, referred to as "first control electrode GE1") and the control electrode GE2 of the second transistor T2 (hereinafter, referred to as "second control electrode GE2") are provided on the first intermediate inorganic layer 10. The first control electrode GE1 and the second control electrode GE2 may be connected to the scan lines SL1 to SLn (refer to FIG. Figure 1 ) are formed by the same photolithography process.

[0134] The first control electrode GE1 is disposed to face the first auxiliary electrode ML1 to form a connection to the storage capacitor Cst (refer to Figure 13 ) of the sub-storage capacitor Ccst. In addition, the first auxiliary electrode ML1 is disposed under the first semiconductor pattern OSP1. In some exemplary embodiments, the first auxiliary electrode ML1 may be formed of a metal material (eg, molybdenum, aluminum, chromium, etc.).

[0135] The second intermediate inorganic layer 20 is provided above the first intermediate inorganic layer 10 to cover the first control electrode GE1 and the second control electrode GE2. The output electrode DE1 (hereinafter referred to as the "first output electrode DE1") and the input electrode SE1 (hereinafter referred to as the "first input electrode SE1") of the first transistor T1, and the output electrode DE2 (hereinafter referred to as the "second output electrode DE2") and the input electrode SE2 (hereinafter referred to as the "second input electrode SE2") of the second transistor T2 are provided on the second intermediate inorganic layer 20.

[0136] The first output electrode DE1 and the first input electrode SE1 are connected to the first semiconductor pattern OSP1 through first and second contact holes CH1 and CH2, respectively, which are defined through the first and second intermediate inorganic layers 10 and 20. The second output electrode DE2 and the second input electrode SE2 are connected to the second semiconductor pattern OSP2 through third and fourth contact holes CH3 and CH4, respectively, which are defined through the first and second intermediate inorganic layers 10 and 20. In some exemplary embodiments, portions of the first and second transistors T1 and T2 may be implemented in a bottom-gate structure.

[0137] The intermediate organic layer 30 is disposed on the second intermediate inorganic layer 20 to cover the first output electrode DE1, the second output electrode DE2, the first input electrode SE1, and the second input electrode SE2. The intermediate organic layer 30 may provide a flat surface.

[0138] The display device layer DP-ED is disposed on the intermediate organic layer 30. The display device layer DP-ED includes a pixel-defining layer PDL and an organic light-emitting diode ED. The pixel-defining layer PDL includes an organic material that may be the same as that of the intermediate organic layer 30. The anode electrode AE of the organic light-emitting diode ED is disposed on the intermediate organic layer 30. The pixel-defining layer PDL includes an opening OP formed therethrough. The opening OP of the pixel-defining layer PDL exposes at least a portion of the anode electrode AE.

[0139] When viewed in plan, the pixel PX_1ij may be disposed in a pixel region. The pixel region includes an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA. In some exemplary embodiments, the emission region PXA is defined to correspond to a portion of the anode electrode AE exposed through the opening OP.

[0140] The hole control layer HCL may be commonly provided in the light emitting region PXA and the non-light emitting region NPXA. Although not shown separately, the hole control layer HCL may be provided in the pixel PX (refer to FIG. Figure 1 ) are commonly formed over the substrate, such as a hole control layer HCL.

[0141] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML is disposed in a region corresponding to the opening OP. For example, the light emitting layer EML may be formed in each pixel PX after being divided. The light emitting layer EML may include an organic material and / or an inorganic material. Figure 14 As shown in FIG, the light emitting layer EML is patterned as a representative example; however, the light emitting layer EML may be collectively provided above the pixel PX. In this case, the light emitting layer EML may generate white light. In addition, the light emitting layer EML may have a multi-layer structure.

[0142] The electron control layer ECL is provided on the light emitting layer EML. Although not shown separately, the electron control layer ECL may be commonly formed in the pixel PX (refer to FIG. Figure 1 ) on top. The cathode electrode CE of the organic light emitting diode ED is disposed on the electronic control layer ECL. The cathode electrode CE is commonly disposed on the pixel PX.

[0143] The thin film encapsulation layer TFE is disposed on the cathode electrode CE of the organic light-emitting diode ED. The thin film encapsulation layer TFE is commonly disposed above the pixels PX. In some exemplary embodiments, the thin film encapsulation layer TFE directly covers the cathode electrode CE. Although not shown, a capping layer may be disposed between the thin film encapsulation layer TFE and the cathode electrode CE to cover the cathode electrode CE. In this case, the thin film encapsulation layer TFE may directly cover the capping layer.

[0144] Figure 15is an equivalent circuit diagram illustrating a pixel according to some exemplary embodiments. Figure 16 According to some exemplary embodiments Figure 15 The pixels include at least Figure 15 A cross-sectional view of part "II" in FIG. Figure 15 and Figure 16 In the figure, the same reference numerals denote Figure 13 and Figure 14 , and therefore, detailed description of the same elements will be omitted.

[0145] Reference Figure 15 and Figure 16 Pixel PX_2ij also includes a second auxiliary electrode ML2 facing the control electrode of the first transistor T1_1. The second auxiliary electrode ML2 is connected to the first voltage node VN1 to receive the first drive voltage ELVDD. The second auxiliary electrode ML2 may face not only the first control electrode GE1 of the first transistor T1_1 but also the first input electrode SE1_1 of the first transistor T1_1.

[0146] Therefore, the second auxiliary electrode ML2 may also form a sub storage capacitor Ccst that increases the capacitance of the storage capacitor Cst and an auxiliary capacitor Cse between the first input electrode SE1_1 and the first voltage node VN1.

[0147] The auxiliary capacitor Cse can improve the Figure 4 ) in a structure where the light emitting control signal ESi is activated multiple times.

[0148] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A pixel, comprising: a light emitting diode comprising an anode electrode and a cathode electrode, wherein the cathode electrode is configured to receive a second driving voltage; a driving transistor including an input electrode connected to the first node, a control electrode connected to the second node, and an output electrode connected to the third node; a switching transistor configured to apply a data signal to the first node in response to a scan signal received in a second period; a first initialization transistor configured to apply a first initialization voltage to the second node in response to an initialization control signal received in a first period; as well as a second initialization transistor configured to apply a second initialization voltage having a voltage level different from the first initialization voltage to the anode electrode in response to the initialization control signal received in the first period, in, The first initialization transistor and the second initialization transistor are configured to be turned on simultaneously in the first period. The second driving voltage has a voltage level lower than the second initialization voltage, and A potential difference between the second driving voltage and the second initialization voltage is smaller than a threshold voltage of the light emitting diode.

2. The pixel according to claim 1, wherein The first initialization transistor includes a control electrode configured to receive the initialization control signal in the first period, an input electrode configured to receive the first initialization voltage, and an output electrode connected to the second node; and The second initialization transistor includes a control electrode configured to receive the initialization control signal, an input electrode configured to receive the second initialization voltage, and an output electrode connected to the anode electrode.

3. The pixel according to claim 2, wherein: The second initialization voltage has a lower voltage level than the first initialization voltage.

4. The pixel according to claim 3, wherein The second driving voltage is in a range of -9V to -11V.

5. The pixel according to claim 1, wherein The potential difference is in the range of 0.5 volts to 0.6 volts.

6. The pixel according to claim 2, wherein: The switching transistor includes a control electrode configured to receive the scan signal in the second period, an input electrode configured to receive the data signal, and an output electrode connected to the first node.

7. The pixel according to claim 1, further comprising: The first control transistor includes a control electrode configured to receive the scan signal in the second period, an input electrode connected to the second node, and an output electrode connected to the output electrode of the driving transistor.

8. The pixel according to claim 1, further comprising: a second control transistor including a control electrode configured to receive a light emission control signal in a light emission period, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light emitting diode; as well as The third control transistor includes a control electrode configured to receive the light emitting control signal, an input electrode configured to receive a first driving voltage different from the second driving voltage, and an output electrode connected to the first node.

9. The pixel according to claim 1 , further comprising: A storage capacitor is connected between the second node and a node configured to receive a first driving voltage different from the second driving voltage.

10. The pixel according to claim 9, further comprising: a first auxiliary electrode facing the control electrode of the driving transistor, The first auxiliary electrode is configured to receive the first driving voltage.

11. The pixel according to claim 10, wherein: The first auxiliary electrode also faces the input electrode of the driving transistor.

12. A pixel, comprising: A light emitting diode comprising an anode electrode and a cathode electrode; a driving transistor including an input electrode connected to the first node, a control electrode connected to the second node, and an output electrode connected to the third node; a switching transistor configured to apply a data signal to the first node in response to a scan signal received in a second period; a first initialization transistor configured to apply a first initialization voltage to the second node in response to a first initialization control signal received in a first period; as well as a second initialization transistor configured to apply a second initialization voltage having a voltage level different from the first initialization voltage to the anode electrode in response to a received second initialization control signal, The switching transistor and the second initialization transistor are configured to be turned on simultaneously in the second period. The cathode electrode of the light emitting diode is configured to receive a second driving voltage, The second driving voltage has a voltage level lower than the second initialization voltage, and A potential difference between the second driving voltage and the second initialization voltage is smaller than a threshold voltage of the light emitting diode.

13. The pixel according to claim 12, wherein: The first initialization control signal is configured to turn on the first initialization transistor during the first period; and The second initialization control signal is configured to turn on the second initialization transistor in the second period.

14. The pixel according to claim 13, wherein: The first initialization transistor includes a control electrode configured to receive the first initialization control signal in the first period, an input electrode configured to receive the first initialization voltage, and an output electrode connected to the second node; and The second initialization transistor includes a control electrode configured to receive the second initialization control signal, an input electrode configured to receive the second initialization voltage, and an output electrode connected to the anode electrode.

15. The pixel according to claim 14, wherein The second initialization voltage has a lower voltage level than the first initialization voltage.

16. The pixel according to claim 14, further comprising: The first control transistor includes a control electrode configured to receive the scan signal in the second period, an input electrode connected to the second node, and an output electrode connected to the output electrode of the driving transistor.

17. A light-emitting display device, comprising: a scan driver configured to apply a scan signal to scan lines extending in a first direction and arranged in a second direction crossing the first direction; a data driver configured to apply a data signal to a data line insulated from the scan line; pixels, at least one of the pixels comprising: a light emitting diode including an anode electrode and a cathode electrode, the cathode electrode being configured to receive a second driving voltage; and a circuit configured to control a light emitting operation of the light emitting diode; and an initialization voltage generator configured to generate a first initialization voltage and a second initialization voltage, and apply the first initialization voltage and the second initialization voltage to the at least one pixel, in, The circuit includes: a driving transistor including an input electrode connected to a first node, a control electrode connected to a second node, and an output electrode connected to a third node; a switching transistor configured to apply a data signal among the data signals to the first node in response to a scan signal received in a second period among the scan signals; a first initialization transistor configured to apply a first initialization voltage to the second node in response to an initialization control signal received in a first period; and a second initialization transistor configured to apply a second initialization voltage having a voltage level different from the first initialization voltage to the anode electrode in response to the initialization control signal received in the first period. The first initialization transistor and the second initialization transistor are connected to the same scan line among the scan lines to receive the initialization control signal, The second driving voltage has a voltage level lower than the second initialization voltage, and A potential difference between the second driving voltage and the second initialization voltage is smaller than a threshold voltage of the light emitting diode.

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