Shift register unit, control method thereof, gate driving circuit, and display device

Abstract

The application discloses a shift register unit and a control method thereof, a gate driving circuit and a display device. The shift register unit comprises an input circuit, a pull-up circuit, a first reset circuit and a second reset circuit. The input circuit transmits a signal at a second input end to a pull-up node under the control of an input signal at a first input end. The pull-up circuit outputs a clock signal at a clock signal end to an output end under the control of a potential at the pull-up node. The first reset circuit resets the pull-up node through a potential at a first power signal end under the control of a signal at a first reset end. The second reset circuit resets the pull-up node through the potential at the first power signal end under the control of a signal at a second reset end. An invalid level of the signals input at the first reset end and the second reset end is less than the potential input at the first power signal end. The embodiments provided in the application reset the pull-up node through the potential greater than the invalid level of the signals at the first reset end and the second reset end, thereby avoiding the output leakage jump.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit and its control method, a gate driving circuit, and a display device. Background Technology

[0002] With the continuous development of the thin-film transistor liquid crystal display (TFT-LCD) industry, low-cost, narrow-bezel, and thin-and-light products have received more attention. Against this backdrop, Gate Driver on Array (GOA) technology has emerged. GOA technology integrates the gate driving circuit and the thin-film transistor (TFT) array on the array substrate. Through the cascading relationship of shift register units, pixels are turned on row by row, thereby enabling the display to show colorful images.

[0003] In each shift register unit of the GOA circuit, the most basic components are the input module, the pull-up module, and the reset module. The output level of the output terminal in the circuit is related to the pull-up node. However, the transistors directly related to the pull-up node are usually in the subthreshold state when they are turned off, which causes leakage current in the pull-up node. When the leakage current is large, the output voltage will show obvious jumps, which will cause uneven horizontal stripes in the display. Summary of the Invention

[0004] To address at least one of the aforementioned problems, a first aspect of this application provides a shift register unit, comprising:

[0005] The input circuit is electrically connected to the first input terminal, the second input terminal, and the pull-up node, and is configured to transmit the signal from the second input terminal to the pull-up node under the control of the input signal from the first input terminal.

[0006] A pull-up circuit, electrically connected to the pull-up node, the clock signal terminal, and the output terminal, is configured to output the clock signal from the clock signal terminal to the output terminal under the control of the potential of the pull-up node;

[0007] A first reset circuit, electrically connected to a pull-up node, a first reset terminal, and a first power supply signal terminal, is configured to reset the pull-up node via the potential of the first power supply signal terminal under the signal control of the first reset terminal; and

[0008] The second reset circuit is electrically connected to the pull-up node, the second reset terminal, and the first power supply signal terminal. It is configured to reset the pull-up node through the potential of the first power supply signal terminal under the signal control of the second reset terminal.

[0009] The invalid level of the signals connected to the first reset terminal and the second reset terminal is lower than the potential of the first power supply signal terminal.

[0010] In some optional embodiments, the shift register unit further includes:

[0011] The first pull-down control circuit is configured to transmit the second power signal to the first pull-down node under the control of the second power signal at the second power signal terminal.

[0012] The first pull-down circuit is configured to pull down the first pull-down node via a third power signal at the third power signal terminal under the control of the potential of the pull-up node; and

[0013] The first noise reduction circuit is electrically connected to the pull-up node, the first power signal terminal, and the first pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the first pull-down node.

[0014] The invalid level of the signal connected to the third power signal terminal is lower than the potential connected to the first power signal terminal.

[0015] In some optional embodiments, the shift register unit further includes:

[0016] The second pull-down control circuit is configured to transmit the fourth power signal to the second pull-down node under the control of the fourth power signal at the fourth power signal terminal;

[0017] The second pull-down circuit is configured to pull down the second pull-down node via a third power signal at the third power signal terminal under the control of the potential of the pull-up node; and

[0018] The second noise reduction circuit is electrically connected to the pull-up node, the first power signal terminal, and the second pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the second pull-down node.

[0019] In some alternative embodiments, wherein,

[0020] The input circuit includes: a first transistor, the first electrode of the first transistor is electrically connected to the second input terminal, the second electrode is electrically connected to the pull-up node, and the control electrode is electrically connected to the first input terminal;

[0021] The pull-up circuit includes: a second transistor and a first capacitor. The first terminal of the second transistor is electrically connected to the clock signal terminal, the second terminal is electrically connected to the output terminal, and the control terminal is electrically connected to the pull-up node. The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal is connected to the output terminal.

[0022] The first reset circuit includes: a third transistor, wherein the first electrode of the third transistor is electrically connected to a pull-up node, the second electrode is electrically connected to a first power supply signal terminal, and the control electrode is electrically connected to a first reset terminal; and...

[0023] The second reset circuit includes a fourth transistor, the first electrode of which is electrically connected to the pull-up node, the second electrode of which is electrically connected to the first power supply signal terminal, and the control electrode of which is electrically connected to the second reset terminal.

[0024] In some alternative embodiments, wherein,

[0025] The first pull-up control circuit includes: a fifth transistor and a sixth transistor. The first terminal and the control terminal of the fifth transistor are electrically connected to the second power supply signal terminal, the second terminal is electrically connected to the control terminal of the sixth transistor, and the first terminal of the sixth transistor is electrically connected to the second power supply signal terminal and the second terminal is electrically connected to the first pull-down node.

[0026] The first pull-down circuit includes: a seventh transistor and an eighth transistor, wherein the first terminal of the seventh transistor is electrically connected to the second terminal of the fifth transistor, the second terminal is electrically connected to the third power supply signal terminal, and the control terminal is electrically connected to the pull-up node; the first terminal of the eighth transistor is electrically connected to the first pull-down node, the second terminal is electrically connected to the third power supply signal terminal, and the control terminal is electrically connected to the pull-up node; and

[0027] The first noise reduction circuit includes: a ninth transistor, the first electrode of the ninth transistor is electrically connected to a pull-up node, the second electrode is electrically connected to a first power signal terminal, and the control electrode is electrically connected to a first pull-down node.

[0028] In some alternative embodiments, wherein,

[0029] The second pull-up control circuit includes: a tenth transistor and an eleventh transistor. The first terminal and the control terminal of the tenth transistor are electrically connected to the fourth power supply signal terminal, and the second terminal is electrically connected to the control terminal of the eleventh transistor. The first terminal of the eleventh transistor is electrically connected to the fourth power supply signal terminal, and the second terminal is electrically connected to the second pull-down node.

[0030] The second pull-down circuit includes: a twelfth transistor and a thirteenth transistor, wherein the first terminal of the twelfth transistor is electrically connected to the second terminal of the tenth transistor, the second terminal is electrically connected to the third power supply signal terminal, and the control terminal is electrically connected to the pull-up node; the first terminal of the thirteenth transistor is electrically connected to the second pull-down node, the second terminal is electrically connected to the third power supply signal terminal, and the control terminal is electrically connected to the pull-up node; and

[0031] The second noise reduction circuit includes: a fourteenth transistor, the first electrode of the fourteenth transistor is electrically connected to a pull-up node, the second electrode is electrically connected to a first power signal terminal, and the control electrode is electrically connected to a second pull-down node.

[0032] In some optional embodiments, the shift register unit further includes:

[0033] An auxiliary pull-up circuit is electrically connected to the clock signal terminal, the pull-up node, and the auxiliary output terminal, and is configured to output the clock signal to the auxiliary output terminal under the control of the pull-up node.

[0034] A third noise reduction circuit, electrically connected to the output terminal, the first pull-down node, the second pull-down node, and the first power signal terminal, is configured to pull down the output terminal through the potential of the first power signal terminal under the control of the first pull-down node, and to pull down the output terminal through the potential of the first power signal terminal under the control of the second pull-down node; and

[0035] An auxiliary noise reduction circuit is electrically connected to an auxiliary output terminal, a first pull-down node, a second pull-down node, and a third power signal terminal. It is configured to pull down the auxiliary output terminal through the potential of the third power signal terminal under the control of the first pull-down node, and to pull down the auxiliary output terminal through the potential of the third power signal terminal under the control of the second pull-down node.

[0036] A second aspect of this application provides a gate driving circuit, comprising N cascaded shift register units as described above, where N is a natural number greater than 2, wherein...

[0037] The shift register unit includes an auxiliary pull-up circuit and an auxiliary noise reduction circuit. The auxiliary pull-up circuit is configured to output the clock signal to the auxiliary output terminal under the control of the pull-up node. The auxiliary noise reduction circuit is configured to pull down the auxiliary output terminal through the potential of the third power supply signal terminal under the control of the first pull-down node, and to pull down the auxiliary output terminal through the potential of the third power supply signal terminal under the control of the second pull-down node.

[0038] The first input terminal of the nth stage shift register unit is electrically connected to the auxiliary output terminal of the (n-1)th stage shift register unit, and the first reset terminal of the mth stage shift register unit is electrically connected to the auxiliary output terminal of the (m+1)th stage shift register unit. n is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N.

[0039] The first input terminal of the first-stage shift register unit is electrically connected to the start signal terminal of the gate drive circuit, and the first reset terminal of the Nth-stage shift register unit is electrically connected to the cutoff signal terminal of the gate drive circuit.

[0040] A third aspect of this application provides a display device including the gate driving circuit described above.

[0041] A fourth aspect of this application provides a control method using a shift register unit as described above, comprising:

[0042] In the first stage, a high-level signal is provided to the first input terminal and the second input terminal. The input circuit transmits the signal connected to the second input terminal to the pull-up node to pull up the potential of the pull-up node.

[0043] In the second stage, the pull-up circuit transmits the clock signal to the output terminal under the control of the potential of the pull-up node;

[0044] In the third stage, the first reset circuit, under the signal control of the first reset terminal, resets the pull-up node and the output terminal through the potential of the first power supply signal terminal.

[0045] The beneficial effects of this application are as follows:

[0046] This application addresses existing problems by providing a shift register unit and its control method, a gate driving circuit, and a display device. By setting up a first reset circuit and a second reset circuit, both connected to a first power supply signal terminal, and ensuring that the invalid level of the signals connected to the first and second reset terminals is lower than the potential of the first power supply signal terminal, leakage current is prevented from occurring during the invalid phase of the first and second reset circuits. This avoids prolonged voltage drop time at the output terminal and voltage jumps in the output voltage, improving the brightness consistency of the displayed image and demonstrating broad application prospects. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of a shift register unit in the prior art is shown;

[0049] Figure 2 Show Figure 1 The current-voltage characteristic curve of the transistor in the shift register unit;

[0050] Figure 3 Show Figure 1 The circuit timing diagram of the key port signals in the shift register unit shown;

[0051] Figure 4 This is a schematic structural block diagram of a shift register unit according to an embodiment of this application;

[0052] Figure 5 This is a schematic circuit diagram of a shift register unit according to an embodiment of this application;

[0053] Figure 6 A schematic timing diagram of the key port signals in the shift register unit according to an embodiment of this application is shown;

[0054] Figure 7 A schematic block diagram of a gate drive circuit according to an embodiment of this application is shown. Detailed Implementation

[0055] To more clearly illustrate this application, the following description, in conjunction with preferred embodiments and accompanying drawings, further clarifies the application. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this application.

[0056] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0057] The transistors used in this application embodiment can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In this application embodiment, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When an N-type transistor is used, the first terminal is the drain of the N-type transistor, the second terminal is the source of the N-type transistor, and when the gate input is high, the source and drain are turned on.

[0058] Before describing the embodiments of this application, the conventional shift register unit in the related art will be explained first.

[0059] like Figure 1 As shown in the figure, the circuit diagram of the shift register unit is illustrated. Figure 1 As can be seen, the shift register unit includes an input module composed of transistor M1, a pull-up module composed of transistor M3 and capacitor C1, a reset module composed of transistor M2, and a global reset module composed of transistor M7. Additionally, in some cases, a noise reduction module composed of transistors M10 and M10' is also included. The sources or drains of transistors M1, M2, M7, M10, and M10' are electrically connected to the pull-up node PU, which is the transistor that affects the output level of the output terminal Gout. (Refer to...) Figure 2As shown, when the transistor's Vgs voltage drop is 0V, the transistor is not completely turned off but is in a subthreshold state. Simulation experiments show that when in the subthreshold state, the transistor's Ids leakage current is as high as 10. -9 A, and an order of magnitude higher than -2V, which is a large leakage current in the display panel's driving circuit.

[0060] Based on the above structural foundation, combined with Figure 1 and Figure 3 As shown, the control electrode of transistor M1 is electrically connected to Out_C of the previous stage, and its first electrode is electrically connected to the output terminal Gout of the previous stage. During the further pull-up node rise phase, the control electrode is connected to a low level pulled down by the power supply terminal LVGL, and the first electrode is connected to a low level pulled down by the power supply terminal VGL. Typically, the low level of LVGL is lower than VGL; for example, LVGL is -10V and VGL is -8V. During the turn-off phase, Vgs = -2V. Therefore, transistor M1 has relatively low leakage current during the pull-up node rise phase. In contrast, the first electrodes of transistors M2, M7, M10, and M10' are all electrically connected to the pull-up node PU, and their control electrodes are connected to the reset terminal RST_PU, the global reset terminal T-RST, the first pull-down node PD1, and the second pull-down node PD2, respectively. The reset terminal RST_PU and the global reset terminal T-RST are typically provided by the power supply terminal LVGL. Figure 1 The low-level signals of the first pull-down node PD1 and the second pull-down node PD2 shown are also provided by the power supply terminal LVGL. During the rise phase, the pull-up node PU is pulled low by the power supply terminal LVGL. Therefore, the Vgs of transistors M2, M7, M10, and M10' are 0V, all in a subthreshold state. (Refer to...) Figure 3 As shown, transistors M2, M7, M10, and M10' have large leakage currents during the pull-up phase, and the pull-up node PU experiences a significant power drop. This voltage drop weakens the conduction capability of transistor M3, resulting in a longer output fall time Tf. Since the GOA circuit provides gate scan signals to each row of pixels through cascading, slight differences in transistor characteristics between different rows of GOA circuit units lead to variations in output fall times. These leakage current differences are amplified, resulting in differences in pixel voltage changes between different rows of pixels in the grayscale pattern. This difference manifests as a difference in pixel voltage, macroscopically presenting differences in brightness between rows, such as horizontal stripes, thus reducing the display effect.

[0061] Based on at least one of the above issues, refer to Figure 4 As shown, this application embodiment provides a shift register unit, including:

[0062] The input circuit 10 is electrically connected to the first input terminal Input1, the second input terminal Input2 and the pull-up node PU, and is configured to transmit the signal of the second input terminal Input2 to the pull-up node PU under the control of the input signal of the first input terminal Input1.

[0063] Pull-up circuit 20 is electrically connected to pull-up node PU, clock signal terminal CLK and output terminal Gout, and is configured to output the clock signal of clock signal terminal CLK to output terminal Gout under the control of the potential of pull-up node PU.

[0064] The first reset circuit 30 is electrically connected to the pull-up node PU, the first reset terminal RST_PU, and the first power signal terminal VGL, and is configured to reset the pull-up node PU by the potential of the first power signal terminal VGL under the signal control of the first reset terminal RST_PU; and

[0065] The second reset circuit 40 is electrically connected to the pull-up node PU, the second reset terminal T-RST, and the first power supply signal terminal VGL. It is configured to reset the pull-up node PU by the potential of the first power supply signal terminal VGL under the signal control of the second reset terminal T-RST.

[0066] Among them, the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST is less than the potential of the first power signal terminal VGL.

[0067] In this embodiment, by setting a first reset circuit and a second reset circuit, both of which are connected to the first power signal terminal, and by ensuring that the invalid level of the signals connected to the first reset terminal and the second reset terminal is less than the potential of the first power signal terminal, the first reset circuit and the second reset circuit will not generate leakage current during the invalid phase, thus avoiding a longer output voltage drop time and voltage jumps in the output voltage, thereby improving the brightness consistency of the displayed image.

[0068] To illustrate the structural and functional advantages of the shift register unit in this application embodiment, a detailed description of the specific circuit structure is provided below with specific examples. However, it should be specifically noted that this application embodiment is not limited to the specific shift register unit circuit structure exemplified below. That is, the input circuit 10 and pull-up circuit 20 included in the shift register unit of this application are essentially the main structural modules in the shift register unit, while the first reset circuit 30 and the second reset circuit 40 are used to perform current-level reset and global reset of the pull-up node PU, respectively. In other words, although the 21T1C circuit structure is described in detail in the figures as an example, this application is not limited to this. Other numbers of shift register units not listed, such as 11T1C, 17T1C, and 17T2C, are also applicable, as long as they satisfy the same inventive concept described above.

[0069] In a specific example, in conjunction with reference Figure 4 and Figure 5 As shown, Figure 3 A schematic block diagram of a shift register unit according to an embodiment of this application is shown. Figure 4 Showing satisfaction Figure 3 The circuit schematic of the 21T1C circuit shown in the block diagram is shown.

[0070] like Figure 4 and Figure 5 As shown, the shift register unit includes: an input circuit 10, a pull-up circuit 20, a first reset circuit 30, and a second reset circuit 40.

[0071] Specifically, the first reset circuit 30 is electrically connected to the pull-up node PU, the first reset terminal RST_PU, and the first power signal terminal VGL, and is configured to reset the pull-up node PU through the potential of the first power signal terminal VGL under the signal control of the first reset terminal RST_PU; the second reset circuit 40 is electrically connected to the pull-up node PU, the second reset terminal T-RST, and the first power signal terminal VGL, and is configured to reset the pull-up node PU through the potential of the first power signal terminal VGL under the signal control of the second reset terminal T-RST, and requires that the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST is less than the potential of the first power signal terminal VGL.

[0072] Typically, when the first reset terminal RST_PU and the second reset terminal T-RST are connected to an invalid level, they are electrically connected to the power signal terminal LVGL (i.e., the third power signal terminal hereinafter). The potential of the power signal terminal LVGL is usually a low-level potential lower than that of the first power signal terminal VGL. Therefore, by following the conventional connection method of connecting the invalid level to the power signal terminal LVGL, the requirement that the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST is lower than the potential of the first power signal terminal VGL can be met. When the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST is the potential of the power signal terminal LVGL, the first reset circuit 30 and the second reset circuit 40 will reset the pull-up node PU through the higher potential of the first power signal terminal VGL. This avoids significant leakage current in the pull-up node PU, prevents a prolonged fall time at the output terminal Gout, and thus avoids voltage jumps at the output terminal Gout.

[0073] It should be noted that the invalid level of the first reset terminal RST_PU and the second reset terminal T-RST being the potential of the power signal terminal LVGL is not a limitation. Rather, it aims to illustrate that without changing the existing connection method of the first reset terminal RST_PU and the second reset terminal T-RST, the requirement of the present application that the invalid level of the first reset terminal RST_PU and the second reset terminal T-RST be lower than the potential of the first power signal terminal VGL can be met, thereby achieving the purpose of reducing output voltage fluctuations without further wiring modifications. In practical applications, any other connection method that can ensure that the invalid level of the first reset terminal RST_PU and the second reset terminal T-RST is lower than the potential of the first power signal terminal VGL is acceptable.

[0074] More specifically, the first reset circuit 30 includes: a third transistor M3, the first electrode of the third transistor M3 is electrically connected to the pull-up node PU, the second electrode is electrically connected to the first power supply signal terminal VGL, and the control electrode is electrically connected to the first reset terminal RST_PU; the second reset circuit 40 includes a fourth transistor M4, the first electrode of the fourth transistor M4 is electrically connected to the pull-up node PU, the second electrode is electrically connected to the first power supply signal terminal VGL, and the control electrode is electrically connected to the second reset terminal T-RST.

[0075] Specifically, because the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST is lower than the potential of the first power supply signal terminal VGL, during the period when it is unnecessary to reset the pull-up node PU, that is, during the period when the third transistor M3 and the fourth transistor M4 need to be turned off, it is ensured that the Vgs of the third transistor M3 and the fourth transistor M4 are less than 0V, so that the third transistor M3 and the fourth transistor M4 are not in the subthreshold region, greatly reducing their leakage current, thereby greatly reducing the impact of leakage current. The potential of the pull-up node PU is pulled low, thereby avoiding the jump of the output terminal Gout.

[0076] Preferably, the difference between the invalid level of the signals connected to the first reset terminal RST_PU and the second reset terminal T-RST and the potential of the first power signal terminal VGL can be set to -2V, thereby referencing Figure 2 The transistor current-voltage characteristic curve shown shows that Vgs = -2V. This reduces the leakage current during the turn-off period of the third transistor M3 and the fourth transistor M4 to 1 / 10 of the existing technology, making the potential leakage current negligible and the output voltage jump negligible, thus avoiding the impact of the output voltage jump.

[0077] Optionally, for example, the invalid level of the first reset terminal RST_PU and the second reset terminal T-RST can be -10V, and the potential of the first power signal terminal VGL can be -8V, or they can be other values, so that the difference between the invalid level of the signal connected to the first reset terminal RST_PU and the second reset terminal T-RST and the potential of the first power signal terminal VGL is -2V. In this way, the leakage current during the turn-off period of the third transistor M3 and the fourth transistor M4 can be reduced to 1 / 10 of that in the prior art. The invalid level of the first reset terminal RST_PU and the second reset terminal T-RST can be provided by the power signal terminal LVGL (i.e., the third power signal terminal in the following text), or it can be provided by other signal lines or power signal terminals. This is not limited. For the sake of convenience, the following embodiments use the example of the invalid level of the signal connected to the first reset terminal RST_PU and the second reset terminal T-RST being provided by the power signal terminal LVGL.

[0078] It should also be noted that this application does not aim to limit the specific potential difference between the invalid level of the first reset terminal RST_PU and the second reset terminal T-RST and the first power signal terminal VGL. Those skilled in the art will understand that the larger the absolute value of the potential difference (i.e., the more negative the potential difference), the better the effect of eliminating leakage.

[0079] To be more specific, continue to refer to Figure 5 As shown, the input circuit 10 includes: a first transistor M1, the first electrode of the first transistor M1 is electrically connected to the second input terminal Input2, the second electrode is electrically connected to the pull-up node PU, and the control electrode is electrically connected to the first input terminal Input1.

[0080] Pull-up circuit 20 includes: a second transistor M2 and a first capacitor C1. The first terminal of the second transistor M2 is electrically connected to the clock signal terminal CLK, the second terminal is electrically connected to the output terminal Gout, and the control terminal is electrically connected to the pull-up node PU. The first terminal of the first capacitor C1 is electrically connected to the pull-up node PU, and the second terminal is connected to the output terminal Gout.

[0081] Furthermore, continue to refer to Figure 4 and Figure 5 As shown, the shift register unit also includes a first pull-down control circuit 51 and a first pull-down circuit 61.

[0082] The first pull-down control circuit 51 is configured to transmit the second power signal to the first pull-down node PD1 under the control of the second power signal at the second power signal terminal VDD1; the first pull-down circuit 61 is configured to pull down the first pull-down node PD1 through the third power signal at the third power signal terminal LVGL under the control of the potential of the pull-up node PU.

[0083] Optionally, the shift register unit further includes: a first noise reduction circuit 71, electrically connected to the pull-up node PU, the first power signal terminal VGL, and the first pull-down node PD1, configured to pull down the pull-up node PU through the potential of the first power signal terminal VGL under the control of the first pull-down node PD1, wherein the invalid level of the signal connected to the third power signal terminal LVGL is less than the potential connected to the first power signal terminal VGL.

[0084] By using the above settings, the first power signal terminal VGL, whose potential is less than the invalid level of the third power signal terminal LVGL, is used as the power signal terminal of the pull-down and pull-up node PU. This avoids leakage and voltage jumps in the pull-up node PU caused by leakage of the first noise reduction circuit when the noise reduction circuit is not working. This also avoids the increase in the fall time and voltage jump of the output terminal Gout.

[0085] Those skilled in the art will understand that the invalid level of the third power signal terminal LVGL is set in the same way as in the above embodiments. More preferably, it can be set to be 2V or more lower than the potential of the first power signal terminal VGL, which will not be elaborated here.

[0086] Specifically, refer to Figure 5 As shown, the first pull-up control circuit 51 includes a fifth transistor M5 and a sixth transistor M6. The first terminal and the control terminal of the fifth transistor M5 are electrically connected to the second power supply signal terminal VDD1, and the second terminal is electrically connected to the control terminal of the sixth transistor M6. The first terminal of the sixth transistor M6 is electrically connected to the second power supply signal terminal VDD1, and the second terminal is electrically connected to the first pull-down node PD1.

[0087] The first pull-down circuit 61 includes a seventh transistor M7 and an eighth transistor M8. The first electrode of the seventh transistor M7 is electrically connected to the second electrode of the fifth transistor M5, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU. The first electrode of the eighth transistor M8 is electrically connected to the first pull-down node PD1, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU.

[0088] The first noise reduction circuit 71 includes: a ninth transistor M9, the first electrode of the ninth transistor is electrically connected to the pull-up node PU, the second electrode is electrically connected to the first power signal terminal VGL, and the control electrode is electrically connected to the first pull-down node PD1.

[0089] Because the invalid level of the signal connected to the control electrode of the ninth transistor M9 is the signal that pulls down the first pull-down node PD1, that is, the potential of the third power supply signal terminal LVGL, which is lower than the potential of the first power supply signal terminal VGL, the ninth transistor M9's Vgs is ensured to be less than 0V during the time period when the pull-up node PU is not pulled down, that is, during the time period when the ninth transistor M9 needs to be turned off. This prevents the ninth transistor M9 from being in the subthreshold range, greatly reducing its leakage current and thus greatly reducing the impact of leakage current. The potential of the pull-up node PU is pulled low, thereby avoiding the jump of the output terminal Gout.

[0090] It should be noted here that, although Figure 5 The example given is that the first pull-down control circuit 51 includes two transistors and the first pull-down circuit 61 includes two transistors. However, this application is not limited to this. In practical applications, the first pull-down control circuit 51 may also include only one transistor and the first pull-down circuit 61 may also include only one transistor. In this case, the first terminal and the control terminal of the transistor of the first pull-down control circuit 51 may still be electrically connected to the second power supply signal terminal VDD1, but its second terminal may be electrically connected to the first pull-down node PD1. The first terminal of the transistor of the first pull-down circuit 61 may be directly electrically connected to the first pull-down node PD1, the second terminal may be electrically connected to the third power supply signal terminal LVGL, and the control terminal may be electrically connected to the pull-up node PU. In this way, the first pull-down control circuit can transmit the second power supply signal to the first pull-down node PD1 under the control of the second power supply signal of the second power supply signal terminal VDD1. The first pull-down circuit 61 pulls down the first pull-down node PD1 through the third power supply signal of the third power supply signal terminal LVGL under the control of the potential of the pull-up node PU. This will not be elaborated further here.

[0091] Further optionally, in addition to the first pull-down control circuit 51 and the second pull-down circuit 61, the shift register unit further includes: a second pull-down control circuit 52, configured to transmit a fourth power signal to the second pull-down node PD2 under the control of the fourth power signal at the fourth power signal terminal VDD2; and a first pull-down circuit 62, configured to pull down the second pull-down node PD2 through the third power signal at the third power signal terminal LVGL under the control of the potential of the pull-up node PU.

[0092] In this case, optionally, the shift register unit further includes: a second noise reduction circuit 72, electrically connected to the pull-up node PU, the first power signal terminal VGL, and the second pull-down node PD2, configured to pull down the pull-up node PU through the potential of the first power signal terminal VGL under the control of the second pull-down node PD2. Similarly, the invalid level of the signal connected to the third power signal terminal LVGL is less than the potential connected to the first power signal terminal VGL.

[0093] By using the above settings, the first power signal terminal VGL, whose potential is greater than the invalid level of the third power signal terminal LVGL, is used as the power signal terminal of the pull-down and pull-up node PU. This avoids leakage and voltage jumps in the pull-up node PU caused by leakage of the first noise reduction circuit when the noise reduction circuit is not working. This also avoids the increase in the fall time and voltage jumps of the output terminal Gout.

[0094] Those skilled in the art will understand that the invalid level of the third power signal terminal LVGL is set in the same way as in the above embodiments. More preferably, it can be set to be 2V or more lower than the potential of the first power signal terminal VGL, which will not be elaborated here.

[0095] Specifically, refer to Figure 5 As shown, the second pull-up control circuit 52 includes: a tenth transistor M10 and an eleventh transistor M11. The first terminal and the control terminal of the tenth transistor M10 are electrically connected to the fourth power supply signal terminal VDD2, and the second terminal is electrically connected to the control terminal of the eleventh transistor M11. The first terminal of the eleventh transistor M11 is electrically connected to the fourth power supply signal terminal VDD2, and the second terminal is electrically connected to the second pull-down node PD2.

[0096] The second pull-down circuit 62 includes: a twelfth transistor M12 and a thirteenth transistor M13. The first terminal of the twelfth transistor M12 is electrically connected to the second terminal of the tenth transistor M10, the second terminal is electrically connected to the third power signal terminal LVGL, and the control terminal is electrically connected to the pull-up node PU. The first terminal of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the second terminal is electrically connected to the third power signal terminal LVGL, and the control terminal is electrically connected to the pull-up node PU.

[0097] The second noise reduction circuit 72 includes: a fourteenth transistor M14, the first electrode of the fourteenth transistor M14 being electrically connected to the pull-up node PU, the second electrode being electrically connected to the first power signal terminal VGL, and the control electrode being electrically connected to the second pull-down node PD2.

[0098] Similarly, since the invalid level of the signal connected to the control electrode of the fourteenth transistor M14 is the signal that pulls down the second pull-down node PD2, that is, the potential of the third power supply signal terminal LVGL, which is lower than the potential of the first power supply signal terminal VGL, the Vgs of the fourteenth transistor M14 is ensured to be less than 0V during the time period when it is not necessary to pull down the pull-up node PU, that is, during the time period when the fourteenth transistor M14 needs to be turned off. This ensures that the fourteenth transistor M14 will not be in the subthreshold range, greatly reducing its leakage current, thereby greatly reducing the impact of leakage current. The potential of the pull-up node PU is pulled down, thereby avoiding the jump of the output terminal Gout.

[0099] Those skilled in the art should understand that when the shift register unit includes a first pull-down control circuit 51, a first pull-down circuit 61, a second pull-down control circuit 52, and a second pull-down circuit 62, the signals connected to the second power supply signal terminal VDD1 and the fourth power supply signal terminal VDD2 should be complementary in time. That is, during the time period when the signal connected to the first power supply signal terminal VDD1 is at a high level, the signal connected to the fourth power supply signal terminal VDD2 should be at a low level, and during the time period when the signal connected to the second power supply signal terminal VDD1 is at a low level, the signal connected to the fourth power supply signal terminal VDD2 should be at a high level, so that the first pull-down control circuit 51 and the first pull-down circuit 61 work alternately with the second pull-down control circuit 52 and the second pull-down circuit 62.

[0100] Additionally, it should be noted here that, although Figure 5 The example given is that the second pull-down control circuit 52 includes two transistors and the second pull-down circuit 62 includes two transistors. However, this application is not limited to this. In practical applications, the second pull-down control circuit 52 may also include only one transistor and the first pull-down circuit 62 may also include only one transistor. In this case, the first terminal and the control terminal of the transistor of the second pull-down control circuit 52 may still be electrically connected to the fourth power supply signal terminal VDD2, but its second terminal may be electrically connected to the second pull-down node PD2. The first terminal of the transistor of the second pull-down circuit 62 may be directly electrically connected to the second pull-down node PD2, the second terminal may be electrically connected to the third power supply signal terminal LVGL, and the control terminal may be electrically connected to the pull-up node PU. Similarly, the first pull-down control circuit can transmit the fourth power supply signal to the second pull-down node PD1 under the control of the fourth power supply signal of the fourth power supply signal terminal VDD2. The second pull-down circuit 62 pulls down the second pull-down node PD2 through the third power supply signal of the third power supply signal terminal LVGL under the control of the potential of the pull-up node PU. This will not be elaborated further here.

[0101] Continue to refer to Figure 4 and Figure 5 As shown, the shift register circuit may also include: an auxiliary pull-up circuit 21, a third noise reduction circuit 73, and an auxiliary noise reduction circuit 74.

[0102] The auxiliary pull-up circuit 21 is electrically connected to the clock signal terminal CLK, the pull-up node PU, and the auxiliary output terminal Out_C. It is configured to output the clock signal from the clock signal terminal CLK to the auxiliary output terminal Out_C under the control of the pull-up node PU. Specifically, the auxiliary pull-up circuit 21 may include a fifteenth transistor M15. The first electrode of the fifteenth transistor M15 is electrically connected to the clock signal terminal CLK, the second electrode is electrically connected to the auxiliary output terminal Out_C, and the control electrode is electrically connected to the pull-up node PU.

[0103] The third noise reduction circuit 73 is electrically connected to the output terminal Gout, the first pull-down node PD1, the second pull-down node PD2, and the first power signal terminal VGL. It is configured to pull down the output terminal Gout through the potential of the first power signal terminal VGL under the control of the first pull-down node PD1, and to pull down the output terminal Gout through the potential of the first power signal terminal VGL under the control of the second pull-down node PD2. Specifically, the third noise reduction circuit 73 includes a noise reduction transistor M16 and a noise reduction transistor M16'. The first electrode of the noise reduction transistor M16 is electrically connected to the output terminal Gout, the second electrode is electrically connected to the first power signal terminal VGL, and the control electrode is electrically connected to the first pull-down node PD1. The first electrode of the noise reduction transistor M16' is electrically connected to the output terminal Gout, the second electrode is electrically connected to the first power signal terminal VGL, and the control electrode is electrically connected to the second pull-down node PD2.

[0104] The auxiliary noise reduction circuit 74 is electrically connected to the auxiliary output terminal Out_C, the first pull-down node PD1, the second pull-down node PD2, and the third power signal terminal LVGL. It is configured to pull down the auxiliary output terminal Out_C through the potential of the third power signal terminal LVGL under the control of the first pull-down node PD1, and to pull down the auxiliary output terminal Out_C through the potential of the third power signal terminal LVGL under the control of the second pull-down node PD2. Specifically, the auxiliary noise reduction circuit 74 includes an auxiliary noise reduction transistor M17 and an auxiliary noise reduction transistor M17'. The first electrode of the auxiliary noise reduction transistor M17 is electrically connected to the auxiliary output terminal Out_C, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the first pull-down node PD1. The first electrode of the auxiliary noise reduction transistor M17' is electrically connected to the auxiliary output terminal Out_C, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the second pull-down node PD2.

[0105] In this application, the function of the fifteenth transistor M15 is equivalent to that of the second transistor M2. Within one scan cycle, the high-level time period of the output signal of the auxiliary output terminal Out_C is the same as the high-level time period of the output signal of the output terminal Gout. The difference is that when the auxiliary output terminal Out_C and the output terminal Gout are pulled low by their respective noise reduction units, the low-level signal values ​​after being pulled low are different. The low-level signal of the auxiliary output terminal Out_C is the potential of the third power supply signal terminal LVGL, and the low-level signal of the output terminal Gout is the potential of the first power supply signal terminal VGL.

[0106] In this example, the first input terminal Input1 is connected to the potential of the auxiliary output terminal Out_C of the previous stage shift register unit, and the second input terminal Input2 is connected to the potential of the output terminal Gout of the previous stage shift register unit. Therefore, the leakage current of the first transistor M1 can be reduced by using the invalid level difference between the auxiliary output terminal Out_C and the output terminal Gout.

[0107] In addition, in the embodiments of this application, in order to prevent the transistor in the first reset circuit 30 from being in the subthreshold region during the time period that needs to be turned off, the auxiliary output terminal Out_C can be used as the cascade port of the first reset terminal RST_PU of the next stage in the cascade. The specific function will be described in detail below.

[0108] In addition to the above-mentioned module circuits, in order to reduce noise for the first pull-down node PD1 and the second pull-down node PD2, refer to... Figure 5 As shown, the shift register unit may further include a fifth noise reduction circuit, which includes transistor M18 and transistor M18'. Specifically, the first electrode of transistor M18 is electrically connected to the first pull-down node PD1, the second electrode is electrically connected to the third power supply signal terminal LVGL, and the control electrode is electrically connected to the first input terminal Input1; the first electrode of transistor M18' is electrically connected to the second pull-down node PD2, the second electrode is electrically connected to the third power supply signal terminal LVGL, and the control electrode is electrically connected to the first input terminal Input1.

[0109] The above settings, based on the input signal connected to the first input terminal Input1, can pull down the first pull-down node PD1 and the second pull-down node PD2 through the potential of the third power signal terminal LVGL to ensure the normal lifting of the pull-up node PU and the normal output of the output terminal Out.

[0110] To further understand the functional advantages of the circuit structure in the embodiments of this application, please refer to the following: Figure 6 The timing diagram of the key port signals shown is further described below. For ease of understanding, the potential of the first power supply signal terminal VGL is denoted as VGL, the potential of the third power supply signal terminal LVGL is denoted as LVGL, and the high-level signal of the clock signal terminal VLK is labeled as VGH.

[0111] Reference Figure 6 As shown, a frame scan signal of a shift register unit mainly includes three stages.

[0112] The first stage corresponds to time period T1. During this stage, a high-level signal is input to the first input terminal Inout1 of the input circuit 10, and a high-level signal is also input to the second input terminal Input2. The first transistor M1 is turned on, and the high-level signal input to the second input terminal Input2 is transmitted to the pull-up node PU to pull up the potential of the pull-up node PU. During the period of pulling up the pull-up node PU, due to the presence of the first capacitor C1 in the pull-up circuit 20, the potential of the pull-up node PU rises at the rate of charging the first capacitor C1.

[0113] In the first stage, because the first reset terminal RST_PU is at a low level LVGL, the third transistor M3 is completely turned off. Additionally, the signal connected to the second reset terminal, which serves as the global reset terminal, should also be at a low level LVGL, thus the fourth transistor M4 is completely turned off. Furthermore, the fourth noise reduction circuit pulls the first pull-down node PD1 and the second pull-down node PD2 low through the low-level signal LVGL of the third power supply signal terminal.

[0114] The second stage corresponds to time period T2. During this stage, the pull-up circuit 20 continues to charge and rise under the action of the first capacitor C1, thus further raising the potential of the pull-up node PU. The potential of the pull-up node PU in this stage is sufficient to turn on the second transistor M2 in the pull-up circuit 20. Under the control of the potential of the pull-up node PU, the pull-up circuit 20 transmits the clock signal of the clock signal terminal CLK to the output terminal Gout, and the output terminal Gout outputs a high-level signal.

[0115] During this stage, under the control of the pull-up node PU, the first pull-down circuit 61 and / or the pull-down circuit 62 keep the first pull-down node PD1 and the second pull-down node PD2 in a low-level state through the low-level signal LVGL of the third power supply signal terminal LVGL.

[0116] Specifically, in this application, the second stage is the circuit output stage, during which the second transistor M2, the ninth transistor M9, and the fourteenth transistor M14 should all be in the off state. To ensure that the above three transistors are not in the subthreshold region during this stage, the potential of the invalid level signal connected to the control electrode of the second transistor M2, the ninth transistor M9, and the fourteenth transistor M14 is made lower than the potential of the first power supply signal connected to the second electrode. This avoids the potential of the pull-up node PU being pulled low, thereby effectively shortening the output turn-off time Tf, avoiding voltage jumps at the output, and improving the display effect.

[0117] In the third stage, the first reset terminal RST_PU is connected to a valid level signal. Under the signal control of the first reset terminal, the pull-up node PU and the output terminal Gout are reset by the potential of the first power supply signal terminal VGL.

[0118] Based on the same inventive concept, a second aspect of this application provides a gate driving circuit, comprising N cascaded shift register units as described in the above embodiments, where N is a natural number greater than 2, wherein...

[0119] The shift register unit includes an auxiliary output circuit and an auxiliary noise reduction circuit. The auxiliary output circuit is configured to output a clock signal to the auxiliary output terminal under the control of a pull-up node. The auxiliary noise reduction circuit is configured to pull down the output terminal through the potential of a third power supply signal terminal under the control of a first pull-down node, and further pull down the output terminal through the potential of a third power supply signal terminal under the control of a second pull-down node.

[0120] The first input terminal of the nth stage shift register unit is electrically connected to the auxiliary output terminal of the (n-1)th stage shift register unit, and the first reset terminal of the mth stage shift register unit is electrically connected to the auxiliary output terminal of the (m+1)th stage shift register unit. n is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N.

[0121] The first input terminal of the first-stage shift register unit is electrically connected to the start signal terminal of the gate drive circuit, and the first reset terminal of the Nth-stage shift register unit is electrically connected to the cutoff signal terminal of the gate drive circuit.

[0122] Specifically, refer to Figure 7As shown in the figure, an exemplary gate drive circuit of four cascaded shift register units GOA-1, GOA-2, GOA-3, and GOA-4 is illustrated. As can be seen in the figure, the auxiliary output terminal Out_C of the first-stage shift register unit GOA-1 is electrically connected to the first input terminal Input1 of the second-stage shift register unit GOA-2, and the output terminal Gout of the first stage is electrically connected to the second input terminal Input2 of the second-stage shift register unit GOA-2. Similarly, the auxiliary output terminal Out_C of the second-stage shift register unit GOA-2 is electrically connected to the first input terminal Input1 of the third-stage shift register unit GOA-3, and the output terminal Gout of the second stage is electrically connected to the second input terminal of the third-stage shift register unit GOA-3. Input2, the auxiliary output Out_C of the second stage is electrically connected to the first reset terminal RST_PU of the first stage shift register unit GOA-1; the auxiliary output Out_C of the third stage shift register unit GOA-3 is electrically connected to the first input terminal Input1 of the fourth stage shift register unit GOA-4, the output Gout of the third stage is electrically connected to the second input terminal Input2 of the fourth stage shift register unit GOA-4, and the auxiliary output Out_C of the third stage is also electrically connected to the first reset terminal RST_PU of the second stage shift register unit GOA-2. The first input terminal Input1 and the second input terminal Input2 of the first stage can be electrically connected to the start signal terminal STV simultaneously, and the first reset terminal of the fourth stage is electrically connected to the cutoff signal terminal (not shown).

[0123] In this application, because the second electrode of the transistor in the first reset circuit is electrically connected to the first power supply signal terminal VGL, the circuit connection structure is simplified by utilizing the characteristic that the invalid level signal of the auxiliary output terminal is less than the potential of the first power supply signal terminal VGL in the cascade. At the same time, the voltage jump at the output terminal can be avoided by using the auxiliary output terminal as the cascade terminal of the first reset terminal. In addition, the gate drive circuit, by including the shift register unit of the above embodiments in the cascade, has the advantages of small fall time of shift register output terminal and reduced voltage jump in the above embodiments, which will not be elaborated here.

[0124] In addition, the above cascading numbers are only illustrative and not intended to be limiting. You can set an appropriate cascading number according to actual needs. Also, the number of clock signal lines is only illustrative and can be adjusted according to specific needs in actual applications.

[0125] A third aspect of this application provides a display device, including a gate driving circuit according to embodiments of this application.

[0126] In this embodiment, by setting the display device to a gate drive circuit composed of cascaded shift register units, and in each shift register unit, the invalid level of the signal connected to the first reset terminal and the second reset terminal is less than the potential of the first power supply signal terminal, so that during the invalid phase of the first reset circuit and the second reset circuit, the first reset circuit and the second reset circuit will not generate leakage current, avoiding the output voltage drop time becoming longer and the output voltage having voltage jumps, thus improving the brightness consistency of the display screen and having broad application prospects.

[0127] It is worth noting that the gate driving circuit with the embodiments of this application can be applied to various forms of display devices. Those skilled in the art should understand that all display devices based on the gate driving circuit operating mode of this application are within the protection scope of this application.

[0128] A fourth aspect of this application provides a control method for a shift register unit utilizing embodiments of this application, comprising:

[0129] In the first stage, a high-level signal is provided to the first input terminal and the second input terminal as an input signal, and the input circuit transmits the signal connected to the second input terminal to the pull-up node to pull up the potential of the pull-up node;

[0130] In the second stage, the pull-up circuit transmits the clock signal to the output terminal under the control of the potential of the pull-up node;

[0131] In the third stage, under the signal control of the first reset terminal, the first reset circuit resets the pull-up node and the output terminal through the potential of the first power signal terminal.

[0132] The above method utilizes the fact that the invalid level of the signals connected to the first reset terminal and the second reset terminal is lower than the potential of the first power signal terminal. This ensures that during the invalid phase of the first and second reset circuits, no leakage current occurs in the first and second reset circuits, preventing a prolonged voltage drop time at the output terminal and avoiding voltage jumps in the output voltage, thus improving the brightness consistency of the displayed image. The specific implementation of this embodiment is the same as the previous embodiment and will not be repeated here.

[0133] This application addresses existing problems by providing a shift register unit and its control method, a gate driving circuit, and a display device. By setting up a first reset circuit and a second reset circuit, both connected to a first power supply signal terminal, and ensuring that the invalid level of the signals connected to the first and second reset terminals is lower than the potential of the first power supply signal terminal, leakage current is prevented from occurring during the invalid phase of the first and second reset circuits. This avoids prolonged voltage drop time at the output terminal and voltage jumps in the output voltage, improving the brightness consistency of the displayed image and demonstrating broad application prospects.

[0134] Obviously, the above embodiments of this application are merely examples for clearly illustrating this application, and are not intended to limit the implementation of this application. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this application are still within the protection scope of this application.

Claims

1. A shift register unit, characterized in that, include: An input circuit, electrically connected to a first input terminal, a second input terminal, and a pull-up node, is configured to transmit the signal from the second input terminal to the pull-up node under the control of the input signal from the first input terminal. A pull-up circuit, electrically connected to the pull-up node, the clock signal terminal, and the output terminal, is configured to output the clock signal from the clock signal terminal to the output terminal under the control of the potential of the pull-up node; A first reset circuit is electrically connected to the pull-up node, the first reset terminal, and the first power signal terminal, and is configured to reset the pull-up node by the potential of the first power signal terminal under the signal control of the first reset terminal. as well as The second reset circuit is electrically connected to the pull-up node, the second reset terminal, and the first power signal terminal, and is configured to reset the pull-up node by the potential of the first power signal terminal under the signal control of the second reset terminal. Wherein, the invalid level of the signals connected to the first reset terminal and the second reset terminal is less than the potential of the first power signal terminal.

2. The shift register unit according to claim 1, characterized in that, Also includes: The first pull-down control circuit is configured to transmit the second power signal to the first pull-down node under the control of the second power signal at the second power signal terminal. The first pull-down circuit is configured to pull down the first pull-down node through a third power signal at the third power signal terminal under the control of the potential of the pull-up node. as well as A first noise reduction circuit is electrically connected to the pull-up node, the first power signal terminal, and the first pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the first pull-down node. Wherein, the invalid level of the signal connected to the third power signal terminal is less than the potential connected to the first power signal terminal.

3. The shift register unit according to claim 2, characterized in that, Also includes: The second pull-down control circuit is configured to transmit the fourth power signal to the second pull-down node under the control of the fourth power signal at the fourth power signal terminal; The second pull-down circuit is configured to pull down the second pull-down node through the third power signal of the third power signal terminal under the control of the potential of the pull-up node; as well as The second noise reduction circuit is electrically connected to the pull-up node, the first power signal terminal, and the second pull-down node, and is configured to pull down the pull-up node through the potential of the first power signal terminal under the control of the second pull-down node.

4. The shift register unit according to claim 1, characterized in that, in, The input circuit includes: a first transistor, wherein a first electrode of the first transistor is electrically connected to the second input terminal, a second electrode is electrically connected to the pull-up node, and a control electrode is electrically connected to the first input terminal; The pull-up circuit includes: a second transistor and a first capacitor. The first terminal of the second transistor is electrically connected to the clock signal terminal, the second terminal is electrically connected to the output terminal, and the control terminal is electrically connected to the pull-up node. The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal is electrically connected to the output terminal. The first reset circuit includes: a third transistor, wherein the first electrode of the third transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the first reset terminal; and The second reset circuit includes a fourth transistor, the first electrode of which is electrically connected to the pull-up node, the second electrode of which is electrically connected to the first power signal terminal, and the control electrode of which is electrically connected to the second reset terminal.

5. The shift register unit according to claim 2, characterized in that, in, The first pull-down control circuit includes a fifth transistor and a sixth transistor. The first terminal and the control terminal of the fifth transistor are electrically connected to the second power signal terminal, and the second terminal is electrically connected to the control terminal of the sixth transistor. The first terminal of the sixth transistor is electrically connected to the second power signal terminal, and the second terminal is electrically connected to the first pull-down node. The first pull-down circuit includes: a seventh transistor and an eighth transistor, wherein the first terminal of the seventh transistor is electrically connected to the second terminal of the fifth transistor, the second terminal is electrically connected to the third power signal terminal, and the control terminal is electrically connected to the pull-up node; the first terminal of the eighth transistor is electrically connected to the first pull-down node, the second terminal is electrically connected to the third power signal terminal, and the control terminal is electrically connected to the pull-up node; and The first noise reduction circuit includes: a ninth transistor, wherein the first electrode of the ninth transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the first pull-down node.

6. The shift register unit according to claim 3, characterized in that, in, The second pull-down control circuit includes a tenth transistor and an eleventh transistor. The first terminal and the control terminal of the tenth transistor are electrically connected to the fourth power signal terminal, and the second terminal is electrically connected to the control terminal of the eleventh transistor. The first terminal of the eleventh transistor is electrically connected to the fourth power signal terminal, and the second terminal is electrically connected to the second pull-down node. The second pull-down circuit includes: a twelfth transistor and a thirteenth transistor, wherein the first terminal of the twelfth transistor is electrically connected to the second terminal of the tenth transistor, the second terminal of the twelfth transistor is electrically connected to the third power signal terminal, and the control terminal of the thirteenth transistor is electrically connected to the second pull-down node; the first terminal of the thirteenth transistor is electrically connected to the second pull-down node, the second terminal of the thirteenth transistor is electrically connected to the third power signal terminal, and the control terminal of the thirteenth transistor is electrically connected to the pull-up node; and The second noise reduction circuit includes: a fourteenth transistor, wherein the first electrode of the fourteenth transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the second pull-down node.

7. The shift register unit according to claim 3, characterized in that, Also includes: An auxiliary pull-up circuit is electrically connected to the clock signal terminal, the pull-up node, and the auxiliary output terminal, and is configured to output the clock signal to the auxiliary output terminal under the control of the pull-up node. The third noise reduction circuit is electrically connected to the output terminal, the first pull-down node, the second pull-down node and the first power signal terminal, and is configured to pull down the output terminal through the potential of the first power signal terminal under the control of the first pull-down node, and to pull down the output terminal through the potential of the first power signal terminal under the control of the second pull-down node. as well as An auxiliary noise reduction circuit is electrically connected to the auxiliary output terminal, the first pull-down node, the second pull-down node, and the third power signal terminal. It is configured to pull down the auxiliary output terminal through the potential of the third power signal terminal under the control of the first pull-down node, and to pull down the auxiliary output terminal through the potential of the third power signal terminal under the control of the second pull-down node.

8. A gate driving circuit, characterized in that, It includes N cascaded shift register units as described in any one of claims 1-7, where N is a natural number greater than 2, wherein The shift register unit includes an auxiliary pull-up circuit and an auxiliary noise reduction circuit. The auxiliary pull-up circuit is configured to output the clock signal to the auxiliary output terminal under the control of the pull-up node. The auxiliary noise reduction circuit is configured to pull down the auxiliary output terminal through the potential of the third power supply signal terminal under the control of the first pull-down node, and to pull down the auxiliary output terminal through the potential of the third power supply signal terminal under the control of the second pull-down node. The first input terminal of the nth stage shift register unit is electrically connected to the auxiliary output terminal of the (n-1)th stage shift register unit, and the first reset terminal of the mth stage shift register unit is electrically connected to the auxiliary output terminal of the (m+1)th stage shift register unit. n is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N. The first input terminal of the first-stage shift register unit is electrically connected to the start signal terminal of the gate drive circuit, and the first reset terminal of the Nth-stage shift register unit is electrically connected to the cutoff signal terminal of the gate drive circuit.

9. A display device, characterized in that, Includes the gate drive circuit as described in claim 8.

10. A control method using a shift register unit as described in any one of claims 1-7, characterized in that, include: In the first stage, a high-level signal is provided to the first input terminal and the second input terminal, and the input circuit transmits the signal connected to the second input terminal to the pull-up node to pull up the potential of the pull-up node; In the second stage, the pull-up circuit transmits the clock signal to the output terminal under the control of the potential of the pull-up node; In the third stage, under the signal control of the first reset terminal, the first reset circuit resets the pull-up node and the output terminal through the potential of the first power signal terminal.

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