Capacitive digital-to-analog converter

Abstract

The application relates to a capacitive digital-to-analog converter, which comprises a sampling switch connected with a logic control module through a comparator, and is further connected with a high-weight array and a low-weight array, wherein the high-weight array and the low-weight array are connected through a bridging part, the high-weight array is composed of a plurality of capacitors and switches with on-resistance, the low-weight array is composed of a plurality of capacitors and switches with on-resistance, the bridging part is composed of a capacitor and at least one normally closed switch, and the low end of the high-weight array and the low-weight array is connected with an input signal V in , a reference signal V REF , and ground. Therefore, impedance can be effectively matched, the impedance matching problem of the low-weight capacitor array and the bridging capacitor can be optimized, and the delay in the establishment process of the CDAC is optimized. The establishment time required by the circuit can be effectively reduced. The overall structure is simple, layout is facilitated, and the application can be effectively applied to various circuits.

Description

Technical Field

[0001] This invention relates to a converter, and more particularly to a capacitive digital-to-analog converter. Background Technology

[0002] like Figure 2 As shown, the CDAC is an important component in a successive approximation analog-to-digital converter (SAR ADC) system. The main function of the CDAC is to provide an analog voltage for comparison with the comparator. The CDAC consists of a capacitor array and corresponding switches. In a traditional CDAC, the capacitor array uses binary weights.

[0003] For traditional binary weighted capacitor arrays, when the minimum capacitance is determined, the capacitance size and area of ​​the overall CDAC increase exponentially, which is very disadvantageous.

[0004] Meanwhile, in the structure of a traditional SAR ADC, an N-bit ADC requires N comparisons to complete, and the time required for each comparison directly corresponds to the ADC frequency. For the traditional structure, the time required for each comparison is mainly limited by three time constraints: the comparator delay, the register setup time, and the CDAC setup time. Among them, the CDAC setup time is caused by the on-resistance of the switching of the capacitor array in the CDAC, which makes its setup process form an RC network.

[0005] For N-bit SAR ADCs, the zero-pole system of their RC network is more complex, and their settling time increases rapidly. Therefore, for high-precision SAR ADCs, the settling time of the CDAC has a particularly significant limitation on the ADC's operating frequency.

[0006] Furthermore, the process of building up a large capacitor requires a switch with extremely low on-resistance to supply a large current, which is difficult to achieve precisely when the capacitor is large enough.

[0007] The current conventional solution is to use bridging capacitors, but this approach still has the following drawbacks:

[0008] For circuits that introduce bridging capacitors, the impedance matching between different switches is lower compared to ordinary binary weighted circuits. This is because it not only needs to meet the matching requirements of the capacitors within the high and low weighted capacitor arrays, but also the matching requirements between the high and low weighted capacitor arrays themselves. The matching degree between the high and low weighted capacitor arrays is largely affected by the bridging capacitor. However, since there is no switch on the bridging capacitor, while the digital code capacitor controlled by the switch has the on-resistance of the switch, the impedance between the two is not matched. The same situation occurs in some capacitors that are constantly grounded.

[0009] In view of the above-mentioned shortcomings, the designer actively researched and innovated in order to create a capacitive digital-to-analog converter that would have greater industrial application value. Summary of the Invention

[0010] To address the aforementioned technical problems, the present invention aims to provide a capacitive digital-to-analog converter.

[0011] The present invention discloses a capacitive digital-to-analog converter (DAC) comprising a sampling switch, wherein: the sampling switch is connected to a logic control module via a comparator; a high-weight array and a low-weight array are also connected to the sampling switch; the high-weight array and the low-weight array are connected via a bridging section; the high-weight array is composed of several capacitors and a switch with on-resistance; the low-weight array is composed of several capacitors and a switch with on-resistance; the bridging section is composed of a capacitor and at least one normally closed switch; and an input signal V is connected to the lower ends of the high-weight array and the low-weight array. in Reference signal V REF One type of grounding.

[0012] Furthermore, in the aforementioned capacitive digital-to-analog converter, the upper end of the capacitor used in the high-weighting array is connected to the common-mode signal and the left end of the bridging section via a sampling switch. The upper end of the capacitor is connected to a comparator, and the lower end of the capacitor is connected to a corresponding switch. The switch selects the input signal V under the control of the logic control module. in Or the reference signal V REF .

[0013] Furthermore, in the aforementioned capacitive digital-to-analog converter, the high-weight array includes capacitors C7, C6, C5, and C4. Switch S7 is connected to capacitor C7, switch S6 is connected to capacitor C6, switch S5 is connected to capacitor C5, and switch S4 is connected to capacitor C4.

[0014] Furthermore, in the aforementioned capacitive digital-to-analog converter, the upper end of the capacitor used in the low-weight array is connected to the right end of the bridging section, and the lower end of the capacitor is connected to a corresponding switch. The switch, under the control of the logic control module, selects the input signal V. in Or the reference signal V REF .

[0015] Furthermore, in the aforementioned capacitive digital-to-analog converter, the low-weight array includes capacitors C3, C2, C1, and C0. Switch S3 is connected to capacitor C3, switch S2 is connected to capacitor C2, switch S1 is connected to capacitor C1, and switch S0 is connected to capacitor C0.

[0016] Furthermore, in the aforementioned capacitive digital-to-analog converter, the bridging section includes a capacitor C. B The capacitor C B A switch S is connected to one side. B The switch S B The capacitor C remains in the ON state. B The other side is connected to a high-weight array, the switch S B Connect the low-weight array.

[0017] By means of the above-described solution, the present invention has at least the following advantages:

[0018] 1. It can effectively match impedance, optimize the impedance matching problem of low-weight capacitor array and bridging capacitor, thereby optimizing the delay in the CDAC establishment process.

[0019] 2. It can effectively reduce the setup time required for the circuit.

[0020] 3. The overall structure is simple and easy to lay out, and it can be effectively applied to various circuits.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a capacitive digital-to-analog converter.

[0023] Figure 2 This is a schematic diagram of the structure of an existing capacitive digital-to-analog converter.

[0024] The meanings of the labels in the figures are as follows.

[0025] U1 Sampling switch, U2 Comparator

[0026] U3 logic control module Detailed Implementation

[0027] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0028] like Figure 1The capacitive digital-to-analog converter includes a sampling switch U1, which is unique in that the sampling switch U1 is connected to a logic control module U3 via a comparator U2. Simultaneously, a high-weight array and a low-weight array are connected to the sampling switch U1, and the high-weight array and the low-weight array are connected by a bridging section to form a complete capacitive weight array. Specifically, the high-weight array consists of several capacitors and switches with on-resistance, and the low-weight array also consists of several capacitors and switches with on-resistance. Furthermore, the bridging section consists of a capacitor and at least one normally closed switch. Moreover, the lower ends of the high-weight array and the low-weight array are connected to an input signal V. in Reference signal V REF One type of grounding.

[0029] During implementation, an analog voltage is established after charge redistribution and passed to comparator U2. Comparator U2 then passes the comparison result to logic control module U3, which controls the switching of the switched capacitor array accordingly based on the comparison result.

[0030] In a preferred embodiment of the present invention, the upper end of the capacitor used in the high-weight array is connected to the common-mode signal and the left end of the bridging section via a sampling switch U1. Simultaneously, the upper end of the capacitor is connected to a comparator U2, and the lower end of the capacitor is connected to a corresponding switch. Therefore, under the control of the logic control module U3, the switch selects the input signal V. in Or the reference signal V REF Specifically, the high-weight array includes capacitors C7, C6, C5, and C4. Switch S7 is connected to capacitor C7, switch S6 is connected to capacitor C6, switch S5 is connected to capacitor C5, and switch S4 is connected to capacitor C4.

[0031] Furthermore, in the low-weight array used in this invention, the upper end of the capacitor is connected to the right end of the bridging section, and the lower end of the capacitor is connected to a corresponding switch. Under the control of the logic control module U3, the switch selects the input signal V. in Or the reference signal V REF Specifically, the low-weight array includes capacitors C3, C2, C1, and C0. Switch S3 is connected to capacitor C3, switch S2 is connected to capacitor C2, switch S1 is connected to capacitor C1, and switch S0 is connected to capacitor C0.

[0032] In practical implementation, the bridging component includes capacitor C. B Capacitor C B A switch S is connected to one side. B Switch S B The capacitor C remains in the on state. B The other side connects to a high-weight array, switch SB Connect the low-weight array.

[0033] During use, the present invention receives the input signal V via switches S7, S6, S5, S4, S3, S2, S1, and S0 when the circuit is in sampling mode. in Then, the input signal is stored as a charge on the capacitor. Simultaneously, switches S7, S6, S5, S4, S3, S2, S1, and S0 are connected to the reference signal V under the control of the logic unit when the circuit is in the CDAC setup state. REF Or ground. That is, sampling switch U1 is turned on when the circuit is in sampling mode, and the voltage above the high-weight array is fed to the common-mode voltage V. CM The sampling switch U1 is open when the circuit is in CDAC establishment state, causing the common-mode voltage V to be open. CM It does not interfere with charge redistribution in subsequent circuits. Especially in capacitor C... B Improve impedance matching.

[0034] The working principle of this invention is as follows: the conversion cycle has two working stages, including a sampling stage and a CDAC establishment stage.

[0035] During the sampling phase, sampling switch U1 is closed, the control switch of the capacitor is connected to the input signal, and the capacitor is connected to the common-mode voltage and the input signal respectively through the two ends of the switch, so the input signal is sampled.

[0036] During the CDAC setup phase, sampling switch U1 is open, and the capacitor control switch is connected to the reference voltage under the control of the logic unit. The entire capacitor array undergoes charge redistribution. When CDAC setup is complete, a voltage Vout is passed to comparator U2. The above operation is repeated until a data conversion is completed.

[0037] As can be seen from the above description and the accompanying drawings, the present invention has the following advantages:

[0038] 1. It can effectively match impedance, optimize the impedance matching problem of low-weight capacitor array and bridging capacitor, thereby optimizing the delay in the CDAC establishment process.

[0039] 2. It can effectively reduce the setup time required for the circuit.

[0040] 3. The overall structure is simple and easy to lay out, and it can be effectively applied to various circuits.

[0041] Furthermore, the orientations or positional relationships described in this invention are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the purpose of facilitating the description of this invention and simplifying the description, and are not intended to indicate or imply that the device or structure referred to must have a specific orientation, or to operate in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0042] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "setup," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, it can be directly on another component or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to that other component or indirectly connected to it.

[0043] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A capacitive digital-to-analog converter, including a sampling switch, characterized in that: The sampling switch is connected to a logic control module via a comparator. A high-weight array and a low-weight array are also connected to the sampling switch, and the high-weight array and low-weight array are connected by a bridging section. The high-weight array is composed of several capacitors and switches with on-resistance, and the low-weight array is also composed of several capacitors and switches with on-resistance. The bridging section is composed of a capacitor and at least one normally closed switch. An input signal V is connected to the lower ends of both the high-weight array and the low-weight array. in Reference signal V REF One type of grounding; The high-weighted array uses a capacitor whose upper end is connected to a common-mode signal and the left end of a bridge section via a sampling switch. The upper end of the capacitor is connected to a comparator, and the lower end is connected to a corresponding switch. This switch, under the control of the logic control module, selects the input signal V. in Or the reference signal V REF The high-weight array includes capacitors C7, C6, C5, and C4. Switch S7 is connected to capacitor C7, switch S6 is connected to capacitor C6, switch S5 is connected to capacitor C5, and switch S4 is connected to capacitor C4. The low-weight array uses a capacitor whose upper end is connected to the right end of the bridging section, and whose lower end is connected to a corresponding switch. This switch, under the control of the logic control module, selects the input signal V. in Or the reference signal V REF The low-weight array includes capacitors C3, C2, C1, and C0. Switch S3 is connected to capacitor C3, switch S2 is connected to capacitor C2, switch S1 is connected to capacitor C1, and switch S0 is connected to capacitor C0. The bridging portion includes a capacitor C. B The capacitor C B A switch S is connected to one side. B The switch S B The capacitor C remains in the on state. B The other side is connected to a high-weight array, the switch S B Connect the low-weight array.

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