Methods of processing substrates and methods of forming 3D NAND devices

Abstract

A method of processing a substrate includes forming a trench through the substrate, depositing a polysilicon layer on sidewalls of the trench, and oxidizing uncovered surfaces of the polysilicon with an oxidizing agent. The oxidizing agent causes formation of an oxide layer having a uniform thickness on the uncovered surfaces of the polysilicon. The method includes removing the oxide layer from the trench with a removal agent, and repeating the steps of oxidizing uncovered surfaces and removing the oxide layer until a predetermined amount of the polysilicon layer is removed.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefits of U.S. Provisional Application No. 63 / 002,771, filed March 31, 2020, and U.S. Non-Provisional Application No. 17 / 121,546, filed December 14, 2020, which are hereby incorporated herein by reference. Technical Field

[0003] The present invention generally relates to a method for etching silicon, and in a particular embodiment, to a method for pseudo-atomic layer etching of silicon-based materials. Background Technology

[0004] Around 2013, planar NAND flash memory reached the physical limits of miniaturization with a 193 nm immersion system. To continue improving performance and meeting bit requirements, the industry turned to 3D designs incorporating high aspect ratio structures with more than 128 layers. The integration of this 3D architecture brought many new challenges.

[0005] The shift from planar to vertical integration has introduced some demanding etching requirements in 3D NAND manufacturing processes. Traditional 3D NAND devices consist of multiple layers of non-volatile transistors stacked and interconnected via vertical channels. As design density increases, the aspect ratio increases due to the addition of extra non-volatile transistors within the word line stack. This increase in aspect ratio presents a fundamental challenge to the definition of the polysilicon transistor channel within the vertical channel. Summary of the Invention

[0006] A method of processing a substrate, the method comprising: forming a trench through the substrate; depositing a polysilicon layer on the sidewalls of the trench; oxidizing an uncovered surface of the polysilicon with an oxidant, the oxidant causing the formation of an oxide layer having a uniform thickness on the uncovered surface of the polysilicon; removing the oxide layer from the trench with a removal agent; and repeating the steps of oxidizing the uncovered surface and removing the oxide layer until a predetermined amount of the polysilicon layer has been removed.

[0007] A method for processing a substrate, the method comprising: forming a silicon-based material layer having a first thickness on a semiconductor substrate; growing an oxidized silicon-based material layer on the silicon-based material layer by wetting the silicon-based material layer with an oxidizing solution; etching the oxidized silicon-based material layer by wetting the oxidized silicon-based material layer with an oxide etching solution; and repeating the growth and etching steps until the silicon-based material layer has a second thickness lower than a predetermined thickness.

[0008] A method for forming a 3D NAND device, the method comprising: forming a channel in a 3D NAND dielectric stack; depositing a polysilicon layer having a first thickness on the sidewalls of the channel; performing a cyclic etching process, wherein each cycle includes forming an oxide layer on the polysilicon layer by wetting an exposed surface of the polysilicon layer with a first solution containing an oxidant, and removing the oxide layer from the polysilicon layer with a second solution containing an oxide etchant; and wherein the cyclic etching process is terminated after the polysilicon layer has a second thickness on the sidewalls of the channel, the second thickness being a predetermined thickness lower than the first thickness.

[0009] A method for processing a substrate includes: depositing a silicon-based material layer on the substrate; oxidizing an uncovered surface of the silicon-based material with an oxidant, the oxidant causing the formation of an oxide layer having a uniform thickness on the uncovered surface of the silicon-based material; removing the oxide layer from the silicon-based material with a removal agent; and repeating the steps of oxidizing the uncovered surface and removing the oxide layer until a predetermined amount of the silicon-based material layer has been removed. Attached Figure Description

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A It is a projected view through a cross section of a 3D-NAND memory array formed according to an embodiment of the present invention;

[0012] Figure 1B This is a cross-sectional view through a stack of memory transistors in a 3D-NAND memory array formed according to an embodiment of the present invention;

[0013] Figures 2A to 2J This is a cross-sectional view of the main fabrication steps for forming polysilicon transistor channels in the channel openings of a 3D NAND memory array;

[0014] Figure 3 It is a description Figures 2A to 2J The flowchart of the processing steps.

[0015] Figure 4 This is a cross-sectional view through a fully depleted silicon-on-insulator (FDSOI) transistor formed according to an embodiment of the present invention;

[0016] Figures 5A to 5H This is a cross-sectional view of the main fabrication steps for forming a channel in a fully depleted type silicon-on-insulator (FDSOI) transistor; and

[0017] Figure 6 It is a description Figures 5A to 5H The flowchart of the processing steps. Detailed Implementation

[0018] Various embodiments provide a self-limiting etching method with atomic-level precision. The etching techniques described herein are applicable to many different semiconductor device fabrication schemes and can be used in any integration scheme that includes silicon-based etching. For example, the etching techniques described herein can be used to etch layers or structures of single-crystal silicon, polycrystalline silicon, and any other silicon-containing layers that can be oxidized. Although the etching techniques described herein can be applied to many different etching schemes, for the sake of convenience in describing the embodiments herein, the discussion will focus primarily on two example cases—regarding the etching of polycrystalline silicon in 3D memory architectures and the application of etching single-crystal silicon in planar fully depleted type silicon-on-insulator (FDSOI) integrated circuits. However, the embodiments of this application can be applied not only to other types of 3D stacked memories and logic devices, but also to the formation of other high aspect ratio features, such as vias and deep trench structures.

[0019] 3D architectures present unique challenges due to the topology of 3D structures. Controlling the channel thickness of polysilicon transistors and the uniformity within these high aspect ratio vertical channels is crucial for maintaining transistor performance and reducing inter-transistor variability. The various embodiments described in this disclosure enable chip manufacturers to tightly control polysilicon etching with atomic-level precision.

[0020] A challenge of FDSOI architecture is the need to form very thin and highly uniform single-crystal silicon channels. In fully depleted type silicon-on-insulator (FDSOI) transistors, thin single-crystal silicon layers form the FDSOI transistor channels. Controlling the thickness and uniformity of the FDSOI transistor channels is crucial for maintaining FDSOI transistor performance and reducing inter-transistor variability. The various embodiments described in this disclosure enable chip manufacturers to precisely control the single-crystal silicon etching of the FDSOI transistor channels with atomic-level precision.

[0021] Although the embodiments are described in the specific context of 3D NAND and FDSOI applications, the various embodiments can be applied to any silicon-based etching in semiconductor manufacturing. Accordingly, the various embodiments disclose etching of silicon-based materials with atomic-level precision and control in semiconductor manufacturing processes. The various embodiments provide an etching method that is self-limiting and independent of etchant concentration (non-transport-limited), thereby achieving atomic-level control.

[0022] Increasing the density of 3D NAND device designs is achieved by increasing the number of layers in the 3D NAND stack. Each set of layers forms a separate non-volatile memory transistor. In the past few years, the number of layers in the word line stack has increased from 32 to 64, and future architectures may include 128 layers or even higher. These layers typically consist of alternating polysilicon and oxide layers or alternating dielectric material layers (such as silicon dioxide and silicon nitride).

[0023] The first embodiment of the pseudo-atom-layer silicon substrate etching process will be described using a cross-sectional view of the 3D NAND structure shown in Figure 1. This structure is used... Figures 2A to 2J as well as Figure 3 The flowchart was created using [the provided text]. Next, we will use [the provided text]... Figure 4 The cross-sectional view of the FDSOI structure shown illustrates a second embodiment of the etching process for a pseudo-atomic layer silicon substrate material, which uses... Figures 5A to 5H as well as Figure 6 The flowchart was created.

[0024] Figure 1A A projected view showing a cross section through a 3D-NAND memory array formed according to an embodiment of the present invention is shown. Figure 1B A cross-sectional view of an exemplary 3D NAND word line stack consisting of alternating metal gates (word lines 106) and silicon dioxide 104, formed according to an embodiment of the present invention, is shown.

[0025] Figure 1A A semiconductor substrate 102 with a common drain bit line 114 is shown. This cross-section shows alternating layers of dielectric material (e.g., silicon dioxide 104) that electrically isolate word line layers 106, for example, made of tungsten. For example, the tungsten-containing word line 106 is an alternating metal gate of a stacked memory transistor in a 3D NAND array. A common source bit line 122 (e.g., containing polysilicon) spans the top surface of the 3D NAND memory array perpendicular to the word line 106 (metal gate). Drain bit line 114 and source bit line 122 are connected to a thin transistor channel 126 (e.g., on the sidewall of channel 130) on the channel 130. Figure 1B As shown, these thin transistor channels are made of, for example, polysilicon. The memory transistors in word line layer 106 all share a common source bit line 122 and a common drain bit line 114.

[0026] In Figure 1B In China and subsequently in Figures 2A to 2J The cross-sectional view shown in the image is created by [author's name - likely a typo]. Figure 1A The dashed box 100 in the middle is used to depict this.

[0027] Each SONOS transistor includes a metal gate (word line 106) (e.g., containing tungsten), which is isolated from the transistor channel 126 (e.g., containing polysilicon) via a gate dielectric 108. Although sometimes referred to as a SONOS transistor, each SONOS transistor is a metal / oxide / nitride / oxide / silicon (MONOS) stack. During programming, electrons can be trapped in the silicon nitride layer within the gate dielectric 108. The trapped electrons increase the turn-on voltage of the SONOS non-volatile transistor. SONOS transistors with electrons trapped in the silicon nitride layer store a logic state "1", while SONOS transistors without trapped electrons store a logic state "0". These logic states can be retained for 10 years or more, even when the 3D NAND memory is not connected to a power source.

[0028] In the word line stack, multiple SONOS transistors are stacked one on top of another. The metal gate (word line 106) of one SONOS transistor is isolated from the other non-volatile SONOS transistors stacked above and below it by a silicon dioxide layer 104. The SONOS transistor stack shares a common source terminal 112 and also shares a common drain terminal 116. A thin layer 110 of lightly doped polysilicon (e.g., doped to a degree of 10) is also present. 14 cm -3 Up to 10 17 cm -3 The lightly doped polysilicon layer 110 forms a channel 126 for stacked SONOS transistors in a 3D NAND memory array. The lightly doped polysilicon layer 110 can be in situ doped with an n-type dopant to form an n-channel transistor. One end of the lightly doped polysilicon layer 110 is shorted to a common source bit line 122, and the other end of the lightly doped polysilicon layer 110 is shorted to a common drain bit line 114.

[0029] During operation, a voltage can be applied to the common drain bit line 114 (drain terminal 116), while the common source bit line 122 (source terminal 112) remains grounded. By turning on one of the gate select transistors 120, the voltage on the gate terminal 118 can be connected to one of the metal gates (word lines 106). If the SONOS transistor is programmed to zero (no trapped electrons), the polysilicon channel will be on, and additional current will flow through the transistor's channel 126. However, if the SONOS transistor is programmed to one (trapped electrons), the channel 126 will remain off, and no additional current will flow. In a 3D NAND memory array, the variability from one SONOS transistor to the next depends on the thickness uniformity of the lightly doped polysilicon transistor channel 126 from one SONOS transistor to the next.

[0030] As described in the various embodiments herein, a uniform, lightly doped polysilicon transistor channel 126 is formed using a cyclic self-limiting deposition and etching process, such as when using Figures 2A to 2J and Figure 3 Further description.

[0031] Now for reference Figure 2A The image shows a cross-sectional view through a 3D NAND substrate 300. Alternating silicon dioxide dielectric layers 104 and silicon nitride dielectric layers 124 are stacked on top of a semiconductor substrate 102. During this fabrication stage, the semiconductor substrate 102 includes multiple device regions, including active transistor regions associated with array programming and logic transistors, and a drain bit line 114, which is formed as a diffusion region within the semiconductor substrate 102 and forms a common bit line for the 3D NAND memory.

[0032] although Figure 2A The diagram shows six alternating layers, but 3D NAND memories can have more than one hundred alternating layers. A trench pattern 128 is formed on the 3D NAND substrate (step 140). Figure 3 The channel pattern has openings that expose the surface of the dielectric stack, through which the channels will be etched.

[0033] As in the following Figure 2B As shown, (step 142, Figure 3 After forming the channel pattern 128 using a photolithography process, a channel 130 is formed through the stacked silicon dioxide dielectric layer 104 and silicon nitride dielectric layer 124. The channel pattern 128 may include a hard mask layer that is resistant to etching in subsequent plasma etching processes. For example, in one embodiment, the channel pattern 128 may include a metal nitride, such as a titanium nitride layer.

[0034] The channel 130 stops on the diffusion region of the bit line 114 in the underlying semiconductor substrate 102 or etch stop layer. The channel 130 can be formed using a plasma etching process within a plasma tool. In various embodiments, the plasma etching process forms a trench with substantially vertical sidewalls. In embodiments, the plasma etching process may include a cyclic process designed to alternately etch alternating layers of silicon dioxide 104 and silicon nitride 124. Alternatively, the plasma etching process may include plasma etching adapted to have the same selectivity for etching silicon dioxide and silicon nitride, and the plasma etching process stops etching on the underlying semiconductor substrate 102.

[0035] In various embodiments, the channel 130 may have an aspect ratio of 50:1 to 100:1. In further embodiments, the channel 130 may have an aspect ratio greater than 100:1, for example, up to 500:1. Any remaining channel pattern 128 is removed after channel etching.

[0036] exist Figure 2C In step 144, after depositing the SONOS gate dielectric 108, a lightly doped polysilicon layer 110 is deposited. Figure 3 The SONOS gate dielectric 108 is deposited to have a uniform thickness on the vertical sidewalls of the channel 130. In various embodiments, the SONOS gate dielectric 108 can be formed using an atomic layer deposition process. Alternatively, the SONOS gate dielectric 108 can be formed using other deposition processes, including chemical vapor deposition, plasma deposition, etc.

[0037] In various embodiments, the SONOS gate dielectric 108 has a thickness of about 2 nm to about 10 nm. In one embodiment, the SONOS gate dielectric 108 comprises an oxide / nitride / oxide (ONO) stack. In another embodiment, the gate dielectric 108 comprises a high-k dielectric / nitride / oxide stack.

[0038] In various embodiments, the polysilicon layer 110 is typically deposited using a deposition process (e.g., chemical vapor deposition (CVD) process) capable of covering the surface of the 3D-NAND substrate 101 and covering the SONOS gate dielectric 108 with polysilicon of uniform thickness (step 144). Figure 4 In various embodiments, the polysilicon layer 110 is in-situ doped to a doping concentration of 10. 14 cm -3 Up to 10 18 cm -3 Furthermore, it can be doped with phosphorus to form the n-type.

[0039] As previously mentioned Figure 1B The polysilicon layer 110 discussed must be very thin. Thinning avoids degradation and runaway in the thin-film transistor and improves the subthreshold characteristics of the transistor. In various embodiments, the polysilicon layer 110 may be deposited slightly thicker than required and then thinned according to the requirements of the SONOS transistor using the pseudo-atomic layer silicon etching process of the embodiments. In various embodiments, the thinned polysilicon layer 110 is from about 5 nm to about 50 nm, for example, between 10 nm and 20 nm in one embodiment.

[0040] Typically, the polysilicon layer 110 must be thinned via a wet etching process. However, the large aspect ratio of the channel 130 (e.g., 50:1 to 500:1) poses a significant challenge to current etching solutions (such as tetramethylammonium hydroxide (TMAH)) because etching with TMAH becomes transport-limited, resulting in an etching rate hampered by the concentration at the bottom of the channel. Limited evacuation of reaction byproducts and restricted etchant replenishment can lead to uneven thinning of the polysilicon layer 110, thereby impairing device performance. For example, the thickness of the polysilicon layer 110 may be greater at the bottom of the channel 130 and smaller at the top.

[0041] Embodiments of this application overcome these limitations by using a self-limiting cycling process. (Reference) Figure 2D The 3D-NAND substrate 101 is wetted by immersing it in a bath of oxidizing solution 132, which then penetrates into the channel 130 due to surface tension (step 146). Figure 3 Alternatively, a wet jet etching tool is used to wet the surface of the polysilicon layer 110 with an oxidizing solution 132. In one embodiment, the oxidizing solution 132 may be hydrogen peroxide in water, with a concentration ranging from 1% to 30% by weight. In another embodiment, the oxidizing solution 132 may include ozone.

[0042] When the oxidizing solution 132 comes into contact with the surface of the polycrystalline silicon layer 110, the oxidizing solution 132 rapidly oxidizes the surface to form an oxide layer 134 (step 146). Figure 3 The thickness of the formed oxide layer 134 is self-limiting and independent of the etchant concentration (non-transport-limited), thus achieving atomic-level control. Specifically, the oxide layer 134 forms a diffusion barrier against the diffusion of the oxidizing solution 132 and the diffusion of silicon atoms from the polysilicon layer 110. This prevents further oxidation after all exposed surfaces of the polysilicon layer 110 are covered by the oxide layer 134. Once the surface of the polysilicon layer 110 is covered by the oxide layer 134, additional oxidizing solution 132 (e.g., hydrogen peroxide) is blocked from the surface of the polysilicon layer 110, and additional oxidation of the surface of the polysilicon layer 110 is effectively stopped.

[0043] To facilitate complete filling of the high aspect ratio channel 130 with the oxidizing solution 132, the 3D-NAND substrate 101 can first be cleaned with carbon dioxide. For example, high-pressure carbon dioxide gas can be directed toward the surface of the 3D-NAND substrate 101. The expansion of the carbon dioxide gas causes it to cool and condense into solid carbon dioxide, which is deposited on the surfaces of the 3D-NAND substrate 101 and the channel 130. The heated solid carbon dioxide sublimates, increasing in volume by up to 800 times. During this process, the carbon dioxide loosens and sweeps away particles.

[0044] refer to Figure 2F Remove oxidizing solution 132 (step 148, Figure 3 The 3D-NAND substrate 101 can be rinsed with a solvent to help remove the oxidizing solution 132. In various embodiments, the 3D-NAND substrate 101 is rinsed by immersion in a bath or by rinsing with a solvent in a wet jet etching tool. In one embodiment, the solvent is deionized water.

[0045] As follows Figure 2G As shown, the 3D-NAND substrate 101 is exposed to oxide removal agent 136 (step 150, Figure 3 In the illustration, oxide remover 136 wets oxide layer 134. Oxide remover 136 may be hydrogen fluoride diluted in water to a concentration ranging from 0.1% by weight to 10% by weight. Once oxide layer 134 is removed, the underlying polysilicon layer 110 is exposed and etching stops. Advantageously, the oxide remover is selected to not etch polysilicon layer 110.

[0046] Figure 2H This demonstrates the removal of oxide layer 134 using oxide remover 136 (step 150). Figure 3 The 3D-NAND substrate 101 follows.

[0047] refer to Figure 2I Oxide removal agent 136 (step 152) Figure 3 The 3D-NAND substrate 101 can then be rinsed with a solvent to help remove the oxide remover 136. In various embodiments, the 3D-NAND substrate 101 is rinsed by immersion in a bath or by rinsing with a solvent in a wet jet etching tool. In one embodiment, the solvent is deionized water.

[0048] Steps 146 to 152 can be repeated multiple times as needed to remove the polysilicon layer 110 of a predetermined thickness (step 154, Figure 3During each cycle of wetting the surface of the polysilicon layer 110 with the oxidizing solution 132, the silicon atom surface layer is transformed into an oxide layer 134 (e.g., silicon dioxide). This silicon atom surface layer is then removed when the oxide layer 134 is etched away with an oxide remover 136. By repeating steps 146 to 152, one layer of silicon atoms is removed at a time in a highly controlled and uniform manner, while simultaneously reducing the surface roughness of the remaining polysilicon layer 110. By removing the polysilicon layer 110 of a predetermined thickness in this controlled and uniform manner, the performance of SONOS transistors in a 3D-NAND memory array can be precisely targeted, and variations between SONOS transistors can be kept to a minimum. In various embodiments, the predetermined thickness of the polysilicon layer 110 can be selected to achieve a target surface roughness or target thickness uniformity of the polysilicon layer 110. In one exemplary embodiment, the predetermined thickness of the polysilicon layer 110 can be a portion of the initial thickness of the polysilicon layer 110, for example, 5% to 20% of the initial thickness of the polysilicon layer 110.

[0049] After the polysilicon layer 110 is thinned to meet specifications, additional processing can be performed to build... Figure 1A and Figure 1B The 3D NAND structure depicted includes the following additional processing: replacing silicon nitride 124 with CVD tungsten to form the gate of a SONOS transistor, forming a bit line by forming a common source bit line 122 and an electrical connection to the source terminal 112, forming a common drain bit line 114 and an electrical connection to the drain terminal 116, forming an electrical connection to the gate terminal 118, and forming a gate select transistor 120.

[0050] Figure 4 A cross-section is shown through a fully depleted silicon-on-insulator (FDSOI) transistor 200 formed according to an embodiment of this application.

[0051] A buried oxide (BOX) layer 204 isolates the channel formed in the monocrystalline silicon 206 of the transistor from the underlying substrate 202. The monocrystalline silicon 206 in the FDSOI transistor 200 is a very thin monocrystalline silicon layer, typically less than 150 nm. In FDSOI transistors with ultrathin channels, the silicon can be 25 nm or smaller. The transistor gate 210 is isolated from the channel in the monocrystalline silicon 206 by a gate dielectric 208. The silicon regions adjacent to the transistor channel in the monocrystalline silicon 206 are heavily doped to form the transistor source 214 and transistor drain 216. A shallow trench isolation 212 electrically isolates the FDSOI transistor 200 from adjacent transistors and other semiconductor devices in the substrate 202. The performance of the FDSOI transistor is highly sensitive to the thickness of the channel formed in the monocrystalline silicon 206. The inter-transistor variability of the FDSOI transistors is highly sensitive to the thickness variation of the transistor channel in the monocrystalline silicon 206 from one FDSOI transistor to the next.

[0052] The performance of a fully depleted type silicon-on-insulator (FDSOI) transistor 200 is highly sensitive to the thickness of the thin channel formed in single-crystal silicon 206. Variations between FDSOI transistors 200 are sensitive to changes in the thickness of the transistor channel in single-crystal silicon 206 from one transistor to another. The thickness of the single-crystal silicon 206 in an FDSOI transistor 200 is typically less than 150 nm. In ultrathin FDSOI transistors, the single-crystal silicon 206 can be 25 nm or less.

[0053] As further described, embodiments of the present invention can be applied to control the thickness uniformity of thin monocrystalline silicon 206.

[0054] Thin-film transistors (TFTs) with polysilicon channels can also be fabricated. These TFTs are used, for example, in liquid crystal displays. These transistors with polysilicon channels are formed on an insulating substrate and, depending on the thickness of the polysilicon channel, exhibit characteristics similar to partially depleted-type silicon-on-insulator (PDSOI) transistors or fully depleted-type silicon-on-insulator (FDSOI) transistors. Like PDSOI and FDSOI transistors with monocrystalline silicon transistor channels, the performance of TFTs with polysilicon channels is highly sensitive to the thickness and uniformity of the polysilicon transistor channel. The techniques used to control the thickness and uniformity of the polysilicon transistor channel at atomic levels are also applicable to polysilicon TFT transistors.

[0055] Figure 5AA cross-sectional view through a fully depleted type silicon-on-insulator (FDSOI) substrate 202 is shown. The electrically isolated single-crystal silicon 206 forming the transistor channel of the FDSOI transistor can then be thinned with extremely high precision using an etching process on a pseudo-atomic layer silicon substrate material as described in this embodiment. In this way, the thickness of the transistor channel in the single-crystal silicon 206 can be reduced to the final thickness required for the performance of the FDSOI transistor.

[0056] The FDSOI transistor channel pattern 128 can be formed on the FDSOI substrate 202, exposing the channel region in the single-crystal silicon 206 of one FDSOI transistor without exposing the transistor channel regions of other FDSOI transistors. In this way, the thickness of the single-crystal silicon 206 can be etched to different thicknesses for different FDSOI transistors to fabricate FDSOI transistors with different performance characteristics (step 230). Figure 6 ).

[0057] exist Figure 5B In step 232, the surface of the single-crystal silicon channel is wetted with oxidizing solution 132. Figure 6 ).

[0058] exist Figure 5C In step 232, an oxide layer 220, such as silicon dioxide, is formed on the monocrystalline silicon 206 by exposing it to an oxidizing solution 132. Figure 6 The FDSOI substrate 202 can be wetted by immersing it in a bath of oxidizing solution 132. Alternatively, the surface of the monocrystalline silicon 206 can be wetted with oxidizing solution 132 using a wet jet etching tool. Oxidizing solution 132 can be hydrogen peroxide in water, with a concentration ranging from approximately 1% to 30% by weight. When hydrogen peroxide comes into contact with the surface of the monocrystalline silicon 206, it rapidly oxidizes the surface to form an oxide layer 220. The formed oxide layer 220 is self-limiting. Once the surface of the monocrystalline silicon 206 is covered by the oxide layer 220, additional hydrogen peroxide is blocked from the surface, and additional oxidation of the surface of the monocrystalline silicon 206 is effectively stopped. Advantageously, oxidation may smooth protrusions or trenches on the surface of the monocrystalline silicon 206 and reduce the surface roughness of the monocrystalline silicon 206.

[0059] exist Figure 5D Remove oxidizing solution 132 (step 234) Figure 6 The FDSOI substrate 202 can be rinsed with a solvent to help remove the oxidizing solution 132. The substrate can be rinsed by immersing it in a bath or by rinsing it with a solvent in a wet jet etching tool. This solvent is typically deionized water.

[0060] Figure 5EThe FDSOI substrate 202 is shown with oxide layer 220 exposed to oxide remover 136 (step 236). Figure 6 In the illustration, oxide remover 136 is wetting oxide layer 220.

[0061] Figure 5F This illustrates the FDSOI substrate 202 after etching the surface oxide layer 220 from the surface using oxide remover 136 (step 236). Figure 6 The oxide remover 136 can be hydrogen fluoride in water, with a concentration ranging from approximately 0.1% to 10% by weight. Once the oxide layer 220 is removed, the underlying monocrystalline silicon 206 is exposed and etching stops. The oxide remover 136 does not etch the monocrystalline silicon 206.

[0062] exist Figure 5G In the process of removing oxides, 136 (step 238) is used to remove oxides. Figure 6 The FDSOI substrate 202 can be rinsed with a solvent to help remove the oxide remover 136. The substrate can be rinsed by immersing it in a bath or by rinsing it with a solvent in a wet jet etching tool. This solvent is typically deionized water.

[0063] Steps 232 to 238 can be repeated multiple times as needed to remove SOI single-crystal silicon 206 of a predetermined thickness (step 240, Figure 6 Each time the surface of the SOI single-crystal silicon 206 is wetted by the oxidizing solution 132, the silicon atom surface layer is transformed into an oxide layer 220. Then, when the oxide layer 220 is exposed to the oxide removal agent 136, the silicon atom surface layer is removed. By repeating steps 232 to 238, one silicon atom surface layer is removed at a time in a highly controlled manner. By removing the SOI single-crystal silicon 206 of a predetermined thickness in this tightly controlled and uniform manner, the performance of FDSOI transistors can be precisely targeted, and variations between FDSOI transistors can be kept to a minimum.

[0064] After thinning SOI single-crystal silicon 206 to meet specifications, additional processing can be performed to produce... Figure 4 The FDSOI transistor 200 shown includes additional processing including depositing a gate dielectric 208, depositing and etching the FDSOI transistor gate 210, and doping the source 214 and drain 216.

[0065] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims set forth herein.

[0066] Example 1. A method of processing a substrate, the method comprising: forming a trench through the substrate; depositing a polysilicon layer on the sidewalls of the trench; oxidizing an uncovered surface of the polysilicon with an oxidant, the oxidant causing the formation of an oxide layer having a uniform thickness on the uncovered surface of the polysilicon; removing the oxide layer from the trench with a removal agent; and repeating the steps of oxidizing the uncovered surface and removing the oxide layer until a predetermined amount of the polysilicon layer has been removed.

[0067] Example 2. The method as described in Example 1, wherein the uncovered surface is oxidized with a solution containing the oxidant.

[0068] Example 3. The method as described in either Example 1 or 2, wherein the remover comprises a solution containing HF.

[0069] Example 4. The method as described in any one of Examples 1 to 3, wherein forming the channel, as part of the NAND memory fabrication process, includes forming the channel through a stack consisting of alternating layers of dielectric material.

[0070] Example 5. The method described in any one of Examples 1 to 4, wherein the channel has an aspect ratio greater than 50:1.

[0071] Example 6. The method as described in any one of Examples 1 to 5, wherein the oxidant comprises an aqueous solution of hydrogen peroxide.

[0072] Example 7. A method of processing a substrate, the method comprising: forming a silicon-based material layer having a first thickness on a semiconductor substrate; growing an oxidized silicon-based material layer on the silicon-based material layer by wetting the silicon-based material layer with an oxidizing solution; etching the oxidized silicon-based material layer by wetting the oxidized silicon-based material layer with an oxide etching solution; and repeating the growth and etching steps until the silicon-based material layer has a second thickness less than a predetermined thickness.

[0073] Example 8. The method as described in Example 7, wherein the silicon-based material is polycrystalline silicon or monocrystalline silicon.

[0074] Example 9. The method as described in any one of Examples 7 or 8 further includes forming a pattern on the silicon-based material before growing the oxidized silicon-based material layer on the exposed area of ​​the silicon-based material.

[0075] Example 10. The method of any one of Examples 7 to 9 further includes rinsing the oxidized silicon-based material with a first rinsing solution before etching the oxidized silicon-based material, and rinsing the silicon-based material with a second rinsing solution after etching away the oxidized silicon-based material.

[0076] Example 11. The method as described in any one of Examples 7 to 10, wherein the first rinse solution and the second rinse solution are deionized water.

[0077] Example 12. The method as described in any one of Examples 7 to 11, wherein the oxidizing solution is hydrogen peroxide in water at a concentration between about 1% by weight and 30% by weight.

[0078] Example 13. The method as described in any one of Examples 7 to 12, wherein the oxide etching solution is hydrogen fluoride in water at a concentration between about 0.1% by weight and 10% by weight.

[0079] Example 14. The method as described in any one of Examples 7 to 13, wherein the silicon-based material is wetted with the oxidizing solution by immersing it in a first bath, and the oxidized silicon-based material layer is wetted with the oxide etching solution by immersing it in a second bath.

[0080] Example 15. The method as described in any one of Examples 7 to 14, wherein the silicon-based material is wetted with the oxidizing solution by immersing it in a bath, and the oxidized silicon-based material layer is wetted with an oxide etching solution in a wet jet etching tool.

[0081] Example 16. The method as described in any one of Examples 7 to 15, wherein the silicon-based material is wetted with an oxidizing solution in a wet jet etching tool, and the oxidized silicon-based material layer is wetted with an oxide etching solution in the wet jet etching tool.

[0082] Example 17. A method of forming a 3D NAND device, the method comprising: forming a channel in a 3D NAND dielectric stack; depositing a polysilicon layer having a first thickness on a sidewall of the channel; performing a cyclic etching process, wherein each cycle comprises forming an oxide layer on the polysilicon layer by wetting an exposed surface of the polysilicon layer with a first solution containing an oxidant, and removing the oxide layer from the polysilicon layer with a second solution containing an oxide etchant; and wherein the cyclic etching process is terminated after the polysilicon layer has a second thickness on the sidewall of the channel, the second thickness being a predetermined thickness lower than the first thickness.

[0083] Example 18. The method of Example 17 further includes rinsing the oxidized silicon-based material with deionized water before etching the oxidized silicon-based material, and rinsing the silicon-based material with deionized water after etching away the oxidized silicon-based material.

[0084] Example 19. The method as described in one of Examples 17 or 18, wherein the first solution is hydrogen peroxide in water at a concentration between about 1% by weight and 30% by weight.

[0085] Example 20. The method as described in any one of Examples 17 to 19, wherein the second solution is hydrogen fluoride in water at a concentration between about 0.1% by weight and 10% by weight.

[0086] Example 21. A method of processing a substrate, the method comprising: depositing a silicon-based material layer on the substrate; oxidizing an uncovered surface of the silicon-based material with an oxidant, the oxidant causing the formation of an oxide layer having a uniform thickness on the uncovered surface of the silicon-based material; removing the oxide layer from the silicon-based material with a removal agent; and repeating the steps of oxidizing the uncovered surface and removing the oxide layer until a predetermined amount of the silicon-based material layer has been removed.

[0087] Example 22. The method as described in Example 21, wherein the uncovered surface is oxidized with a solution containing the oxidant.

[0088] Example 23. The method as described in either Example 21 or 22, wherein the oxidant comprises an aqueous solution of hydrogen peroxide.

[0089] Example 24. The method as described in any one of Examples 21 to 23, wherein the remover comprises a solution containing HF.

[0090] Example 25. The method of any one of Examples 21 to 24 further includes forming a transistor, wherein the silicon-based material is the channel of the transistor.

[0091] Example 26. The method as described in any one of Examples 21 to 25, wherein the transistor is a silicon-on-insulator (SOI) transistor having a single-crystal silicon channel.

[0092] Example 27. The method as described in any one of Examples 21 to 26, wherein the SOI transistor is a fully depleted SOI transistor or a partially depleted SOI transistor.

[0093] Example 28. The method as described in any one of Examples 21 to 27, wherein the transistor is a polycrystalline silicon thin-film transistor (TFT).

[0094] Example 29. The method as described in any one of Examples 21 to 28, wherein the transistor is a NAND non-volatile transistor having a polysilicon transistor channel.

[0095] Example 30. The method as described in any one of Examples 21 to 29, wherein a polysilicon transistor channel is formed on the sidewall of the channel in a 3D NAND memory array.

[0096] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations thereof will be apparent to those skilled in the art from the description, illustrative embodiments, and other embodiments of the invention. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, the method comprising: A high aspect ratio channel is formed through the substrate, the high aspect ratio channel having an aspect ratio greater than 50:1; A polycrystalline silicon layer is deposited on the sidewall of the high aspect ratio channel; An oxidant is delivered into the high aspect ratio channel to oxidize the uncovered surface of the polysilicon layer, the oxidant causing the formation of an oxide layer with a uniform thickness on the uncovered surface of the polysilicon layer; A removal agent is delivered into the high aspect ratio channel to remove the oxide layer from the high aspect ratio channel; as well as Repeat the steps of oxidizing the uncovered surface and removing the oxide layer until a predetermined amount of the polysilicon layer has been removed.

2. The method as described in claim 1, wherein, The uncovered surface is oxidized using a solution containing the oxidant.

3. The method as described in claim 1, wherein, The remover includes a solution containing HF.

4. The method of claim 1, wherein, As part of the NAND memory manufacturing process, forming the high aspect ratio channel involves forming the channel through a stack of alternating layers of dielectric material.

5. The method of claim 1, wherein, The oxidant includes an aqueous solution of hydrogen peroxide.

6. The method of claim 1, wherein, The oxidant includes a solution containing ozone.

7. The method of claim 1, wherein, The polycrystalline silicon is doped with phosphorus.

8. The method of claim 1, further comprising rinsing the oxide layer with deionized water before removing the oxide layer.

9. The method of claim 1, further comprising rinsing the polycrystalline silicon with deionized water after removing the oxide layer.

10. The method of claim 1, wherein, After removing the predetermined amount of polysilicon layer, the final thickness of the polysilicon layer on the sidewall is 5 nm to 50 nm.

11. A method for forming a 3D NAND device, the method comprising: High aspect ratio channels are formed in 3D NAND dielectric stacks; A polycrystalline silicon layer of first thickness is deposited on the sidewall of the high aspect ratio channel; Perform a cyclic etching process, wherein each cycle includes: An oxide layer is formed on the polysilicon layer by wetting the exposed surface of the polysilicon layer within the high aspect ratio channel with a first solution containing an oxidant. Rinse the oxide layer with deionized water; The oxide layer within the high aspect ratio channel is removed from the polysilicon layer using a second solution containing an oxide etchant; and The polysilicon layer is rinsed with deionized water, and the cyclic etching process is terminated after the polysilicon layer has a second thickness on the sidewall of the high aspect ratio channel, the second thickness being a predetermined thickness lower than the first thickness.

12. The method of claim 11, wherein, The first solution is hydrogen peroxide in water, with a concentration between 1% and 30% by weight.

13. The method of claim 11, wherein, The second solution is hydrogen fluoride in water, with a concentration between 0.1% by weight and 10% by weight.

14. The method of claim 11, wherein, The exposed surface of the polysilicon layer is wetted with the first solution by immersing it in the first bath, and the oxide layer is wetted with the second solution by immersing it in the second bath.

15. The method of claim 11, wherein, The exposed surface of the polysilicon layer is wetted with the first solution by immersing it in a bath, and the oxide layer is wetted with the second solution in a wet jet etching tool.

16. The method of claim 11, wherein, The exposed surface of the polysilicon layer is wetted with the first solution in the wet jet etching tool, and the oxide layer is wetted with the second solution in the wet jet etching tool.

17. A method for forming a 3D NAND device, the method comprising: High aspect ratio channels are formed in 3D NAND dielectric stacks; A polycrystalline silicon layer of first thickness is deposited on the sidewall of the high aspect ratio channel; Perform a cyclic etching process, wherein each cycle includes An oxide layer is formed on the polysilicon layer by wetting the exposed surface of the polysilicon layer within the high aspect ratio channel with a first solution containing an oxidant, and The oxide layer within the high aspect ratio channel is removed from the polysilicon layer using a second solution containing an oxide etchant; and wherein the cyclic etching process is terminated after the polysilicon layer has a second thickness on the sidewall of the high aspect ratio channel, the second thickness being a predetermined thickness lower than the first thickness.

18. The method of claim 17, further comprising rinsing the oxide layer with deionized water before etching the oxide layer, and rinsing the polysilicon layer with deionized water after etching away the oxide layer.

19. The method of claim 17, wherein, The first solution is hydrogen peroxide in water, with a concentration between 1% and 30% by weight.

20. The method of claim 17, wherein, The second solution is hydrogen fluoride in water, with a concentration between 0.1% by weight and 10% by weight.

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