Pixel driving circuit and driving method thereof, and display panel

Abstract

The embodiments of the present disclosure provide a pixel driving circuit and a driving method thereof, and a display panel, which relate to the field of display technology and are used to prevent the problem of frequency switching flicker of the display panel. The pixel driving circuit includes a driving subcircuit, a writing subcircuit, a compensation subcircuit, a light-emitting control subcircuit and a first reset subcircuit. The driving subcircuit is coupled to the first node, the second node and the third node. The writing subcircuit is coupled to the second node, the first scanning signal terminal and the data signal terminal. The compensation subcircuit is coupled to the first node, the third node and the second scanning signal terminal. The light-emitting control subcircuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light-emitting device. The first reset subcircuit is coupled to the third node, the third scanning signal terminal and the first reference voltage signal terminal, and under the control of the third scanning signal, transmits the first reference voltage received by the first reference voltage signal terminal to the third node to refresh the third node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic Light-Emitting Device (OLED) display is a type of display that is different from traditional Liquid Crystal Display (LCD). It has the advantages of active luminescence, good temperature characteristics, low power consumption, fast response, flexibility, ultra-lightness and low cost, and has been widely used in the display field. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a pixel driving circuit and a driving method thereof, and a display panel, so as to prevent the problem of frequency switching flickering of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a pixel driver circuit is provided. The pixel driver circuit includes a driver subcircuit, a write subcircuit, a compensation subcircuit, a light-emission control subcircuit, and a first reset subcircuit. The driver subcircuit is coupled to a first node, a second node, and a third node. The driver subcircuit is configured to transfer a voltage from the second node to the third node under control of the voltage at the first node. The write subcircuit is coupled to the second node, a first scan signal terminal, and a data signal terminal. The write subcircuit is configured to transfer a data signal received at the data signal terminal to the second node under control of a first scan signal received from the first scan signal terminal during a write phase. The compensation subcircuit is coupled to the first node, the third node, and the second scan signal terminal. The compensation subcircuit is configured to transfer the voltage of the third node to the first node under control of a second scan signal received from the second scan signal terminal during a write phase. The light-emission control subcircuit is coupled to a first voltage terminal, an enable signal terminal, the second node, the third node, and a light-emitting device. The light-emitting control subcircuit is configured to, under control of an enable signal from the enable signal terminal, cooperate with the driver subcircuit to transmit a drive signal to the light-emitting device. A first reset subcircuit is coupled to the third node, the third scan signal terminal, and the first reference voltage signal terminal. The first reset subcircuit is configured to, under control of a third scan signal received from the third scan signal terminal, transmit a first reference voltage received from the first reference voltage signal terminal to the third node, thereby refreshing the third node.

[0006] The aforementioned pixel drive circuit is further provided with a first reset subcircuit. The first reset subcircuit is configured to, under control of the third scan signal received from the third scan signal terminal, transmit the first reference voltage received by the first reference voltage signal terminal to the third node, thereby refreshing the third node. This allows the first reset subcircuit to refresh the potential of the third node prior to the light-emitting phase in the refresh frame and the hold frame, ensuring that the potential at the third node is the same during the light-emitting phase in the refresh frame and the hold frame. This prevents significant brightness differences caused by different potentials at the third node during the frequency switching process between the refresh frame and the hold frame, thereby improving flickering issues that may occur during screen switching.

[0007] In some embodiments, the first reset subcircuit includes a first transistor, a gate of the first transistor being coupled to the third scan signal terminal, a first electrode of the first transistor being coupled to the third node, and a second electrode of the first transistor being coupled to the first reference voltage signal terminal.

[0008] In some embodiments, the driving sub-circuit includes a driving transistor, wherein a gate of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

[0009] In some embodiments, the writing sub-circuit includes a second transistor, wherein a gate of the second transistor is coupled to the first scan signal terminal, a first electrode of the second transistor is coupled to the data signal terminal, and a second electrode of the second transistor is coupled to the second node.

[0010] In some embodiments, the compensation sub-circuit includes a third transistor. The third transistor is a metal oxide transistor. The gate of the third transistor is coupled to the second scan signal terminal, the first electrode of the third transistor is coupled to the first node, and the second electrode of the third transistor is coupled to the third node.

[0011] In some embodiments, the light-emitting control subcircuit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is coupled to the enable signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node. The gate of the fifth transistor is coupled to the enable signal terminal, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the light-emitting device.

[0012] In some embodiments, the first reference voltage signal received at the first reference voltage signal terminal has a value range of 0V to 6.5V.

[0013] In some embodiments, the pixel driving circuit further includes a second reset subcircuit. The second reset subcircuit is coupled to the first node, the first reset signal terminal, and the first initialization signal terminal. The second reset subcircuit is configured to, during a reset phase, under the control of a reset signal received from the first reset signal terminal, transmit the first initialization signal received from the first initialization signal terminal to the first node, thereby resetting the first node.

[0014] In some embodiments, the second reset sub-circuit includes a sixth transistor. The sixth transistor is a metal oxide transistor. The gate of the sixth transistor is coupled to the first reset signal terminal, the first electrode of the sixth transistor is coupled to the first node, and the second electrode of the sixth transistor is coupled to the first initialization signal terminal.

[0015] In some embodiments, the pixel driving circuit further includes a third reset subcircuit. The third reset subcircuit is coupled to the second reset signal terminal, the second initialization signal terminal, and the light-emitting device. The third reset subcircuit is configured to, under control of the reset signal received from the second reset signal terminal, transmit the second initialization signal received from the second initialization signal terminal to the light-emitting device.

[0016] In some embodiments, the third reset subcircuit includes a seventh transistor, a gate of which is coupled to the second reset signal terminal, a first electrode of which is coupled to the light-emitting device O, and a second electrode of which is coupled to the second initialization signal terminal.

[0017] In some embodiments, the second reset signal terminal and the first scan signal terminal respond to control of the same control signal.

[0018] In some embodiments, the pixel driving circuit further includes a first storage subcircuit. The first storage subcircuit is coupled to the first voltage terminal and the first node. The first storage subcircuit includes a first capacitor, a first plate of the first capacitor is coupled to the first voltage terminal, and a second plate of the first capacitor is coupled to the first node.

[0019] In another aspect, a driving method for a pixel driving circuit is provided. The pixel driving circuit includes a driving subcircuit, a writing subcircuit, a compensation subcircuit, a light-emitting control subcircuit, and a first reset subcircuit. The driving subcircuit is coupled to a first node, a second node, and a third node. The writing subcircuit is coupled to the second node, a first scan signal terminal, and a data signal terminal. The compensation subcircuit is coupled to the first node, the third node, and the second scan signal terminal. The light-emitting control subcircuit is coupled to a first voltage terminal, an enable signal terminal, the second node, the third node, and a light-emitting device. The first reset subcircuit is coupled to the third node, a third scan signal terminal, and a first reference voltage signal terminal. The driving method includes multiple light-emitting cycles, each light-emitting cycle comprising a refresh frame and multiple hold frames. The refresh frame comprises an initialization phase, a writing phase, a first reset phase, and a first light-emitting phase. The hold frame comprises an adjustment phase, a second reset phase, and a second light-emitting phase. During the writing phase, the writing subcircuit, under control of a first scan signal received from the first scan signal terminal, transmits a data signal received at the data signal terminal to the second node. The data signal received at the data signal terminal is a first data signal. The driver sub-circuit transmits the first data signal from the second node to a third node. The compensation sub-circuit transmits the voltage of the third node to the first node. During the first reset phase, under the control of the third scan signal received from the third scan signal terminal, the first reset sub-circuit transmits the first reference voltage received at the first reference voltage signal terminal to the third node, refreshing the first data signal received at the third node to the first reference voltage. During the first light-emitting phase, under the control of the enable signal received from the enable signal terminal, the first reference voltage received at the third node and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device in cooperation with the driver sub-circuit to drive the light-emitting device to emit light. During the regulation phase, under the control of the first scan signal received from the first scan signal terminal, the data signal received at the data signal terminal is transmitted to the second node. The data signal received at the data signal terminal is a second data signal. The driver sub-circuit transmits the second data signal from the second node to the third node. The magnitude of the second data signal is different from that of the first data signal. In the second reset stage: the first reset sub-circuit, under the control of the third scan signal received from the third scan signal terminal, transmits the first reference voltage received at the first reference voltage signal terminal to the third node, and refreshes the second data signal received at the third node to the first reference voltage.In the second light-emitting stage: under the control of the enable signal received from the enable signal terminal, in cooperation with the driving sub-circuit, the first reference voltage received at the third node and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device to drive the light-emitting device to emit light.

[0020] In yet another aspect, a display panel is provided, comprising: a pixel driving circuit as described in any one of the above embodiments, and a light-emitting device electrically connected to the pixel driving circuit.

[0021] The above-mentioned display panel has the same structure and beneficial technical effects as the pixel driving circuit provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] Figure 1 is a structural diagram of a display device according to some embodiments;

[0024] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0025] Figure 3 is a structural diagram of a pixel driving circuit according to some embodiments;

[0026] Figure 4 is a structural diagram of a pixel driving circuit according to some other embodiments;

[0027] Figure 5 is a structural diagram of a pixel driving circuit according to some further embodiments;

[0028] Figure 6 is a structural diagram of a pixel driving circuit according to some further embodiments;

[0029] Figure 7 is a structural diagram of a pixel driving circuit according to some further embodiments;

[0030] Figure 8 is a timing diagram of a pixel driving circuit according to some embodiments;

[0031] Figure 9 is a cross-sectional view of a display panel according to some embodiments;

[0032] Figure 10 is a flow chart of a method for manufacturing a display panel according to some embodiments;

[0033] Figure 11 for Figure 10 Structural diagrams of some steps in the process;

[0034] Figure 12 for Figure 10 Structural diagrams of other steps in the

[0035] Figure 13 for Figure 10 The structural diagram of some steps in the process;

[0036] Figure 14 for Figure 10 There are some steps in the structure diagram. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0042] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0043] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0044] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0045] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0046] In the circuit structure (e.g., pixel driving circuit) provided in the embodiments of the present disclosure, the transistors used in the circuit structure may be thin film transistors (TFT), field effect transistors (MOS), or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0047] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor used is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0048] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0049] The transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or may be partly N-type transistors and partly P-type transistors. In the present disclosure, "effective level" refers to the level at which a transistor can be turned on. Among them, a P-type transistor can be turned on under the control of a low-level signal, and an N-type transistor can be turned on under the control of a high-level signal.

[0050] In the present disclosure, a P-type transistor may be turned on under the control of a low-level signal, and an N-type transistor may be turned on under the control of a high-level signal.

[0051] Figure 1 FIG is a structural diagram of a display device according to some embodiments. Figure 1 As shown, some embodiments of the present disclosure provide a display device 300 , which includes: a display panel 200 .

[0052] In some examples, the display device 300 may be an OLED (Organic Light Emitting Diode) display device.

[0053] Exemplarily, the display device 300 further includes a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0054] Exemplarily, the display device 300 can be any display device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of jewelry), etc.

[0055] Figure 2 is a structural diagram of a display panel according to some embodiments.

[0056] In some embodiments, see Figure 2 As shown, the display panel 200 includes a substrate 000, a plurality of pixel driving circuits 100 disposed on one side of the substrate 000, and a plurality of light-emitting devices O disposed on a side of the plurality of pixel driving circuits 100 away from the substrate 000. The plurality of pixel driving circuits 100 are coupled to the plurality of light-emitting devices O.

[0057] Illustratively, the substrate 000 may be a flexible substrate or a rigid substrate.

[0058] For example, when the substrate 000 is a flexible substrate, the material of the substrate 000 may be a material with high elasticity, such as dimethylsiloxane, PI (Polyimide), or PET (Polyethylene Terephthalate).

[0059] For another example, when the substrate 000 is a rigid substrate, the material of the substrate 000 may be glass or the like.

[0060] In some examples, the plurality of pixel driving circuits 100 may be coupled to the plurality of light emitting devices O in a one-to-one correspondence. In other examples, one pixel driving circuit 100 may be coupled to multiple light emitting devices O, or multiple pixel driving circuits 100 may be coupled to one light emitting device O.

[0061] Below, the present disclosure takes the coupling of one pixel driving circuit 100 and one light-emitting device O as an example to schematically illustrate the structure of the display panel 200 .

[0062] For example, in the display panel 200, the pixel driving circuit 100 can generate a driving signal. Each light-emitting device O can emit light under the driving effect of the driving signal generated by the corresponding pixel driving circuit 100. The light emitted by multiple light-emitting devices O cooperates with each other, thereby enabling the display panel 200 to achieve a display function.

[0063] Exemplarily, the light-emitting device O may be an OLED light-emitting device.

[0064] In some implementations, the display panel 200 utilizes an LTPS (Low Temperature PolySi) substrate to form the pixel driver circuit 100. The pixel driver circuit may have a 7T1C circuit structure, comprising seven P-type TFTs and one capacitor. LTPS substrates offer advantages such as high electron mobility (approximately 100 cm² / Vs) and simple manufacturing. However, due to inherent limitations of LTPS technology, high leakage current can lead to severe screen flicker and render the display unusable at low frequencies.

[0065] To achieve low-frequency display and reduce power consumption, display panels can use LTPO technology (Low Temperature PolySilicon And Oxide). This technology combines the characteristics of LTPS (Low Temperature PolySi) and IGZO (indium gallium zinc oxide). IGZO (indium gallium zinc oxide) oxide semiconductors have low electron mobility (approximately 10cm2 / Vs) and very low leakage current. This means that LTPO technology can reduce leakage in pixel drive circuits, reduce screen flicker, and achieve low-frequency display.

[0066] Below, a schematic explanation is given by taking the circuit structure provided in the embodiment of the present disclosure using LTPO technology as an example.

[0067] Figure 3 is a structural diagram of a pixel driving circuit according to some embodiments.

[0068] In some embodiments, the present disclosure provides a pixel driving circuit, such as Figure 3 As shown, the pixel driving circuit 100 includes a driving sub-circuit 10 , a writing sub-circuit 20 , a compensation sub-circuit 30 , a light emitting control sub-circuit 40 and a first reset sub-circuit 50 .

[0069] The driving sub-circuit 10 is coupled to the first node N1, the second node N2, and the third node N3. The driving sub-circuit 10 is configured to transmit the voltage from the second node N2 to the third node N3 under the control of the voltage of the first node N1.

[0070] The write sub-circuit 20 is coupled to the second node N2, the first scan signal terminal G1, and the data signal terminal D. The write sub-circuit 20 is configured to, during a write phase, transmit a data signal received at the data signal terminal D to the second node N2 under the control of the first scan signal received from the first scan signal terminal G1.

[0071] The compensation sub-circuit 30 is coupled to the first node N1, the third node N3 and the second scan signal terminal G2. The compensation sub-circuit 30 is configured to transfer the voltage of the third node N3 to the first node N1 under the control of the second scan signal received from the second scan signal terminal G2 during the write phase.

[0072] It is understandable that, with the above configuration, during the writing phase, the first scanning signal terminal G1 receives a valid signal of the first scanning signal, and the second scanning signal terminal G2 receives a valid signal of the second scanning signal at least partially simultaneously.

[0073] Exemplarily, the valid signal of the first scanning signal received by the first scanning signal terminal G1 is synchronous with the valid signal of the second scanning signal received by the second scanning signal terminal G2.

[0074] Based on this, the writing sub-circuit 20 can be turned on under the control of the first scanning signal received at the first scanning signal terminal G1, so that the writing sub-circuit 20 transmits the data signal received at the data signal terminal D to the second node N2. The data signal is converted into a compensation signal after passing through the driving sub-circuit 10, and the compensation signal is transmitted to the first node N1 through the compensation sub-circuit 30. That is, the writing of the compensation signal is completed, and the compensation of the threshold voltage Vth of the driving sub-circuit 10 is also achieved.

[0075] It should be noted that each subpixel in the display panel 200 is driven by multiple thin-film transistors (TFTs). Using TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFTs exhibit a hysteresis effect. This hysteresis effect is an uncertainty in the TFT's electrical characteristics under a certain bias voltage. Specifically, the current flowing through the TFT depends not only on the current bias voltage but also on the TFT's state at the previous moment. The hysteresis effect of the TFT is related to the TFT's gate dielectric, semiconductor material, and the interface state traps between them. During the light-emitting phase, the hysteresis effect of the TFT causes a current decrease within a frame, which the human eye perceives as flicker, thereby affecting the display quality of the display panel 200.

[0076] The light emitting control sub-circuit 40 is coupled to the first voltage terminal VDD, the enable signal terminal EM, the second node N2, the third node N3, and the light emitting device O. The light emitting control sub-circuit 40 is configured to cooperate with the driving sub-circuit 10 to transmit a driving signal to the light emitting device O under the control of the enable signal from the enable signal terminal EM.

[0077] Based on this, under the control of the enable signal from the enable signal terminal EM, the light-emitting control sub-circuit 40 cooperates with the driving sub-circuit 10 to transmit the first voltage provided by the first voltage terminal VDD to the second node N2. The second node N2 transmits the electrical signal (first voltage) to the third node N3. The third node N3 further transmits the electrical signal to the light-emitting device O. This electrical signal can cooperate with the second voltage provided by the second voltage signal terminal Vss coupled to the light-emitting device O to drive the light-emitting device O to emit light normally, thereby achieving display.

[0078] A lighting cycle (a frame) includes a refresh frame and multiple hold frames. For example, a lighting cycle (a frame) includes one refresh frame and 11 hold frames. A lighting cycle (a frame) is a display frame, that is, a display screen. The refresh frame includes a reset phase, a write phase, and a first lighting phase. The hold frame includes an adjustment phase and a second lighting phase. The inventors of this disclosure have discovered that:

[0079] After the data writing phase within the refresh frame and before the first light-emitting phase, the write sub-circuit 20 transmits the data signal received at the data signal terminal D to the third node N3. At this point, the data signal received at the data signal terminal D is the first data signal. That is, the voltage at the third node N3 is the first data signal. After the intra-frame adjustment phase and before the second light-emitting phase, the write sub-circuit 20 transmits the data signal received at the data signal terminal D to the third node N3. At this point, the data signal received at the data signal terminal D is the second data signal. That is, the voltage at the third node N3 is the second data signal.

[0080] During the first and second light-emitting phases, when the light-emitting control subcircuit 40 is turned on under the control of the enable signal at the enable signal terminal EM, the signal at the third node N3 is transmitted to the anode of the light-emitting device O, causing the light-emitting device O to emit light. However, because the magnitude of the second data signal differs from that of the first data signal, the magnitude of the signal received by the light-emitting device O differs during the first and second light-emitting phases, which in turn results in different brightness levels of the light-emitting device O. That is, during the frequency switching process between the refresh frame and the hold frame, the difference in brightness due to the different voltages at the third node N3 can lead to significant differences, easily causing flicker during screen switching and degrading the display quality of the display panel 200.

[0081] Based on this, some embodiments of the present disclosure provide a pixel driving circuit 100 that further includes a first reset sub-circuit 50. The first reset sub-circuit 50 is coupled to the third node N3, the third scan signal terminal G3, and the first reference voltage signal terminal V1. The first reset sub-circuit 50 is configured to, under control of the third scan signal received from the third scan signal terminal G3, transmit the first reference voltage received from the first reference voltage signal terminal V1 to the third node N3, thereby refreshing the third node N3.

[0082] In this embodiment, the pixel driving circuit 100 is additionally provided with a first reset subcircuit 50. The first reset subcircuit 50 is configured to transmit the first reference voltage received by the first reference voltage signal terminal V1 to the third node N3 under the control of the third scan signal received from the third scan signal terminal G3, thereby refreshing the third node. Specifically:

[0083] After the data writing phase in the refresh frame and before the first light emitting phase, the potential of the third node N3 is refreshed by the first reset sub-circuit 50. At this time, the first data signal at the third node N3 is refreshed to the first reference voltage.

[0084] And, after the adjustment phase within the frame and before the second light-emitting node, the potential of the third node N3 is refreshed by the first reset sub-circuit 50. At this time, the second data signal at the third node N3 is refreshed to the first reference voltage.

[0085] Thus, the voltage at the third node N3 can be refreshed to a consistent value before the first light-emitting phase and before the second light-emitting phase. This prevents the problem of different brightness caused by different values ​​at the third node N3 in different phases. In other words, it prevents the problem of large brightness differences caused by different potentials at the third node during the switching process between the refresh frame and the hold frame. This helps to improve the flicker problem that occurs during the screen switching process and enhances the display quality of the display panel 200.

[0086] In some embodiments, as Figure 3 As shown, the value range of the first reference voltage signal received at the first reference voltage signal terminal V1 is 0V~6.5V.

[0087] When the first reference voltage signal is equal to or close to 6.5V, it can satisfy the requirement of uniform luminous brightness of the light-emitting device O and prevent the load of the driving chip IC in the display panel 200 from being affected.

[0088] In some examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 0 V to 3 V. In other examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 3 V to 6.5 V. In still other examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 2 V to 4 V.

[0089] For example, the value of the first reference voltage signal received at the first reference voltage signal terminal V1 is 1V, 2V, 3V, 4V, 5V, 6V or 6.5V.

[0090] For example, the first reference voltage signal received at the first reference voltage signal terminal V1 is 6.5V.

[0091] After the data writing phase in the refresh frame and before the first light emitting phase, the potential of the third node N3 is refreshed by the first reset sub-circuit 50. At this time, the first data signal at the third node N3 is refreshed to the first reference voltage 6.5V.

[0092] After the adjustment phase within the frame and before the second light-emitting node, the potential of the third node N3 is refreshed by the first reset sub-circuit 50. At this time, the second data signal at the third node N3 is refreshed to the first reference voltage 6.5V.

[0093] That is, before the first light-emitting stage and the second light-emitting stage, the voltage of the third node N3 is 6.5V. This allows the light-emitting device O to emit light with consistent brightness when the light-emitting control subcircuit 40 is turned on under the control of the enable signal of the enable signal terminal EM during the first light-emitting stage and the second light-emitting stage. This prevents the problem of large brightness differences caused by different potentials at the third node during the frequency switching process between the refresh frame and the hold frame, thereby improving the flicker problem that occurs during the screen switching process and enhancing the display quality of the display panel 200.

[0094] Figure 4 is a structural diagram of a pixel driving circuit according to some other embodiments.

[0095] In some embodiments, as Figure 4 As shown, the pixel driving circuit 100 further includes a second reset sub-circuit 60. The second reset sub-circuit 60 is coupled to the first node N1, the first reset signal terminal R1, and the first initialization signal terminal V2. The second reset sub-circuit 60 is configured to, during a reset phase, under the control of the reset signal received from the first reset signal terminal R1, transmit the first initialization signal received at the first initialization signal terminal V2 to the first node N1, thereby resetting the first node N1.

[0096] Based on this, during the reset phase within the refresh frame, the second reset sub-circuit 60 is turned on under the control of the reset signal received from the first reset signal terminal R1, and transmits the first initialization signal received from the first initialization signal terminal V2 to the first node N1, thereby resetting the first node N1. This fixes the initial state of the transistors in the driver sub-circuit 10 before the write phase, facilitating a stable state of the transistors in the driver sub-circuit 10 during the write phase, thereby significantly improving the hysteresis effect of the transistors in the driver sub-circuit 10.

[0097] In some examples, during the reset phase, the second reset sub-circuit 60 can be used to reset the first node N1 multiple times, which is more conducive to ensuring the stability of the voltage of the first node N1.

[0098] The present disclosure does not limit the number of times the second reset sub-circuit 60 is used to reset the first node N1 during the reset phase, and the number of times may be 1, 2, or 3.

[0099] Figure 5 is a structural diagram of a pixel driving circuit according to some further embodiments.

[0100] In some embodiments, as Figure 5 As shown, the pixel driving circuit further includes a third reset sub-circuit 70. The third reset sub-circuit 70 is coupled to the second reset signal terminal R2, the second initialization signal terminal V3, and the light-emitting device O. The third reset sub-circuit 70 is configured to transmit the second initialization signal received at the second initialization signal terminal V3 to the light-emitting device O under the control of the reset signal received from the second reset signal terminal R2.

[0101] Based on this, the third reset sub-circuit 70 is turned on under the control of the reset signal received from the second reset signal terminal R2, and transmits the second initialization signal received at the second initialization signal terminal V3 to the light-emitting device O, resets the anode of the light-emitting device O, and improves the stability of the light-emitting device O.

[0102] Figure 6 is a structural diagram of a pixel driving circuit according to some further embodiments.

[0103] In some embodiments, as Figure 6 As shown, the pixel driving circuit further includes a first storage subcircuit 80. The first storage subcircuit 80 is coupled to the first voltage terminal VDD and the first node N1. The first storage subcircuit 80 includes a first capacitor C, a first plate c1 of the first capacitor C is coupled to the first voltage terminal VDD, and a second plate c2 of the first capacitor C is coupled to the first node N1.

[0104] Based on this, the write sub-circuit 20 is turned on under the control of the first scan signal transmitted by the first scan signal terminal G1. At this time, the data signal received at the data signal terminal D is transmitted to the second node N2. At the same time, the data signal received at the data signal terminal D is also transmitted to the first capacitor C to charge the first capacitor C. The compensation sub-circuit 30 is turned on under the control of the second scan signal transmitted by the second scan signal terminal G2. At this time, the data signal received at the second node N2 is transmitted to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to Vdata+Vth. Here, Vdata is the voltage value of the data signal provided by the data signal terminal D, and Vth is the threshold voltage of the transistor in the driving sub-circuit 10. When the potential of the first node N1 is Vdata+Vth, the charging process is completed. Subsequently, the discharge of the first capacitor C is used to keep the driving sub-circuit 10 continuously turned on to ensure that the light-emitting device O emits light.

[0105] Figure 7 is a structural diagram of a pixel driving circuit according to some further embodiments.

[0106] In some embodiments, as Figure 7 As shown, the driving sub-circuit 10 includes a driving transistor TD. A gate of the driving transistor TD is coupled to the first node N1 , a first electrode of the driving transistor TD is coupled to the second node N2 , and a second electrode of the driving transistor TD is coupled to the third node N3 .

[0107] When the voltage of the first node N1 is at an active level, the driving transistor TD may be turned on under the control of the voltage of the first node N1 to transmit the electrical signal (eg, data signal) from the second node N2 to the third node N3 .

[0108] In some embodiments, as Figure 7 As shown, the first reset sub-circuit 50 includes a first transistor T1, a gate of which is coupled to the third scan signal terminal G3, a first electrode of which is coupled to the third node N3, and a second electrode of which is coupled to the first reference voltage signal terminal V1.

[0109] Based on this, the first transistor T1 is turned on under the control of the effective signal of the third scan signal received from the third scan signal terminal G3, and the first reference voltage received by the first reference voltage signal terminal V1 is transmitted to the third node N3, refreshing the third node N3. It can be achieved that before the first light-emitting stage and before the second light-emitting stage, the voltage at the third node N3 is refreshed to a consistent value. This can prevent the problem of different brightness caused by different values ​​at the third node N3 in different stages. In other words, it prevents the problem of large brightness differences caused by different potentials at the third node during the switching process of refreshing the frame and holding the frame, which is beneficial to improving the flickering problem that occurs during the screen switching process and improving the display effect of the display panel 200.

[0110] In some examples, the first transistor T1 may be an N-type transistor. In other examples, the first transistor T1 may be a P-type transistor. The present disclosure does not limit the type of the first transistor T1, and the first transistor T1 may be configured uniformly in combination with the types of other transistors in the pixel driving circuit 100. For example, when the driving transistor TD is a P-type transistor, the first transistor T1 may also be a P-type transistor.

[0111] It should be noted that the "active level" in this disclosure refers to the level that can turn on a transistor. When the transistor is an N-type transistor, the "active level" is a high level; when the transistor is a P-type transistor, the "active level" is a low level. The following embodiments are the same and will not be repeated here.

[0112] In some embodiments, as Figure 7 As shown, the writing sub-circuit 20 includes a second transistor T2 , a gate of which is coupled to the first scan signal terminal G1 , a first electrode of which is coupled to the data signal terminal D, and a second electrode of which is coupled to the second node N2 .

[0113] Based on this, when the first scanning signal received by the first scanning signal terminal G1 is a low-level signal (valid signal), the second transistor T2 receives this low-level signal and turns on. At this time, the data signal received at the data signal terminal D is transmitted to the second node N2. Furthermore, after passing through the driving sub-circuit 10, the data signal is converted into a compensation signal, which is then transmitted to the first node N1 via the compensation sub-circuit 30. This completes the writing of the compensation signal and achieves compensation for the threshold voltage Vth. This improves the brightness retention within a frame, thereby improving the flickering phenomenon of the display panel 200 at low frequencies.

[0114] In some embodiments, as Figure 7As shown, the compensation sub-circuit 30 includes a third transistor T3 , a gate of which is coupled to the second scan signal terminal G2 , a first electrode of which is coupled to the first node N1 , and a second electrode of which is coupled to the third node N3 .

[0115] Based on this, when the second scan signal provided by the second scan signal terminal G2 is a high-level signal (valid signal), the third transistor T3 receives this high-level signal and turns on. During the write phase, the write sub-circuit 20 is turned on under the control of the gate scan signal received by the first scan signal terminal G1. The write sub-circuit 20 transmits the data signal received at the data signal terminal D to the second node N2. After passing through the driver sub-circuit 10, the data signal is converted into a compensation signal. The compensation signal is transmitted to the first node N1 through the third transistor T3 of the compensation sub-circuit 30, thus completing the writing of the compensation signal and achieving compensation for the threshold voltage Vth of the driver sub-circuit 10.

[0116] In some examples, the third transistor T3 is an oxide transistor. Exemplarily, the third transistor T3 is a metal oxide transistor. For example, the third transistor is an N-type indium gallium zinc oxide (IGZO) transistor. Using an IGZO transistor can reduce leakage current in the third transistor T3, ensure the stability of the first node N1, and reduce screen flickering in the display panel 200. This allows for low-frequency display of the display panel 200, which helps reduce power consumption of the display panel 200.

[0117] In some embodiments, as Figure 7 As shown, the light-emitting control subcircuit 40 includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is coupled to the enable signal terminal EM, the first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor T4 is coupled to the second node N2. The gate of the fifth transistor T5 is coupled to the enable signal terminal EM, the first electrode of the fifth transistor T5 is coupled to the third node N3, and the second electrode of the fifth transistor T5 is coupled to the light-emitting device O.

[0118] Based on this, when the enable signal provided by the enable signal terminal EM is a low-level signal (valid signal), the fourth transistor T4 and the fifth transistor T5 receive this low-level signal and turn on. In cooperation with the driver sub-circuit 10, the first voltage provided by the first voltage terminal VDD is transmitted to the second node N2. The second node N2 transmits the signal (first voltage) to the third node N3. The third node N3 then transmits the signal to the light-emitting device O. This signal can cooperate with the second voltage provided by the second voltage signal terminal Vss coupled to the light-emitting device O to drive the light-emitting device O to emit light normally, thereby achieving display.

[0119] In some embodiments, as Figure 7 As shown, the second reset subcircuit 60 includes a sixth transistor T6 , a gate of which is coupled to the first reset signal terminal R1 , a first electrode of which is coupled to the first node N1 , and a second electrode of which is coupled to the first initialization signal terminal V2 .

[0120] Based on this, when the first reset signal provided by the first reset signal terminal R1 is a high-level signal (valid signal), the sixth transistor T6 is turned on. The first reset signal provided by the first initialization signal terminal V2 is transmitted to the first node N1, resetting the first node N1, that is, resetting the voltage at the gate terminal of the drive transistor TD. This stabilizes the initial state of the drive transistor TD before the write phase, facilitating a stable state of the drive transistor TD during the write phase and significantly reducing the hysteresis effect of the drive transistor TD.

[0121] In some examples, the sixth transistor T6 is an oxide transistor. Exemplarily, the sixth transistor T6 is a metal oxide transistor. For example, the sixth transistor T6 is an N-type indium gallium zinc oxide (IGZO) transistor. Using an IGZO transistor can reduce leakage current in the sixth transistor T6, ensure the stability of the first node N1, and reduce screen flickering in the display panel 200. This allows for low-frequency display on the display panel 200, reducing power consumption of the display panel 200.

[0122] In some embodiments, as Figure 7 As shown, the third reset subcircuit 70 includes a seventh transistor T7, a gate of which is coupled to the second reset signal terminal R2, a first electrode of which is coupled to the light emitting device O, and a second electrode of which is coupled to the second initialization signal terminal V3.

[0123] Based on this, when the second reset signal provided by the second reset signal terminal R2 is a low-level signal (valid signal), the seventh transistor T7 is turned on. At this time, the second initialization signal provided by the second initialization signal terminal V3 is transmitted to the anode of the light-emitting device O, resetting the anode of the light-emitting device O and improving the stability of the light-emitting device O.

[0124] In some embodiments, as Figure 7 As shown, the second reset signal terminal R2 and the first scan signal terminal G1 respond to the control of the same control signal.

[0125] For example, the first scan signal terminal G1 can be multiplexed into the second reset signal terminal R2. Alternatively, the second reset signal terminal R2 can be multiplexed into the first scan signal terminal G1. In this embodiment, the first scan signal terminal G1 can be multiplexed into the second reset signal terminal R2 as an example.

[0126] With this arrangement, the first scan signal terminal G1 is multiplexed as the second reset signal terminal R2, simplifying the structure of the pixel driving circuit 100 and reducing the layout complexity within the display panel 200. Furthermore, when writing data, the first scan signal provided by the first scan signal terminal G1 turns on the seventh transistor T7 in the third reset sub-circuit 70, and the second initialization signal provided by the second initialization signal terminal V3 is transmitted to the anode of the light-emitting device O, thereby resetting the anode of the light-emitting device O. In other words, the anode of the light-emitting device O can be reset before the first light-emitting phase, thereby improving the stability of the light-emitting device O.

[0127] In addition, the first scan signal terminal G1 is multiplexed as the second reset signal terminal R2. The first scan signal terminal G1 can reset the anode of the light-emitting device O multiple times within one frame, thereby further improving the stability of the light-emitting device O.

[0128] above Figures 3 to 7 In the illustrated pixel driving circuit 100, the third transistor T3 in the compensation subcircuit 30 and the sixth transistor T6 in the second reset subcircuit 60 may be N-type IGZO transistors. Transistors in other subcircuits, such as the driving transistor TD in the driving subcircuit 10, the second transistor T2 in the writing subcircuit 20, the fourth and fifth transistors in the light emitting control subcircuit 40, the first transistor T1 in the first reset subcircuit 50, and the seventh transistor T7 in the third reset subcircuit 70, are P-type LTPS (Low Temperature PolySi) transistors, as an example.

[0129] Figure 8 is a timing diagram of a pixel driving circuit according to some embodiments.

[0130] In some embodiments, the present disclosure provides a driving method for a pixel driving circuit, such as Figure 8 As shown, and combined Figure 3 As shown, the pixel driving circuit 100 includes a driving sub-circuit 10 , a writing sub-circuit 20 , a compensation sub-circuit 30 , a light emitting control sub-circuit 40 and a first reset sub-circuit 50 .

[0131] The driving sub-circuit 10 is coupled to the first node N1, the second node N2, and the third node N3. The writing sub-circuit 20 is coupled to the second node N2, the first scan signal terminal G1, and the data signal terminal D. The compensation sub-circuit 30 is coupled to the first node N1, the third node N3, and the second scan signal terminal G2. The light-emitting control sub-circuit 40 is coupled to the first voltage terminal, the enable signal terminal EM, the second node N2, the third node N3, and the light-emitting device O. The first reset sub-circuit 50 is coupled to the third node N3, the third scan signal terminal G3, and the first reference voltage signal terminal V1.

[0132] For example, the third transistor T3 in the compensation sub-circuit 30 and the sixth transistor T6 in the second reset sub-circuit 60 may be N-type IGZO transistors. For example, the driving transistor TD in the driving sub-circuit 10, the second transistor T2 in the writing sub-circuit 20, the fourth and fifth transistors in the light emitting control sub-circuit 40, the first transistor T1 in the first reset sub-circuit 50, and the seventh transistor T7 in the third reset sub-circuit 70 may be P-type LTPS (Low Temperature PolySi) transistors.

[0133] The driving method includes: multiple light-emitting cycles F, each light-emitting cycle F includes one refresh frame F1 and multiple hold frames F2. For example, when 120Hz is switched to 10Hz, one light-emitting cycle F includes one refresh frame F1 and 11 hold frames F2. Figure 8 The timing of only one refresh frame F1 and the first hold frame F2 is shown. The timing of other hold frames can be combined with Figure 8 The timing of the holding frame F2 is shown in FIG.

[0134] The refresh frame F1 includes an initialization phase t11, a writing phase t12, a first reset phase t13, and a first light-emitting phase t14.

[0135] The holding frame F2 includes an adjustment phase t22, a second reset phase t23 and a second light emitting phase t24.

[0136] During write phase t12, the write sub-circuit 20, under control of the first scan signal received from the first scan signal terminal G1, transmits the data signal received at the data signal terminal D to the second node N2. The data signal received at the data signal terminal D is the first data signal. The driver sub-circuit 10 transmits the first data signal from the second node N2 to the third node N3. The compensation sub-circuit 30 transmits the voltage of the third node N3 to the first node N1.

[0137] At this point, the first scan signal received by the first scan signal terminal G1 is a low-level signal, a valid signal. The second transistor T2 in the write sub-circuit 20 receives this low-level signal and turns on. The write sub-circuit 20 transmits the first data signal received at the data signal terminal D to the second node N2. In conjunction with the driver sub-circuit 10, the driver sub-circuit 10 transmits the first data signal from the second node N2 to the third node N3. Furthermore, the compensation sub-circuit 30 transmits the voltage of the third node N3 to the first node N1.

[0138] In the first reset stage t13: the first reset sub-circuit 50, under the control of the third scan signal received from the third scan signal terminal G3, transmits the first reference voltage received at the first reference voltage signal terminal V1 to the third node N3, and refreshes the first data signal received at the third node N3 to the first reference voltage.

[0139] At this point, the third scan signal received by the third scan signal terminal G3 is a low-level signal, indicating a valid signal. The first transistor T1 in the first reset sub-circuit 50 receives this low-level signal and turns on. The first reset sub-circuit 50 transmits the first reference voltage received at the first reference voltage signal terminal V1 to the third node N3, refreshing the first data signal received at the third node N3 to the first reference voltage.

[0140] In some examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 0 V to 6.5 V.

[0141] When the first reference voltage signal is equal to or close to 6.5V, it can satisfy the requirement of uniform luminous brightness of the light-emitting device O and prevent the load of the driving chip IC in the display panel 200 from being affected.

[0142] In some examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 0 V to 3 V. In other examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 3 V to 6.5 V. In still other examples, the first reference voltage signal received at the first reference voltage signal terminal V1 has a value range of 2 V to 4 V.

[0143] For example, the value of the first reference voltage signal received at the first reference voltage signal terminal V1 is 1V, 2V, 3V, 4V, 5V, 6V or 6.5V.

[0144] For example, the first reference voltage signal received at the first reference voltage signal terminal V1 is 6.5V. At the first reset stage t13, the voltage at the third node N3 is refreshed to 6.5V.

[0145] In the first light-emitting stage t14: under the control of the enable signal received from the enable signal terminal EM, in cooperation with the driving sub-circuit 10, the first reference voltage received at the third node N3 and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device O to drive the light-emitting device O to emit light.

[0146] At this point, the enable signal received by the enable signal terminal EM is a low-level signal, representing a valid signal. The fourth transistor T4 and the fifth transistor T5 in the light-emitting control subcircuit 40 receive this low-level signal and turn on. The first voltage provided by the first voltage terminal VDD is sequentially transmitted through the fourth transistor T4, the second node N2, the drive transistor TD, the third node N3, and the fifth transistor T5 until it reaches the anode of the light-emitting device O. This electrical signal (the first voltage) cooperates with the second voltage provided by the second voltage signal terminal Vss coupled to the light-emitting device O to drive the light-emitting device O to emit light normally, thereby achieving display.

[0147] Furthermore, since the light-emitting device O is coupled to the third node N3 via the fifth transistor T5, when the fifth transistor T5 receives the enable signal and turns on, the first reference voltage at the third node N3 is first transmitted through the fifth transistor T5 to the anode of the light-emitting device O. Thereafter, the first voltage provided by the first voltage terminal VDD is transmitted to the anode of the light-emitting device O via the light-emission control sub-circuit 40. The light-emitting device O then emits light.

[0148] During the adjustment phase t22, under the control of the first scan signal received from the first scan signal terminal G1, the data signal received at the data signal terminal D is transmitted to the second node N2. The data signal received at the data signal terminal D is a second data signal. The driver sub-circuit 10 transmits the second data signal from the second node N2 to the third node N3. The magnitude of the second data signal is different from that of the first data signal.

[0149] At this point, the first scan signal received by the first scan signal terminal G1 is a low-level signal, a valid signal. The second transistor T2 in the write sub-circuit 20 receives this low-level signal and turns on. The write sub-circuit 20 transmits the second data signal received at the data signal terminal D to the second node N2. In conjunction with the driver sub-circuit 10, the driver sub-circuit 10 transmits the second data signal from the second node N2 to the third node N3.

[0150] In the second reset stage t23: the first reset sub-circuit 50, under the control of the third scan signal received from the third scan signal terminal G3, transmits the first reference voltage received at the first reference voltage signal terminal V1 to the third node N3, and refreshes the second data signal received at the third node N3 to the first reference voltage.

[0151] At this point, the third scan signal received by the third scan signal terminal G3 is a low-level signal, indicating a valid signal. The first transistor T1 in the first reset sub-circuit 50 receives this low-level signal and turns on. The first reset sub-circuit 50 transmits the first reference voltage received at the first reference voltage signal terminal V1 to the third node N3, refreshing the second data signal received at the third node N3 to the first reference voltage. This means that the voltage at the third node N3 is now the first reference voltage of 6.5V. In other words, the voltage at the third node N3 is the first reference voltage of 6.5V during both the first reset phase t13 and the second reset phase t23.

[0152] In the second light-emitting stage t24: under the control of the enable signal received from the enable signal terminal EM, in cooperation with the driving sub-circuit 10, the first reference voltage received at the third node N3 and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device O to drive the light-emitting device O to emit light.

[0153] At this point, the enable signal received by the enable signal terminal EM is a low-level signal, representing a valid signal. The fourth transistor T4 and the fifth transistor T5 in the light-emitting control subcircuit 40 receive this low-level signal and turn on. The first voltage provided by the first voltage terminal VDD is sequentially transmitted through the fourth transistor T4, the second node N2, the drive transistor TD, the third node N3, and the fifth transistor T5 until it reaches the anode of the light-emitting device O. This electrical signal (the first voltage) cooperates with the second voltage provided by the second voltage signal terminal Vss coupled to the light-emitting device O to drive the light-emitting device O to emit light normally, thereby achieving display.

[0154] Furthermore, since the light-emitting device O is coupled to the third node N3 via the fifth transistor T5, when the fifth transistor T5 receives the enable signal and turns on, the first reference voltage at the third node N3 is first transmitted through the fifth transistor T5 to the anode of the light-emitting device O. Thereafter, the first voltage provided by the first voltage terminal VDD is transmitted to the anode of the light-emitting device O via the light-emission control sub-circuit 40. The light-emitting device O then emits light.

[0155] During the data writing phase t12, the voltage at the third node N3 is the first data signal, while during the adjustment phase t22, the voltage at the third node N3 is the second data signal. Furthermore, the magnitude of the first data signal is different from the magnitude of the second data signal. For example, the first data signal is greater than the second data signal. Alternatively, the first data signal is less than the second data signal. Regardless of the magnitude relationship between the first and second data signals, when the fifth transistor T5 is turned on during the first light-emitting phase t14 and the second light-emitting phase t24, the magnitude of the signals received by the light-emitting device O is different, resulting in different brightness levels of the light-emitting device O.

[0156] However, in the driving method provided in the embodiment of the present disclosure, a first reset phase t13 is added between the data writing phase t12 and the first light-emitting phase t14. A second reset phase t23 is added between the adjustment phase t22 and the second light-emitting phase t24. The voltage of the third node N3 is reset to the first reference voltage during the first reset phase t13 and the second reset phase t23. This allows the voltage of the third node N3 to remain consistent during the period preceding the first light-emitting phase t14 and the second light-emitting phase t24. This helps ensure that the signal magnitudes received by the light-emitting device O are consistent when the fifth transistor T5 turns on during the first light-emitting phase t14 and the second light-emitting phase t24. This further helps ensure that the brightness of the light-emitting device O is consistent during the first light-emitting phase t14 and the second light-emitting phase t24. This alleviates the flickering issue that occurs during the screen switching process between the refresh frame F1 and the hold frame F2, thereby enhancing the display quality of the display panel 200.

[0157] In some embodiments, as Figure 8 As shown, the holding frame F2 also includes a holding phase t21 , during which all transistors ( T1 - T7 ) in the pixel driving circuit 100 are turned off.

[0158] In some embodiments, as Figure 8 As shown, in the initialization phase t11 within the refresh frame F1: the second reset sub-circuit 60 is configured to transmit the first initialization signal received at the first initialization signal terminal V2 to the light-emitting device O under the control of the reset signal received from the second reset signal terminal R2.

[0159] At this point, the reset signal received by the second reset signal terminal R2 is a high-level signal, a valid signal. The sixth transistor T6 in the second reset sub-circuit 60 receives this high-level signal and turns on. The second reset sub-circuit 60 transmits the first initialization signal received by the first initialization signal terminal V2 to the first node N1, resetting the first node N1. This also resets the voltage at the gate terminal of the drive transistor TD. This stabilizes the initial state of the drive transistor TD before the write phase t12, facilitating a stable state for the drive transistor TD during the write phase and significantly reducing the hysteresis effect of the drive transistor TD.

[0160] Figure 9 is a cross-sectional view of a display panel according to some embodiments.

[0161] In other embodiments, the present disclosure provides a display panel, such as Figure 9 As shown, the display panel 200 includes: a substrate 000, a first buffer layer 201, and a driving circuit layer 202 located on a side of the first buffer layer 201 away from the substrate 000. The driving circuit layer 202 includes the pixel driving circuit 100 shown in any of the above embodiments.

[0162] The driving circuit layer 202 includes: a first active layer 203, a first gate insulation layer 204, a first gate metal layer 205, a second gate insulation layer 206, a second gate metal layer 207, a first interlayer dielectric layer 208, a second buffer layer 209, a second active layer 210, a third gate insulation layer 211, a third gate metal layer 212, a second interlayer dielectric layer 213, a first planarization layer 214, and a source-drain metal layer 215.

[0163] Exemplarily, the first active layer 203 is low temperature polysilicon (LTPS), and the second active layer 210 is indium gallium zinc oxide (IGZO).

[0164] Exemplarily, the first gate insulating layer 204 insulates the first active layer 203 from the first gate metal layer 205. The material of the first gate insulating layer 204 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer 204 may include silicon dioxide, but the present disclosure is not limited thereto.

[0165] Exemplarily, the second gate insulating layer 206 insulates the first gate metal layer 205 from the second gate metal layer 207. The material of the second gate insulating layer 206 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer 206 may include silicon dioxide, but the present disclosure is not limited thereto.

[0166] Exemplarily, the third gate insulating layer 211 insulates the second active layer 210 from the third gate metal layer 212. The material of the third gate insulating layer 211 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the third gate insulating layer 211 may include silicon dioxide, but the present disclosure is not limited thereto.

[0167] Illustratively, the first interlayer dielectric layer 208 insulates the second gate metal layer 207 from the second active layer 210. The material of the first interlayer dielectric layer 208 may be silicon oxide (SiOx).

[0168] Illustratively, the second interlayer dielectric layer 213 insulates the third gate metal layer 212 from the source / drain metal layer 215. The material of the second interlayer dielectric layer 213 may be silicon oxide (SiOx).

[0169] When in the pixel driving circuit 100: the third transistor T3 in the compensation subcircuit 30 and the sixth transistor T6 in the second reset subcircuit 60 can be N-type IGZO transistors. The driving transistor TD in the driving subcircuit 10, the second transistor T2 in the writing subcircuit 20, the fourth transistor T4 and the fifth transistor T5 in the light emitting control subcircuit 40, the first transistor T1 in the first reset subcircuit 50, and the seventh transistor T7 in the third reset subcircuit 70 are P-type LTPS transistors (Low Temperature PolySi, low temperature polysilicon). Figure 9 The driving transistor TD and the third transistor T3 are taken as examples for illustration.

[0170] The third transistor T3 and the sixth transistor T6 include a top gate 011, a bottom gate 012, a source 013 (first electrode), a drain 014 (second electrode), and a channel 015. The bottom gate 012 is located in the second gate metal layer 207, and the top gate 011 is located in the third gate metal layer 212. The source 013 and drain 014 are located in the source-drain metal layer 215. The channel 015 is located in the second active layer 210. The source 013 and drain 014 are connected to the channel 015 of the second active layer 210 through a first connection hole K1.

[0171] In some examples, the first connecting hole K1 includes a first hole segment K11 and a second hole segment K12 that are connected. That is, the first hole segment K11 and the second hole segment K12 are connected to form the first connecting hole K1.

[0172] The second hole segment K12 penetrates the first planarization layer 214, exposing the second interlayer dielectric layer 213. The first hole segment K11 penetrates the third gate insulation layer 211 and the second interlayer dielectric layer 213, exposing the second active layer 210. This allows the source electrode 013 and the drain electrode 014 to be connected to the second active layer 210 through the first connection hole K1.

[0173] The first connection hole K1 is configured to include a first hole segment K11 and a second hole segment K12. The segmented drilling design reduces the via depth, which helps alleviate the problem of poor via contact. Furthermore, reducing the via depth can also help reduce the difficulty of the drilling process.

[0174] It is understandable that, in other embodiments, the first connection hole K1 can also be formed by a one-time punching process.

[0175] The first transistor T1, the second transistor T2, the driving transistor TD, the fourth transistor, the fifth transistor, and the seventh transistor T7 include a gate 021, a source 022 (first electrode), a drain 023 (second electrode), and a channel 024. The gate 021 is located in the first gate metal layer 205. The source 022 and drain 023 are located in the source-drain metal layer 215. The channel 024 is located in the first active layer 203. The source 022 and drain 023 are connected to the channel 024 of the first active layer 203 through a second connection hole K2.

[0176] In some examples, the second connecting hole K2 includes a third hole segment K21 and a fourth hole segment K22 that are connected. That is, the third hole segment K21 and the fourth hole segment K22 are connected to form the second connecting hole K2.

[0177] The fourth hole segment K22 penetrates the first planarization layer 214, exposing the second interlayer dielectric layer 213. The third hole segment K21 penetrates the second interlayer dielectric layer 213, the third gate insulation layer 211, the second buffer layer 209, the first interlayer dielectric layer 208, the second gate insulation layer 206, and the first gate insulation layer 204, exposing the first active layer 203. This allows the source electrode 022 and the drain electrode 023 to be connected to the channel 024 of the first active layer 203 through the second connection hole K2.

[0178] The second connection hole K2 includes a third hole segment K21 and a fourth hole segment K22. The segmented hole drilling design reduces the via depth, which helps alleviate the problem of poor via contact. Furthermore, reducing the via depth can also help reduce the difficulty of the drilling process.

[0179] It is understandable that in other embodiments, the second connection hole K2 can also be formed by a one-time punching process.

[0180] In some embodiments, as Figure 9 As shown, the display panel 200 further includes an anode layer 217, a second planarization layer 216 located between the anode layer 217 and the source / drain metal layer 215, and a pixel definition layer 218 located on a side of the anode layer 217 away from the substrate 000. The anode layer 217 can be connected to the drain electrode 023 through a third via K3.

[0181] Figure 10 is a flow chart of a method for manufacturing a display panel according to some embodiments. Figure 11 for Figure 10 Structural diagram of some steps in . Figure 12 for Figure 10 Structural diagrams of other steps in . Figure 13 for Figure 10 There are some steps in the structure diagram. Figure 14 for Figure 10 There are some steps in the structure diagram.

[0182] In some embodiments, the present disclosure provides a method for manufacturing a display panel, such as Figure 10 As shown, the production method includes:

[0183] Take the driving transistor TD and the third transistor T3 in the display panel 200 as an example for illustration:

[0184] S1: providing a substrate; forming a first buffer layer on one side of the substrate.

[0185] In step S1: Figure 11 As shown, a first buffer layer 201 is formed on one side of the substrate 000 .

[0186] S2: depositing a first active layer on a side of the first buffer layer away from the substrate, and etching the first active layer to form a channel of the driving transistor.

[0187] In step S2, if Figure 11 As shown, a first active layer 203 is formed on a side of the first buffer layer 201 away from the substrate 000. Exemplarily, the first active layer 203 can be deposited using plasma enhanced chemical vapor deposition (PECVD) equipment. The first active layer 203 is then etched to form the channel 024 of the drive transistor TD. Exemplarily, the first active layer 203 is dry-etched. Exemplarily, the material of the first active layer 203 is low-temperature polycrystalline silicon (LTPS).

[0188] S3: forming a first gate insulating layer on a side of the first active layer away from the substrate.

[0189] In step S3, Figure 11 As shown, a first gate insulating layer 204 can be formed on a side of the first active layer 203 away from the substrate 000. In some examples, the first gate insulating layer 204 can be deposited on a side of the first active layer 203 away from the substrate 000. Exemplarily, the material of the first gate insulating layer 204 can be an inorganic layer. For example, the material of the first gate insulating layer 204 can be silicon oxide (SiOx).

[0190] S4: forming a first gate metal layer on a side of the first gate insulating layer away from the substrate, and etching the first gate metal layer to form a gate of the driving transistor.

[0191] In step S4, if Figure 11 As shown, a first gate metal layer 205 is formed on a side of the first gate insulating layer 204 away from the substrate 000 , and the first gate metal layer 205 is etched to form a gate 021 of the driving transistor TD.

[0192] In some examples, a first gate metal layer 205 is deposited on a side of the first gate insulating layer 204 away from the substrate 000 and dry-etched to form the gate 021 of the driving transistor TD. For example, the material of the first gate metal layer 205 can be molybdenum (Mo).

[0193] S5: forming a second gate insulating layer on a side of the first gate metal layer away from the substrate.

[0194] In step S5, if Figure 11 As shown, a second gate insulating layer 206 is formed on a side of the first gate metal layer 205 away from the substrate 000. In some examples, the second gate insulating layer 206 can be deposited on a side of the first gate metal layer 205 away from the substrate 000. Exemplarily, the material of the second gate insulating layer 206 can be an inorganic layer. For example, the material of the second gate insulating layer 206 can be silicon nitride (SiNx).

[0195] S6: forming a second gate metal layer on a side of the second gate insulating layer away from the substrate, and etching the second gate metal layer to form a bottom gate of the third transistor.

[0196] In step S6, if Figure 11 As shown, a second gate metal layer 207 is formed on a side of the second gate insulating layer 206 away from the substrate 000 , and the second gate metal layer 207 is etched to form a bottom gate 012 of the third transistor T3 .

[0197] In some examples, a second gate metal layer 207 is deposited on a side of the second gate insulating layer 206 away from the substrate 000 and dry-etched to form the bottom gate 012 of the third transistor T3. Exemplarily, the second gate metal layer 207 may be made of molybdenum (Mo).

[0198] S7: forming a first interlayer dielectric layer on a side of the second gate metal layer away from the substrate, and forming a second buffer layer on a side of the first interlayer dielectric layer away from the substrate.

[0199] In step S7, if Figure 11 As shown, a first interlayer dielectric layer 208 is formed on a side of the second gate metal layer 207 away from the substrate 000 , and a second buffer layer 209 is formed on a side of the first interlayer dielectric layer 208 away from the substrate 000 .

[0200] In some examples, the first interlayer dielectric layer 208 and the second buffer layer 209 may be deposited using a plasma enhanced chemical vapor deposition (PECVD) device.

[0201] Exemplarily, the material of the first interlayer dielectric layer 208 may be silicon oxide (SiOx). Exemplarily, the material of the second buffer layer 209 may be silicon nitride (SiNx).

[0202] S8: forming a second active layer on a side of the second buffer layer away from the substrate, and etching the second active layer to form a channel of the third transistor.

[0203] In step S8, Figure 11 As shown, a second active layer 210 is formed on the side of the second buffer layer 209 away from the substrate 000, and the second active layer 210 is etched to form the channel 015 of the third transistor T3. Exemplarily, the material of the second active layer 210 can be indium gallium zinc oxide (IGZO).

[0204] In some examples, a second active layer 210 may be deposited on a side of the second buffer layer 209 away from the substrate 000 , and the second active layer 210 may be dry-etched to form the channel 015 of the third transistor T3 .

[0205] S9: forming a third gate insulating layer on a side of the second active layer away from the substrate.

[0206] In step S9, if Figure 12 As shown, a third gate insulating layer 211 is formed on a side of the second active layer 210 away from the substrate 000 .

[0207] In some examples, a third gate insulating layer 211 is deposited on a side of the second active layer 210 away from the substrate 000. The third gate insulating layer 211 may be deposited using a plasma enhanced chemical vapor deposition (PECVD) device.

[0208] For example, the material of the third gate insulating layer 211 may be an inorganic layer, for example, the material of the third gate insulating layer 211 may be silicon oxide (SiOx).

[0209] S10: forming a third gate metal layer on a side of the third gate insulating layer away from the substrate, and etching the third gate metal layer to form a top gate of the third transistor.

[0210] In step S10, if Figure 12 As shown, a third gate metal layer 212 is formed on a side of the third gate insulating layer 211 away from the substrate 000 , and the third gate metal layer 212 is etched to form a top gate 011 of the third transistor T3 .

[0211] In some examples, a third gate metal layer 212 is deposited on a side of the third gate insulating layer 211 away from the substrate 000, and the third gate metal layer 212 is dry-etched to form the top gate 011 of the third transistor T3. Exemplarily, the material of the third gate insulating layer 211 can be molybdenum (Mo) or titanium nitride (TiN).

[0212] S11: forming a second interlayer dielectric layer on a side of the third gate metal layer away from the substrate.

[0213] In step S11, if Figure 12 As shown, a second interlayer dielectric layer 213 is formed on a side of the third gate metal layer 212 away from the substrate 200. CNT dry etching is then performed to form a third hole segment K21 that penetrates the second interlayer dielectric layer 213, the third gate insulating layer 211, the second buffer layer 209, the first interlayer dielectric layer 208, the second gate insulating layer 206, and the first gate insulating layer 204. Furthermore, a first hole segment K11 is formed that penetrates the third gate insulating layer 211 and the second interlayer dielectric layer 213.

[0214] S12: forming a first source / drain metal layer on a side of the second interlayer dielectric layer away from the substrate, the first source / drain metal layer filling the first hole segment and connecting to the first active layer, and the first source / drain metal layer filling the third hole segment and connecting to the second active layer.

[0215] In step S12, if Figure 12 As shown, a first source-drain metal layer 2151 is formed on the side of the second interlayer dielectric layer 213 away from the substrate 000 , the first source-drain metal layer 2151 fills the first hole segment K11 and connects to the first active layer 203 , and the first source-drain metal layer 2151 fills the third hole segment K21 and connects to the second active layer 210 .

[0216] In some examples, a first source-drain metal layer 2151 is deposited on a side of the second interlayer dielectric layer 213 away from the substrate 000 , the first source-drain metal layer 2151 fills the first hole segment K11 and connects to the first active layer 203 , and the first source-drain metal layer 2151 fills the third hole segment K21 and connects to the second active layer 210 .

[0217] For example, the material of the first source / drain metal layer 2151 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0218] S13: Forming a first planarization layer on a side of the first source / drain metal layer away from the substrate, and applying optical adhesive to the first planarization layer, exposing, developing, and curing the layer to form a second hole segment and a fourth hole segment. The second hole segment is connected to the first hole segment, and the fourth hole segment is connected to the third hole segment.

[0219] In step S13, if Figure 13As shown, a first planarization layer 214 is formed on the side of the first source / drain metal layer 2151 away from the substrate 000. The first planarization layer 214 is coated with optical adhesive, exposed, developed and cured to form a second hole segment K12 and a fourth hole segment K22.

[0220] The second hole segment K12 penetrates the first planarization layer 214 and exposes the first source / drain metal layer 2151. The second hole segment K12 is connected to the first hole segment K11 to form a first connection hole K1.

[0221] The fourth hole segment K22 penetrates the first planarization layer 214 and exposes the first source / drain metal layer 2151. The fourth hole segment K22 is connected to the third hole segment K21 to form a second connection hole K2.

[0222] In some examples, the material of the first planarization layer 214 is an organic material. For example, the material of the first planarization layer 214 can be polyimide (PI).

[0223] S14: Forming a second source / drain metal layer on a side of the first planarization layer away from the substrate. The second source / drain metal layer fills the second hole segment and is connected to the first source / drain metal layer. The second source / drain metal layer also fills the fourth hole segment and is connected to the first source / drain metal layer. Etching the second source / drain metal layer to form the source and drain of the third transistor and the source and drain of the driver transistor.

[0224] In step S14, if Figure 13 As shown, a second source-drain metal layer 2152 is formed on a side of the first planarization layer 214 away from the substrate. The second source-drain metal layer 2152 fills the second hole segment K12 and is connected to the first source-drain metal layer 2151. The second source-drain metal layer 2152 also fills the fourth hole segment K22 and is connected to the first source-drain metal layer 2151. The second source-drain metal layer 2152 is dry-etched to form the source 013 and drain 014 of the third transistor T3, and the source 022 and drain 023 of the drive transistor TD.

[0225] The second source-drain metal layer 2152 in the second hole segment K12 and the first source-drain metal layer 2151 in the first hole segment K11 form a source-drain metal layer 215, so that the source electrode 013 and the drain electrode 014 can be connected to the second active layer 210 through the first connection hole K1.

[0226] Furthermore, the second source-drain metal layer 2152 in the fourth hole segment K22 and the first source-drain metal layer 2151 in the third hole segment K21 form a source-drain metal layer 215, so that the source 022 and the drain 023 are connected to the channel 024 of the first active layer 203 through the second connection hole K2.

[0227] S15: forming a second planarization layer on a side of the second source / drain metal layer away from the substrate, and coating the second planarization layer with optical adhesive, exposing, developing, and curing the second planarization layer to form a third via hole.

[0228] In step S15, if Figure 14 As shown, a second planarization layer 216 is formed on the side of the second source / drain metal layer 2152 away from the substrate 000. That is, the second planarization layer 216 is formed on the side of the source / drain metal layer 215 away from the substrate 000, and the second planarization layer 216 is coated with optical adhesive, exposed, developed, and cured to form the third via hole K3.

[0229] In some examples, the material of the second planarization layer 216 is an organic material. For example, the material of the second planarization layer 216 can be polyimide (PI).

[0230] S16: forming an anode layer on a side of the second planarization layer away from the substrate, wherein the anode layer fills the third via hole and is connected to the source / drain metal layer.

[0231] In step S16, if Figure 14 As shown, an anode layer 217 is formed on the side of the second planarization layer 216 away from the substrate 000. The anode layer 217 fills the third via hole K3, connecting the anode layer 217 to the source / drain metal layer 215. For example, the anode layer 217 is connected to the drain electrode 023 of the driving transistor TD through the third via hole K3.

[0232] In some examples, an anode layer 217 is deposited on a side of the second planarization layer 216 away from the substrate 000, and an anode is formed by wet etching the anode layer 217. For example, the material of the anode layer 217 can be an ITO / Ag / ITO multilayer composite material.

[0233] S17: forming a pixel definition layer on a side of the anode layer away from the substrate, and coating the pixel definition layer with optical adhesive, exposing, developing, and curing the pixel definition layer to expose the anode layer.

[0234] In step S17, if Figure 9 As shown, a pixel definition layer 218 is formed on a side of the anode layer 217 away from the substrate, and the pixel definition layer 218 is coated with an optical adhesive, exposed, developed and cured to expose the anode layer 217 .

[0235] In some examples, the material of the second planarization layer 216 is an organic material. For example, the material of the pixel definition layer 218 can be polyimide (PI).

[0236] In some embodiments, a light-emitting device may be formed on a side of the pixel definition layer 218 away from the substrate, and the light-emitting device is located on a side of the anode layer away from the substrate.

[0237] The above manufacturing method is illustrated using only the third transistor T3 and the driving transistor TD as examples. The structure of the sixth transistor T6 can refer to the structure of the third transistor T3. The structures of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can also refer to the structure of the driving transistor TD.

[0238] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit having a light-emitting cycle, wherein the light-emitting cycle includes a refresh frame and multiple hold frames, wherein the refresh frame includes a write phase, a first reset phase, and a first light-emitting phase; and the hold frame includes an adjustment phase, a second reset phase, and a second light-emitting phase; characterized in that: include: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a light emitting control sub-circuit, and a first reset sub-circuit; The driving sub-circuit is coupled to the first node, the second node, and the third node, and is configured to transmit the voltage from the second node to the third node under the control of the voltage of the first node during the writing phase; The write sub-circuit is coupled to the second node, the first scan signal terminal, and the data signal terminal, and is configured to transmit the data signal received at the data signal terminal to the second node under the control of the first scan signal received from the first scan signal terminal during the write phase and the adjustment phase; The compensation sub-circuit is coupled to the first node, the third node, and the second scan signal terminal, and is configured to, during the write phase, transfer the voltage of the third node to the first node under the control of the second scan signal received from the second scan signal terminal; The light emitting control subcircuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light emitting device; The light-emitting control subcircuit is configured to cooperate with the driving subcircuit to transmit a driving signal to the light-emitting device under the control of the enable signal from the enable signal terminal during the first light-emitting phase and the second light-emitting phase; The first reset sub-circuit is coupled to the third node, the third scan signal terminal and the first reference voltage signal terminal; the first reset sub-circuit is configured to, in the first reset phase and the second reset phase, under the control of the third scan signal received from the third scan signal terminal, transmit the first reference voltage received by the first reference voltage signal terminal to the third node to refresh the third node.

2. The pixel driving circuit according to claim 1, wherein: The first reset sub-circuit includes a first transistor; The gate of the first transistor is coupled to the third scan signal terminal, the first electrode of the first transistor is coupled to the third node, and the second electrode of the first transistor is coupled to the first reference voltage signal terminal.

3. The pixel driving circuit according to claim 1, wherein: The driving sub-circuit includes a driving transistor; The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node.

4. The pixel driving circuit according to claim 1, wherein: The write sub-circuit includes a second transistor; A gate of the second transistor is coupled to the first scan signal terminal, a first electrode of the second transistor is coupled to the data signal terminal, and a second electrode of the second transistor is coupled to the second node.

5. The pixel driving circuit according to claim 1, wherein: The compensation sub-circuit includes a third transistor; the third transistor is a metal oxide transistor; A gate of the third transistor is coupled to the second scan signal terminal, a first electrode of the third transistor is coupled to the first node, and a second electrode of the third transistor is coupled to the third node.

6. The pixel driving circuit according to claim 1, wherein: The light emitting control subcircuit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the enable signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node; A gate of the fifth transistor is coupled to the enable signal terminal, a first electrode of the fifth transistor is coupled to the third node, and a second electrode of the fifth transistor is coupled to the light emitting device.

7. The pixel driving circuit according to claim 1, wherein: The value range of the first reference voltage signal received at the first reference voltage signal terminal is 0V~6.5V.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein: Also includes: The second reset sub-circuit is coupled to the first node, the first reset signal terminal, and the first initialization signal terminal; the second reset sub-circuit is configured to, in a reset phase, under the control of the reset signal received from the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the first node to reset the first node.

9. The pixel driving circuit according to claim 8, wherein: The second reset sub-circuit includes a sixth transistor; the sixth transistor is a metal oxide transistor; A gate of the sixth transistor is coupled to the first reset signal terminal, a first electrode of the sixth transistor is coupled to the first node, and a second electrode of the sixth transistor is coupled to the first initialization signal terminal.

10. The pixel driving circuit according to any one of claims 1 to 7, wherein: Also includes: a third reset subcircuit coupled to the second reset signal terminal, the second initialization signal terminal, and the light emitting device; The third reset sub-circuit is configured to, under the control of the reset signal received from the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the light-emitting device.

11. The pixel driving circuit according to claim 10, wherein: The third reset sub-circuit includes a seventh transistor; A gate of the seventh transistor is coupled to the second reset signal terminal, a first electrode of the seventh transistor is coupled to the light emitting device, and a second electrode of the seventh transistor is coupled to the second initialization signal terminal.

12. The pixel driving circuit according to claim 10, wherein: The second reset signal terminal and the first scan signal terminal respond to control of the same control signal.

13. The pixel driving circuit according to any one of claims 1 to 7, wherein: Also includes: a first storage sub-circuit coupled to the first voltage terminal and the first node; The first storage sub-circuit includes a first capacitor, a first plate of the first capacitor is coupled to the first voltage terminal, and a second plate of the first capacitor is coupled to a first node.

14. A driving method for a pixel driving circuit, characterized in that: The pixel driving circuit includes: a driving subcircuit, a writing subcircuit, a compensation subcircuit, a light emitting control subcircuit and a first reset subcircuit; The driving sub-circuit is coupled to the first node, the second node and the third node; The writing sub-circuit is coupled to the second node, the first scanning signal terminal and the data signal terminal; The compensation sub-circuit is coupled to the first node, the third node and the second scan signal terminal; The light emitting control subcircuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light emitting device; The first reset sub-circuit is coupled to the third node, the third scan signal terminal and the first reference voltage signal terminal; The driving method includes: a plurality of light-emitting cycles, wherein one light-emitting cycle includes a refresh frame and a plurality of hold frames; The refresh frame includes an initialization phase, a write phase, a first reset phase, and a first light-emitting phase; the hold frame includes an adjustment phase, a second reset phase, and a second light-emitting phase; In the write phase, the write sub-circuit, under the control of the first scan signal received from the first scan signal terminal, transmits the data signal received at the data signal terminal to the second node; the data signal received at the data signal terminal is a first data signal; the drive sub-circuit transmits the first data signal from the second node to a third node; and the compensation sub-circuit transmits the voltage of the third node to the first node; In the first reset phase, the first reset sub-circuit, under the control of the third scan signal received from the third scan signal terminal, transmits the first reference voltage received at the first reference voltage signal terminal to the third node, and refreshes the first data signal received at the third node to the first reference voltage; In the first light-emitting phase, under the control of the enable signal received from the enable signal terminal, in cooperation with the driving sub-circuit, the first reference voltage received at the third node and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device to drive the light-emitting device to emit light; In the adjustment phase, under the control of the first scan signal received from the first scan signal terminal, the data signal received at the data signal terminal is transmitted to the second node; the data signal received at the data signal terminal is a second data signal; the driving sub-circuit transmits the second data signal from the second node to the third node; wherein the magnitude of the second data signal is different from the magnitude of the first data signal; In the second reset phase, the first reset sub-circuit, under the control of the third scan signal received from the third scan signal terminal, transmits the first reference voltage received at the first reference voltage signal terminal to the third node, and refreshes the second data signal received at the third node to the first reference voltage; In the second light-emitting stage, under the control of the enable signal received from the enable signal terminal, in cooperation with the driving sub-circuit, the first reference voltage received at the third node and the first voltage signal provided by the first voltage terminal are transmitted to the light-emitting device to drive the light-emitting device to emit light.

15. A display panel, characterized in that: include: A plurality of pixel driving circuits according to any one of claims 1 to 13, and A light emitting device electrically connected to the pixel driving circuit.

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