A compatible thyristor dimming circuit and a compatible dimming method

Abstract

The present invention discloses a compatible thyristor dimming circuit, which includes an input end, a peak voltage sampling circuit, a control chip U4, a mains input detection circuit, a linear compensation circuit, a power supply circuit and an output circuit. The control chip U4 is electrically connected to the peak voltage sampling circuit, the mains input detection circuit, the linear compensation circuit, the power supply circuit and the output circuit. The present invention also discloses a compatible dimming method. The present invention realizes automatic judgment of the mains input, peak voltage sampling processing and linear compensation, so that the thyristor dimming circuit can be compatible with thyristor dimming application products that work at full voltages such as US standard 120V and European standard 230V, thereby improving compatibility and applicability, and eliminating the need to set up two dimming circuits of different specifications, reducing costs, eliminating the need for manual judgment and conversion of the input mains voltage, improving compatibility efficiency, and meeting the use of voltage ranges in various regions around the world.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor dimming circuits, and in particular to a compatible thyristor dimming circuit and a compatible dimming method. Background Art

[0002] Thyristor dimming technology is a traditional dimming technology. Currently, the circuits using thyristor dimming in the industry mainly include European 230V dimmers and US 120V dimmers. Due to the different regions and requirements for use of European 230V dimmers and US 120V dimmers, the mains input voltages used are different. Their dimming circuits are independent and cannot achieve adaptive adjustment of multiple voltages on a single dimmer. This leads to poor compatibility and low applicability. When compatibility is required, two specifications of dimmers need to be equipped for dimming processing, which is costly and requires manual judgment and conversion. The steps are cumbersome and labor-intensive. Conversion errors are prone to damage to connected equipment and cannot meet the existing voltage ranges in various regions around the world. As a result, the dimming voltage on the market is high in cost and difficult to control in quality. Summary of the Invention

[0003] This invention aims to solve the current technical deficiencies and provides a compatible thyristor dimming circuit.

[0004] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0005] A compatible thyristor dimming circuit, the compatible thyristor dimming circuit includes an input end, a peak voltage sampling circuit, a mains input detection circuit, a linear compensation circuit, a power supply circuit and an output circuit, the input end is connected to the peak voltage sampling circuit, one end of the peak voltage sampling circuit is connected to the mains input detection circuit, the other end of the peak voltage sampling circuit is connected to one end of the linear compensation circuit, and the other end of the mains input detection circuit is connected to the other end of the linear compensation circuit, the compatible thyristor dimming circuit is provided with a control chip U4, the control chip U4 is electrically connected to the peak voltage sampling circuit, the mains input detection circuit, the linear compensation circuit, the power supply circuit and the output circuit, the control chip U4 is used to play a control role, the power supply circuit is provided with a first node, a connection end VCC and a connection end VCC2, the first node is connected to the other end of the mains input detection circuit, the output circuit is connected to the linear compensation circuit, and the control chip is provided with a pin end VDD, a pin end DIM, a pin end GND, a pin end FB, a pin end CS and a pin end GATE.

[0006] As a further improvement, the peak voltage sampling circuit includes a resistor RR1, a rectifier bridge BD1, a film capacitor CB1, a film capacitor CB2, a diode D1, an electrolytic capacitor EC1 and a first ground terminal, the rectifier bridge is provided with a pin terminal one, a pin terminal two, a pin terminal three and a pin terminal four, the input terminal includes a live wire connection terminal L and a neutral wire connection terminal N, the live wire connection terminal L is connected to the pin terminal one, the neutral wire connection terminal N is connected to the pin three, the pin two is connected to one end of the resistor RR1, the other end of the resistor RR1 is connected to one end of the film capacitor CB1, the pin four is connected to the other end of the film capacitor CB1, the pin two is connected to the resistor R A second node and a third node are provided between the pin R1, a fourth node and a fifth node are provided between the pin four and the thin-film capacitor CB1, one end of the thin-film capacitor CB2 is connected to the second node, and the other end of the thin-film capacitor CB2 is connected to the fourth node, a sixth node is provided between the resistor RR1 and the thin-film capacitor CB1, one end of the diode D1 is connected to the sixth node, and the other end of the diode D1 is connected to the mains input detection circuit, a seventh node is provided between the diode D1 and the mains input detection circuit, the seventh node is connected to one end of the electrolytic capacitor EC1, and the other end of the electrolytic capacitor EC1 is connected to the first ground end.

[0007] As a further improvement, the control chip U4 includes a pin DIM, a pin VDD, a pin GATE, a pin CS, a pin FB and a pin GND, and the mains input detection circuit includes a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C2, a capacitor C3, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a three-terminal regulator U3, a follower comparator U2, a resistor R12, a resistor R14 and a MOS tube Q1, one end of the resistor R7 is connected in series with the seventh node, the other end of the resistor R7 is connected in series with one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected in series with the thin film capacitor CB1 The resistor R8 is connected to the resistor R10, and an eighth node is provided between the resistor R8 and the resistor R10. The follower comparator U2 includes a positive pin, a negative pin, a pin two, a pin four and a pin six. The positive pin is connected to the eighth node. A connection point B is provided between the positive pin and the eighth node. The connection point B is connected to the pin four. The pin six is ​​connected to the connection terminal one VCC. A ninth node is provided between the positive pin and the eighth node. The ninth node is connected to the pin four. One end of the capacitor C3 is connected in series with the resistor R10, and the other end of the capacitor C3 is connected to the connection terminal one VCC. The other end of the capacitor C3 is also connected in series with one end of the resistor R11, and the other end of the resistor R11 is connected to the The negative pin of the follower comparator U2 is connected, and a tenth node and an eleventh node are provided between the resistor R11 and the negative pin. The three-terminal regulator U3 includes a first pin end, a second pin end, and a third pin end. The tenth node is connected in series with the second pin end, the first pin end is connected in series with one end of the capacitor C3, the third pin end is connected to the eleventh node, the negative pin is connected in series with the first pin end, and a twelfth node is provided between the negative pin and the first pin end. The twelfth node is connected to one end of the resistor R14, the other end of the resistor R14 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the pin four, and the resistor R14 is connected to the resistor R1 2, the MOS transistor Q1 includes a gate, a source, and a drain, the thirteenth node is connected to the gate, the twelfth node of the source is connected in series, the drain is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the pin end DIM, a fourteenth node, a fifteenth node, and a connection point C are provided between the resistor R9 and the pin end DIM, the fifteenth node is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the source, a seventeenth node is provided between the source and the capacitor C2, the seventeenth node is provided with a second ground terminal, the connection point C is connected to one end of the resistor R13, and the other end of the resistor R13 is connected in series with the seventeenth node.

[0008] As a further improvement, the linear compensation circuit includes a resistor R1, a resistor R4, a resistor R5, a capacitor C1, a follower comparator U1, a voltage regulator diode ZD1 and a resistor R6, one end of the resistor R1 is connected in series with one end of the resistor RR1, the other end of the resistor R1 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to a third ground terminal, an eighteenth node is provided between the resistor R5 and the third ground terminal, a nineteenth node is provided between the resistor R4 and the resistor R5, and the follower comparator U1 includes a positive pin 1, a negative pin 1, a first pin Pin 2, first pin 4 and first pin 6, the positive pin 1 is connected to the nineteenth node, a connection point A is provided between the positive pin 1 and the nineteenth node, the connection point A is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the eighteenth node, the first pin 2 is connected to a third ground terminal, the first pin 6 is connected to the connection terminal 2 VCC2, the first pin 4 is connected in series with the negative pin 1, the first pin 4 is connected to one end of the Zener diode ZD1, the positive end of the Zener diode ZD1 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the fourteenth node.

[0009] As a further improvement, the capacitive thyristor dimming circuit is further provided with a first voltage divider circuit and a second voltage divider circuit, the first voltage divider circuit includes a resistor R2 and a resistor R3, the second voltage divider circuit includes a resistor R15 and a resistor R16, one end of the resistor R2 is connected in series with one end of the resistor R1, the other end of the resistor R2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the connection point C, one end of the resistor R15 is connected in series with one end of the resistor R2, the other end of the resistor R15 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the pin end VDD.

[0010] As a further improvement, the output circuit includes a MOS transistor Q2, a transformer T, a diode D2, an electrolytic capacitor EC1, an output terminal Vout+, and an output terminal Vout-. The transformer T includes a transformer terminal T1A and a transformer terminal T1C. The MOS transistor Q2 includes a second gate, a second source, and a second drain. One end of the transformer terminal T1A is connected to one end of the resistor R15, the other end of the transformer terminal T1A is connected to the second drain, the second gate is connected to the pin terminal GATE, the second source is connected to the pin terminal CS, and a twenty-first node is provided between the second source and the pin terminal CS. One end of the transformer terminal T1C is connected to one end of the diode D2, the other end of the diode D2 is connected to the output terminal Vout+, the other end of the transformer terminal T1C is connected to the output terminal Vout-, one end of the electrolytic capacitor EC1 is connected between the diode D2 and the output terminal Vout+, and the other end of the electrolytic capacitor EC1 is connected between the other end of the transformer terminal T1C and the output terminal Vout-.

[0011] As a further improvement, the 21st node is provided with a resistor RS1, the 21st node is connected in series with one end of the resistor RS1, the other end of the resistor RS1 is connected to the first node, the first node is connected to the other end of the resistor R13, a 22nd node is provided between the first node and the resistor R13, and the 22nd node is connected to the pin end GND.

[0012] As a further improvement, the power supply circuit includes an electrolytic capacitor EC3, a diode D3, a diode D4, a voltage-stabilizing diode ZD2, a transistor Q3, a resistor R17, an electrolytic capacitor EC4 and a magnetic core inductor T1B, one end of the magnetic core inductor T1B is connected to one end of the diode D4, the other end of the magnetic core inductor T1B is connected to the first node, the transistor Q3 is an NPN transistor, the other end of the diode D4 is connected to the C pole of the transistor Q3, the E pole of the transistor Q3 is connected to one end of the diode D3, the other end of the diode D3 is connected to one end of the electrolytic capacitor EC3, the other end of the electrolytic capacitor EC3 is connected to the first node, the B pole of the transistor Q3 is connected to one end of the voltage-stabilizing diode ZD2, and the other end of the voltage-stabilizing diode ZD2 is connected to The other end of EC3 is connected, a twenty-third node is provided between the transistor Q3 and the Zener diode ZD2, a twenty-fourth node and a twenty-fifth node are provided between the transistor Q3 and the diode D4, one end of the resistor R17 is connected to the twenty-third node, the other end of the resistor R17 is connected to the twenty-fourth node, a twenty-fifth node is provided between the magnetic core inductor T1B and the first node, one end of the electrolytic capacitor EC4 is connected to the twenty-fourth node, the other end of the electrolytic capacitor EC4 is connected to the twenty-fifth node, a twenty-sixth node is provided between the E pole of the transistor Q3 and the diode D3, the twenty-sixth node is connected to the second connection terminal VCC2, a twenty-seventh node is provided between the diode D3 and the electrolytic capacitor EC3, and the first connection terminal VCC is connected to the twenty-seventh node.

[0013] A compatible dimming method for the compatible thyristor dimming circuit includes the following steps:

[0014] (1) Electrical connection: The input terminal is connected to the mains electricity, and the power supply circuit provides power to the circuit in the compatible thyristor dimming circuit and the control chip U4 after voltage transformation;

[0015] (2) Peak voltage sampling: After the mains is connected, the rectifier bridge of the peak voltage sampling circuit is used for rectification to obtain the rectified output voltage and the pulsed DC voltage. The pulsed DC voltage is input to the linear compensation circuit for processing. The rectified output voltage is processed by the resistor RR1. The resistor RR1 attenuates the peak noise interference of the rectified output voltage to reduce the influence of the interference. The rectified output voltage after attenuation is used to charge and discharge the film capacitor CB1 to obtain a pulse voltage, which is then rectified by the diode D1 and output to the electrolytic capacitor EC1 for filtering to obtain a peak DC voltage.

[0016] (3) Mains input detection: The DC voltage obtained by the peak voltage sampling action is processed by the mains input detection circuit, and the DC voltage is divided by resistors R7, R8 and R10. The divided voltage is input to the positive pin of the follower comparator U2 through the connection point B. The three-terminal voltage regulator U3 is connected to the negative pin of the follower comparator U2 to generate a voltage of a reference voltage source after power is turned on. The divided voltage obtained by the positive pin of the follower comparator U2 is compared with the reference voltage of the reference voltage source obtained by the negative pin. If the input voltage is 120V, the divided voltage at the connection point B is lower than the reference voltage of the negative pin, the follower comparator U2 outputs a low level, the MOS tube Q2 of the output circuit is cut off and does not conduct, and the dimming control detection signal can only be divided by the resistors R2, R3 and R13 of the first voltage divider circuit to obtain a secondary divided voltage. The secondary divided voltage is input to the pin DIM of the control chip U4 through the connection point C for dimming processing;

[0017] If the input voltage is 230V, the divided voltage at the connection point B is higher than the reference voltage of the negative pin, the follower comparator U2 outputs a high level, the MOS tube Q2 of the output circuit is saturated and turned on, and the resistors R9 and R13 are connected in parallel. The dimming control detection signal is obtained by dividing the resistors R2, R3, R13, and R9 of the first voltage divider circuit to obtain a secondary divided voltage at the connection point C, which is then input to the pin DIM of the control chip U4. The obtained voltage can almost maintain the corresponding potential of the control voltage when the input is 120V;

[0018] (4) Linear compensation processing: The pulsed DC voltage passes through the voltage divider circuit composed of resistors R1, R4 and R5 to obtain the divided voltage of the connection point A, which is input to the positive pin 1 of the follower comparator U1. The output end follows the divided voltage of the positive pin 1 to output. When the input voltage is in the 120V voltage range, the divided voltage of the connection point A obtained by voltage division will be lower than the minimum working voltage of the Zener diode ZD1, which is equivalent to the Zener diode ZD1 being cut off. Therefore, the linear compensation circuit does not compensate for the dimming detection voltage of the pin DIM; when the input working voltage is in the 230V high voltage range, the divided voltage of the connection point A obtained by voltage division will be higher than the minimum working voltage of the Zener diode ZD1. Therefore, the linear compensation circuit compensates for the dimming detection voltage of the pin DIM accordingly.

[0019] (5) Output drive: The voltage after the linear compensation circuit is supplemented and processed passes through the output circuit. After the output circuit is processed by the transformer T, the voltage is driven by the output terminal Vout+ and the output terminal Vout- to drive the dimming action.

[0020] Beneficial effects of the present invention: The present invention realizes automatic judgment of mains input, peak voltage sampling processing and linear compensation by setting a peak voltage sampling circuit, a mains input detection circuit, a linear compensation circuit, a first voltage divider circuit, a second voltage divider circuit and a control chip U4, so that the thyristor dimming circuit can be compatible with thyristor dimming application products that work at full voltages such as US standard 120V and European standard 230V, greatly improving compatibility and applicability, and there is no need to set up two dimming circuits of different specifications, reducing the cost and the overall volume of the dimmer, while eliminating the need for manual judgment and conversion of the input mains voltage, improving compatibility efficiency, and by setting a linear compensation circuit to perform corresponding compensation for the dimming detection voltage, ensuring dimming smoothness, dimming efficiency and effect; the circuit structure of the present invention is simple, meeting the use of the existing voltage ranges in various regions of the world, and by setting a rectifier bridge for sorting and protection, ensuring the service life of the compatible thyristor dimming circuit, and attenuating the peak noise, reducing interference, and ensuring the accuracy of peak voltage sampling.

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of a compatible thyristor dimming circuit of this embodiment;

[0023] Figure 2 Schematic diagram of the steps of the compatible dimming method of this embodiment. DETAILED DESCRIPTION

[0024] The following description is merely a preferred embodiment of the present invention and does not limit the scope of protection of the present invention.

[0025] For example, see the attached Figures 1 and 2, a compatible thyristor dimming circuit, the compatible thyristor dimming circuit includes an input end, a peak voltage sampling circuit, a mains input detection circuit, a linear compensation circuit, a power supply circuit and an output circuit, the input end is connected to the peak voltage sampling circuit, one end of the peak voltage sampling circuit is connected to the mains input detection circuit, the other end of the peak voltage sampling circuit is connected to one end of the linear compensation circuit, and the other end of the mains input detection circuit is connected to the other end of the linear compensation circuit, the compatible thyristor dimming circuit is provided with a control chip U4, the control chip U4 is electrically connected to the peak voltage sampling circuit, the mains input detection circuit, the linear compensation circuit, the power supply circuit and the output circuit, the control chip U4 is used to play a control role, the power supply circuit is provided with a first node, a connection end VCC and a connection end VCC2, the first node is connected to the other end of the mains input detection circuit, the output circuit is connected to the linear compensation circuit, the control chip is provided with a pin end VDD, a pin end DIM, a pin end GND, a pin end FB, a pin end CS and a pin end GATE.

[0026] The peak voltage sampling circuit includes a resistor RR1, a rectifier bridge BD1, a film capacitor CB1, a film capacitor CB2, a diode D1, an electrolytic capacitor EC1 and a first ground terminal. The rectifier bridge is provided with a pin terminal 1, a pin terminal 2, a pin terminal 3 and a pin terminal 4. The input terminal includes a live wire connection terminal L and a neutral wire connection terminal N. The live wire connection terminal L is connected to the pin terminal 1, the neutral wire connection terminal N is connected to the pin 3, the pin 2 is connected to one end of the resistor RR1, the other end of the resistor RR1 is connected to one end of the film capacitor CB1, the pin 4 is connected to the other end of the film capacitor CB1, and the pin 2 is connected to the resistor RR1. A second node and a third node are provided between the pin four and the thin-film capacitor CB1, a fourth node and a fifth node are provided between the pin four and the thin-film capacitor CB1, one end of the thin-film capacitor CB2 is connected to the second node, and the other end of the thin-film capacitor CB2 is connected to the fourth node, a sixth node is provided between the resistor RR1 and the thin-film capacitor CB1, one end of the diode D1 is connected to the sixth node, and the other end of the diode D1 is connected to the mains input detection circuit, a seventh node is provided between the diode D1 and the mains input detection circuit, the seventh node is connected to one end of the electrolytic capacitor EC1, and the other end of the electrolytic capacitor EC1 is connected to the first ground end.

[0027] The control chip U4 includes a pin DIM, a pin VDD, a pin GATE, a pin CS, a pin FB and a pin GND. The mains input detection circuit includes a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C2, a capacitor C3, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a three-terminal regulator U3, a follower comparator U2, a resistor R12, a resistor R14 and a MOS tube Q1. One end of the resistor R7 is connected in series with the seventh node, the other end of the resistor R7 is connected in series with one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected in series with the thin film capacitor CB1. An eighth node is provided between the resistor R8 and the resistor R10, and the follower comparator U2 includes a positive pin, a negative pin, a pin two, a pin four, and a pin six. The positive pin is connected to the eighth node, and a connection point B is provided between the positive pin and the eighth node, and the connection point B is connected to the pin four. The pin six is ​​connected to the connection terminal one VCC. A ninth node is provided between the positive pin and the eighth node, and the ninth node is connected to the pin four. One end of the capacitor C3 is connected in series with the resistor R10, and the other end of the capacitor C3 is connected to the connection terminal one VCC. The other end of the capacitor C3 is also connected in series with one end of the resistor R11, and the other end of the resistor R11 is connected to the follower comparator U2. The negative pin of the comparator U2 is connected, and a tenth node and an eleventh node are provided between the resistor R11 and the negative pin. The three-terminal regulator U3 includes a first pin end, a second pin end and a third pin end. The tenth node is connected in series with the second pin end, the first pin end is connected in series with one end of the capacitor C3, the third pin end is connected to the eleventh node, the negative pin is connected in series with the first pin end, and a twelfth node is provided between the negative pin and the first pin end. The twelfth node is connected to one end of the resistor R14, the other end of the resistor R14 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the pin four, and the resistor R14 is connected to the resistor R12. A thirteenth node is provided between the two terminals. The MOS transistor Q1 includes a gate, a source, and a drain. The thirteenth node is connected to the gate. The twelfth node of the source is connected in series. The drain is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the pin end DIM. A fourteenth node, a fifteenth node, and a connection point C are provided between the resistor R9 and the pin end DIM. The fifteenth node is connected to one end of the capacitor C2. The other end of the capacitor C2 is connected to the source. A seventeenth node is provided between the source and the capacitor C2. The seventeenth node is provided with a second ground terminal. The connection point C is connected to one end of the resistor R13. The other end of the resistor R13 is connected in series with the seventeenth node.

[0028] The linear compensation circuit includes a resistor R1, a resistor R4, a resistor R5, a capacitor C1, a follower comparator U1, a voltage regulator diode ZD1 and a resistor R6. One end of the resistor R1 is connected in series with one end of the resistor RR1, the other end of the resistor R1 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to a third ground terminal, an eighteenth node is provided between the resistor R5 and the third ground terminal, a nineteenth node is provided between the resistor R4 and the resistor R5, and the follower comparator U1 includes a positive pin 1, a negative pin 1, a first pin 2, The first pin four and the first pin six, the positive pin one is connected to the nineteenth node, a connection point A is provided between the positive pin one and the nineteenth node, the connection point A is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the eighteenth node, the first pin two is connected to a third ground terminal, the first pin six is ​​connected to the connection terminal two VCC2, the first pin four is connected in series with the negative pin one, the first pin four is connected to one end of the Zener diode ZD1, the positive end of the Zener diode ZD1 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the fourteenth node.

[0029] The capacitive thyristor dimming circuit is also provided with a first voltage divider circuit and a second voltage divider circuit, the first voltage divider circuit includes a resistor R2 and a resistor R3, the second voltage divider circuit includes a resistor R15 and a resistor R16, one end of the resistor R2 is connected in series with one end of the resistor R1, the other end of the resistor R2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the connection point C, one end of the resistor R15 is connected in series with one end of the resistor R2, the other end of the resistor R15 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the pin end VDD.

[0030] The output circuit includes a MOS transistor Q2, a transformer T, a diode D2, an electrolytic capacitor EC1, an output terminal Vout+, and an output terminal Vout-. The transformer T includes a transformer terminal T1A and a transformer terminal T1C. The MOS transistor Q2 includes a second gate, a second source, and a second drain. One end of the transformer terminal T1A is connected to one end of the resistor R15, the other end of the transformer terminal T1A is connected to the second drain, the second gate is connected to the pin terminal GATE, the second source is connected to the pin terminal CS, and a twenty-first node is provided between the second source and the pin terminal CS. One end of the transformer terminal T1C is connected to one end of the diode D2, the other end of the diode D2 is connected to the output terminal Vout+, the other end of the transformer terminal T1C is connected to the output terminal Vout-, one end of the electrolytic capacitor EC1 is connected between the diode D2 and the output terminal Vout+, and the other end of the electrolytic capacitor EC1 is connected between the other end of the transformer terminal T1C and the output terminal Vout-.

[0031] The 21st node is provided with a resistor RS1, the 21st node is connected in series with one end of the resistor RS1, the other end of the resistor RS1 is connected to the first node, the first node is connected to the other end of the resistor R13, a 22nd node is provided between the first node and the resistor R13, and the 22nd node is connected to the pin end GND.

[0032] The power supply circuit includes an electrolytic capacitor EC3, a diode D3, a diode D4, a voltage-stabilizing diode ZD2, a transistor Q3, a resistor R17, an electrolytic capacitor EC4 and a magnetic core inductor T1B, one end of the magnetic core inductor T1B is connected to one end of the diode D4, the other end of the magnetic core inductor T1B is connected to the first node, the transistor Q3 is an NPN transistor, the other end of the diode D4 is connected to the C pole of the transistor Q3, the E pole of the transistor Q3 is connected to one end of the diode D3, the other end of the diode D3 is connected to one end of the electrolytic capacitor EC3, the other end of the electrolytic capacitor EC3 is connected to the first node, the B pole of the transistor Q3 is connected to one end of the voltage-stabilizing diode ZD2, the other end of the voltage-stabilizing diode ZD2 is connected to the E pole of the transistor Q3. The other end of C3 is connected, a twenty-third node is provided between the transistor Q3 and the Zener diode ZD2, a twenty-fourth node and a twenty-fifth node are provided between the transistor Q3 and the diode D4, one end of the resistor R17 is connected to the twenty-third node, the other end of the resistor R17 is connected to the twenty-fourth node, a twenty-fifth node is provided between the magnetic core inductor T1B and the first node, one end of the electrolytic capacitor EC4 is connected to the twenty-fourth node, the other end of the electrolytic capacitor EC4 is connected to the twenty-fifth node, a twenty-sixth node is provided between the E pole of the transistor Q3 and the diode D3, the twenty-sixth node is connected to the second connection terminal VCC2, a twenty-seventh node is provided between the diode D3 and the electrolytic capacitor EC3, and the first connection terminal VCC is connected to the twenty-seventh node.

[0033] A compatible dimming method for the compatible thyristor dimming circuit includes the following steps:

[0034] (1) Electrical connection: The input terminal is connected to the mains electricity, and the power supply circuit provides power to the circuit in the compatible thyristor dimming circuit and the control chip U4 after voltage transformation;

[0035] (2) Peak voltage sampling: After the mains is connected, the rectifier bridge of the peak voltage sampling circuit is used for rectification to obtain the rectified output voltage and the pulsed DC voltage. The pulsed DC voltage is input to the linear compensation circuit for processing. The rectified output voltage is processed by the resistor RR1. The resistor RR1 attenuates the peak noise interference of the rectified output voltage to reduce the influence of the interference. The rectified output voltage after attenuation is used to charge and discharge the film capacitor CB1 to obtain a pulse voltage, which is then rectified by the diode D1 and output to the electrolytic capacitor EC1 for filtering to obtain a peak DC voltage.

[0036] (3) Mains input detection: The DC voltage obtained by the peak voltage sampling action is processed by the mains input detection circuit, and the DC voltage is divided by resistors R7, R8 and R10. The divided voltage is input to the positive pin of the follower comparator U2 through the connection point B. The three-terminal voltage regulator U3 is connected to the negative pin of the follower comparator U2 to generate a voltage of a reference voltage source after power is turned on. The divided voltage obtained by the positive pin of the follower comparator U2 is compared with the reference voltage of the reference voltage source obtained by the negative pin. If the input voltage is 120V, the divided voltage at the connection point B is lower than the reference voltage of the negative pin, the follower comparator U2 outputs a low level, the MOS tube Q2 of the output circuit is cut off and does not conduct, and the dimming control detection signal can only be divided by the resistors R2, R3 and R13 of the first voltage divider circuit to obtain a secondary divided voltage. The secondary divided voltage is input to the pin DIM of the control chip U4 through the connection point C for dimming processing;

[0037] If the input voltage is 230V, the divided voltage at the connection point B is higher than the reference voltage of the negative pin, the follower comparator U2 outputs a high level, the MOS tube Q2 of the output circuit is saturated and turned on, and the resistors R9 and R13 are connected in parallel. The dimming control detection signal is obtained by dividing the resistors R2, R3, R13, and R9 of the first voltage divider circuit to obtain a secondary divided voltage at the connection point C, which is then input to the pin DIM of the control chip U4. The obtained voltage can almost maintain the corresponding potential of the control voltage when the input is 120V;

[0038] (4) Linear compensation processing: The pulsed DC voltage passes through the voltage divider circuit composed of resistors R1, R4 and R5 to obtain the divided voltage of the connection point A, which is input to the positive pin 1 of the follower comparator U1. The output end follows the divided voltage of the positive pin 1 to output. When the input voltage is in the 120V voltage range, the divided voltage of the connection point A obtained by voltage division will be lower than the minimum working voltage of the Zener diode ZD1, which is equivalent to the Zener diode ZD1 being cut off. Therefore, the linear compensation circuit does not compensate for the dimming detection voltage of the pin DIM; when the input working voltage is in the 230V high voltage range, the divided voltage of the connection point A obtained by voltage division will be higher than the minimum working voltage of the Zener diode ZD1. Therefore, the linear compensation circuit compensates for the dimming detection voltage of the pin DIM accordingly.

[0039] (5) Output drive: The voltage after the linear compensation circuit is supplemented and processed passes through the output circuit. After the output circuit is processed by the transformer T, the voltage is driven by the output terminal Vout+ and the output terminal Vout- to drive the dimming action.

[0040] The present invention realizes automatic judgment of mains input, peak voltage sampling processing and linear compensation by setting a peak voltage sampling circuit, a mains input detection circuit, a linear compensation circuit, a first voltage divider circuit, a second voltage divider circuit and a control chip U4, so that the thyristor dimming circuit can be compatible with thyristor dimming application products with full voltage operation such as US standard 120V and European standard 230V, greatly improving compatibility and applicability, and there is no need to set up two dimming circuits of different specifications, reducing the cost and the overall volume of the dimmer, while eliminating the need for manual judgment and conversion of the input mains voltage, improving compatibility efficiency, and by setting a linear compensation circuit to perform corresponding compensation for the dimming detection voltage, ensuring dimming smoothness, efficiency and effect; the circuit structure of the present invention is simple, meeting the use of the existing voltage ranges in various regions of the world, and by setting a rectifier bridge for sorting and protection, ensuring the service life of the compatible thyristor dimming circuit, and attenuating the peak noise, reducing interference, and ensuring the accuracy of peak voltage sampling.

[0041] The present invention is not limited to the above-mentioned embodiments. Other compatible thyristor dimming circuits and compatible dimming methods obtained by using the same or similar structures, devices, processes or methods as the above-mentioned embodiments of the present invention are within the scope of protection of the present invention.

Claims

1. A compatible thyristor dimming circuit, characterized by: The compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and is compatible with full voltage operation. The dimming circuit includes an input end, a peak voltage sampling circuit, a mains input detection circuit, a linear compensation circuit, a power supply circuit and an output circuit. The input end is connected to the peak voltage sampling circuit, one end of the peak voltage sampling circuit is connected to the mains input detection circuit, the other end of the peak voltage sampling circuit is connected to one end of the linear compensation circuit, the other end of the mains input detection circuit is connected to the other end of the linear compensation circuit, and the ... the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input, performs peak voltage sampling processing and linear compensation, and the compatibility thyristor dimming circuit automatically judges the mains input The silicon dimming circuit is provided with a control chip U4, which is electrically connected to the peak voltage sampling circuit, the mains input detection circuit, the linear compensation circuit, the power supply circuit and the output circuit. The control chip U4 is used to perform a control function. The power supply circuit is provided with a first node, a connection terminal VCC and a connection terminal VCC2. The first node is connected to the other end of the mains input detection circuit. The output circuit is connected to the linear compensation circuit. The control chip is provided with a pin terminal VDD, a pin terminal DIM, a pin terminal GND, a pin terminal FB, a pin terminal CS and a pin terminal GATE; The peak voltage sampling circuit includes a resistor RR1, a rectifier bridge BD1, a film capacitor CB1, a film capacitor CB2, a diode D1, an electrolytic capacitor EC1 and a first ground terminal. The rectifier bridge is provided with a pin terminal 1, a pin terminal 2, a pin terminal 3 and a pin terminal 4. The input terminal includes a live wire connection terminal L and a neutral wire connection terminal N. The live wire connection terminal L is connected to the pin terminal 1, the neutral wire connection terminal N is connected to the pin 3, the pin 2 is connected to one end of the resistor RR1, the other end of the resistor RR1 is connected to one end of the film capacitor CB1, the pin 4 is connected to the other end of the film capacitor CB1, and the pin 2 is connected to the resistor RR1. A second node and a third node are provided between the pin four and the thin-film capacitor CB1, a fourth node and a fifth node are provided between the pin four and the thin-film capacitor CB1, one end of the thin-film capacitor CB2 is connected to the second node, and the other end of the thin-film capacitor CB2 is connected to the fourth node, a sixth node is provided between the resistor RR1 and the thin-film capacitor CB1, one end of the diode D1 is connected to the sixth node, and the other end of the diode D1 is connected to the mains input detection circuit, a seventh node is provided between the diode D1 and the mains input detection circuit, the seventh node is connected to one end of the electrolytic capacitor EC1, and the other end of the electrolytic capacitor EC1 is connected to the first ground end.

2. The compatible thyristor dimming circuit according to claim 1, characterized in that: The control chip U4 includes a pin DIM, a pin VDD, a pin GATE, a pin CS, a pin FB and a pin GND. The mains input detection circuit includes a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C2, a capacitor C3, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a three-terminal regulator U3, a follower comparator U2, a resistor R12, a resistor R14 and a MOS tube Q1. One end of the resistor R7 is connected in series with the seventh node, the other end of the resistor R7 is connected in series with one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected in series with the thin film capacitor CB1. An eighth node is provided between the resistor R8 and the resistor R10, and the follower comparator U2 includes a positive pin, a negative pin, a pin two, a pin four, and a pin six. The positive pin is connected to the eighth node, and a connection point B is provided between the positive pin and the eighth node, and the connection point B is connected to the pin four. The pin six is ​​connected to the connection terminal one VCC. A ninth node is provided between the positive pin and the eighth node, and the ninth node is connected to the pin four. One end of the capacitor C3 is connected in series with the resistor R10, and the other end of the capacitor C3 is connected to the connection terminal one VCC. The other end of the capacitor C3 is also connected in series with one end of the resistor R11, and the other end of the resistor R11 is connected to the follower comparator U2. The negative pin of the comparator U2 is connected, and a tenth node and an eleventh node are provided between the resistor R11 and the negative pin. The three-terminal regulator U3 includes a first pin end, a second pin end and a third pin end. The tenth node is connected in series with the second pin end, the first pin end is connected in series with one end of the capacitor C3, the third pin end is connected to the eleventh node, the negative pin is connected in series with the first pin end, and a twelfth node is provided between the negative pin and the first pin end. The twelfth node is connected to one end of the resistor R14, the other end of the resistor R14 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the pin four, and the resistor R14 is connected to the resistor R12. A thirteenth node is provided between the two terminals. The MOS transistor Q1 includes a gate, a source, and a drain. The thirteenth node is connected to the gate. The twelfth node of the source is connected in series. The drain is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the pin end DIM. A fourteenth node, a fifteenth node, and a connection point C are provided between the resistor R9 and the pin end DIM. The fifteenth node is connected to one end of the capacitor C2. The other end of the capacitor C2 is connected to the source. A seventeenth node is provided between the source and the capacitor C2. The seventeenth node is provided with a second ground terminal. The connection point C is connected to one end of the resistor R13. The other end of the resistor R13 is connected in series with the seventeenth node.

3. The compatible thyristor dimming circuit according to claim 2, characterized in that: The linear compensation circuit includes a resistor R1, a resistor R4, a resistor R5, a capacitor C1, a follower comparator U1, a voltage regulator diode ZD1 and a resistor R6. One end of the resistor R1 is connected in series with one end of the resistor RR1, the other end of the resistor R1 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to a third ground terminal, an eighteenth node is provided between the resistor R5 and the third ground terminal, a nineteenth node is provided between the resistor R4 and the resistor R5, and the follower comparator U1 includes a positive pin 1, a negative pin 1, a first pin 2, The first pin four and the first pin six, the positive pin one is connected to the nineteenth node, a connection point A is provided between the positive pin one and the nineteenth node, the connection point A is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the eighteenth node, the first pin two is connected to a third ground terminal, the first pin six is ​​connected to the connection terminal two VCC2, the first pin four is connected in series with the negative pin one, the first pin four is connected to one end of the Zener diode ZD1, the positive end of the Zener diode ZD1 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the fourteenth node.

4. The compatible thyristor dimming circuit according to claim 3, characterized in that: The capacitive thyristor dimming circuit is also provided with a first voltage divider circuit and a second voltage divider circuit, the first voltage divider circuit includes a resistor R2 and a resistor R3, the second voltage divider circuit includes a resistor R15 and a resistor R16, one end of the resistor R2 is connected in series with one end of the resistor R1, the other end of the resistor R2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the connection point C, one end of the resistor R15 is connected in series with one end of the resistor R2, the other end of the resistor R15 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the pin end VDD.

5. The compatible thyristor dimming circuit according to claim 4, characterized in that: The output circuit includes a MOS transistor Q2, a transformer T, a diode D2, an electrolytic capacitor EC1, an output terminal Vout+, and an output terminal Vout-. The transformer T includes a transformer terminal T1A and a transformer terminal T1C. The MOS transistor Q2 includes a second gate, a second source, and a second drain. One end of the transformer terminal T1A is connected to one end of the resistor R15, the other end of the transformer terminal T1A is connected to the second drain, the second gate is connected to the pin terminal GATE, the second source is connected to the pin terminal CS, and a twenty-first node is provided between the second source and the pin terminal CS. One end of the transformer terminal T1C is connected to one end of the diode D2, the other end of the diode D2 is connected to the output terminal Vout+, the other end of the transformer terminal T1C is connected to the output terminal Vout-, one end of the electrolytic capacitor EC1 is connected between the diode D2 and the output terminal Vout+, and the other end of the electrolytic capacitor EC1 is connected between the other end of the transformer terminal T1C and the output terminal Vout-.

6. The compatible thyristor dimming circuit according to claim 5, characterized in that: The 21st node is provided with a resistor RS1, the 21st node is connected in series with one end of the resistor RS1, the other end of the resistor RS1 is connected to the first node, the first node is connected to the other end of the resistor R13, a 22nd node is provided between the first node and the resistor R13, and the 22nd node is connected to the pin end GND.

7. The compatible thyristor dimming circuit according to claim 6, characterized in that: The power supply circuit includes an electrolytic capacitor EC3, a diode D3, a diode D4, a voltage-stabilizing diode ZD2, a transistor Q3, a resistor R17, an electrolytic capacitor EC4 and a magnetic core inductor T1B, one end of the magnetic core inductor T1B is connected to one end of the diode D4, the other end of the magnetic core inductor T1B is connected to the first node, the transistor Q3 is an NPN transistor, the other end of the diode D4 is connected to the C pole of the transistor Q3, the E pole of the transistor Q3 is connected to one end of the diode D3, the other end of the diode D3 is connected to one end of the electrolytic capacitor EC3, the other end of the electrolytic capacitor EC3 is connected to the first node, the B pole of the transistor Q3 is connected to one end of the voltage-stabilizing diode ZD2, the other end of the voltage-stabilizing diode ZD2 is connected to the E pole of the transistor Q3. The other end of C3 is connected, a twenty-third node is provided between the transistor Q3 and the Zener diode ZD2, a twenty-fourth node and a twenty-fifth node are provided between the transistor Q3 and the diode D4, one end of the resistor R17 is connected to the twenty-third node, the other end of the resistor R17 is connected to the twenty-fourth node, a twenty-fifth node is provided between the magnetic core inductor T1B and the first node, one end of the electrolytic capacitor EC4 is connected to the twenty-fourth node, the other end of the electrolytic capacitor EC4 is connected to the twenty-fifth node, a twenty-sixth node is provided between the E pole of the transistor Q3 and the diode D3, the twenty-sixth node is connected to the second connection terminal VCC2, a twenty-seventh node is provided between the diode D3 and the electrolytic capacitor EC3, and the first connection terminal VCC is connected to the twenty-seventh node.

8. A compatible dimming method for implementing the compatible thyristor dimming circuit according to any one of claims 2 to 7, characterized in that: It includes the following steps: (1) Electrical connection: The input terminal is connected to the mains electricity, and the power supply circuit provides power to the circuit and control chip U4 in the compatible thyristor dimming circuit after voltage transformation; (2) Peak voltage sampling: After the mains is connected, the rectifier bridge of the peak voltage sampling circuit is used to rectify the rectified output voltage and pulse DC voltage. The pulse DC voltage is input to the linear compensation circuit for processing. The rectified output voltage is processed by the resistor RR1. The resistor RR1 attenuates the peak noise interference of the rectified output voltage to reduce the impact of the interference. The rectified output voltage after attenuation is used to charge and discharge the film capacitor CB1 to obtain a pulse voltage, which is then rectified by the diode D1 and output to the electrolytic capacitor EC1 for filtering to obtain a peak DC voltage. (3) Mains input detection: The DC voltage obtained by the peak voltage sampling action is processed by the mains input detection circuit, and the DC voltage is divided by resistors R7, R8 and R10. The divided voltage is input to the positive pin of the follower comparator U2 through the connection point B. The three-terminal voltage regulator U3 is connected to the negative pin of the follower comparator U2 to generate a voltage of a reference voltage source after power is turned on. The divided voltage obtained by the positive pin of the follower comparator U2 is compared with the reference voltage of the reference voltage source obtained by the negative pin. If the input voltage is 120V, the divided voltage at the connection point B is lower than the reference voltage of the negative pin, the follower comparator U2 outputs a low level, the MOS tube Q2 of the output circuit is cut off and does not conduct, and the dimming control detection signal can only be divided by the resistors R2, R3 and R13 of the first voltage divider circuit to obtain a secondary divided voltage. The secondary divided voltage is input to the pin DIM of the control chip U4 through the connection point C for dimming processing; If the input voltage is 230V, the divided voltage at the connection point B is higher than the reference voltage of the negative pin, the follower comparator U2 outputs a high level, the MOS tube Q2 of the output circuit is saturated and turned on, and the resistors R9 and R13 are connected in parallel. The dimming control detection signal is obtained by dividing the resistors R2, R3, R13, and R9 of the first voltage divider circuit to obtain a secondary divided voltage at the connection point C, which is then input to the pin DIM of the control chip U4. The obtained voltage can almost maintain the corresponding potential of the control voltage when the input is 120V; (4) Linear compensation processing: The pulsed DC voltage passes through the voltage divider circuit composed of resistors R1, R4 and R5 to obtain the divided voltage of the connection point A, which is input to the positive pin 1 of the follower comparator U1. The output end follows the divided voltage of the positive pin 1 to output. When the input voltage is in the 120V voltage range, the divided voltage of the connection point A obtained by voltage division will be lower than the minimum working voltage of the Zener diode ZD1, which is equivalent to the Zener diode ZD1 being cut off. Therefore, the linear compensation circuit does not compensate for the dimming detection voltage of the pin DIM; when the input working voltage is in the 230V high voltage range, the divided voltage of the connection point A obtained by voltage division will be higher than the minimum working voltage of the Zener diode ZD1. Therefore, the linear compensation circuit compensates for the dimming detection voltage of the pin DIM accordingly. (5) Output drive: The voltage after the linear compensation circuit is supplemented and processed passes through the output circuit. After the output circuit is processed by transformer T, the voltage is driven by the output terminal Vout+ and the output terminal Vout- to drive the dimming action.

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