A multi-mode based SIMD application efficient execution method and system

Abstract

The present invention proposes a multi-mode SIMD application efficient execution method and system, comprising: a SIMD component architecture that can flexibly control SIMD components to operate at different granularities, enabling SIMD components to maintain efficient utilization in different applications, as well as in scenarios where the same application is used at different scales. A corresponding method for searching for the optimal application granularity and generating a mapping solution for the application at the corresponding granularity is also provided, thereby fully utilizing the capabilities of the multi-mode SIMD components. This multi-mode SIMD component can be applied to a variety of chip types.

Description

Technical Field

[0001] The present invention relates to the technical field of computer architecture, and in particular to a multi-mode based SIMD application efficient execution method and system. Background Art

[0002] SIMD (Single Instruction Multiple Data) is a common technology in computer architecture. By adding execution units, a single instruction can process multiple data simultaneously, greatly increasing parallel capabilities. The increase in computing units increases the chip's peak computing performance exponentially. In high-throughput application scenarios, especially when many data need to perform the same operation - such as multimedia data processing, this performance gain can be fully exploited, resulting in performance several times that of traditional computers.

[0003] SIMD technology has been widely used in both computer chips and some embedded systems. For example, the SEE instruction commonly used in CPUs is a 128-bit SIMD instruction. In recent years, the AVX-512 instruction has expanded the SIMD width to 512 bits. Increasing SIMD widths mean increasing power consumption. Furthermore, the optimal SIMD width varies for each specific application and method. Wider SIMD widths increase the potential for significant waste.

[0004] There are two common approaches to this problem. One is to pad the data with zeros. This approach is simple to implement, but wastes component computing resources. The more zeros padded, the greater the waste. The other approach uses gating technology to disable inactive SIMD branches, thereby reducing power consumption. This approach solves the power consumption problem, but also comes at the expense of performance. Summary of the Invention

[0005] The purpose of the present invention is to solve the low efficiency problem caused by the existing solution when the task intensity is less than the working intensity of the SIMD components. A dynamically reconfigurable SIMD architecture and a method for finding the optimal SIMD granularity and a dynamic kernel mapping method are proposed.

[0006] In view of the shortcomings of the existing technology, the present invention proposes a multi-mode based SIMD application efficient execution method, which includes:

[0007] Step 1: According to the SIMD architecture characteristics of the computing platform, all SIMD working granularities of the computing platform are obtained, and the working granularity with the largest granularity is selected as the current working granularity;

[0008] Step 2: According to the parameter configuration of the application to be executed, the maximum parallel granularity of the application is obtained as the remaining parallel granularity;

[0009] Step 3: Determine whether the remaining parallel granularity is greater than or equal to the current working granularity or the result of subtracting the remaining parallel granularity from the current working granularity is less than a preset value. If so, add the current working granularity as an execution plan to the set, subtract the current working granularity from the remaining parallel granularity, update and replace the remaining parallel granularity, and execute step 4. Otherwise, select a SIMD working granularity lower than the current working granularity, update and replace the current working granularity, and execute step 3 again.

[0010] Step 4: Determine whether the remaining parallelism is greater than 0. If so, execute step 3 again; otherwise, execute step 5.

[0011] Step 5: Remove the execution plan with the largest work granularity from the set and use it as the current execution plan; determine the number of programs to run in parallel based on the allocation granularity of the execution plan and the number of nodes in the data flow graph of the application to be executed; traverse all mappable logical PEs of the computing platform for each node in the data flow graph and select the mappable logical PE with the shortest distance to its upstream and downstream node PEs as the mapping plan for the logical PE array;

[0012] Step 6: Determine whether there are any execution plans in the set. If so, execute step 5 again until all execution plans have mapping plans. Each PE in the computing platform generates multiple logical PEs according to the mapping plan configuration, and executes the application to be executed with the computing array composed of the logical PEs to obtain the execution result.

[0013] The multi-mode based SIMD application efficient execution method, wherein step 5 includes: dividing the number of SIMD components of the PE by the allocation granularity of the execution scheme to obtain the number of logical PEs that can be configured for each PE, multiplying the number of logical PEs that can be configured by the total number of PEs of the computing platform to obtain the total number of logical PEs of the computing platform, and dividing the total number of logical PEs by the number of nodes in the data flow graph of the application to be executed to obtain the number of kernels running in parallel.

[0014] The multi-mode based SIMD application efficient execution method, wherein the computing platform is a coarse-grained reconfigurable array (CGRA) platform; the application to be executed is a highly parallel image processing, neural network or matrix operation application.

[0015] The multi-mode based SIMD application efficient execution method, wherein step 2 includes searching for the maximum SIMD granularity configuration of the application to be executed as the maximum parallel granularity by a greedy method during compilation according to the parameter configuration of the application to be executed;

[0016] Step 5 includes generating a data flow graph of the application to be executed by compiling the application to be executed by a compiler.

[0017] The present invention also proposes a multi-mode based SIMD application efficient execution system, which includes:

[0018] Module 1: According to the SIMD architecture characteristics of the computing platform, obtain all SIMD working granularities of the computing platform, and select the working granularity with the largest granularity as the current working granularity;

[0019] Module 2: According to the parameter configuration of the application to be executed, the maximum parallel granularity of the application is obtained as the remaining parallel granularity;

[0020] Module 3: Determine whether the remaining parallel granularity is greater than or equal to the current working granularity or the result of subtracting the remaining parallel granularity from the current working granularity is less than a preset value. If so, add the current working granularity as an execution plan to the set, subtract the current working granularity from the remaining parallel granularity, update and replace the remaining parallel granularity, and call module 4. Otherwise, select a SIMD working granularity lower than the current working granularity, update and replace the current working granularity, and call module 3 again.

[0021] Module 4, determines whether the remaining parallelism is greater than 0, if so, calls module 3 again, otherwise calls module 5;

[0022] Module 5: Remove the execution plan with the largest work granularity from the set and use it as the current execution plan; determine the number of programs to run in parallel based on the allocation granularity of the execution plan and the number of nodes in the data flow graph of the application to be executed; traverse all mappable logical PEs of the computing platform for each node in the data flow graph and select the mappable logical PE with the shortest distance to its upstream and downstream node PEs as the mapping plan for the logical PE array;

[0023] Module 6 determines whether there are any execution plans in the set. If so, module 5 is called again until all execution plans have mapping plans. Each PE in the computing platform generates multiple logical PEs according to the mapping plan configuration. The computing array composed of the logical PEs executes the application to be executed to obtain the execution result.

[0024] The multi-mode based SIMD application efficient execution system, wherein the module 5 includes: the number of SIMD components of the PE is divided by the allocation granularity of the execution scheme to obtain the number of logical PEs that can be configured for each PE, the number of logical PEs that can be configured is multiplied by the total number of PEs of the computing platform to obtain the total number of logical PEs of the computing platform, and the total number of logical PEs is divided by the number of nodes in the data flow graph of the application to be executed to obtain the number of kernels running in parallel.

[0025] The multi-mode based SIMD application efficient execution system, wherein the computing platform is a coarse-grained reconfigurable array (CGRA) platform; the application to be executed is a highly parallel image processing, neural network or matrix operation application.

[0026] The multi-mode based SIMD application efficient execution system, wherein the module 2 includes searching for the maximum SIMD granularity configuration of the application to be executed as the maximum parallel granularity by a greedy method during compilation according to the parameter configuration of the application to be executed;

[0027] The module 5 includes generating a data flow graph of the application to be executed by compiling the application to be executed by a compiler.

[0028] The present invention also proposes a storage medium for storing a program for executing any one of the multi-mode based SIMD application efficient execution methods.

[0029] The present invention also proposes a client for use in any of the multi-mode based SIMD application efficient execution systems.

[0030] From the above scheme, it can be seen that the advantages of the present invention are:

[0031] Compared to existing technologies, the present invention can effectively utilize idle components when the optimal SIMD granularity of the application is smaller than the granularity of the physical SIMD components, thereby improving the chip's parallel capability, peak performance, and energy efficiency. The greater the difference between the SIMD granularity of the application and the granularity of the physical SIMD components, the more significant the improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the architecture of reconfigurable SIMD;

[0033] Figure 2 This is a schematic diagram of the SIMD16 architecture;

[0034] Figure 3 Flowchart of the method for selecting the optimal SIMD granularity;

[0035] Figure 4 It is a flowchart of the dynamic kernel mapping method;

[0036] Figure 5 A schematic diagram of the FSC working status when running a SIMD4 application. DETAILED DESCRIPTION

[0037] Previous solutions to this problem have not considered how to fully utilize these idle SIMD branches when the task granularity is smaller than the SIMD branch width. To accommodate flexible task granularity while fully utilizing the performance of SIMD components in these scenarios, the present invention proposes a SIMD dynamic reconfiguration architecture that can be applied to any chip architecture using SIMD technology.

[0038] In the embodiment of the present invention, the CGRA (Coarse-Grained Reconfigurable Array) platform is taken as an example to implement this reconfigurable SIMD architecture. CGRA is generally composed of on-chip network connection, PE (Processing Element) array, Host, cache, etc. CGRA has better programmability than FPGA (Field Programmable Gate Array), better power consumption performance and more general parallel capabilities than GPU. The architecture proposed in the present invention can make full use of these originally non-working SIMD branches to expand parallelism, fully tap the hardware performance, and improve the energy efficiency ratio. In addition, in order for the entire new architecture to be able to run, the invention also proposes a set of methods for selecting the best SIMD granularity that are compatible with this hardware architecture and a set of dynamic kernel mapping methods.

[0039] The present invention includes the following key technical points:

[0040] Key Point 1: Optimal SIMD Granularity Selection Method; Technical Effect: Application work granularity can be decomposed during the compilation phase into a combination of work granularities that are most suitable for the reconfigurable SIMD architecture proposed in this invention. Applications running at the work granularity generated using this method can fully leverage the reconfigurable SIMD architecture's support for different SIMD granularities, improving SIMD component utilization.

[0041] Key Point 2: Dynamic Kernel Mapping Method; Technical Effect: Based on the granularity combination output by the "Optimal SIMD Granularity Selection Method," this method automatically calculates the corresponding logical PE array size and number, thereby determining the number of kernels to execute at a time and the instruction mapping for each kernel. This method fully utilizes the characteristics of the logical PE array in the reconfigurable SIMD architecture by introducing more kernels, thereby improving SIMD component utilization.

[0042] Key Point 3: Reconfigurable SIMD Architecture. Technical Effect: This allows SIMD components to operate at different granularities and can be virtualized into multiple SIMD logic components, significantly increasing SIMD component utilization in small-granularity scenarios. This SIMD architecture can be applied to SIMD components in any architecture, making it widely applicable.

[0043] In order to make the above features and effects of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

[0044] The present invention mainly includes three parts:

[0045] 1. Application-optimal SIMD granularity search method: Based on the application parameters, a greedy search is performed during compilation to find the maximum SIMD granularity configuration suitable for the application. This configuration is then used to generate the PE mapping configuration in the PE dynamic mapping method; applications can be highly parallel image processing, neural networks, or matrix operations.

[0046] 2. Dynamic PE mapping method: Calculates the PE mapping method by inputting the configuration information generated by the SIMD granularity selection method and the application's data flow graph;

[0047] 3. Dynamically Reconfigurable SIMD Hardware Architecture: The dynamic SIMD architecture exemplified in this invention is primarily implemented on the CGRA, but its application is not limited to the CGRA. The CGRA primarily consists of the PE array, host, buffer, and on-chip interconnect network. The PE in this invention consists of the BPU and FSC. The BPU is the basic arithmetic unit, while the FSC is the control unit organized in a hierarchical tree. Through the FSC's control of the BPU, a single PE can be transformed into multiple logical PEs.

[0048] The present invention only takes the CGRA architecture as an example platform and provides a schematic diagram of a dynamically reconfigurable SIMD architecture, such as Figure 1 As shown in the figure, it shows the organization of each SIMD branch component in a physical PE component. It includes a certain number of BPUs (Basic Process Units) and FSCs (Flex-SIMD controllers). Each BPU is a branch of SIMD and has a computing component. FSCs are organized in a tree-like form. Figure 1 In the example, each parent node of the FSC tree has two child nodes. In practice, the number of child nodes can vary as needed, but the following example assumes that each FSC controls two child nodes. All BPUs are on the leaf nodes of the FSC and are controlled by the FSC.

[0049] The structure of the FSC tree is determined by the width of the SIMD component and how many child nodes a FSC node can control. For example, the number of branches of the SIMD component is 2 n When the architecture of the present invention is used, it means that the BPU is 2 n At this time, just let the depth of the FSC tree be n, which is enough to control 2 n Another method is to increase the width of the FSC number so that each FSC can control 2 k nodes, then the FSC number only needs to reach a depth of n / k to control 2 n BPUs. Figure 2 This is an example diagram of the FSC tree structure when the SIMD width is 16 and each parent node of the FSC has two child nodes.

[0050] By controlling the BPU in this tree-like hierarchical form, it is possible to determine which BPUs perform the same operation and which BPUs perform different operations. The upper FSC receives the control information (generated by the first two methods of the present invention) and then distributes the information to the FSCs of its child nodes. When the number of SIMD branches is 2 n If you want to control the SIMD components to SIMD2 k When running in this mode, we can find that the number of BPUs managed by the FSC at the (n-k+1) layer is exactly 2. k Therefore, the FSC at this layer will control its child FSCs so that all the BPUs it manages will perform the same operation. This group of BPUs that perform the same operation is equivalent to a logically independent SIMD component. The FSCs at the (n-k+1) layer will be assigned different tasks, which is equivalent to a SIMD2 n Components are virtualized into multiple SIMD2 k More specifically, the number of SIMD branches is 16, and the state of running in SIMD4 mode is as follows Figure 5 As shown: The black FSC components in the figure represent their parallel operation, and the tasks distributed by the upper-level FSC will be distributed to the child nodes controlled by it as is.

[0051] It can be found that in the above example, there are 2 layers (n-k+1) n-k FSCs that perform different operations, the entire PE is equivalent to having 2 n-k个 Logical SIMD2 k components, can also be regarded as a physical PE with 2 n-k logical PEs, each of which has a SIMD2 k The entire logical PEArray also has a logical PE number that is twice the number of physical PEs. n-k times, which is equivalent to running SIMD2 kWhen performing tasks with the same granularity, its peak performance can reach 2 times that of the original architecture. n-k times.

[0052] The specific workflow of the present invention is as follows:

[0053] For a certain application, first, according to its parameters, an optimal SIMD granularity selection method is used to determine the SIMD granularity configuration of the application during compilation.

[0054] This method requires providing a list of SIMD modes that the current chip can support. The method first calculates the maximum number of parallelism of this application through the application parameters during the compilation phase. Then try to decompose this maximum number of parallelism in the SIMD mode support list in order from large granularity to small granularity. Specifically, first try to continuously allocate the number of parallelism of the application to the maximum granularity in the supported mode. If the current or remaining number of parallelism is already smaller than the working mode granularity of this round, then try to use a smaller working mode granularity to decompose the remaining number of parallelism of the application in the next round. By repeating the above process, you can get a decomposition of the number of parallelism of the application under the existing working mode granularity support list. The decomposed configuration is a combination of various SIMD working granularities, which can be sufficiently close to this number of parallelism when the sum of the granularities is greater than the number of parallelism required by the application. The following is combined with its steps Figure 3 The workflow of the method is described:

[0055] Step S101: First, based on the specific reconfigurable SIMD architecture features, list all supported SIMD work granularities and arrange them from largest to smallest. Select the first mode (i.e., the one with the largest granularity) as the test mode.

[0056] Step S102: Calculate the maximum parallel granularity of the application based on the application parameter configuration. In subsequent steps, it will be continuously allocated to different working modes until all parallel granularities are allocated;

[0057] In step S103, the selected working granularity is compared with the current remaining parallelism. If the remaining parallelism is greater than or equal to the currently selected working granularity, or if the working granularity is greater than the remaining parallelism but the two are very close, then in step S106, the working granularity is added to the configuration and the remaining parallelism is subtracted from the granularity of the currently selected working mode.

[0058] If the above conditions are not met, that is, in step S105, the next smaller working granularity should be selected and the process should be repeated from step S103;

[0059] Step S107, determine the remaining parallelism: if there is still parallelism remaining, jump back to step S103, otherwise end the program.

[0060] Next, based on the SIMD granularity configuration generated in the previous step and the data flow graph of the application, the dynamic Kernel (a program running on CGRA) mapping method is used to generate the mapping configuration of the Kernel's data flow graph to the PE. This method first calculates the scale of the logical PE array based on the configuration information obtained by the previous method. Then calculate how many Kernels can be mapped at one time under this scale. The last step is to complete the mapping from the Kernel's data flow graph to the logical PE. In this method, the corresponding PE is assigned to the nodes in the data flow graph based on the principle of minimum distance. The specific implementation steps are as follows: Figure 4 As shown:

[0061] Step S201: Select the next conf in the SIMD granularity configuration set conf generated in the previous method. In subsequent steps, the corresponding Kernel mapping configuration information will be generated for this configuration.

[0062] In step S202, based on the conf selected in S201 and the number of nodes in the kernel's data flow graph, determine how many kernels should be run in parallel to fully utilize the scale of the logical PE array. For example, when conf is SIMD4, the PE array has 16 PEs, and the SIMD component of each PE is SIMD16, and the number of nodes in the kernel's data flow graph is 4. At this time, since each PE can be virtualized into 4 logical PEs, the entire PE array has a total of 64 logical PEs, and each kernel only occupies 4 logical PEs. In other words, 64 / 4 = 16 kernels in parallel can fully load the entire logical PE array.

[0063] Step S203 completes the mapping of all kernel dataflow graphs to the logical PE array. This step traverses all mappable logical PEs for each node and selects the available PE with the shortest distance to its upstream and downstream PEs in the dataflow graph as the mapping candidate. Using distance as the selection factor can reduce communication overhead and latency.

[0064] A PE can map to at most one node, and a node can only map to one PE. After a node is mapped to a PE in each round, the PE is no longer available.

[0065] In step S205, it is determined whether there are any remaining confs, and if so, the process jumps to S201 until corresponding mapping information is generated for all confs.

[0066] Finally, the configuration information generated by the dynamic kernel mapping method is passed to the top-level FSC in each PE, and the FSC of each parent node will continuously distribute control information to the FSC of its child node to control whether the FSC of its child node performs the same operation or a different operation. For example, when configured in SIMD4 mode, the working status of the entire FSC tree of the SIMD16 component is as follows: Figure 5 As shown, only the FSCs for L1 through L3 are active because the four BPUs, controlled by different L3-SIMD controllers, are performing different operations. The FSC for L4 is disabled because the four BPUs, managed by different L4-SIMD controllers under the same L3-SIMD controller, are performing the same operation. At this point, the entire PE can emulate four logical PEs, effectively quadrupling the number of active PEs in the entire PE array. This significantly enhances the hardware's parallel capabilities.

[0067] Multiple configurations are executed sequentially, not in parallel. Only one configuration is executed at a time. That is, after the mapping method and number of loops corresponding to the first conf are completed, the mapping method and number of loops corresponding to the second conf are executed.

[0068] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0069] The present invention also proposes a multi-mode based SIMD application efficient execution system, which includes:

[0070] Module 1: According to the SIMD architecture characteristics of the computing platform, obtain all SIMD working granularities of the computing platform, and select the working granularity with the largest granularity as the current working granularity;

[0071] Module 2: According to the parameter configuration of the application to be executed, the maximum parallel granularity of the application is obtained as the remaining parallel granularity;

[0072] Module 3: Determine whether the remaining parallel granularity is greater than or equal to the current working granularity or the result of subtracting the remaining parallel granularity from the current working granularity is less than a preset value. If so, add the current working granularity as an execution plan to the set, subtract the current working granularity from the remaining parallel granularity, update and replace the remaining parallel granularity, and call module 4. Otherwise, select a SIMD working granularity lower than the current working granularity, update and replace the current working granularity, and call module 3 again.

[0073] Module 4, determines whether the remaining parallelism is greater than 0, if so, calls module 3 again, otherwise calls module 5;

[0074] Module 5: Remove the execution plan with the largest work granularity from the set and use it as the current execution plan; determine the number of programs to run in parallel based on the allocation granularity of the execution plan and the number of nodes in the data flow graph of the application to be executed; traverse all mappable logical PEs of the computing platform for each node in the data flow graph and select the mappable logical PE with the shortest distance to its upstream and downstream node PEs as the mapping plan for the logical PE array;

[0075] Module 6 determines whether there are any execution plans in the set. If so, module 5 is called again until all execution plans have mapping plans. Each PE in the computing platform generates multiple logical PEs according to the mapping plan configuration. The computing array composed of the logical PEs executes the application to be executed to obtain the execution result.

[0076] The multi-mode based SIMD application efficient execution system, wherein the module 5 includes: the number of SIMD components of the PE is divided by the allocation granularity of the execution scheme to obtain the number of logical PEs that can be configured for each PE, the number of logical PEs that can be configured is multiplied by the total number of PEs of the computing platform to obtain the total number of logical PEs of the computing platform, and the total number of logical PEs is divided by the number of nodes in the data flow graph of the application to be executed to obtain the number of kernels running in parallel.

[0077] The multi-mode based SIMD application efficient execution system, wherein the computing platform is a coarse-grained reconfigurable array (CGRA) platform; the application to be executed is a highly parallel image processing, neural network or matrix operation application.

[0078] The multi-mode based SIMD application efficient execution system, wherein the module 2 includes searching for the maximum SIMD granularity configuration of the application to be executed as the maximum parallel granularity by a greedy method during compilation according to the parameter configuration of the application to be executed;

[0079] The module 5 includes generating a data flow graph of the application to be executed by compiling the application to be executed by a compiler.

[0080] The present invention also proposes a storage medium for storing a program for executing any one of the multi-mode based SIMD application efficient execution methods.

[0081] The present invention also proposes a client for use in any of the multi-mode based SIMD application efficient execution systems.

Claims

1. A multi-mode based SIMD application efficient execution method, characterized in that: include: Step 1: According to the SIMD architecture characteristics of the computing platform, all SIMD working granularities of the computing platform are obtained, and the working granularity with the largest granularity is selected as the current working granularity; Step 2: According to the parameter configuration of the application to be executed, the maximum parallel granularity of the application is obtained as the remaining parallel granularity; Step 3: Determine whether the remaining parallel granularity is greater than or equal to the current working granularity or the result of subtracting the remaining parallel granularity from the current working granularity is less than a preset value. If so, add the current working granularity as an execution plan to the set, subtract the current working granularity from the remaining parallel granularity, update and replace the remaining parallel granularity, and execute step 4. Otherwise, select a SIMD working granularity lower than the current working granularity, update and replace the current working granularity, and execute step 3 again. Step 4: Determine whether the remaining parallel granularity is greater than 0. If so, execute step 3 again; otherwise, execute step 5. Step 5: Remove the execution plan with the largest work granularity from the set and use it as the current execution plan; determine the number of programs to run in parallel based on the allocation granularity of the execution plan and the number of nodes in the data flow graph of the application to be executed; For each node in the data flow graph, all mappable logical PEs of the computing platform are traversed, and the mappable logical PE with the shortest distance to its upstream and downstream node PEs is selected as the mapping scheme of the logical PE array; Step 6: Determine whether there are any execution plans in the set. If so, execute step 5 again until all execution plans have mapping plans. Each PE in the computing platform generates multiple logical PEs according to the mapping plan configuration, and executes the application to be executed with the computing array composed of the logical PEs to obtain the execution result.

2. The method for efficient execution of SIMD applications based on multiple modes according to claim 1, wherein: This step 5 includes: dividing the number of SIMD components of the PE by the allocation granularity of the execution scheme to obtain the number of logical PEs that can be configured for each PE, multiplying the number of logical PEs that can be configured by the total number of PEs of the computing platform to obtain the total number of logical PEs of the computing platform, and dividing the total number of logical PEs by the number of data flow graph nodes of the application to be executed to obtain the number of kernels running in parallel.

3. The multi-mode based SIMD application efficient execution method according to claim 1, wherein: The computing platform is a coarse-grained reconfigurable array (CGRA) platform; the application to be executed is a highly parallel image processing, neural network or matrix operation application.

4. The method for efficient execution of SIMD applications based on multiple modes according to claim 1, wherein: Step 2 includes searching for a maximum SIMD granularity configuration of the application to be executed as the maximum parallel granularity by a greedy method during compilation according to the parameter configuration of the application to be executed; Step 5 includes generating a data flow graph of the application to be executed by compiling the application to be executed by a compiler.

5. A multi-mode based SIMD application efficient execution system, characterized in that: include: Module 1: According to the SIMD architecture characteristics of the computing platform, obtain all SIMD working granularities of the computing platform, and select the working granularity with the largest granularity as the current working granularity; Module 2: According to the parameter configuration of the application to be executed, the maximum parallel granularity of the application is obtained as the remaining parallel granularity; Module 3: Determine whether the remaining parallel granularity is greater than or equal to the current working granularity or the result of subtracting the remaining parallel granularity from the current working granularity is less than a preset value. If so, add the current working granularity as an execution plan to the set, subtract the current working granularity from the remaining parallel granularity, update and replace the remaining parallel granularity, and call module 4. Otherwise, select a SIMD working granularity lower than the current working granularity, update and replace the current working granularity, and call module 3 again. Module 4: Determine whether the remaining parallel granularity is greater than 0. If so, call module 3 again; otherwise, call module 5. Module 5: Remove the execution plan with the largest work granularity from the set and use it as the current execution plan; determine the number of programs to run in parallel based on the allocation granularity of the execution plan and the number of nodes in the data flow graph of the application to be executed; For each node in the data flow graph, all mappable logical PEs of the computing platform are traversed, and the mappable logical PE with the shortest distance to its upstream and downstream node PEs is selected as the mapping scheme of the logical PE array; Module 6 determines whether there are any execution plans in the set. If so, module 5 is called again until all execution plans have mapping plans. Each PE in the computing platform generates multiple logical PEs according to the mapping plan configuration. The computing array composed of the logical PEs executes the application to be executed to obtain the execution result.

6. The multi-mode based SIMD application efficient execution system according to claim 5, characterized in that: This module 5 includes: dividing the number of SIMD components of the PE by the allocation granularity of the execution scheme to obtain the number of logical PEs that can be configured for each PE, multiplying the number of logical PEs that can be configured by the total number of PEs of the computing platform to obtain the total number of logical PEs of the computing platform, and dividing the total number of logical PEs by the number of nodes in the data flow graph of the application to be executed to obtain the number of kernels running in parallel.

7. The multi-mode based SIMD application efficient execution system according to claim 5, characterized in that: The computing platform is a coarse-grained reconfigurable array (CGRA) platform; the application to be executed is a highly parallel image processing, neural network or matrix operation application.

8. The multi-mode based SIMD application efficient execution system according to claim 5, characterized in that: The module 2 includes searching for the maximum SIMD granularity configuration of the application to be executed as the maximum parallel granularity by a greedy method during compilation according to the parameter configuration of the application to be executed; The module 5 includes generating a data flow graph of the application to be executed by compiling the application to be executed by a compiler.

9. A storage medium for storing a program for executing any one of the multi-mode based SIMD application efficient execution methods according to claims 1 to 4.

10. A client, used in any one of the multi-mode based SIMD application efficient execution systems according to claims 5 to 8.

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