Ion trap chip and quantum computing device having the same

Abstract

The present invention discloses an ion trap chip and a quantum computing device having the same. The ion trap chip includes a support; a chip electrode mounted on the support; and a substrate and a conductive layer disposed on the surface of the substrate. The substrate is a zirconia ceramic. The ion trap chip according to an embodiment of the present invention has advantages such as high structural strength, high resistance to damage, high voltage tolerance, low dielectric loss, low equivalent capacitance, low thermal effect, and high flatness.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to an ion trap chip and a quantum computing device having the ion trap chip. Background Art

[0002] Ion trap quantum computing systems are currently one of the most promising approaches to physically realizing quantum computing. Ion trap chips are the core device for precisely manipulating ions to achieve quantum computing. The chip's materials, structural dimensions, and fabrication process directly impact the system's core performance. For example, the chip's structure and materials have a direct impact on the ions' heating rate. Excessive heating rates prevent ions from maintaining their ground state for extended periods, affecting the fidelity and coherence time of quantum manipulation. For multi-quantum systems, this also affects the degree of quantum entanglement, which is detrimental to the construction of large-scale quantum computers.

[0003] The ion trap chips in related technologies use silicon-based materials, aluminum nitride ceramics, alumina ceramics and other materials as substrates, which have shortcomings such as low mechanical strength, easy brittle cracking during bonding and pressure welding, weak high voltage tolerance, high dielectric loss of the material itself, and large equivalent capacitance. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides an ion trap chip having the advantages of high structural strength, resistance to damage, high voltage tolerance, low dielectric loss, small equivalent capacitance, low thermal effect, and high flatness.

[0005] The present invention also provides a quantum computing device having the ion trap chip.

[0006] To achieve the above-mentioned purpose, an ion trap chip is proposed according to an embodiment of the first aspect of the present invention, wherein the ion trap chip comprises: a bracket; a chip electrode, wherein the chip electrode is mounted on the bracket, and wherein the chip electrode comprises a substrate and a conductive layer, wherein the conductive layer is provided on the surface of the substrate, wherein the substrate is a zirconia ceramic part, and the conductive layer is an electroplated layer.

[0007] The ion trap chip according to the embodiment of the present invention has the advantages of high structural strength, not easy to be damaged, high voltage bearing capacity, low dielectric loss, small equivalent capacitance, low thermal effect, and high flatness.

[0008] In addition, the ion trap chip according to the above embodiment of the present invention may also have the following additional technical features:

[0009] According to an embodiment of the present invention, the conductive layer is a gold-plated layer.

[0010] According to one embodiment of the present invention, a transition layer is provided between the conductive layer and the substrate, and the transition layer is a titanium layer.

[0011] According to one embodiment of the present invention, the chip electrode is sheet-shaped and has opposite front and back surfaces, the conductive layer is located on the front and back surfaces of the chip electrode, the back surface has a bonding area that is bonded to the bracket and a conductive layer area where the conductive layer is provided, and there is an avoidance gap between the bonding area and the conductive layer area.

[0012] According to one embodiment of the present invention, there are multiple chip electrodes including DC electrodes and RF electrodes, the front surface of the DC electrode has a blank area extending along the length direction of the DC electrode, the front surface of the DC electrode is divided into a signal area and a grounding area by the blank area, the signal area and the grounding area are both provided with the conductive layer, the DC electrode has a plurality of insulating separation grooves passing through the DC electrode along the thickness direction, one end of the insulating separation groove is connected to the blank area and the other end extends to the edge of the DC electrode, the conductive layer of the signal area is divided into a plurality of sub-signal conductive layers by the plurality of insulating separation grooves, the conductive layer of the grounding area is grounded, and the sub-signal conductive layer is connected to the conductive layer of the grounding area through an RF grounding wire, and the entire front surface of the RF electrode is provided with the conductive layer.

[0013] According to one embodiment of the present invention, the chip electrode includes a main body and a blade, the main body and the blade are connected and arranged in the width direction of the chip electrode, and the thickness of the blade gradually decreases from close to the main body to away from the main body.

[0014] According to one embodiment of the present invention, the main body includes a straight section and a contraction section, the straight section and the contraction section are connected and arranged in the width direction of the chip electrode, the blade is connected to the contraction section, and the length of the contraction section gradually decreases from close to the straight section to away from the straight section.

[0015] According to one embodiment of the present invention, the thickness of the edge of the blade portion away from the main body portion is 0.03-0.07 mm.

[0016] According to one embodiment of the present invention, the length of the edge of the blade away from the main body is 7-12 mm.

[0017] According to an embodiment of the second aspect of the present invention, a quantum computing device is provided. The quantum computing device includes the ion trap chip according to the embodiment of the first aspect of the present invention.

[0018] The quantum computing device according to the embodiment of the present invention, by utilizing the ion trap chip according to the embodiment of the first aspect of the present invention, has the advantages of high assembly robustness, excellent performance, etc.

[0019] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 3 is a schematic structural diagram of an ion trap chip according to an embodiment of the present invention.

[0022] Figure 2 3 is a schematic structural diagram of an ion trap chip according to an embodiment of the present invention.

[0023] Figure 3 4 is a schematic structural diagram of a DC electrode of an ion trap chip according to an embodiment of the present invention.

[0024] Figure 4 3 is a schematic structural diagram of a radio frequency electrode of an ion trap chip according to an embodiment of the present invention.

[0025] Figure 5 3 is a schematic structural diagram of chip electrodes of an ion trap chip according to an embodiment of the present invention.

[0026] Figure 6 3 is a schematic structural diagram of the front side of the DC electrode of the ion trap chip according to an embodiment of the present invention.

[0027] Figure 7 3 is a schematic structural diagram of the reverse side of the DC electrode of the ion trap chip according to an embodiment of the present invention.

[0028] Figure 8 3 is a schematic structural diagram of the front side of the radio frequency electrode of the ion trap chip according to an embodiment of the present invention.

[0029] Figure 9 3 is a schematic structural diagram of the reverse side of the radio frequency electrode of the ion trap chip according to an embodiment of the present invention.

[0030] Figure numerals: ion trap chip 1, bracket 100, chip electrode 200, main body 201, straight section 2011, contraction section 2012, blade 202, DC electrode 210, insulating separation groove 211, blank area 212, grounding area 213, signal area 214, sub-signal conductive layer 2141, RF electrode 220, bonding area 215, conductive layer area 216, avoidance gap 217, conductive layer 230. DETAILED DESCRIPTION

[0031] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0032] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0033] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0034] The following describes an ion trap chip 1 according to an embodiment of the present invention with reference to the accompanying drawings.

[0035] like Figures 1-9 As shown, the ion trap chip 1 according to an embodiment of the present invention includes a support 100 and a chip electrode 200 .

[0036] The chip electrode 200 is mounted on the bracket 100 . The chip electrode 200 includes a substrate and a conductive layer 230 . The conductive layer 230 is provided on the surface of the substrate. The substrate is a zirconia ceramic component, and the conductive layer 230 is an electroplating layer.

[0037] For ease of understanding, the conductive layer 230 is shown as a shaded portion in the figure.

[0038] Specifically, the bracket 100 can support and position the chip electrode 200, which is convenient for the installation and positioning of the chip electrode 200. The substrate can provide a certain structural strength for the chip electrode 200, which is convenient for the setting of the conductive layer 230. The conductive layer 230 can provide the chip electrode 200 with conductivity, which is used to apply voltage to generate a potential well for trapped ions.

[0039] According to the ion trap chip 1 of the embodiment of the present invention, by using zirconia ceramic material as the substrate, compared with the technical solutions in the related art that use silicon-based materials, aluminum nitride or aluminum oxide as the substrate, since the toughness of zirconia ceramic is 4 times that of alumina ceramic, the density is 2 times that of alumina ceramic, the bending strength of zirconia ceramic is 2 times that of glass, and the fracture toughness is 10 times that of glass, by using zirconia ceramic material as the substrate, the mechanical strength and toughness of the substrate can be effectively improved, so that the chip electrode 200 is not easily damaged by external force, the pressure resistance and drop resistance of the chip electrode 200 are improved, the toughness of the chip electrode 200 is improved, and the yield rate in the bonding and pressure welding process is improved.

[0040] Moreover, by using zirconia ceramic material as the substrate, since the dielectric loss of zirconia ceramic is only 1 / 20 of that of glass, the dielectric loss of the chip electrode 200 can be effectively reduced, the heating effect on the trapped ions can be greatly reduced, the decoherence time of the ions can be increased, and the voltage bearing capacity of the chip electrode 200 can be improved, the equivalent capacitance of the chip electrode 200 can be reduced, and the wear resistance and high temperature resistance of the substrate can be improved, thereby improving the wear resistance and heat resistance of the chip electrode 200.

[0041] In addition, by using zirconia ceramic material as the substrate, since zirconia ceramic has a higher density and better surface finish after fine processing, the flatness after setting the conductive layer 230 is also higher, reducing the impact of the chip electrode 200 surface fragmentation potential on the ion trap ion heating rate.

[0042] Therefore, by using the zirconium oxide ceramic material as the substrate, the robustness of the assembly of the chip electrode 200 and the index performance of the quantum computer can be improved.

[0043] Therefore, the ion trap chip 1 according to the embodiment of the present invention has the advantages of high structural strength, not easy to be damaged, high voltage bearing capacity, low dielectric loss, small equivalent capacitance, low thermal effect, and high flatness.

[0044] The following describes an ion trap chip 1 according to a specific embodiment of the present invention with reference to the accompanying drawings.

[0045] In some specific embodiments of the present invention, Figures 1-9 As shown, the ion trap chip 1 according to an embodiment of the present invention includes a support 100 and a chip electrode 200 .

[0046] Optionally, the conductive layer 230 is a gold-plated layer, which can make the conductive layer 230 have high conductivity, good anti-oxidation and anti-corrosion capabilities, good mechanical strength, and be non-magnetic, suitable for vacuum conditions, high flatness, and neat edges after etching.

[0047] Furthermore, a transition layer is provided between the conductive layer 230 and the substrate, and the transition layer is a titanium layer. This can improve the adhesion of the conductive layer 230 and facilitate the installation of the conductive layer 230. The titanium layer is a transition layer that facilitates the coating process and is non-magnetic, thus avoiding magnetic field interference.

[0048] Figure 6-Figure 9 FIG. 1 shows an ion trap chip 1 according to some examples of the present invention. Figure 6-Figure 9 As shown, the chip electrode 200 is in sheet shape and has opposite front and back surfaces, and the conductive layer 230 is located on the front and back surfaces of the chip electrode 200. Figure 7 and Figure 9 As shown, the reverse side has a bonding region 215 that is bonded to the support 100 and a conductive layer region 216 having a conductive layer 230, with a clearance gap 217 being defined between the bonding region 215 and the conductive layer region 216. Those skilled in the art will appreciate that the width of the clearance gap 217 can be minimized to prevent contact between the support 100 and the conductive layer 230. This prevents contact between the conductive layer 230 and the support 100, thereby avoiding additional dielectric loss and affecting the inductance Q value of the ion trap chip 1.

[0049] Specifically, if Figures 1-9 As shown, the chip electrodes 200 are multiple and include a DC electrode 210 and a RF electrode 220. Figure 6 As shown, the front side of the DC electrode 210 has a blank area 212 extending along the length direction of the DC electrode 210, and the front side of the DC electrode 210 is divided into a signal area 214 and a ground area 213 by the blank area 212. The signal area 214 and the ground area 213 are both provided with a conductive layer 230. The DC electrode 210 has a plurality of insulating separation grooves 211 passing through the DC electrode 210 along the thickness direction, one end of the insulating separation groove 211 is connected to the blank area 212 and the other end extends to the edge of the DC electrode 210, the conductive layer 230 of the signal area 214 is divided into a plurality of sub-signal conductive layers 2141 by the plurality of insulating separation grooves 211, the conductive layer 230 of the ground area 213 is grounded, and the sub-signal conductive layer 2141 is connected to the conductive layer 230 of the ground area 213 through a radio frequency grounding line, as shown. Figure 8 As shown, the entire front surface of the RF electrode 220 is provided with a conductive layer 230. In this way, a plurality of sub-signal conductive layers 2141 can be used to apply a DC signal for trapping ions, and the inductance Q value of the ion trap chip 1 can be increased.

[0050] Specifically, if Figure 1 and Figure 2 As shown, the ion trap chip 1 includes two DC electrodes 210 and two RF electrodes 220 . The two DC electrodes 210 are located on the same plane and the two RF electrodes 220 are located on the same plane, which can facilitate the formation of ion trapping sites.

[0051] Advantageously, as Figure 3-Figure 5 As shown, the chip electrode 200 includes a main portion 201 and a blade portion 202. The main portion 201 and the blade portion 202 are connected and arranged in the width direction of the chip electrode 200. The thickness of the blade portion 202 gradually decreases from the main portion 201 to the direction away from the main portion 201. Specifically, the edge of the blade portion 202 away from the main portion 201 faces the ion trapping site of the ion trap chip 1. This can facilitate reducing the surface area of ​​the chip electrode 200 facing the ion trapping site, reduce the thermal effect of the chip electrode 200, and increase the decoherence time of the ions.

[0052] More advantageously, if Figure 3-Figure 5 As shown, the main body 201 includes a straight section 2011 and a contracted section 2012. The straight section 2011 and the contracted section 2012 are connected and arranged in the width direction of the chip electrode 200. The blade 202 is connected to the contracted section 2012. The length of the contracted section 2012 gradually decreases from the direction close to the straight section 2011 to the direction away from the straight section 2011. This can easily reduce the area of ​​the chip electrode 200 surface facing the ion trapping site, reducing the impact of the thermal effect of the chip electrode 200 on the ions.

[0053] Alternatively, as Figure 5 As shown, the thickness d of the edge of the blade 202 away from the main body 201 is 0.03-0.07 mm. Here, 0.05 mm is preferred. This can facilitate reducing the area of ​​the surface of the chip electrode 200 facing the ion trapping site while maintaining a reasonable processing difficulty.

[0054] Furthermore, if Figure 4 As shown, the length D of the edge of the blade 202 away from the main body 201 is 7-12 mm. Here, 9.45 mm is preferred. This can facilitate reducing the area of ​​the surface of the chip electrode 200 facing the ion trapping site while maintaining a reasonable processing difficulty.

[0055] The following describes a quantum computing device according to an embodiment of the present invention. The quantum computing device according to an embodiment of the present invention includes the ion trap chip 1 according to the above-mentioned embodiment of the present invention.

[0056] The quantum computing device according to the embodiment of the present invention has the advantages of high assembly robustness, excellent performance, etc. by utilizing the ion trap chip 1 according to the above embodiment of the present invention.

[0057] Other structures and operations of the quantum computing device according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0058] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0059] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. An ion trap chip, characterized in that: The ion trap chip is an ion trap quantum computing chip, comprising: Bracket; A chip electrode is mounted on the bracket. The chip electrode comprises a substrate and a conductive layer. The conductive layer is arranged on the surface of the substrate. The substrate is a zirconia ceramic piece. The conductive layer is an electroplating layer.

2. The ion trap chip according to claim 1, characterized in that A transition layer is provided between the conductive layer and the substrate, the transition layer is a titanium layer, and the conductive layer is a gold-plated layer.

3. The ion trap chip according to claim 1, characterized in that The chip electrode is sheet-shaped and has opposite front and back surfaces. The conductive layer is located on the front and back surfaces of the chip electrode. The back surface has a bonding area that is bonded to the bracket and a conductive layer area where the conductive layer is provided. There is an avoidance gap between the bonding area and the conductive layer area.

4. The ion trap chip according to claim 3, characterized in that There are multiple chip electrodes and include DC electrodes and RF electrodes. The front side of the DC electrode has a blank area extending along the length direction of the DC electrode. The front side of the DC electrode is divided into a signal area and a grounding area by the blank area. Both the signal area and the grounding area are provided with the conductive layer. The DC electrode has a plurality of insulating separation grooves passing through the DC electrode along the thickness direction. One end of the insulating separation groove is connected to the blank area and the other end extends to the edge of the DC electrode. The conductive layer in the signal area is divided into a plurality of sub-signal conductive layers by the plurality of insulating separation grooves. The conductive layer in the grounding area is grounded, and the sub-signal conductive layer is connected to the conductive layer in the grounding area through an RF grounding wire. The entire front side of the RF electrode is provided with the conductive layer.

5. The ion trap chip according to claim 1, characterized in that The chip electrode includes a main body and a blade. The main body and the blade are connected and arranged in the width direction of the chip electrode. The thickness of the blade gradually decreases from close to the main body to away from the main body.

6. The ion trap chip according to claim 5, characterized in that The main body includes a straight section and a contraction section, the straight section and the contraction section are connected and arranged in the width direction of the chip electrode, the blade is connected to the contraction section, and the length of the contraction section gradually decreases from close to the straight section to away from the straight section.

7. The ion trap chip according to claim 5, characterized in that The thickness of the edge of the blade away from the main body is 0.03-0.07 mm.

8. The ion trap chip according to claim 6, characterized in that The length of the edge of the blade away from the main body is 7-12 mm.

9. A quantum computing device, characterized in that The invention comprises the ion trap chip according to any one of claims 1 to 8.

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