Single-coil multi-core inductor-capacitor oscillator

Abstract

This invention provides a single-coil multi-core inductive-capacitive (LC) oscillator. The single-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer conductor and a center conductor, wherein the outer conductor is coupled to a first core circuit and a second core circuit, and the center conductor is coupled between a first node and a second node of the outer conductor. More specifically, an outer loop formed by the outer conductor corresponds to a first mode of the single-coil multi-core LC oscillator, and an inner loop formed by the outer conductor and the center conductor corresponds to a second mode of the single-coil multi-core LC oscillator. The at least one mode suppression device is configured to suppress one of the first mode and the second mode. This invention can reduce the phase noise of the LC oscillator.

Description

Technical Field

[0001] This invention generally relates to inductor-capacitor (LC) oscillators, and more specifically, to a one-coil multi-core LC oscillator. Background Technology

[0002] For LC oscillators, it is necessary to reduce the equivalent inductance of the internal inductor to reduce the phase noise. Typically, directly reducing the inductor's inductance by shrinking its size leads to a degradation / decrease in the inductor's quality factor. Therefore, it is difficult to reduce phase noise simply by reducing the inductor's size. Related techniques have provided some methods to reduce the equivalent inductance without shrinking the inductor's size. However, these also have drawbacks. For example, if a 3 dB reduction in phase noise is required, the overall circuit area of ​​the proposed architecture needs to be doubled.

[0003] Therefore, there is a need for a novel architecture and related mode control method for LC oscillators to improve phase noise reduction in a way that does not introduce any side effects or is unlikely to introduce side effects. Summary of the Invention

[0004] In view of this, one of the objectives of the present invention is to provide a single-coil multi-core inductor-capacitor (LC) oscillator that can improve / enhance phase noise reduction (i.e., reduce the phase noise of the LC oscillator) without significantly increasing additional costs (e.g., circuit area).

[0005] In a first aspect, the present invention provides a single-coil multi-core inductive-capacitive LC oscillator, wherein the single-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer conductor and a center conductor. The outer conductor is coupled to a first core circuit and a second core circuit of the single-coil multi-core LC oscillator. The center conductor is coupled between a first node and a second node of the outer conductor. The outer loop formed by the outer conductor corresponds to a first mode of the single-coil multi-core LC oscillator, while the inner loop formed by the outer conductor and the center conductor corresponds to a second mode of the single-coil multi-core LC oscillator. The at least one mode suppression device is used to suppress one of the first mode and the second mode.

[0006] In some embodiments, the at least one mode suppression device includes: a plurality of resonant capacitors for coupling to the center wire to suppress the second mode so that the single-coil multi-core LC oscillator operates in the first mode.

[0007] In some embodiments, each of the plurality of resonant capacitors is a switchable capacitor circuit that provides switchable capacitance.

[0008] In some embodiments, the at least one mode suppression device includes: a twisted pair coil for forming a closed loop to suppress the second mode so that the single-coil multi-core LC oscillator operates in the first mode, wherein the twisted pair coil is positioned concentric with the main coil.

[0009] In some embodiments, the at least one mode suppression device further includes at least one capacitor connected in series with the twisted pair coil.

[0010] In some embodiments, each of the at least one capacitor is a switchable capacitor circuit that provides switchable capacitance.

[0011] In some embodiments, the at least one mode suppression device includes: a mutual inductance coil for forming a closed loop to suppress the first mode so that the single-coil multi-core LC oscillator operates in the second mode; wherein the mutual inductance coil is positioned concentrically with the main coil.

[0012] In some embodiments, the mutual inductance coil includes a first mutual inductance coil and a second mutual inductance coil, and each of the first mutual inductance coil and the second mutual inductance coil is positioned concentrically with the main coil.

[0013] In some embodiments, the at least one mode suppression device further includes at least one capacitor connected in series with the mutual inductance coil.

[0014] In some embodiments, each of the at least one capacitor is a switchable capacitor circuit that provides switchable capacitance.

[0015] In some embodiments, the first segment of the outer conductor is coupled between the first core circuit and the second core circuit, the second segment of the outer conductor is coupled between the second core circuit and the third core circuit, the third segment of the outer conductor is coupled between the third core circuit and the fourth core circuit, and the fourth segment of the outer conductor is coupled between the fourth core circuit and the first core circuit, wherein the first segment of the outer conductor includes the first node, the second segment of the outer conductor includes the second node, the third segment of the outer conductor includes the third node, and the fourth segment of the outer conductor includes the fourth node; and the first segment of the central conductor is coupled between the first node of the outer conductor and the central node of the central conductor, the second segment of the central conductor is coupled between the second node of the outer conductor and the central node of the central conductor, the third segment of the central conductor is coupled between the third node of the outer conductor and the central node of the central conductor, and the fourth segment of the central conductor is coupled between the fourth node of the outer conductor and the central node of the central conductor.

[0016] In some embodiments, the at least one mode suppression device includes a first resonant capacitor, a second resonant capacitor, a third resonant capacitor, and a fourth resonant capacitor, wherein the first resonant capacitor, the second resonant capacitor, the third resonant capacitor, and the fourth resonant capacitor are respectively coupled to the first segment, the second segment, the third segment, and the fourth segment of the center conductor to suppress the second mode, so that the single-coil multi-core LC oscillator operates in the first mode.

[0017] In some embodiments, the at least one mode suppression device includes: a mutual inductance coil for suppressing the first mode so that the single-coil multi-core LC oscillator operates in the second mode; wherein the first segment, the second segment, the third segment, and the fourth segment of the mutual inductance coil are arranged concentrically with the main coil.

[0018] In some embodiments, when the single-coil multi-core LC oscillator is configured to operate in the second mode, the first port of the first segment of the mutual inductance is coupled to the second port of the fourth segment of the mutual inductance, the first port of the second segment of the mutual inductance is coupled to the second port of the first segment of the mutual inductance, the first port of the third segment of the mutual inductance is coupled to the second port of the second segment of the mutual inductance, the first port of the fourth segment of the mutual inductance is coupled to the second port of the third segment of the mutual inductance, the third port of the second segment of the mutual inductance is coupled to the third port of the fourth segment of the mutual inductance, and the third port of the first segment of the mutual inductance is coupled to the third port of the third segment of the mutual inductance.

[0019] In some embodiments, the single-coil multi-core LC oscillator is located within a multi-coil multi-core LC oscillator, and the multi-coil multi-core LC oscillator includes: a first single-coil multi-core LC oscillator; a second single-coil multi-core LC oscillator; and a switching circuit coupled between the first single-coil multi-core LC oscillator and the second single-coil multi-core LC oscillator for controlling whether the first single-coil multi-core LC oscillator and the second single-coil multi-core LC oscillator are connected in parallel; wherein either the first single-coil multi-core LC oscillator or the second single-coil multi-core LC oscillator includes the single-coil multi-core LC oscillator.

[0020] In a second aspect, the present invention provides a single-coil multi-core inductor-capacitor LC oscillator, the single-coil multi-core LC oscillator including a main coil, the main coil including: an outer conductor coupled to a first core circuit and a second core circuit of the single-coil multi-core LC oscillator; and a center conductor coupled between a first node and a second node of the outer conductor, wherein the center conductor includes at least one bent segment.

[0021] In some embodiments, the at least one bent segment includes a stranded conductor, a first segment of which is routed counterclockwise from the first node of the outer conductor to the middle segment of the stranded conductor, and a second segment of which is routed clockwise from the middle segment of the stranded conductor to the second node of the outer conductor.

[0022] In some embodiments, the at least one bent segment comprises one or more looped conductors connected in series.

[0023] In some embodiments, the at least one curved segment includes a serpentine conductor.

[0024] Thirdly, the present invention provides a single-coil multi-core inductive-capacitive LC oscillator, the single-coil multi-core LC oscillator including a main coil, the main coil including: an outer conductor coupled to a first core circuit and a second core circuit of the single-coil multi-core LC oscillator; and a center conductor coupled between a first node and a second node of the outer conductor; wherein a first segment of the outer conductor is coupled between a first end of the first core circuit and a first end of the second core circuit, a second segment of the outer conductor is coupled between a second end of the first core circuit and a second end of the second core circuit, and the resistance of the first segment and the second segment of the outer conductor is greater than the resistance of the center conductor.

[0025] Fourthly, the present invention provides a single-coil multi-core inductor-capacitor LC oscillator, the single-coil multi-core LC oscillator including a main coil, the main coil including an outer conductor and a center conductor, the outer conductor including: a first sub-coil coupled between a first terminal of a first core circuit and a first terminal of a second core circuit; and a second sub-coil coupled between a second terminal of the first core circuit and a second terminal of the second core circuit; wherein the first sub-coil and the second sub-coil are concentric; wherein the center conductor is coupled between a first node and a second node of the outer conductor.

[0026] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the present invention. The included drawings are used to provide a further understanding of embodiments of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the present disclosure.

[0028] Figure 1A This is a schematic diagram of a one-coil multi-core inductor-capacitor (LC) oscillator according to an embodiment of the present invention.

[0029] Figure 1B This is a schematic diagram of a single-coil multi-core LC oscillator according to an embodiment of the present invention.

[0030] Figure 1C This is a schematic diagram of a single-coil multi-core LC oscillator according to an embodiment of the present invention.

[0031] Figure 1D This is a schematic diagram of a single-coil multi-core LC oscillator according to an embodiment of the present invention.

[0032] Figure 1E This is a schematic diagram of a single-coil multi-core LC oscillator according to an embodiment of the present invention.

[0033] Figure 2A This is a schematic diagram of a single-coil multi-core LC oscillator with a resonance capacitor, according to an embodiment of the present invention.

[0034] Figure 2B This is a schematic diagram of a single-coil multi-core LC oscillator with a twisted mutual coil, as shown in an embodiment of the present invention.

[0035] Figure 2C This is a schematic diagram of a single-coil multi-core LC oscillator with twisted mutual coils and mutual capacitors, according to an embodiment of the present invention.

[0036] Figure 3A This is a schematic diagram of a single-coil multi-core LC oscillator with mutual coils, as shown in an embodiment of the present invention.

[0037] Figure 3B This is a schematic diagram of a single-coil multi-core LC oscillator with multiple mutual inductance coils, as shown in an embodiment of the present invention.

[0038] Figure 3C This is a schematic diagram of a single-coil multi-core LC oscillator with mutual inductance coils and mutual inductance capacitors according to an embodiment of the present invention.

[0039] Figure 4 This is a schematic diagram of a single-coil dual-core LC oscillator according to an embodiment of the present invention.

[0040] Figure 5This is a flowchart illustrating a method for controlling the operating mode of a multi-core LC oscillator according to an embodiment of the present invention.

[0041] Figure 6A This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates a single-coil dual-core LC oscillator configured to operate in a high-frequency band mode.

[0042] Figure 6B This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates a single-coil dual-core LC oscillator configured to operate in the disabled mode of the high-frequency band.

[0043] Figure 6C This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates the equivalent circuit of a single-coil dual-core LC oscillator operating in high-frequency band mode.

[0044] Figure 7A This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates a single-coil dual-core LC oscillator configured to operate in a low-frequency band mode.

[0045] Figure 7B This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates a single-coil dual-core LC oscillator configured to operate in the disabled mode of the low-frequency band.

[0046] Figure 7C This is illustrated in the embodiments of the present invention. Figure 4 The diagram shown illustrates the equivalent circuit of a single-coil dual-core LC oscillator operating in low-frequency band mode.

[0047] Figure 8 This is a schematic diagram of a single-coil dual-core LC oscillator according to an embodiment of the present invention.

[0048] Figure 9 This is a schematic diagram of a single-coil quad-core LC oscillator according to an embodiment of the present invention.

[0049] Figure 10 This is a schematic diagram of a single-coil quad-core LC oscillator according to an embodiment of the present invention.

[0050] Figure 11 This is a schematic diagram of a dual-coil quad-core LC oscillator 90 according to an embodiment of the present invention.

[0051] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0052] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0053] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0054] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0055] One of the objectives of this invention is to provide a single-coil multi-core inductor-capacitor (LC) oscillator that can improve / enhance phase noise reduction (i.e., reduce the phase noise of the LC oscillator) without significantly increasing additional costs (e.g., circuit area). Figure 1A This is a schematic diagram of a one-coil multi-core inductor-capacitor (LC) oscillator 100A according to an embodiment of the present invention. Figure 1AAs shown, the single-coil multi-core LC oscillator 100A includes a main coil. Figure 1A In the diagram, the main coil is shown by metal layer M1. The main coil may include outer wires (such as outer wires W11 and W12) and a central wire W2. Outer wires W11 and W12 are coupled to a first core circuit and a second core circuit. Figure 1A In the example, the first core circuit includes a transconductance device (also interchangeably referred to as a "transconductance device") Gm1 and a tank capacitor (also interchangeably referred to as a "slot capacitor") C1, and the second core circuit includes a transconductance device Gm2 and a tank capacitor C2. Specifically, the first segment of the outer conductor (e.g., outer conductor W11) is coupled to the first terminal of the first core circuit (e.g., ...). Figure 1A The left end of the transconductance device Gm1 shown) and the first end of the second core circuit (e.g., Figure 1A The left end of the transconductance device Gm2 shown is connected to the second end of the first core circuit (e.g., the left end of the transconductance device Gm2 shown), and the second segment of the outer conductor (e.g., outer conductor W12) is coupled to the second end of the first core circuit (e.g., the left end of the transconductance device Gm2 shown). Figure 1A The right end of the transconductance device Gm1 shown) and the second end of the second core circuit (e.g., Figure 1A The center conductor W2 is coupled between the right end of the transconductance device Gm2 shown. The center conductor W2 is coupled between node N1 of the outer conductor W11 and node N2 of the outer conductor W12. Understandably, the center conductor W2 and the outer conductors W11 and W12 may overlap at the coupling point, such as... Figure 1A As shown, nodes N1 and N2 can also be nodes on the center conductor W2. In this embodiment, the resistance of the first and second segments of the outer conductors (e.g., the resistance of each of the outer conductors W11 and W12) can be greater than the resistance (or interchangeably described as "resistance value" or "resistance value") of the center conductor W2, and the main coil allows the single-coil multi-core LC oscillator 100A to operate in both a first mode (e.g., a high-frequency band mode corresponding to a relatively low equivalent inductance) and a second mode (e.g., a low-frequency band mode corresponding to a relatively high equivalent inductance).

[0056] In some embodiments, the resistance of each of the first and second segments of the outer conductors (e.g., the resistance of each of the outer conductors W11 and W12) need not be greater than the resistance of the center conductor W2. More specifically, the center conductor W2 may include at least one bend segment (or alternatively described as a “bent portion”). This document will... Figure 1B , Figure 1C and Figure 1D Different architectures of at least one curved segment are described in the embodiments. Figure 1B , Figure 1C and Figure 1D In the embodiments, the implementation of the outer conductor, the first core circuit, and the second core circuit is similar to... Figure 1A The implementation examples are similar. Therefore, for the sake of simplicity, they will not be described in detail.

[0057] It should be noted that the transconductance device Gm1 can be the same as the transconductance device Gm2, and the slot capacitor C1 can be the same as the slot capacitor C2. Furthermore, the slot capacitors C1 and C2 are configured (or can be described as "configured" or "used for") to control the oscillation frequency of the single-coil multi-core LC oscillator 100A. More specifically, the oscillation frequency is determined by the capacitance (or interchangeably described as "capacitance value") of each of the slot capacitors C1 and C2 and the equivalent inductance of the single-coil multi-core LC oscillator 100A. Detailed implementations of the first core circuit (e.g., the transconductance device Gm1 and slot capacitor C1 therein) and the second core circuit (e.g., the transconductance device Gm2 and slot capacitor C2 therein) are well known to those skilled in the art; therefore, their descriptions are omitted here for brevity.

[0058] Figure 1B This is a schematic diagram of a single-coil multi-core LC oscillator 100B according to an embodiment of the present invention. Figure 1B In one embodiment, at least one bent segment may include a twisted wire having a first segment W21, a middle segment W2C, and a second segment W22. Specifically, the first segment W21 of the twisted wire is routed counterclockwise from node N1 of the outer conductor W11 to the middle segment W2C, and the second segment W22 of the twisted wire is routed clockwise from the middle segment W2C to node N2 of the outer conductor W12. The middle segment W2C may be implemented on a metal layer M3. Specifically, a first end of the first segment W21 is coupled to node N1, a first end of the middle segment W2C is coupled to a second end of the first segment W21, a first end of the second segment W22 is coupled to a second end of the middle segment W2C, and a second end of the second segment W22 is coupled to node N2. Figure 1A Compared to the central conductor W2 shown in the embodiment, Figure 1B The length of the center conductor shown (e.g., the center conductor consisting of the first segment W21, the middle segment W2C, and the second segment W22) is increased, therefore, compared to Figure 1A Compared to the center conductor W2 shown, Figure 1B The equivalent inductance of the center conductor shown is increased.

[0059] Figure 1CThis is a schematic diagram of a single-coil multi-core LC oscillator 100C according to an embodiment of the present invention. Figure 1C In some embodiments, at least one bent segment may include one or more ringed wires connected in series, such as ringed wires WR1 and WR2 connected in series. Each of the ringed wires WR1 and WR2 can be considered as two inductors connected in parallel, therefore, with Figure 1A Compared to the central conductor W2 shown in the embodiment, Figure 1C The equivalent inductance of the center conductors, including the loop conductors WR1 and WR2, shown is reduced.

[0060] Figure 1D This is a schematic diagram of a single-coil multi-core LC oscillator 100D according to an embodiment of the present invention. Figure 1D In one embodiment, at least one bent segment includes a serpentine (e.g., S-serpentine) conductor WS. Figure 1D As shown, Figure 1D The length of the center conductor shown (e.g., the S-shaped conductor WS) is compared to Figure 1A The center conductor W2 shown is enlarged, therefore, Figure 1D The equivalent inductance of the center conductor shown is... Figure 1A The equivalent inductance of the center conductor shown is increased compared to the previous example.

[0061] In some embodiments, the external conductor of the single-coil multi-core LC oscillator 100E can be utilized Figure 1E This is achieved through a multi-turn architecture, as shown. Figure 1E This is a schematic diagram of a single-coil multi-core LC oscillator 100E according to an embodiment of the present invention. Figure 1EAs shown, the external leads of the single-coil multi-core LC oscillator 100E include a first sub-coil and a second sub-coil. The first sub-coil is coupled between a first terminal of a first core circuit (e.g., the transconductance device Gm1 therein) and a first terminal of a second core circuit (e.g., the transconductance device Gm2 therein). For example, the first sub-coil may include segments (also interchangeably referred to as "segments" or "sections") WT11, WT12, WT13, WT14, and WT15, wherein the first terminal of segment WT11 is coupled to the first terminal of the first core circuit, the first terminal of segment WT12 is coupled to the second terminal of segment WT11, the first terminal of segment WT13 is coupled to the second terminal of segment WT12, the first terminal of segment WT14 is coupled to the second terminal of segment WT13, the first terminal of segment WT15 is coupled to the second terminal of segment WT14, and the second terminal of segment WT15 is coupled to the first terminal of the second core circuit. The second sub-coil is coupled between a second terminal of the first core circuit (e.g., the transconductance device Gm1 therein) and a second terminal of the second core circuit (e.g., the transconductance device Gm2 therein). For example, the second sub-coil may include segments (also interchangeably referred to as "segments" or "sections") WT21, WT22, WT23, WT24, and WT25, wherein a first terminal of segment WT21 is coupled to a second terminal of the first core circuit, a first terminal of segment WT22 is coupled to a second terminal of segment WT21, a first terminal of segment WT23 is coupled to a second terminal of segment WT22, a first terminal of segment WT24 is coupled to a second terminal of segment WT23, a first terminal of segment WT25 is coupled to a second terminal of segment WT24, and a second terminal of segment WT25 is coupled to a second terminal of the second core circuit. Furthermore, the first and second sub-coils are configured to be concentric. Figure 1A Compared to the previous embodiment, Figure 1E The embodiments can increase the equivalent inductance of the outer conductor without significantly increasing the additional area.

[0062] exist Figure 1E In some embodiments, the center conductor can be a straight wire coupled between nodes N1 and N2 of the outer conductor, but the invention is not limited thereto. For example, in some embodiments, it can be... Figure 1E The main coil shown uses Figure 1B , Figure 1C and Figure 1D Alternative designs for the center conductor in any of the embodiments shown.

[0063] exist Figures 1A to 1EIn some embodiments, two transconductance devices are used to drive the LC load of a single-coil multi-core LC oscillator (e.g., one transconductance device per core circuit), but the invention is not limited thereto. In some embodiments, any of the single-coil multi-core LC oscillators 100A to 100E can utilize a single transconductance device to drive the whole LC load; for example, one of the transconductance devices Gm1 and Gm2 can be omitted. When the number of transconductance devices is reduced, the overall power consumption is reduced.

[0064] To better understand, the following embodiments will be based on Figure 1A The architecture is described below. In some embodiments, the width of the center conductor W2 may be much smaller than the width of each of the outer conductors W11 and W12, which causes the center conductor W2 to have a much higher impedance than each of the outer conductors W11 and W12, and the current on the main coil tends to prevent flow through the center conductor W2 between nodes N1 and N2. In some embodiments, the center conductor W2 is not limited to having an impedance much higher than each of the outer conductors W11 and W12, and allows multiple behaviors or operating modes corresponding to relatively high equivalent inductance and relatively low equivalent inductance to coexist on the main coil. For example, the impedance (e.g., resistance) of the center conductor W2 may be close to / approximately equal to the impedance (e.g., resistance) of each of the outer conductors W11 and W12. In another example, the impedance (e.g., resistance) of the center conductor W2 may be less than the impedance of each of the outer conductors W11 and W12.

[0065] In addition to the main coil, the first core circuit, and the second core circuit, the single-coil multi-core LC oscillator 100A may also include at least one mode suppression device. Specifically, the outer loop formed by the outer conductors may correspond to a first mode of the single-coil multi-core LC oscillator 100A (e.g., a high-frequency band mode corresponding to a relatively low equivalent inductance), and the inner loop formed by the outer conductors and the center conductors may correspond to a second mode of the single-coil multi-core LC oscillator 100A (e.g., a low-frequency band mode corresponding to a relatively high equivalent inductance). More specifically, at least one mode suppression device may be configured to suppress one of the first and second modes, thereby increasing the quality factor of the other of the first and second modes. Figure 2A , Figure 2B and Figure 2CIn one embodiment, at least one mode suppression device can be configured to suppress low-band modes to increase the quality factor of high-band modes. Figure 3A , Figure 3B and Figure 3C In one embodiment, at least one mode suppression device can be configured to suppress high-frequency band modes in order to increase the quality factor of low-frequency band modes.

[0066] exist Figure 2A In some embodiments, at least one mode suppression device may include resonance capacitors CR1 and CR2, and the resonance capacitors CR1 and CR2 are configured to be coupled to the center wire when switches SHB1 and SHB2 are turned on to suppress low-frequency band modes, thereby allowing the single-coil multi-core LC oscillator 100A to operate in high-frequency band modes (e.g., increasing the quality factor of high-frequency band modes). In some embodiments, each of the resonance capacitors CR1 and CR2 may be a switchable capacitor circuit providing switchable capacitance, so that the single-coil multi-core LC oscillator 100A is suitable for wide-band applications. It is understood that although the resonance capacitors CR1 and CR2 in the figure are simply shown as capacitor symbols, they may actually be a device (or circuit) including switches and capacitors, and the capacitance value of the device can be changed by switching the switch in the device. It should be noted that in Figure 2A In the example shown, the positions (e.g., nodes) of the main coil coupled to the resonant capacitors CR1 and CR2 are for illustrative purposes only and do not imply limitation of the invention. For example, the resonant capacitors CR1 and CR2 can be symmetrically coupled to any node / position on the center conductor W2. It should be noted that in Figure 2A In the example, the center conductor W2 and the main coils W11 and W12 overlap at the coupling point, therefore Figure 2A The nodes N1 and N2 shown are located on the central conductor W2.

[0067] exist Figure 2BIn this embodiment, at least one mode suppression device includes a twisted mutual coil shown by metal layers M5 and M6. The twisted mutual coil is configured to form a closed loop when switches SHB3 and SHB4 are turned on to suppress low-frequency modes, causing the single-coil multi-core LC oscillator 100A to operate in high-frequency modes (e.g., increasing the quality factor of high-frequency modes). Specifically, the twisted mutual coil is placed concentrically with the main coil (it can be located above, below, or near the main coil), that is, the center position of the twisted mutual coil is the same as or approximately the same as the center position of the main coil. In this embodiment, each of switches SHB3 and SHB4 is connected in series with metal layer M5 on the closed loop of the twisted mutual coil, but the invention is not limited thereto.

[0068] Furthermore, at least one mode suppression device may also include at least one capacitor, for example, Figure 2C The shown are mutual capacitors CM1 and CM2, which are connected in series with twisted-pair coils. Mutual capacitors CM1 and CM2 are configured to introduce maximum loss for low-frequency band modes at a specific frequency (e.g., oscillation frequency). Based on the frequency selectivity introduced by mutual capacitors CM1 and CM2, Figure 2C Implementation examples and Figure 2B Compared to other embodiments, this can further improve the quality factor of the high-frequency band mode. In some embodiments, each of the mutual inductors CM1 and CM2 can be a switchable capacitor circuit that provides switchable capacitance, so that the frequency selectivity introduced by the mutual inductors CM1 and CM2 is suitable for broadband applications.

[0069] exist Figure 3A In some embodiments, at least one mode suppression device may include a mutual coil shown by the metal layer M2, wherein the mutual coil may be positioned along the outer conductors W11 and W12 (which may be above, below, or near the outer conductors). For example, the mutual coil is positioned concentrically with the main coil (i.e., the mutual coil is concentric with the main coil). The mutual coil may be configured to form a closed loop for suppressing high-frequency band modes, such that the single-coil multi-core LC oscillator 100A operates in low-frequency band modes (e.g., increasing the quality factor of the low-frequency band modes).

[0070] exist Figure 3BIn some embodiments, at least one mode suppression device may include a plurality of mutual inductance coils, for example, a first mutual inductance coil shown by metal layer M2 and a second mutual inductance coil shown by metal layer M4, wherein each of the first and second mutual inductance coils is positioned along outer conductors W11 and W12 (which may be located above, below, or near the outer conductors). Specifically, each of the first and second mutual inductance coils may be... Figure 3A The example shown is a mutually inductant coil. Similar to using... Figure 3A Compared to the single mutual inductance coil shown, using, as Figure 3B The multiple mutual inductance coils shown can further enhance the suppression of high-frequency band modes, thereby improving the quality factor of low-frequency band modes.

[0071] exist Figure 3C In embodiments, at least one mode suppression device may further include at least one capacitor, such as mutually inductant capacitors CM3 and CM4, wherein each of the mutually inductant capacitors CM3 and CM4 is connected to... Figure 3C The mutually inductant coils shown are connected in series. Similar to... Figure 2C The mutual inductors CM1 and CM2, and CM3 and CM4 shown introduce frequency selectivity, which maximizes the loss of high-frequency band modes at a specific frequency (e.g., the oscillation frequency). In some embodiments, each of the mutual inductors CM3 and CM4 can be a switchable capacitor circuit providing switchable capacitance, so that the frequency selectivity introduced by the mutual inductors CM3 and CM4 is suitable for broadband applications.

[0072] Different implementations of at least one mode suppression device mentioned in the above embodiments are based on Figure 1A The architecture is described herein, but the invention is not limited thereto. These embodiments of at least one mode suppression device can also be applied to Figure 1B , Figure 1C , Figure 1D and Figure 1E Any architecture within it.

[0073] It should be noted that the various mode suppression devices mentioned in the foregoing embodiments may be included in a single-coil multi-core LC oscillator for different purposes. In some embodiments, by Figures 2A to 2C The embodiments provided suggest that two or more mode suppression devices can be included in a single-coil multi-core LC oscillator, which enhances the ability to suppress low-frequency modes compared to using only one mode suppression device, thus further increasing the quality factor of high-frequency modes. In some embodiments, by Figures 3A to 3CThe embodiments provided suggest that two or more mode suppression devices can be included in a single-coil multi-core LC oscillator, which can enhance the ability to suppress high-frequency band modes compared to using only one mode suppression device, thus further increasing the quality factor of low-frequency band modes. In some embodiments, Figures 2A to 2C The embodiments provide at least one mode suppression device and Figures 3A to 3C The embodiments provided at least one mode suppression device can be included in the mode suppression device so that the single-coil multi-core LC oscillator can selectively operate in high-frequency band mode and low-frequency band mode, thereby having a wide tuning range.

[0074] Another object of the present invention is to provide a single-coil multi-core LC oscillator that enables the equivalent inductance of the multi-core LC oscillator to be switchable without reducing the quality factor. Figure 4 This is a schematic diagram of a single-coil dual-core LC oscillator 10 according to an embodiment of the present invention, wherein the single-coil dual-core LC oscillator 10 may be... Figure 2A and Figure 3A This is a superimposed example of an embodiment. In this embodiment, resonant capacitors CR1 and CR2 are controlled by a first set of switches, which may include switches SHB1 and SHB2, and the mutual inductance coil is controlled by a second set of switches, which includes switches SLB1 and SLB2. As described in the above embodiments, depending on the design related to the size / dimension or impedance of the main coil, multiple behaviors or operating modes corresponding to higher / relatively high equivalent inductance and lower / relatively low equivalent inductance can coexist on the main coil. In particular, the single-coil dual-core LC oscillator 10 can be configured in a first mode (e.g., corresponding to such as L) in response to the single-coil dual-core LC oscillator 10 being set to a first mode (e.g., corresponding to such as L HB The high-frequency band mode with relatively low equivalent inductance) or the second mode (e.g., corresponding to such as L) LB In the case of low-frequency band mode operation with relatively high equivalent inductance, the resonant capacitors CR1 and CR2 or the mutual inductance coil are selectively enabled to suppress unwanted behavior or modes on the main coil, so as to prevent the quality factor of the equivalent inductance of the first and second modes from deteriorating due to mode coexistence.

[0075] Figure 5 This is an embodiment of the invention illustrating a method for controlling a multi-core LC oscillator (e.g., Figure 4 The diagram illustrates the operation flow of the single-coil dual-core LC oscillator 10) in its operating mode. It should be noted that... Figure 5 The illustrated operation flow is for illustrative purposes only and does not imply limitation of the invention. In some embodiments, it is possible to... Figure 5Add, delete, or modify one or more steps in the illustrated workflow. Furthermore, if the same result can be obtained, these steps do not need to be followed. Figure 5 The exact order of execution is shown.

[0076] In step S110, the multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 10) uses a first set of switches (e.g., switches SHB1 and SHB2) to control whether multiple resonant capacitors (e.g., resonant capacitors CR1 and CR2) are coupled to the main coil (e.g., Figure 4 The portion shown is the metal layer M1. (As shown) Figure 4 As shown, switch SHB1 is coupled between node N1 and resonant capacitor CR1, and switch SHB2 is coupled between node N2 and resonant capacitor CR2.

[0077] In step S120, the multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 10) can utilize a second set of switches (e.g., switches SLB1 and SLB2) to control whether mutual inductance is generated (e.g., Figure 4 The closed loop shown is the portion of the metal layer M2 shown. Figure 4 As shown, each of switches SLB1 and SLB2 is connected in series with the metal layer M2 on the closed loop of the mutual inductance coil.

[0078] Specifically, when the single-coil dual-core LC oscillator 10 is configured to operate in a first mode (e.g., high-frequency mode), the first set of switches (e.g., switches SHB1 and SHB2) are turned on to couple resonant capacitors CR1 and CR2 to the main coil (e.g., coupled to nodes N1 and N2, respectively), while the second set of switches (e.g., switches SLB1 and SLB2) are turned off to prevent the formation of a closed loop in the mutual inductance. When the single-coil dual-core LC oscillator 10 is configured to operate in a second mode (e.g., low-frequency mode), the first set of switches (e.g., switches SHB1 and SHB2) are turned off to prevent resonant capacitors CR1 and CR2 from being coupled to the main coil, while the second set of switches (e.g., switches SLB1 and SLB2) are turned on to form a closed loop in the mutual inductance. It should be noted that the above description of the control of the first and second sets of switches is for illustrative purposes only and is not intended to limit the invention. For example, the first set of switches does not necessarily have to be turned off when the second set of switches is turned on, and the second set of switches does not necessarily have to be turned off when the first set of switches is turned on. In some embodiments, the first set of switches and the second set of switches can be turned on or off together.

[0079] Figure 6AThis is a schematic diagram illustrating an operating mode (e.g., desired and required behavior or mode) of a single-coil dual-core LC oscillator 10 configured to operate in a high-frequency band mode according to an embodiment of the present invention. Since the second set of switches (e.g., switches SLB1 and SLB2) are open when the single-coil dual-core LC oscillator 10 is configured to operate in high-frequency band mode to prevent the formation of a closed loop of mutual inductance, the mutual inductance can be considered disabled. Therefore, for simplicity, [the diagram is omitted here]. Figure 6A The middle part is omitted. For example... Figure 6A As shown, the first terminal of the first core circuit (e.g., the left terminal of the transconductance device Gm1 and the slot capacitor C1) is used as the positive terminal (labeled "+" for better understanding), and the second terminal of the first core circuit (e.g., the right terminal shown in the figure) is used as the negative terminal (labeled "-" for better understanding). Furthermore, the first terminal of the second core circuit (e.g., the left terminal of the transconductance device Gm2 and the slot capacitor C2) is used as the negative terminal (labeled "-" for better understanding), and the second terminal of the second core circuit (e.g., its right terminal shown in the figure) is used as the positive terminal (labeled "+" for better understanding). That is, W11 or W12 is excited by an out-of-phase signal. Therefore, nodes N1 and N2 can be considered as a virtual short, and no current flows between nodes N1 and N2 through the central conductor W2 (labeled "Zero" for better understanding). Furthermore, since nodes N1 and N2 are considered as virtual short circuits, the resonant capacitors CR1 and CR2 coupled to nodes N1 and N2 respectively will not interfere with the operation of the single-coil dual-core LC oscillator 10, which is set to operate in high-frequency band mode.

[0080] Figure 6B This is a schematic diagram illustrating a single-coil dual-core LC oscillator 10 configured to operate in a disabled mode (e.g., undesirable and suppressable behavior or mode) in a high-frequency band mode according to an embodiment of the present invention. Since the second set of switches (e.g., switches SLB1 and SLB2) are open when the single-coil dual-core LC oscillator 10 is configured to operate in a high-frequency band mode to prevent the formation of a closed loop of mutual inductance, the mutual inductance can be considered disabled; therefore, for simplicity, [the diagram is omitted here]. Figure 6B The middle part is omitted. For example... Figure 6BAs shown, the first terminal of the first core circuit is used as the positive terminal (labeled "+" for better understanding), and the second terminal of the first core circuit is used as the negative terminal (labeled "-" for better understanding). Furthermore, the first terminal of the second core circuit is used as the positive terminal (labeled "+" for better understanding), and the second terminal of the second core circuit is used as the negative terminal (labeled "-" for better understanding). Since nodes N1 and N2 are not virtually short-circuited in the disabled mode when the single-coil dual-core LC oscillator 10 is set to operate in high-frequency band mode, current flows from node N1 to node N2 via the center wire W2 if the resonant capacitors CR1 and CR2 are disabled. In this embodiment, the central conductor W2 includes a central inductor LD coupled between nodes N1 and N2. Since resonant capacitors CR1 and CR2 are coupled to nodes N1 and N2 when the single-coil dual-core LC oscillator 10 is configured to operate in high-frequency band mode, the network Zin includes resonant capacitors CR1 and CR2. Furthermore, the central inductor LD ensures that the path of the central conductor between nodes N1 and N2 has a much higher impedance than the outer conductors W11 and W12, thereby suppressing current on the central conductor W2. Therefore, it is possible to suppress the single-coil dual-core LC oscillator 10 from being configured to operate in high-frequency band mode in a disabled mode.

[0081] Figure 6C This is a schematic diagram of the equivalent circuit of a single-coil dual-core LC oscillator 10 configured to operate in a high-frequency band mode, according to an embodiment of the present invention. In the high-frequency band operation mode, nodes N1 and N2 can be considered as follows: Figure 6A The virtual short circuit is shown. More specifically, the single-coil dual-core LC oscillator 10 operating in high-frequency band mode can be considered as two single-coil single-core LC oscillators connected in parallel, such as... Figure 6C As shown. For the first single-coil single-core LC oscillator of these two single-coil single-core LC oscillators (e.g. Figure 6C As shown in the upper half, the outer conductor W11 is connected to node N1 and Figure 4 The upper segment between the first core circuits shown is considered as inductor L11, with external conductor W12 coupled to node N2 and Figure 4 The upper section between the first core circuits shown is considered as inductor L12, where the inductance of the first single-coil single-core LC oscillator (e.g., the inductance of inductors L11 and L12 as a whole) is L HB1 For the second single-coil single-core LC oscillator in these two single-coil single-core LC oscillators (such as...) Figure 6C As shown in the lower half, the outer conductor W11 is coupled to node N1 and as shown in the lower half. Figure 4The lower segment between the second core circuit shown can be considered as inductor L21, with external conductor W12 coupled to node N2 and Figure 4 The lower section between the second core circuits shown can be considered as inductor L22, where the inductance of the second single-coil single-core LC oscillator (e.g., the inductance of inductors L21 and L22 as a whole) is L HB2 Assuming the inductance of the external conductors W11 and W12 as a whole is L (i.e., the total inductance of the external conductors W11 and W12 is L), then the inductance L HB1 and L HB2 Each of these is (L / 2), and the equivalent inductance L of the single-coil dual-core LC oscillator 10 operating in high-frequency band mode. HB Yes (L / 4).

[0082] Figure 7A This is a schematic diagram illustrating the operating mode (e.g., desired and required behavior or mode) of a single-coil dual-core LC oscillator 10 configured to operate in a low-frequency band mode according to an embodiment of the present invention. Since the first set of switches (e.g., switches SHB1 and SHB2) are open when the single-coil dual-core LC oscillator 10 is configured to operate in low-frequency band mode to prevent resonant capacitors CR1 and CR2 from being coupled to the main coil, resonant capacitors CR1 and CR2 can be considered disabled. Therefore, for simplicity, in... Figure 7A The middle part is omitted. For example... Figure 7AAs shown, the first terminal of the first core circuit (e.g., its left terminal shown in the figure) is the positive terminal (labeled "+" for ease of understanding), and the second terminal of the first core circuit is the negative terminal (labeled "-" for ease of understanding). Similarly, the first terminal of the second core circuit (e.g., its left terminal shown in the figure) is the positive terminal (labeled "+" for ease of understanding), and the second terminal of the second core circuit is the negative terminal (labeled "-" for ease of understanding). That is, W11 or W12 is excited by an in-phase signal. Therefore, current from the positive terminals of the first and second core circuits, respectively, can flow from node N1 to node N2 via the central conductor W2. It is important to note that the magnetic field introduced by the upper-half current loop (e.g., the current flowing through the positive terminal of the first core circuit, node N1, center wire W2, node N2, and the negative terminal of the first core circuit) and the magnetic field introduced by the lower-half current loop (e.g., the current flowing through the positive terminal of the second core circuit, node N1, center wire W2, node N2, and the negative terminal of the second core circuit) have opposite directions, and the induced currents generated in the mutual inductance coils in response to the upper and lower current loops cancel each other out. Therefore, the operation of the single-coil dual-core LC oscillator 10 in the low-frequency band mode will not be hindered by the mutual inductance coils.

[0083] Figure 7B This is a schematic diagram illustrating a single-coil dual-core LC oscillator 10 configured to operate in a disabled mode (e.g., unwanted and suppressed behavior or mode) in a low-frequency band mode according to an embodiment of the present invention. Since the first set of switches (e.g., switches SHB1 and SHB2) are open when the single-coil dual-core LC oscillator 10 is configured to operate in a low-frequency band mode to prevent resonant capacitors CR1 and CR2 from being coupled to the main coil, resonant capacitors CR1 and CR2 can be considered disabled, thereby... Figure 7B The middle part is omitted. For example... Figure 7BAs shown, the first terminal of the first core circuit is the positive terminal (marked "+" for better understanding), and the second terminal of the first core circuit is the negative terminal (marked "-" for better understanding). Furthermore, the first terminal of the second core circuit is the negative terminal (marked "-" for better understanding), and the second terminal of the second core circuit is the positive terminal (marked "+" for better understanding). Therefore, nodes N1 and N2 can act as a virtual short circuit, and no current flows between nodes N1 and N2 through the central conductor W2 (marked "Zero" for better understanding). Moreover, the current flowing from the positive terminal of the first core circuit to the negative terminal of the second core circuit and the current flowing from the positive terminal of the second core circuit to the negative terminal of the first core circuit form an outer current loop on the outer conductors W11 and W12. According to Lenz's law, in response to the induced current generated in the mutual inductance coil by the external current loop, the current in the external current loop (e.g., the current flowing from the positive terminal of the first core circuit to the negative terminal of the second core circuit, or the current flowing from the positive terminal of the second core circuit to the negative terminal of the first core circuit) is suppressed. Therefore, the operation of the inhibit mode of the single-coil dual-core LC oscillator 10, which is set to operate in low-frequency band mode, can be suppressed.

[0084] Figure 7C This is a schematic diagram of the equivalent circuit of a single-coil dual-core LC oscillator 10 configured to operate in low-frequency mode according to an embodiment of the present invention. In low-frequency operation mode, there is a current flowing between nodes N1 and N2 via the center conductor W2, and the inductor LD on the center conductor W2 affects the equivalent inductance L of the single-coil dual-core LC oscillator 10 operating in low-frequency mode. LB More specifically, the single-coil dual-core LC oscillator 10 operating in low-frequency mode can be considered as two single-coil single-core LC oscillators connected in parallel, such as... Figure 7C As shown. For the first single-coil single-core LC oscillator in these two single-coil single-core LC oscillators (e.g. Figure 7C As shown in the upper part), Figure 4 The center conductor W2 shown can be considered as inductor LD1 (e.g., center inductor LD), wherein the first core circuit and inductors L11, L12 and Figure 6C Similar to the example shown, the relevant details will not be repeated here. The inductance of the first single-coil single-core LC oscillator (e.g., the inductance of inductors L11, LD1, and L12 as a whole) is L LB1 For the second single-coil single-core LC oscillator in these two single-coil single-core LC oscillators (such as...) Figure 7C As shown in the lower half, Figure 4The center conductor W2 shown can be considered as inductor LD2 (e.g., center inductor LD), where the second core circuit and inductors L21 and L22 are similar to Figure 6C As shown, the relevant details will not be repeated here. The inductance of the second single-coil single-core LC oscillator (e.g., the inductance of inductors L21, LD2, and L22 as a whole) is L LB1 For example, in Figure 1A In the diagram, since the inductance of the outer conductors W11 and W12 as a whole is L, and the inductance of the center conductor W2 is also L, therefore, the inductance L is... LB1 and L LB2 Each of them is approximately L, and the equivalent inductance L of the single-coil dual-core LC oscillator 10 is L. LB It is (L / 2).

[0085] It should be noted that the main coil and the mutual inductance coil can be implemented on different metal layers. In some embodiments, the main coil and the mutual inductance coil can overlap in the normal direction of any metal layer M1, M2, etc., which means that the mutual inductance coil does not significantly increase the overall circuit area of ​​the single-coil dual-core LC oscillator 10, but the present invention is not limited thereto.

[0086] exist Figure 4 In this embodiment, the center conductor W2 can be a straight conductor routed from node N1 of the outer conductor W11 to node N2 of the outer conductor W12. More specifically, Figure 4 The embodiments can make the tuning range of the high-frequency band mode and the tuning range of the low-frequency band mode substantially continuous without significant overlap, but the invention is not limited thereto. For example, the tuning range of the low-frequency band mode can be 6.6 GHz to 9.6 GHz, and the tuning range of the high-frequency band mode can be 9.6 GHz to 14 GHz. In some embodiments, the center conductor W2 can be implemented with an inductance that is either higher or lower than that implemented by a straight conductor.

[0087] In one embodiment, the architecture of the main coil of the single-coil dual-core LC oscillator 10 can be replaced with... Figure 1B The architecture shown. (As in...) Figure 1B As mentioned in the embodiments, due to Figure 1B The length of the central conductor W2 of the structure shown (e.g., the entirety of the first segment W21, the middle segment W2C, and the second segment W22) is... Figure 1A The illustrated embodiment is larger than the previous one; therefore, the inductance (also described as the "inductance value") of the center inductor LD is correspondingly increased, which shifts the tuning range of the low-frequency mode to a lower frequency band. More specifically, using... Figure 1BThe illustrated architecture allows for separation of the tuning ranges of the high-frequency mode and the low-frequency mode, but the invention is not limited thereto. For example, the tuning range of the low-frequency mode could be 3.6 GHz to 5.4 GHz, while the tuning range of the high-frequency mode could be 9.6 GHz to 14 GHz. Note that... Figure 1D The architecture shown can achieve similar results, and the relevant details will not be elaborated here.

[0088] In one embodiment, the architecture of the main coil of the single-coil dual-core LC oscillator 10 can be replaced with... Figure 1C The architecture shown. (As in...) Figure 1C As mentioned in the embodiments, with Figure 1A Compared to the center conductor W2 shown in the embodiment, the equivalent inductance of the center conductor including the loop conductors WR1 and WR2 is reduced. Therefore, compared to using... Figure 1A Compared to the architecture shown, Figure 1C The center conductor W2 shown (e.g., the entirety of the loop conductors WR1 and WR2) enables the tuning range of the low-frequency mode of the single-coil dual-core LC oscillator 10 to shift to a higher frequency band. More specifically, Figure 1C The embodiments allow the tuning range of the high-frequency band mode and the tuning range of the low-frequency band mode of the single-coil dual-core LC oscillator 10 to overlap, but the invention is not limited thereto. For example, the tuning range of the low-frequency band mode of the single-coil dual-core LC oscillator 10 may be 10 GHz to 13 GHz, while the tuning range of the high-frequency band mode of the single-coil dual-core LC oscillator 10 may be 11 GHz to 14 GHz.

[0089] Figure 8 This is a schematic diagram of a single-coil dual-core LC oscillator 70 according to an embodiment of the present invention. The single-coil dual-core LC oscillator 70 can be... Figure 2A , Figure 2B and Figure 3B Examples of superimposed embodiments, wherein, for the sake of brevity, Figure 8 Some symbols for components described in the previous embodiments have been omitted. For example... Figure 8 As shown, the single-coil dual-core LC oscillator 70 may include, for example: Figure 3B The embodiment mentions a first mutual inductor coil shown by metal layer M2 and a second mutual inductor coil shown by metal layer M4. The first and second mutual inductor coils are positioned along outer conductors W11 and W12 (which may be located above, below, or near the outer conductors). Each of the first and second mutual inductor coils is controlled by a second set of switches (e.g., switches SLB1, SLB2, SLB3, and SLB4 of the second set of switches). Furthermore, as... Figure 2BThe single-coil dual-core LC oscillator 70 mentioned in the embodiments may further include a stranded coil (which may be located above, below, or near the outer conductors W11 and W12), as shown in metal layers M5 and M6, wherein the stranded coil is controlled by a first set of switches (e.g., switches SHB3 and SHB4 of the first set of switches). More specifically, switches SHB3 and SHB4 are configured to control whether a closed loop of the stranded coil is generated. For example, each of switches SHB3 and SHB4 is connected in series with metal layer M5 on the closed loop of the stranded coil.

[0090] Specifically, when the single-coil dual-core LC oscillator 70 is configured to operate in high-frequency mode, the first set of switches (e.g., switches SHB3 and SHB4) is turned on to generate a closed loop of the stranded coil (i.e., the stranded coil forms a closed loop); when the single-coil dual-core LC oscillator 70 is configured to operate in low-frequency mode, the first set of switches (e.g., switches SHB3 and SHB4) is turned off to prevent the generation of a closed loop of the stranded coil. It should be noted that when the single-coil dual-core LC oscillator 70 is configured to operate in high-frequency mode, mutual currents can be generated on the closed loop of the stranded coil (e.g., induced currents generated based on Lenz's law in response to the upper and lower current loops). It should be explained that once mutual currents are generated on the closed loop of the stranded coil, when in the first part of the stranded coil (e.g., ... Figure 8 When the mutual current flowing through the upper half (as shown) is in a clockwise direction, in the second part of the stranded coil (e.g., Figure 8 The mutual current flowing in the lower half (shown) is in a counterclockwise direction; while when in the first part of the stranded coil (e.g., Figure 8 When the mutual current flowing in the upper part (as shown) is in the counterclockwise direction, then in the second part of the stranded coil (for example, Figure 8 The mutual current flowing in the lower half (shown) is in a clockwise direction. Therefore, by means of the stranded coil, the current from the first core circuit to the second core circuit or from the second core circuit to the first core circuit (for example, the single-coil dual-core LC oscillator 70 is set to the inhibit mode of the high-frequency band mode) can be further suppressed.

[0091] It should be noted that the implementation method of the main coil of the single-coil dual-core LC oscillator 70 is not limited to... Figure 8 The illustrated embodiment. For example, the main coil of the single-coil dual-core LC oscillator 70 can be based on... Figures 1A to 1EThis is implemented using the architecture shown in any of the embodiments. Furthermore, the control of the first and second sets of switches described in this embodiment is for illustrative purposes only and is not intended to limit the invention. For example, the first set of switches does not necessarily need to be disconnected when the second set of switches is turned on, and the second set of switches does not necessarily need to be disconnected when the first set of switches is turned on. In some embodiments, the first and second sets of switches can be turned on or off together.

[0092] Figure 4 The concepts illustrated in the embodiments can be applied to single-coil quad-core LC oscillators, which can further reduce the equivalent inductance, thereby improving / enhancing phase noise reduction without reducing the quality factor. Figure 9 This is a schematic diagram of a single-coil quad-core LC oscillator 80 according to an embodiment of the present invention. Figure 9 As shown, the one-coil quad-core LC oscillator 80 may include four core circuits, each of which may include transconductance devices (e.g., Gm1, Gm2, Gm3, or Gm4) and slot capacitors (e.g., C1, C2, C3, or C4). The specific implementation of the four core circuits in this embodiment is similar to the implementation of each of the first and second core circuits in the previous embodiments, and related details will not be repeated here. Furthermore, the one-coil quad-core LC oscillator 80 may also include a main coil represented by metal layer M1, mutually inducting coils represented by metal layer M2 (e.g., the entirety of segments W51, W52, W53, and W54), and resonant capacitors CR1, CR2, CR3, and CR4. The main coil of the one-coil quad-core LC oscillator 80 may include external conductors (e.g., transconductance devices Gm1, Gm2, Gm3, and Gm4 and slot capacitors C1, C2, C3, and C4) coupled to the four core circuits. Figure 9 The segments W31, W32, W33, and W34 shown (as a whole) and the center conductor (e.g.,) coupled between nodes N1, N2, N3, and N4 of the outer conductor. Figure 9 The entirety of segments W41, W42, W43, and W44 shown.

[0093] Specifically, segment W31 of the outer conductor is coupled between the first core circuit and the second core circuit; segment W32 of the outer conductor is coupled between the second core circuit and the third core circuit; segment W33 of the outer conductor is coupled between the third core circuit and the fourth core circuit; and segment W34 of the outer conductor is coupled between the fourth core circuit and the first core circuit. Segment W31 includes node N1, segment W32 includes node N2, segment W33 includes node N3, and segment W34 includes node N4. Segment W41 of the center conductor is coupled between node N1 of the outer conductor and the center node of the center conductor; segment W42 of the center conductor is coupled between node N2 of the outer conductor and the center node of the center conductor; segment W43 of the center conductor is coupled between node N3 of the outer conductor and the center node of the center conductor; and segment W44 of the center conductor is coupled between node N4 of the outer conductor and the center node of the center conductor. Segment W51 of the mutual inductance coil is placed along segment W31 of the outer conductor and segment W41 of the center conductor; segment W52 of the mutual inductance coil is placed along segment W32 of the outer conductor and segment W42 of the center conductor; segment W53 of the mutual inductance coil is placed along segment W33 of the outer conductor and segment W43 of the center conductor; and segment W54 of the mutual inductance coil is placed along segment W34 of the outer conductor and segment W44 of the center conductor. Figure 9 In the embodiment, the mutual inductance coil composed of segments W51, W52, W53 and W54 is concentric with the main coil.

[0094] Resonant capacitors CR1, CR2, CR3, and CR4 are controlled by a first set of switches (e.g., switches SHB1, SHB2, SHB3, and SHB4) (the first set of switches is turned on in response to the single-coil quad-core LC oscillator 80 being set to operate in high-frequency mode, and turned off in response to the single-coil quad-core LC oscillator 80 being set to operate in low-frequency mode). The mutual inductance coil is controlled by a second set of switches (e.g., switches SLB1, SLB2, SLB3, SLB4, SLB5, and SLB6) (the second set of switches is turned on in response to the single-coil quad-core LC oscillator 80 being set to operate in low-frequency mode, and turned off in response to the single-coil quad-core LC oscillator 80 being set to operate in high-frequency mode). Specifically, switch SHB1 is coupled between node N1 and resonant capacitor CR1, switch SHB2 is coupled between node N2 and resonant capacitor CR2, switch SHB3 is coupled between node N3 and resonant capacitor CR3, and switch SHB4 is coupled between node N4 and resonant capacitor CR4. Furthermore, switch SLB1 is coupled between the first end of segment W51 of the mutual inductance coil and the second end of segment W54 of the mutual inductance coil; switch SLB2 is coupled between the first end of segment W52 of the mutual inductance coil and the second end of segment W51 of the mutual inductance coil; switch SLB3 is coupled between the first end of segment W53 of the mutual inductance coil and the second end of segment W52 of the mutual inductance coil; switch SLB4 is coupled between the first end of segment W54 of the mutual inductance coil and the second end of segment W53 of the mutual inductance coil; switch SLB5 is coupled between the third end of segment W52 of the mutual inductance coil and the third end of segment W54 of the mutual inductance coil; and switch SLB6 is coupled between the third end of segment W51 of the mutual inductance coil and the third end of segment W53 of the mutual inductance coil.

[0095] For a single-coil quad-core LC oscillator 80 configured to operate in either high-frequency or low-frequency mode, multiple modes (including a desired operating mode and multiple unwanted inhibited modes) coexist on the main coil of the single-coil quad-core LC oscillator 80, each with different electrode polarity definitions for each of the four core circuits. Due to the self-damping of the quality factor, some inhibited modes may cancel each other out or suppress each other, thus these inhibited modes do not significantly affect the operating mode, while the remaining inhibited modes can be suppressed by means of resonant capacitors {CR1, CR2, CR3, CR4} or mutual inductance coils.

[0096] In this embodiment, the single-coil quad-core LC oscillator 80 can be considered as four parallel single-core LC oscillators (corresponding to the four core circuits respectively). For better illustration, assume the inductance of the entire outer conductor (e.g., the entirety of segments W31, W32, W33, and W34) is L. When the single-coil quad-core LC oscillator 80 is set to operate in high-frequency band mode, the first set of switches (e.g., switches SHB1, SHB2, SHB3, and SHB4) is turned on, and the second set of switches (e.g., switches SLB1, SLB2, SLB3, SLB4, SLB5, and SLB6) is turned off. For the single-core LC oscillator corresponding to the first core circuit, since nodes N1 and N4 are virtual short circuits, the equivalent inductance of the single-core LC oscillator corresponding to the first core circuit is (L / 4), which is provided by half of segment W31 and half of segment W34 of the outer conductor, and so on for the remaining single-core LC oscillators corresponding to the second, third, and fourth core circuits respectively. Since the equivalent inductance of the four single-core LC oscillators corresponding to each of the four core circuits is (L / 4), the overall equivalent inductance of the single-coil quad-core LC oscillator 80, which is set to operate in high-frequency band mode, is (L / 16).

[0097] When the single-coil quad-core LC oscillator 80 is configured to operate in low-frequency mode, the first set of switches (e.g., switches SHB1, SHB2, SHB3, and SHB4) is open, and the second set of switches (e.g., switches SLB1, SLB2, SLB3, SLB4, SLB5, and SLB6) is closed. For the single-core LC oscillator corresponding to the first core circuit, since nodes N1 and N4 are not virtually short-circuited, this means that the inductance on segments W41 and W44 will be effective. Therefore, the equivalent inductance of the single-core LC oscillator corresponding to the first core circuit is (L / 2), which is provided by half of segment W31 of the outer conductor, half of segment W34, segment W41 of the center conductor, and segment W44 of the center conductor. The same applies to the other single-core LC oscillators corresponding to the second, third, and fourth core circuits, respectively. Since the equivalent inductance of each of the four single-core LC oscillators corresponding to the four core circuits is (L / 2), the overall equivalent inductance of the single-coil quad-core LC oscillator 80, which is set to operate in low-frequency mode, is (L / 8).

[0098] It should be noted that the main coil of the single-coil quad-core LC oscillator 80 is not limited to... Figure 9 The structure shown. For example, any one of the segments W41, W42, W43, and W44 of the center wire of the single-coil quad-core LC oscillator 80 can be based on... Figure 1BThe implementation uses the stranded wire architecture shown in the embodiment. In another example, any one of the segments W41, W42, W43, and W44 of the center wire of the single-coil quad-core LC oscillator 80 can be implemented according to, for example, the stranded wire architecture shown in the embodiment. Figure 1C The embodiment shown in the example implements a series-connected loop conductor architecture. In another example, any one of the segments W41, W42, W43, and W44 of the center conductor of the single-coil quad-core LC oscillator 80 can be implemented according to, as shown in the example... Figure 1D The implementation uses the S-shaped serpentine wire architecture shown in the embodiment. Furthermore, the control of the first set of switches (e.g., switches SHB1, SHB2, SHB3, and SHB4) and the second set of switches (e.g., switches SLB1, SLB2, SLB3, SLB4, SLB5, and SLB6) described in this embodiment is for illustrative purposes only and does not imply limitation of the invention. For example, the first set of switches does not necessarily need to be closed when the second set of switches is turned on, and the second set of switches does not necessarily need to be closed when the first set of switches is turned on. In some embodiments, the first set of switches and the second set of switches can be turned on or off together.

[0099] exist Figure 9 In some embodiments, four transconductance devices (e.g., one transconductance device per core circuit) are used to drive the LC load of the single-coil quad-core LC oscillator 80, but the invention is not limited thereto. In some embodiments, the single-coil quad-core LC oscillator 80 may utilize a single transconductance device to drive the entire LC load; for example, one of the transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1) is used to drive the whole LC load, while the others (e.g., Gm2, Gm3, and Gm4) may be omitted. In some embodiments, the single-coil quad-core LC oscillator 80 may utilize two transconductance devices to drive the entire LC load; for example, any two of the transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1 and Gm3) are used to drive the entire LC load, while the others (e.g., Gm2 and Gm4) may be omitted. It should be noted that the arrangement of the transconductance devices is preferably symmetrical. For example, transconductance devices Gm1 and Gm3 are retained, while transconductance devices Gm2 and Gm4 are omitted. In some embodiments, the layout of the transconductance devices is not necessarily symmetrical. For example, transconductance devices Gm1 and Gm2 are retained, while transconductance devices Gm3 and Gm4 are omitted. In some embodiments, the single-coil quad-core LC oscillator 80 may utilize three transconductance devices to drive the entire LC load; for example, any three of transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1, Gm2, and Gm3) are used to drive the entire LC load, and the rest (e.g., Gm4) may be omitted.

[0100] Furthermore, thanks to the technology of suppressing low-frequency band modes using twisted-pair coils (such as...) Figure 2B The embodiment described above is also applicable to the single-coil quad-core LC oscillator 80. For example... Figure 10 As shown, the single-coil quad-core LC oscillator 80 may further include a twisted-pair coil shown by metal layers M5 and M6. It should be noted that segments W41, W42, W43, and W44 of the center conductor divide the main coil into four sections. Each of these four sections may correspond to an inner loop of the main coil. The first segment of the twisted-pair coil (e.g., the upper quarter of the twisted-pair coil) is routed counterclockwise, the second segment (e.g., the left quarter of the twisted-pair coil) is routed clockwise, the third segment (e.g., the lower quarter of the twisted-pair coil) is routed counterclockwise, and the fourth segment (e.g., the right quarter of the twisted-pair coil) is routed clockwise, all of which are placed concentrically with the main coil (it may be above, below, or near the main coil). The twisted-pair coil of this embodiment achieves the same effect as... Figure 2B The implementation examples are similar and will not be repeated here for the sake of brevity.

[0101] Figure 11 This is a schematic diagram of a dual-coil quad-core LC oscillator 90 according to an embodiment of the present invention. Figure 11 As shown, the dual-coil quad-core LC oscillator 90 includes a first single-coil multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 91), a second single-coil multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 92), and a switching circuit 90SW coupled between the first single-coil multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 91) and the second single-coil multi-core LC oscillator (e.g., a single-coil dual-core LC oscillator 92). For example, the switching circuit 90SW can be coupled to the single-coil dual-core LC oscillator 91 through ports NS1 and NS2, and the switching circuit 90SW can be coupled to the single-coil dual-core LC oscillator 92 through ports NS3 and NS4. In some embodiments, the switching circuit 90SW may include a first switch coupled between ports NS1 and NS4, and may also include a second switch coupled between ports NS2 and NS3, but the invention is not limited thereto.

[0102] In this embodiment, either (e.g., each) of the single-coil dual-core LC oscillator 91 and the single-coil dual-core LC oscillator 92 can be Figure 4An example of a single-coil dual-core LC oscillator 10 is shown. As described above, when the dual-coil quad-core LC oscillator 90 is configured to operate in high-frequency band mode, the equivalent inductance of the single-coil dual-core LC oscillator 91 and 92 is (L / 4), and when the dual-coil quad-core LC oscillator 90 is configured to operate in low-frequency band mode, the equivalent inductance of the single-coil dual-core LC oscillator 91 and 92 is (L / 2). To reduce phase noise, a switching circuit 90SW (e.g., a first switch and a second switch) can be switched on to connect the single-coil dual-core LC oscillator 91 and the single-coil dual-core LC oscillator 92 in parallel. When the dual-coil quad-core LC oscillator 90 operates in high-frequency mode, the equivalent inductance of the dual-coil quad-core LC oscillator 90 is (L / 8), and when the dual-coil quad-core LC oscillator 90 is set to operate in low-frequency mode, the equivalent inductance of the dual-coil quad-core LC oscillator 90 is (L / 4). According to the power saving requirements, the switching circuit 90SW (e.g., the first switch and the second switch) can be turned off to disconnect the single-coil dual-core LC oscillator 91 and the single-coil dual-core LC oscillator 92, and disable the single-coil dual-core LC oscillator 92 (e.g., power off). When the dual-coil quad-core LC oscillator 90 is set to operate in high-frequency band mode, the equivalent inductance of the dual-coil quad-core LC oscillator 90 is (L / 4), and when the dual-coil quad-core LC oscillator 90 is set to operate in low-frequency band mode, the equivalent inductance of the dual-coil quad-core LC oscillator 90 is (L / 2).

[0103] exist Figure 11In some embodiments, four transconductance devices are used to drive the LC load of the dual-coil quad-core LC oscillator 90 (e.g., one transconductance device per core circuit), but the invention is not limited thereto. In some embodiments, the single-coil quad-core LC oscillator 90 may utilize a single transconductance device to drive the entire LC load; for example, one of the transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1) is used to drive the entire LC load, and the others (e.g., Gm2, Gm3, and Gm4) may be omitted. In some embodiments, the single-coil quad-core LC oscillator 90 may utilize two transconductance devices to drive the entire LC load; for example, any two of the transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1 and Gm3) are used to drive the entire LC load, and the others (e.g., Gm2 and Gm4) may be omitted. It should be noted that the arrangement of the transconductance devices is preferably symmetrical. For example, transconductance devices Gm1 and Gm3 are retained, while transconductance devices Gm2 and Gm4 are omitted. In some embodiments, the layout of the transconductance devices is not necessarily symmetrical. For example, transconductance devices Gm1 and Gm2 are retained, while transconductance devices Gm3 and Gm4 are omitted. In some embodiments, the single-coil quad-core LC oscillator 90 can utilize three transconductance devices to drive the entire LC load; for example, any three of transconductance devices Gm1, Gm2, Gm3, and Gm4 (e.g., Gm1, Gm2, and Gm3) are used to drive the entire LC load, and the rest (e.g., Gm4) can be omitted.

[0104] The above embodiments utilize multiple metal layers to represent individual coils, wires, or segments. However, this is for illustrative purposes only and is not intended to limit the invention. Components represented by different metal layers in the figures are merely for better understanding of the wiring / line of these components and for better identification of different components, wherein these components are not necessarily implemented using different metal layers. As long as the overall electrical behavior is substantially the same, these components can be implemented on the same or different metal layers, and these alternative designs should fall within the scope of the invention.

[0105] In summary, the multi-core LC oscillator provided by the embodiments of the present invention can reduce its equivalent inductance by leveraging a multi-core architecture, thereby reducing phase noise without significantly increasing overall cost (e.g., circuit area). To overcome the inductance ratio bottleneck of the prior art, various types of master coils are also provided. Furthermore, resonant capacitors and mutual inductors can be used in high-frequency and low-frequency modes respectively to suppress one or more coexisting inhibited modes. Therefore, the tuning range of the multi-core LC oscillator can be switched without mode ambiguity, effectively extending the overall tuning range. Moreover, the embodiments of the present invention will not significantly increase overall cost (e.g., circuit area). Therefore, the present invention can improve phase noise reduction and increase the overall tuning range in a manner that introduces no side effects or is unlikely to introduce side effects.

[0106] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify claim elements does not in itself indicate any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with the same name from another element with the same name.

[0107] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. A single-coil multi-core inductor-capacitor LC oscillator, characterized in that, The single-coil multi-core LC oscillator includes a main coil and at least one mode suppression device, wherein the main coil includes: External wires are coupled to the first and second core circuits of the single-coil multi-core LC oscillator; and, The center conductor is coupled between the first and second nodes of the outer conductor; The outer loop formed by the outer conductor corresponds to the first mode of the single-coil multi-core LC oscillator, while the inner loop formed by the outer conductor and the center conductor corresponds to the second mode of the single-coil multi-core LC oscillator. The at least one mode suppression device is used to suppress one of the first mode and the second mode; The first segment of the external conductor is coupled between the first core circuit and the second core circuit; the second segment of the external conductor is coupled between the second core circuit and the third core circuit; the third segment of the external conductor is coupled between the third core circuit and the fourth core circuit; and the fourth segment of the external conductor is coupled between the fourth core circuit and the first core circuit. The first segment of the external conductor includes the first node; the second segment includes the second node; the third segment includes the third node; and the fourth segment includes the fourth node. The first segment of the central conductor is coupled between the first node of the outer conductor and the center node of the central conductor; the second segment of the central conductor is coupled between the second node of the outer conductor and the center node of the central conductor; the third segment of the central conductor is coupled between the third node of the outer conductor and the center node of the central conductor; and the fourth segment of the central conductor is coupled between the fourth node of the outer conductor and the center node of the central conductor.

2. The single-coil multi-core LC oscillator as described in claim 1, characterized in that, The at least one mode suppression device includes: Multiple resonant capacitors are used to couple to the center wire to suppress the second mode so that the single-coil multi-core LC oscillator operates in the first mode.

3. The single-coil multi-core LC oscillator as described in claim 2, characterized in that, Each of these multiple resonant capacitors is a switchable capacitor circuit that provides switchable capacitance.

4. The single-coil multi-core LC oscillator as described in claim 1, characterized in that, The at least one mode suppression device includes: A twisted pair coil is used to form a closed loop to suppress the second mode so that the single-coil multi-core LC oscillator operates in the first mode, wherein the twisted pair coil is placed concentrically with the main coil.

5. The single-coil multi-core LC oscillator as described in claim 4, characterized in that, The at least one mode suppression device further includes: At least one capacitor is connected in series with the twisted pair coil.

6. The single-coil multi-core LC oscillator as described in claim 5, characterized in that, Each of the at least one capacitor is a switchable capacitor circuit that provides switchable capacitance.

7. The single-coil multi-core LC oscillator as described in claim 1, characterized in that, The at least one mode suppression device includes: Mutual inductance coils are used to form a closed loop to suppress the first mode, so that the single-coil multi-core LC oscillator operates in the second mode; The mutual inductance coil is placed concentrically with the main coil.

8. The single-coil multi-core LC oscillator as described in claim 7, characterized in that, The mutual inductance coil includes a first mutual inductance coil and a second mutual inductance coil, and each of the first mutual inductance coil and the second mutual inductance coil is placed concentrically with the main coil.

9. The single-coil multi-core LC oscillator as described in claim 7, characterized in that, The at least one mode suppression device further includes: At least one capacitor is connected in series with the mutual inductance coil.

10. The single-coil multi-core LC oscillator as described in claim 9, characterized in that, Each of the at least one capacitor is a switchable capacitor circuit that provides switchable capacitance.

11. The single-coil multi-core LC oscillator as described in claim 1, characterized in that, The at least one mode suppression device includes a first resonant capacitor, a second resonant capacitor, a third resonant capacitor, and a fourth resonant capacitor, wherein the first resonant capacitor, the second resonant capacitor, the third resonant capacitor, and the fourth resonant capacitor are respectively coupled to the first segment, the second segment, the third segment, and the fourth segment of the center conductor to suppress the second mode, so that the single-coil multi-core LC oscillator operates in the first mode.

12. The single-coil multi-core LC oscillator as described in claim 1, characterized in that, The at least one mode suppression device includes: Mutual inductance coils are used to suppress the first mode so that the single-coil multi-core LC oscillator can operate in the second mode; The first, second, third, and fourth segments of the mutual inductance coil are arranged concentrically with the main coil.

13. The single-coil multi-core LC oscillator as described in claim 12, characterized in that, When the single-coil multi-core LC oscillator is configured to operate in the second mode, the first port of the first segment of the mutual inductor is coupled to the second port of the fourth segment of the mutual inductor, the first port of the second segment of the mutual inductor is coupled to the second port of the first segment of the mutual inductor, the first port of the third segment of the mutual inductor is coupled to the second port of the second segment of the mutual inductor, the first port of the fourth segment of the mutual inductor is coupled to the second port of the third segment of the mutual inductor, the third port of the second segment of the mutual inductor is coupled to the third port of the fourth segment of the mutual inductor, and the third port of the first segment of the mutual inductor is coupled to the third port of the third segment of the mutual inductor.

14. A single-coil multi-core LC oscillator, characterized in that, The single-coil multi-core LC oscillator is located within a multi-coil multi-core LC oscillator, and the multi-coil multi-core LC oscillator includes: First single-coil multi-core LC oscillator; A second single-coil multi-core LC oscillator; and A switching circuit, coupled between the first single-coil multi-core LC oscillator and the second single-coil multi-core LC oscillator, is used to control whether the first single-coil multi-core LC oscillator and the second single-coil multi-core LC oscillator are connected in parallel; Either the first single-coil multi-core LC oscillator or the second single-coil multi-core LC oscillator includes a main coil and at least one mode suppression device, wherein the main coil includes: External wires are coupled to the first and second core circuits of the single-coil multi-core LC oscillator; and, The center conductor is coupled between the first and second nodes of the outer conductor; The outer loop formed by the outer conductor corresponds to the first mode of the single-coil multi-core LC oscillator, while the inner loop formed by the outer conductor and the center conductor corresponds to the second mode of the single-coil multi-core LC oscillator. The at least one mode suppression device is used to suppress one of the first mode and the second mode.

15. A single-coil multi-core inductor-capacitor LC oscillator, characterized in that, The single-coil multi-core LC oscillator includes a main coil, which comprises: External wires are coupled to the first and second core circuits of the single-coil multi-core LC oscillator; and, A central conductor is coupled between a first node and a second node of the outer conductor, wherein the central conductor includes at least one curved segment; The at least one bent section includes a stranded conductor, a first segment of which is routed counterclockwise from the first node of the outer conductor to the middle segment of the stranded conductor, and a second segment of which is routed clockwise from the middle segment of the stranded conductor to the second node of the outer conductor.

16. The single-coil multi-core LC oscillator as described in claim 15, characterized in that, The at least one curved segment also includes one or more looped conductors connected in series.

17. The single-coil multi-core LC oscillator as described in claim 15, characterized in that, The at least one curved section also includes a serpentine conductor.

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