Integrated ultra-wideband amplifier

Abstract

This invention discloses an integrated ultra-wideband amplifier, comprising: a first-stage differential amplifier circuit, a second-stage amplifier circuit, an output matching circuit, and a feedback circuit connected in sequence. The feedback circuit is connected across the first-stage differential amplifier circuit. The first-stage differential amplifier circuit is also connected to a first port, and the output matching circuit is also connected to a second port. The first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit are not isolated by capacitors but are interconnected via MOSFETs. This invention achieves high gain, operates over a wide bandwidth from near DC to tens of GHz, achieves good input and output matching, has in-band flatness varying within 1 dB, and exhibits good linearity.

Description

Technical Field

[0001] This invention relates to the field of radio frequency amplifier technology, and in particular to an integrated ultra-wideband amplifier. Background Technology

[0002] Radio frequency (RF) amplifiers are a crucial component of various radio amplifiers. In the preamplifier circuitry of a transmitter, the RF signal generated by the modulation oscillator circuit has very low power. It needs to pass through a series of amplification buffer stages, intermediate amplification stages, and a final power amplification stage to obtain sufficient RF power before it can be fed to the antenna for radiation. To obtain sufficiently high RF output power, an RF power amplifier is necessary. However, existing RF power amplifiers have some problems. They either cannot amplify near-DC signals, or their RF amplification bandwidth is limited to a few GHz, failing to meet wide bandwidth requirements. Some RF amplifier designs include DC blocking capacitors as independent interstage bias, but the on-chip interstage capacitance is only a few picofarads, preventing low-frequency bandgap from reaching DC. Other amplifiers, while lacking on-chip DC blocking capacitors and able to approach DC, still do not reach high frequencies close to tens of GHz. Summary of the Invention

[0003] The purpose of this invention is to provide an integrated ultra-wideband amplifier that can achieve high gain and operate over a wide bandwidth range from near DC to tens of GHz.

[0004] To address the aforementioned technical problems, this invention provides an integrated ultra-wideband amplifier, comprising: a first-stage differential amplifier circuit, a second-stage amplifier circuit, an output matching circuit, and a feedback circuit connected in sequence. The feedback circuit is connected across the first-stage differential amplifier circuit. The first-stage differential amplifier circuit is also connected to a first port, and the output matching circuit is also connected to a second port. The first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit are not isolated by capacitors but are interconnected via MOSFETs.

[0005] Furthermore, the first-stage differential amplifier circuit includes: MOS transistors T5 and T6; the source of T5 is connected to the source of T6, the gate and drain of T5 are connected to the feedback circuit, the gate of T6 is grounded, and the drains of T5 and T6 are both connected to the second-stage amplifier circuit.

[0006] Furthermore, the feedback circuit includes a resistor R2 and a capacitor C1 connected in series.

[0007] Furthermore, after the source of T5 is connected to the source of T6, one end of capacitor C2 is also connected, and the other end of capacitor C2 is grounded.

[0008] Furthermore, the second-stage amplifier circuit includes MOSFETs T8 and T9; the drain of T8 is connected to the drain of T5, the source is connected to the source of T9 and grounded, and the gate is connected to the drain of T6; the gate of T9 is connected to the drain of T5, and the drain is connected to the output matching circuit.

[0009] Further, the output matching circuit includes MOSFETs T11, T12, T13, T15, T16, T17 and inductor L3; L3, T11, T12 and T13 are connected in parallel, one end of L3 is connected to the drain of T15 and the other end is connected to the drain of T11, the gate of T11 is connected to the drain of T9, the gate of T12 is connected to its own drain, and the gate of T13 is connected to its own drain; T15, T16 and T17 are connected in series, the gate of T15 is connected to the connection node of T11 and T12, the gate of T16 is connected to its own drain, the gate of T17 is connected to its own drain, and the source of T17 is connected to the second port.

[0010] Furthermore, it also includes a positive power supply bias, which is connected to the first-stage differential amplifier circuit, the second-stage amplifier circuit, the output matching circuit, and the feedback circuit.

[0011] Further, the positive power supply bias includes: resistors R5, R6, R7, R10 and inductor L2; one end of R6 is connected to the connection node of T5 and T9, and the other end is connected to one end of R5, one end of R7 and the drain of T8; the other end of R7 is connected to the drain of T6; the other end of R5 is connected to the positive power supply Vcc1; one end of R10 is connected to one end of L2, and the other end is connected to the connection node of the gate of T11 and the drain of T9, and the other end of L2 is connected to the positive power supply Vcc1.

[0012] Furthermore, it also includes a negative power supply bias, which is connected to the first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit.

[0013] Further, the negative power supply bias includes MOSFETs T1, T2, T3, T4, T7, T10, T14, and T18, and resistors R3, R4, R8, R9, R11, R12, R13, and R14; wherein in the first branch, R3, T4, and R4 are connected sequentially; in the second branch, T1, T2, and T3, the gate of T2 is connected to its own drain, the gate of T1 is connected to its own drain, and R3 of the first branch and the positive power supply Vcc1 are connected at this node; the gate of T3 is connected to the connection node where R3 connects T4 and R3, and the source is connected to the gate of T4; in the third branch, R8, T7, and R9 are connected sequentially, and R8 is connected to T5. The connection node of T6 is connected to the connection node of T3 and T4; the fourth branch R11, T10, and R12 are connected in sequence, R11 is connected to the connection node of T8 and T9, the gate of T10 is connected to its own drain, and the connection node of T3 and T4 is connected at this node; the fifth branch T14 and R13 are connected, T14 is connected to the connection node of T3 and T4 and the source of T13; the sixth branch T18 and R14 are connected, the drain of T18 is connected to the source of T17, and the gate is connected to the connection node of T3 and T4; R4, R9, R12, R13, and R14 are also connected to the negative power supply VEE.

[0014] Furthermore, it also includes an input matching circuit, which is disposed between the first port and the first stage differential amplifier circuit.

[0015] Furthermore, the input matching circuit includes an inductor L1 and a resistor R1; L1 and R1 are connected in series, with one end of L1 grounded and the other end of R1 connected to the first port.

[0016] Compared with existing technologies, this invention provides an integrated ultra-wideband amplifier, comprising: a first-stage differential amplifier circuit, a second-stage amplifier circuit, an output matching circuit, and a feedback circuit connected in sequence. The feedback circuit is connected across the first-stage differential amplifier circuit. The first-stage differential amplifier circuit is also connected to a first port, and the output matching circuit is also connected to a second port. The first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit are not isolated by capacitors but are interconnected via MOSFETs. This invention can achieve high gain, operate over a wide bandwidth range from near DC to tens of GHz, achieve good input and output matching, have in-band flatness varying within 1 dB, and exhibit good linearity. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of an integrated ultra-wideband amplifier chip according to an embodiment of the present invention;

[0018] Figure 2This is a circuit schematic diagram of an integrated ultra-wideband amplifier chip according to an embodiment of the present invention;

[0019] Figure 3 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 10MHz-16GHz in one embodiment of the present invention. Figure 1 ;

[0020] Figure 4 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 10MHz-16GHz in one embodiment of the present invention. Figure 2 ;

[0021] Figure 5 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 10MHz-16GHz in one embodiment of the present invention. Figure 3 ;

[0022] Figure 6 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 20kHz-10MHz in one embodiment of the present invention. Figure 1 ;

[0023] Figure 7 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 20kHz-10MHz in one embodiment of the present invention. Figure 2 ;

[0024] Figure 8 This is the S-parameter curve of the integrated ultra-wideband amplifier chip with a bandwidth of 20kHz-10MHz in one embodiment of the present invention. Figure 3 . Detailed Implementation

[0025] The integrated ultra-wideband amplifier of the present invention will now be described in more detail with reference to the schematic diagrams, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0026] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0027] This invention provides an integrated ultra-wideband amplifier, reference Figure 1As shown, the receiving signal processing circuit includes: a first-stage differential amplifier circuit 120, a second-stage amplifier circuit 130, an output matching circuit 140, and a feedback circuit 150 connected in sequence. The feedback circuit 150 is connected to both ends of the first-stage differential amplifier circuit 120. The first-stage differential amplifier circuit 120 is also connected to a first port P1, and the output matching circuit 140 is also connected to a second port P2. The first-stage differential amplifier circuit 120, the second-stage amplifier circuit 130, and the output matching circuit 140 are not isolated by capacitors, but are connected to each other through MOSFETs.

[0028] In this invention, no DC blocking capacitors are used between the input matching circuit 110, the first-stage differential amplifier circuit 120, the second-stage amplifier circuit 130, and the output matching circuit 140. In the circuit of this invention, the gate bias of the next stage comes from the drain voltage of the previous stage. High gain can be achieved, and it can operate over a wide bandwidth range from near DC to tens of GHz.

[0029] Please combine Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the first-stage differential amplifier circuit 120 includes: MOS transistors T5 and T6; the source of T5 is connected to the source of T6, the gate and drain of T5 are connected to the feedback circuit 150, the gate of T6 is grounded, and the drains of T5 and T6 are both connected to the second-stage amplifier circuit 130.

[0030] Furthermore, after the source of T5 is connected to the source of T6, one end of capacitor C2 is also connected, and the other end of capacitor C2 is grounded.

[0031] The integrated ultra-wideband amplifier in this invention adopts a single-ended input, zero-bias gate differential circuit structure in the first-stage differential amplifier circuit 120. There is an on-chip capacitor C2 of more than ten picofarads at the common-mode signal point, which is used to achieve negative voltage bias of the source stage of the first-stage amplifier circuit 120 (T7, R8, R9, described below) and ground the source stage RF signal to achieve RF signal amplification.

[0032] In one embodiment of the present invention, the feedback circuit 150 includes a resistor R2 and a capacitor C1 connected in series.

[0033] In this embodiment, R2 and C1 are added between the drain and gate of the first-stage amplifier 120 to achieve better wide input matching and maintain good low-frequency gain flatness.

[0034] Furthermore, it also includes an input matching circuit 110, which is disposed between the first port P1 and the first stage differential amplifier circuit 120.

[0035] As an example, the input matching circuit 110 includes an inductor L1 and a resistor R1; L1 and R1 are connected in series, with one end of L1 grounded and the other end of R1 connected to the first port.

[0036] In the input matching circuit 110, a resistor R1 and an inductor L1 are introduced to achieve input width matching and to implement the zero bias circuit of the gate at the input terminal of the first-stage differential amplifier circuit 120.

[0037] In one embodiment of the present invention, the second-stage amplifier circuit 130 includes MOSFETs T8 and T9; the drain of T8 is connected to the drain of T5, the source of T8 is connected to the source of T9 and grounded, and the gate is connected to the drain of T6; the gate of T9 is connected to the drain of T5, and the drain is connected to the output matching circuit.

[0038] In this embodiment, a MOSFET T8 is introduced into the second-stage amplifier circuit 130 to achieve a flatter in-band gain, and an L2 is introduced to improve the high-frequency gain.

[0039] In one embodiment of the present invention, the output matching circuit includes MOSFETs T11, T12, T13, T15, T16, T17 and inductor L3; L3, T11, T12 and T13 are connected in parallel, one end of L3 is connected to the drain of T15 and the other end is connected to the drain of T11, the gate of T11 is connected to the drain of T9, the gate of T12 is connected to its own drain, and the gate of T13 is connected to its own drain; T15, T16 and T17 are connected in series, the gate of T15 is connected to the connection node of T11 and T12, the gate of T16 is connected to its own drain, the gate of T17 is connected to its own drain, and the source of T17 is connected to the second port.

[0040] In this embodiment, MOSFETs T15, T16, and T17 are introduced into the output matching circuit 140 to improve the linearity of the circuit and to achieve a wider output matching range.

[0041] In this embodiment of the invention, a positive power supply bias 160 is also included, which is connected to the first stage differential amplifier circuit 120, the second stage amplifier circuit 130, the output matching circuit 140, and the feedback circuit 150.

[0042] For example, the positive power supply bias 160 includes: resistors R5, R6, R7, R10 and inductor L2; one end of R6 is connected to the connection node of T5 and T9, and the other end is connected to one end of R5, one end of R7 and the drain of T8; the other end of R7 is connected to the drain of T6; the other end of R5 is connected to the positive power supply Vcc1; one end of R10 is connected to one end of L2, and the other end is connected to the connection node of the gate of T11 and the drain of T9, and the other end of L2 is connected to the positive power supply Vcc1.

[0043] In this embodiment of the invention, a negative power supply bias 170 is also included, which is connected to the first-stage differential amplifier circuit 120, the second-stage amplifier circuit 130, and the output matching circuit 140.

[0044] As an example, the negative power supply bias includes MOSFETs T1, T2, T3, T4, T7, T10, T14, and T18, and resistors R3, R4, R8, R9, R11, R12, R13, and R14; wherein in the first branch, R3, T4, and R4 are connected sequentially; in the second branch, T1, T2, and T3, the gate of T2 is connected to its own drain, the gate of T1 is connected to its own drain, and R3 of the first branch and the positive power supply Vcc1 are connected at this node, the gate of T3 is connected to the connection node of R3 connecting T4 and R3, and the source is connected to the gate of T4; in the third branch, R8, T7, and R9 are connected sequentially, R8 is connected to the connection node of T5 and T6, and the gate of T7 is connected to the connection node of T6. The first branch connects to its own drain and connects to the connection node of T3 and T4 at this node; the fourth branch connects R11, T10, and R12 in sequence, with R11 connecting to the connection node of T8 and T9, and the gate of T10 connected to its own drain and connected to the connection node of T3 and T4 at this node; the fifth branch connects T14 and R13, with the gate of T14 connected to its own drain and connected to the connection node of T3 and T4 and the source of T13 at this node; the sixth branch connects T18 and R14, with the drain of T18 connected to the source of T17 and the gate connected to the connection node of T3 and T4; R4, R9, R12, R13, and R14 are also connected to the negative power supply VEE.

[0045] MOSFETs T11, T12, and T13, along with inductor L3, are used to broaden the in-band gain at high frequencies.

[0046] like Figures 3-5 As shown, Figures 3-5 The diagram illustrates the S-parameter curves of the integrated ultra-wideband amplifier chip in the high-frequency band according to an embodiment of the present invention. It can be seen that S11 / S22 of this integrated ultra-wideband amplifier chip are both below -10dB over a wide operating frequency range in the high-frequency band, meaning its input-output matching meets the requirements; S21 can achieve a high gain of over 20dB and a gain flatness of less than 1dB over a wide frequency range.

[0047] like Figures 6-8 As shown, Figures 6-8 The diagram illustrates the S-parameter curves of the integrated ultra-wideband amplifier chip in the low-frequency band according to an embodiment of the present invention. It can be seen that S11 / S22 of this integrated ultra-wideband amplifier chip are both around -10dB in the low-frequency operating frequency range, which means that its input-output matching can meet the requirements. S21 can achieve a high gain of more than 20dB and a gain flatness of less than 1dB in the low-frequency band. The low-frequency operating frequency of this integrated ultra-wideband amplifier chip is close to DC.

[0048] In summary, this invention, through the design of an integrated ultra-wideband amplifier circuit, can achieve high gain while operating within a wide bandwidth range from near DC to tens of GHz. It exhibits good performance in both high and low frequency bands, with good input and output matching, in-band flatness varying within 1 dB, and good linearity.

[0049] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An integrated ultra-wideband amplifier, characterized in that, include: A first-stage differential amplifier circuit, a second-stage amplifier circuit, an output matching circuit, and a feedback circuit are connected in sequence. The feedback circuit is connected to both ends of the first-stage differential amplifier circuit. The first-stage differential amplifier circuit is also connected to a first port, and the output matching circuit is also connected to a second port. The first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit are not isolated by capacitors, but are connected to each other through MOSFETs. The first-stage differential amplifier circuit includes: MOS transistors T5 and T6; the source of T5 is connected to the source of T6, the gate and drain of T5 are connected to the feedback circuit, the gate of T6 is grounded, and the drains of T5 and T6 are also connected to the second-stage amplifier circuit. The second-stage amplifier circuit includes MOSFETs T8 and T9; the drain of T8 is connected to the drain of T5, the source is connected to the source of T9 and grounded, and the gate is connected to the drain of T6; the gate of T9 is connected to the drain of T5, and the drain is connected to the output matching circuit. The output matching circuit includes MOSFETs T11, T12, T13, T15, T16, T17 and inductor L3; The source of T11 is connected to the drain of T12, and the drain of T11 is connected to one end of inductor L3. The other end of inductor L3 is connected to power supply VCC2. The gate of T11 is connected to the drain of T9 and the positive power supply bias. The gate of T12 is connected to its own drain, and the source of T12 is connected to the drain of T13. The gate of T13 is connected to its own drain. One end of inductor L3 is also connected to the drain of T15. The gate of T15 is connected to the connection node of T11 and T12, and the source of T15 is connected to the drain of T16. The gate of T16 is connected to its own drain, and the source of T16 is connected to the drain of T17. The gate of T17 is connected to its own drain, and the source of T17 is connected to the second port.

2. The integrated ultra-wideband amplifier as described in claim 1, characterized in that, The feedback circuit includes a resistor R2 and a capacitor C1 connected in series.

3. The integrated ultra-wideband amplifier as described in claim 1, characterized in that, The source of T5 is connected to the source of T6 and then connected to one end of capacitor C2, and the other end of capacitor C2 is grounded.

4. The integrated ultra-wideband amplifier as described in claim 3, characterized in that, It also includes a positive power supply bias, which is connected to the first-stage differential amplifier circuit, the second-stage amplifier circuit, the output matching circuit, and the feedback circuit.

5. The integrated ultra-wideband amplifier as described in claim 4, characterized in that, The positive power supply bias includes: resistors R5, R6, R7, R10 and inductor L2; one end of R6 is connected to the connection node of T5 and T9, and the other end is connected to one end of R5, one end of R7 and the drain of T8; the other end of R7 is connected to the drain of T6; the other end of R5 is connected to the positive power supply Vcc1; one end of R10 is connected to one end of L2, and the other end is connected to the connection node of the gate of T11 and the drain of T9, and the other end of L2 is connected to the positive power supply Vcc1.

6. The integrated ultra-wideband amplifier as described in claim 3, characterized in that, It also includes a negative power supply bias, which is connected to the first-stage differential amplifier circuit, the second-stage amplifier circuit, and the output matching circuit.

7. The integrated ultra-wideband amplifier as described in claim 6, characterized in that, The negative power supply bias includes a first branch, a second branch, a third branch, a fourth branch, a fifth branch, and a sixth branch; The first branch includes: resistor R3, MOSFET T4, and resistor R4; One end of the resistor R3 is connected to the positive power supply VCC1, and the other end is connected to the second branch and the drain of the MOS transistor T4. The source of T4 is connected to the negative power supply VEE through the resistor R4. The second branch includes: MOSFET T1, MOSFET T2 and MOSFET T3; The source of MOSFET T1 is connected to the positive power supply VCC1. The gate of MOSFET T1 is connected to its own drain. The drain of MOSFET T1 is connected to the source of MOSFET T2. The gate of MOSFET T2 is connected to its own drain. The drain of MOSFET T2 is connected to the drain of MOSFET T3. The gate of MOSFET T3 is connected to the source of T1 through resistor R3. The gate of MOSFET T3 is also connected to the drain of MOSFET T4. The source of MOSFET T3 is connected to the gate of MOSFET T4. The third branch includes: resistor R8, MOSFET T7 and MOSFET R9; The gate of MOSFET T7 is connected to the gate of MOSFET T4, the source is connected to the negative power supply VEE through MOSFET R9, and the drain is connected to the source of MOSFET T5 through resistor R8. The fourth branch includes: resistor R11, MOSFET T10 and resistor R12; The gate of MOSFET T10 is connected to the gate of MOSFET T4, the source is connected to the negative power supply VEE through MOSFET R12, and the drain is connected to the source of MOSFET T8 through resistor R11. The fifth branch includes: MOSFET T14 and resistor R13; The gate of the MOSFET T14 is connected to the gate of the MOSFET T14, the source is connected to the negative power supply VEE through the resistor R13, and the drain is connected to the source of the MOSFET T13. The sixth branch includes: MOSFET T18 and resistor R14; The drain of the MOSFET T18 is connected to the source of the MOSFET T17, the gate is connected to the gate of the MOSFET T4, and the source is connected to the negative power supply VEE through the resistor R14.

8. The integrated ultra-wideband amplifier as described in claim 1, characterized in that, It also includes an input matching circuit, which is disposed between the first port and the first stage differential amplifier circuit.

9. The integrated ultra-wideband amplifier as described in claim 8, characterized in that, The input matching circuit includes an inductor L1 and a resistor R1; L1 and R1 are connected in series, with one end of L1 grounded and the other end of R1 connected to the first port.

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