Pixel driving circuit, driving method thereof, display substrate, and display device

Abstract

A pixel driving circuit and driving method thereof, a display substrate, and a display device. In the pixel driving circuit, a compensation subcircuit is respectively coupled to a first control terminal (AZn), a control terminal of a driving subcircuit, and a second terminal of the driving subcircuit; a first terminal of a first coupling subcircuit is coupled to the control terminal of the driving subcircuit; a first terminal of a second coupling subcircuit is coupled to the second terminal of the first coupling subcircuit; a first reset subcircuit is respectively coupled to a second control terminal (SnB), the control terminal of the driving subcircuit, and an initialization signal output terminal (Init); a second reset subcircuit is respectively coupled to a third control terminal (AZn-1), the second terminal of the first coupling subcircuit, and a first level signal output terminal (VDD); a first light-emitting control subcircuit is respectively coupled to a light-emitting control terminal (EM), the second terminal of the second coupling subcircuit, and a reference signal output terminal (Ref); and a data writing subcircuit is respectively coupled to a write control terminal (Sn), the second terminal of the second coupling subcircuit, and a data signal input terminal (DA).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) displays are widely used in various fields due to their high brightness, low power consumption, fast response, high definition, flexibility, and high luminous efficiency. OLED displays require different drive frequencies in different application scenarios, with common drive modes including low-frequency and high-frequency. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a pixel driving circuit and a driving method thereof, a display substrate, and a display device.

[0004] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0005] A first aspect of the present disclosure provides a pixel driving circuit for driving a light-emitting element, the pixel driving circuit comprising:

[0006] a driving sub-circuit, wherein a first terminal of the driving sub-circuit is coupled to the first level signal output terminal, and a second terminal of the driving sub-circuit is coupled to the light-emitting element; the driving sub-circuit includes a third active pattern;

[0007] a compensation subcircuit, coupled to the first control terminal, the control terminal of the driving subcircuit, and the second terminal of the driving subcircuit, respectively; the compensation subcircuit includes a second active pattern;

[0008] a first coupling subcircuit, wherein a first terminal of the first coupling subcircuit is coupled to a control terminal of the driving subcircuit;

[0009] a second coupling subcircuit, wherein a first end of the second coupling subcircuit is coupled to a second end of the first coupling subcircuit;

[0010] a first reset subcircuit, coupled to the second control terminal, the control terminal of the driving subcircuit, and the initialization signal output terminal; the first reset subcircuit includes a fourth active pattern;

[0011] a second reset subcircuit, coupled to a third control terminal, the second terminal of the first coupling subcircuit, and the first level signal output terminal, respectively; and configured to, under control of the third control terminal, control the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal to be opened or closed; the second reset subcircuit comprising a fifth active pattern;

[0012] a first light-emitting control subcircuit, coupled to the light-emitting control terminal, the second terminal of the second coupling subcircuit, and the reference signal output terminal, respectively; and configured to, under the control of the light-emitting control terminal, control the electrical connection between the second terminal of the second coupling subcircuit and the reference signal output terminal to be turned on or off;

[0013] a data writing sub-circuit, coupled to the writing control terminal, the second terminal of the second coupling sub-circuit and the data signal input terminal respectively;

[0014] The second active pattern, the fourth active pattern and the fifth active pattern are all arranged in different layers from the third active pattern.

[0015] Optionally, the pixel driving circuit further includes:

[0016] a second light-emitting control subcircuit, the second light-emitting control subcircuit being coupled to the light-emitting control terminal, the second terminal of the driving subcircuit, and the light-emitting element, respectively; and configured to control, under the control of the light-emitting control terminal, to switch on or off the electrical connection between the second terminal of the driving subcircuit and the light-emitting element;

[0017] The third reset subcircuit is coupled to the first control terminal, the light-emitting element and the initialization signal output terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal under the control of the first control terminal.

[0018] Optionally, the pixel driving circuit further includes:

[0019] a second light-emitting control subcircuit, wherein the second end of the driver subcircuit is coupled to the light-emitting element via the second light-emitting control subcircuit; the second light-emitting control subcircuit is coupled to the light-emitting control end, the second end of the driver subcircuit, and the light-emitting element, respectively; and is configured to control the electrical connection between the second end of the driver subcircuit and the light-emitting element to be turned on or off under the control of the light-emitting control end;

[0020] The fourth reset subcircuit is coupled to the write control terminal, the light emitting element and the initialization signal output terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the light emitting element and the initialization signal output terminal under the control of the write control terminal.

[0021] Optionally, the data writing subcircuit includes a first transistor, the compensation subcircuit includes a second transistor, the driving subcircuit includes a third transistor, the first reset subcircuit includes a fourth transistor, the second reset subcircuit includes a fifth transistor, the first light emission control subcircuit includes a sixth transistor, the first coupling subcircuit includes a first capacitor, and the second coupling subcircuit includes a second capacitor;

[0022] The gate of the first transistor is coupled to the write control terminal, the first electrode of the first transistor is coupled to the data signal input terminal, and the second electrode of the first transistor is coupled to the second terminal of the second capacitor;

[0023] The gate of the second transistor is coupled to the first control terminal, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the gate of the third transistor;

[0024] The first electrode of the third transistor is coupled to the first level signal output terminal;

[0025] The gate of the fourth transistor is coupled to the second control terminal, the first electrode of the fourth transistor is coupled to the initialization signal output terminal, and the second electrode of the fourth transistor is coupled to the gate of the third transistor;

[0026] The gate of the fifth transistor is coupled to the third control terminal, the first electrode of the fifth transistor is coupled to the first level signal output terminal, and the second electrode of the fifth transistor is coupled to the second terminal of the first capacitor;

[0027] The gate of the sixth transistor is coupled to the light emitting control terminal, the first electrode of the sixth transistor is coupled to the reference signal output terminal, and the second electrode of the sixth transistor is coupled to the second terminal of the second capacitor;

[0028] A first terminal of the first capacitor is coupled to the gate of the third transistor;

[0029] The first end of the second capacitor is coupled to the second end of the first capacitor.

[0030] Optionally, the first transistor, the third transistor and the sixth transistor all include P-type low-temperature polysilicon transistors, and the second transistor, the fourth transistor and the fifth transistor all include N-type oxide transistors.

[0031] Optionally, the second light-emitting control subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the light-emitting control terminal, a first electrode of the seventh transistor is coupled to the second terminal of the driving subcircuit, and a second electrode of the seventh transistor is coupled to the light-emitting element;

[0032] The third reset sub-circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the first control terminal, a first electrode of the eighth transistor is coupled to the initialization signal output terminal, and a second electrode of the eighth transistor is coupled to the light-emitting element.

[0033] Optionally, the second light-emitting control subcircuit includes a seventh transistor, a gate of the seventh transistor is coupled to the light-emitting control terminal, a first electrode of the seventh transistor is coupled to the second terminal of the driving subcircuit, and a second electrode of the seventh transistor is coupled to the light-emitting element;

[0034] The fourth reset sub-circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the write control terminal, a first electrode of the ninth transistor is coupled to the initialization signal output terminal, and a second electrode of the ninth transistor is coupled to the light-emitting element.

[0035] Based on the technical solution of the above pixel driving circuit, the second aspect of the present disclosure provides a driving method of the pixel driving circuit, which is used to drive the above pixel driving circuit. The driving method includes: in each display cycle,

[0036] During the reset period, under the control of the second control terminal, the first reset subcircuit controls the electrical connection between the control terminal of the drive subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit controls the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; and under the control of the write control terminal, the data write subcircuit controls the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal.

[0037] During the compensation period, under the control of the second control terminal, the first reset subcircuit controls the disconnection of the electrical connection between the control terminal of the driver subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit continues to control the disconnection of the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; under the control of the write control terminal, the data write subcircuit controls the disconnection of the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal; under the control of the first control terminal, the compensation subcircuit controls the disconnection of the electrical connection between the control terminal of the driver subcircuit and the second terminal of the driver subcircuit; the driver subcircuit connects the electrical connection between the first level signal output terminal and the compensation subcircuit until the threshold voltage of the driver subcircuit is written to the control terminal of the driver subcircuit;

[0038] During the light-emitting period, under the control of the second control terminal, the first reset subcircuit controls the disconnection of the electrical connection between the control terminal of the driving subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit controls the disconnection of the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; under the control of the write control terminal, the data write subcircuit controls the disconnection of the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal; under the control of the first control terminal, the compensation subcircuit controls the disconnection of the electrical connection between the control terminal of the driving subcircuit and the second terminal of the driving subcircuit; under the control of the light-emitting control terminal, the first light-emitting control subcircuit controls the connection of the electrical connection between the second terminal of the second coupling subcircuit and the reference signal output terminal; the driving subcircuit connects the electrical connection between the first level signal output terminal and the light-emitting element, and transmits the generated driving signal to the light-emitting element.

[0039] Optionally, when the pixel driving circuit further includes a second light emitting control subcircuit and a third reset subcircuit, the driving method further includes:

[0040] During the reset period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the first control terminal, the third reset subcircuit controls to disconnect the electrical connection between the light-emitting element and the initialization signal output terminal.

[0041] During the compensation period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the first control terminal, the third reset subcircuit controls to connect the electrical connection between the light-emitting element and the initialization signal output terminal.

[0042] During the light-emitting period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element; under the control of the first control terminal, the third reset subcircuit controls the disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal.

[0043] Optionally, when the pixel driving circuit further includes a second light emitting control subcircuit and a fourth reset subcircuit, the driving method further includes:

[0044] During the reset period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the write control terminal, the fourth reset subcircuit controls to connect the electrical connection between the light-emitting element and the initialization signal output terminal.

[0045] During the compensation period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the write control terminal, the fourth reset subcircuit controls to disconnect the electrical connection between the light-emitting element and the initialization signal output terminal.

[0046] During the light-emitting period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element; under the control of the write control terminal, the fourth reset subcircuit controls the disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal.

[0047] Based on the technical solution of the above pixel driving circuit, a third aspect of the present disclosure provides a display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels include the above pixel driving circuit, and the sub-pixels further include:

[0048] a power line pattern, at least a portion of which extends along a first direction, and the power line pattern is multiplexed as a first level signal output terminal;

[0049] a data line pattern, at least a portion of which extends along the first direction, and the data line pattern is multiplexed as a data signal input terminal;

[0050] a reference signal line pattern, at least a portion of which extends along the first direction, and the reference signal line pattern is multiplexed as a reference signal output terminal; the data line pattern is located between the power line pattern and the reference signal line pattern;

[0051] a first control signal line pattern, at least a portion of the first control signal line pattern extending along a second direction, the second direction intersecting the first direction, the first control signal line pattern being multiplexed as a first control terminal coupled to a compensation subcircuit in a pixel driving circuit;

[0052] a second control signal line pattern, at least a portion of the second control signal line pattern extending along the second direction, the second control signal line pattern being multiplexed as a second control end;

[0053] a third control signal line pattern, at least a portion of the third control signal line pattern extending along the second direction, the third control signal line pattern being multiplexed as a third control end;

[0054] an initialization signal line pattern, at least a portion of which extends along the second direction, and the initialization signal line pattern is multiplexed as an initialization signal output terminal;

[0055] a light-emitting control signal line pattern, at least a portion of which extends along the second direction, and the light-emitting control signal line pattern is multiplexed as a light-emitting control terminal;

[0056] A data writing control line pattern, at least a portion of which extends along the second direction, and the data writing control line pattern is multiplexed as a writing control terminal.

[0057] Optionally, the data writing subcircuit in the pixel driving circuit includes a first transistor, the compensation subcircuit includes a second transistor, the driving subcircuit includes a third transistor, the first reset subcircuit includes a fourth transistor, the second reset subcircuit includes a fifth transistor, the first light emitting control subcircuit includes a sixth transistor, the first coupling subcircuit includes a first capacitor, and the second coupling subcircuit includes a second capacitor;

[0058] The first capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, and the first electrode plate is located between the second electrode plate and the substrate;

[0059] The second transistor, the fourth transistor, and the fifth transistor each include an N-type oxide transistor, the second transistor includes a second active pattern, the fourth transistor includes a fourth active pattern, and the fifth transistor includes a fifth active pattern;

[0060] The second active pattern, the fourth active pattern and the fifth active pattern are provided in the same layer and the same material. The fourth active pattern is located between the second control signal line and the substrate. The fourth active pattern is located on a side of the second electrode away from the substrate.

[0061] Optionally, the second active pattern extends along the second direction, the fourth active pattern extends along the first direction, the second active pattern and the fourth active pattern form an integral structure, and the orthographic projection of the second active pattern on the substrate is located between the orthographic projection of the first control signal line pattern on the substrate and the orthographic projection of the second control signal line pattern on the substrate.

[0062] Optionally, the fifth active pattern extends along the second direction, and the orthographic projection of the fifth active pattern on the substrate is located between the orthographic projection of the third control signal line pattern on the substrate and the orthographic projection of the second electrode plate on the substrate.

[0063] Optionally, when the pixel driving circuit further includes a second light-emitting control subcircuit and a third reset subcircuit, the third reset subcircuit includes an eighth transistor, the eighth transistor includes an eighth active pattern, the eighth active pattern extends along the second direction, and the eighth active pattern is arranged in the same layer and material as the second active pattern.

[0064] Optionally, the third control signal line pattern is also multiplexed as a first control terminal coupled to a third reset sub-circuit included in a pixel driving circuit in an adjacent sub-pixel along the first direction; the gate of the eighth transistor is coupled to the third control signal line pattern in the adjacent sub-pixel along the first direction; and the positive projection of the eighth active pattern on the substrate is located between the positive projection of the initialization signal line pattern on the substrate and the positive projection of the third control signal line pattern in the adjacent sub-pixel along the first direction on the substrate.

[0065] Optionally, in the case where the pixel driving circuit further includes a second light-emitting control subcircuit and a fourth reset subcircuit, the second light-emitting control subcircuit includes a seventh transistor, the seventh transistor includes a seventh active pattern, the fourth reset subcircuit includes a ninth transistor, the ninth transistor includes a ninth active pattern, the seventh active pattern and the ninth active pattern both extend along the first direction, and the seventh active pattern and the ninth active pattern form an integral structure.

[0066] Optionally, the orthographic projection of the ninth active pattern on the substrate is located between the orthographic projection of the light emitting control signal line pattern on the substrate and the orthographic projection of the initialization signal line pattern on the substrate.

[0067] Optionally, the plurality of sub-pixels are divided into a plurality of sub-pixel rows arranged along the first direction, and each sub-pixel row includes a plurality of sub-pixels arranged along the second direction;

[0068] The display substrate further includes a plurality of first compensation lines corresponding to at least some sub-pixel rows one by one, and the first compensation lines are respectively coupled to reference signal line patterns included in each sub-pixel in the corresponding sub-pixel row.

[0069] Based on the technical solution of the above-mentioned display substrate, a fourth aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0071] Figure 1 A first basic structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0072] Figure 2 A schematic diagram of a first specific structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0073] Figure 3 This is a working timing diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0074] Figure 4 A first schematic layout diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0075] Figure 5 for Figure 4 Schematic diagram of the layout of the first active layer;

[0076] Figure 6 for Figure 4 Schematic diagram of the layout of the first gate metal layer;

[0077] Figure 7 for Figure 4 Schematic diagram of the layout of the second gate metal layer;

[0078] Figure 8 for Figure 4 Schematic diagram of the layout of the second active layer;

[0079] Figure 9 for Figure 4 Schematic diagram of the layout of the third gate metal layer;

[0080] Figure 10 for Figure 4 Schematic diagram of the layout of the source and drain metal layers;

[0081] Figure 11 A second basic structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0082] Figure 12 A second specific structural diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0083] Figure 13 A second schematic layout diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0084] Figure 14 for Figure 13 Schematic diagram of the layout of the first active layer;

[0085] Figure 15 for Figure 13 Schematic diagram of the layout of the first gate metal layer;

[0086] Figure 16 for Figure 13 Schematic diagram of the layout of the second gate metal layer;

[0087] Figure 17 for Figure 13 Schematic diagram of the layout of the second active layer;

[0088] Figure 18 for Figure 13 Schematic diagram of the layout of the third gate metal layer;

[0089] Figure 19 for Figure 13 Schematic diagram of the layout of the source and drain metal layers;

[0090] Figure 20 This is a schematic cross-sectional view of each film layer in the display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] In order to further illustrate the pixel driving circuit and driving method thereof, the display substrate, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0092] As display demand gradually increases, the high and low frequency display of display devices has become a hot topic. How to effectively make display devices compatible with high and low frequency display to meet people's demand for high refresh rate and low power consumption has become an urgent problem to be solved.

[0093] See also Figure 1 and Figure 11 The embodiment of the present disclosure provides a pixel driving circuit for driving a light emitting element EL, the pixel driving circuit comprising:

[0094] a driving sub-circuit, wherein a first terminal of the driving sub-circuit is coupled to the first level signal output terminal VDD, and a second terminal of the driving sub-circuit is coupled to the light-emitting element EL; the driving sub-circuit includes a third active pattern;

[0095] a compensation sub-circuit, coupled to the first control terminal AZn, the control terminal of the driving sub-circuit, and the second terminal of the driving sub-circuit, respectively; the compensation sub-circuit includes a second active pattern;

[0096] a first coupling subcircuit, wherein a first terminal of the first coupling subcircuit is coupled to a control terminal of the driving subcircuit;

[0097] a second coupling subcircuit, wherein a first end of the second coupling subcircuit is coupled to a second end of the first coupling subcircuit;

[0098] a first reset sub-circuit, coupled to the second control terminal SnB, the control terminal of the driving sub-circuit, and the initialization signal output terminal Init; the first reset sub-circuit includes a fourth active pattern;

[0099] a second reset subcircuit, coupled to the third control terminal AZn-1, the second terminal of the first coupling subcircuit, and the first level signal output terminal VDD, respectively; and configured to, under the control of the third control terminal AZn-1, control the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal VDD to be opened or closed; the second reset subcircuit includes a fifth active pattern;

[0100] a first light-emitting control subcircuit, coupled to the light-emitting control terminal EM, the second terminal of the second coupling subcircuit, and the reference signal output terminal Ref, respectively; and configured to, under the control of the light-emitting control terminal EM, control the electrical connection between the second terminal of the second coupling subcircuit and the reference signal output terminal Ref to be turned on or off;

[0101] The data writing subcircuit is coupled to the writing control terminal Sn, the second terminal of the second coupling subcircuit and the data signal input terminal DA. The second active pattern, the fourth active pattern and the fifth active pattern are all arranged in different layers from the third active pattern.

[0102] Exemplarily, the first-level signal outputted by the first-level signal output terminal VDD includes a positive power signal.

[0103] Exemplarily, the anode of the light-emitting element EL is coupled to the second end of the driving sub-circuit, the cathode of the light-emitting element EL is coupled to the second level signal output end VSS, and the second level signal output by the second level signal output end includes a negative power supply signal.

[0104] Exemplarily, the first end of the driving subcircuit is an input end, and the second end of the driving subcircuit is an output end. The driving subcircuit can generate a driving signal and transmit the driving signal to the light-emitting element EL to drive the light-emitting element EL to emit light.

[0105] Exemplarily, the first control terminal AZn outputs a first control signal, and under the control of the first control signal, the compensation sub-circuit controls the conduction or disconnection of the electrical connection between the control terminal of the driving sub-circuit and the second terminal of the driving sub-circuit.

[0106] Exemplarily, the second control terminal SnB outputs a second control signal, and the initialization signal output terminal Init outputs an initialization signal; under the control of the second control signal, the first reset sub-circuit controls the conduction or disconnection of the electrical connection between the control terminal of the driving sub-circuit and the initialization signal output terminal Init to control whether the initialization signal is transmitted to the control terminal of the driving sub-circuit.

[0107] Exemplarily, the third control terminal AZn-1 outputs a third control signal. Under the control of the third control signal, the second reset sub-circuit controls whether to turn on or off the electrical connection between the second end of the first coupling sub-circuit and the first level signal output terminal VDD to control whether to transmit the first level signal to the second end of the first coupling sub-circuit.

[0108] Exemplarily, the light-emitting control terminal EM outputs a light-emitting control signal, and the reference signal output terminal Ref outputs a reference signal; under the control of the light-emitting control signal, the first light-emitting control sub-circuit controls the conduction or disconnection of the electrical connection between the second end of the second coupling sub-circuit and the reference signal output terminal Ref to control whether the reference signal is transmitted to the second end of the second coupling sub-circuit.

[0109] Exemplarily, the write control terminal Sn inputs a write control signal, and the data signal input terminal DA inputs a data signal; under the control of the write control signal, the data write sub-circuit controls the conduction or disconnection of the electrical connection between the second end of the second coupling sub-circuit and the data signal input terminal DA to control whether the data signal is transmitted to the second end of the second coupling sub-circuit.

[0110] like Figure 3 As shown, the specific working process of the above pixel driving circuit in each display cycle includes:

[0111] During reset period P1, under the control of the second control signal output from the second control terminal SnB, the first reset sub-circuit controls the electrical connection between the control terminal of the driver sub-circuit and the initialization signal output terminal Init, transmits the initialization signal to the control terminal N1 of the driver sub-circuit, and resets the potential of the control terminal N1 of the driver sub-circuit to the potential Vinit of the initialization signal. Under the control of the third control signal output from the third control terminal AZn-1, the second reset sub-circuit controls the electrical connection between the second terminal N2 of the first coupling sub-circuit and the first level signal output terminal VDD, transmits the first level signal to the second terminal N2 of the first coupling sub-circuit, and resets the potential of the second terminal N2 of the first coupling sub-circuit to the potential Vdd of the first level signal. Under the control of the write control signal output from the write control terminal Sn, the data write sub-circuit controls the electrical connection between the second terminal N3 of the second coupling sub-circuit and the data signal input terminal DA, transmits the data signal to the second terminal N3 of the second coupling sub-circuit, and changes the potential of the second terminal N3 of the second coupling sub-circuit to the potential Vdata of the data signal.

[0112] During compensation period P2, under the control of a second control signal output from the second control terminal SnB, the first reset sub-circuit controls the disconnection between the control terminal of the driver sub-circuit and the initialization signal output terminal Init. Under the control of a third control signal output from the third control terminal AZn-1, the second reset sub-circuit continues to control the disconnection between the second terminal of the first coupling sub-circuit and the first level signal output terminal VDD, maintaining the potential of the second terminal N2 of the first coupling sub-circuit at Vdd. Under the control of a write control signal output from the write control terminal Sn, the data write sub-circuit controls the disconnection between the second terminal of the second coupling sub-circuit and the data signal input terminal DA. Under the control of a first control signal output from the first control terminal AZn, the compensation sub-circuit controls the disconnection between the control terminal of the driver sub-circuit and the second terminal of the driver sub-circuit. The driver sub-circuit connects the first level signal output terminal VDD to the compensation sub-circuit until the threshold voltage of the driver sub-circuit is written to the control terminal of the driver sub-circuit, causing the potential of the control terminal N1 of the driver sub-circuit to reach Vdd-|Vth_T3|, where Vth_T3 is the threshold voltage corresponding to the driver sub-circuit.

[0113] During the light-emitting period P3, under the control of the second control signal output from the second control terminal SnB, the first reset sub-circuit controls the disconnection of the electrical connection between the control terminal of the driving sub-circuit and the initialization signal output terminal Init; under the control of the third control signal output from the third control terminal AZn-1, the second reset sub-circuit controls the disconnection of the electrical connection between the second terminal of the first coupling sub-circuit and the first level signal output terminal VDD; under the control of the write control signal output from the write control terminal Sn, the data write sub-circuit controls the disconnection of the electrical connection between the second terminal of the second coupling sub-circuit and the data signal input terminal DA; under the control of the first control signal output from the first control terminal AZn, the compensation sub-circuit controls the disconnection of the control terminal of the driving sub-circuit and the second terminal of the driving sub-circuit an electrical connection between the first and second coupling subcircuits; under the control of the light-emitting control signal outputted from the light-emitting control terminal EM, the first light-emitting control subcircuit controls the electrical connection between the second terminal of the second coupling subcircuit and the reference signal output terminal Ref, so that the potential of the second terminal N3 of the second coupling subcircuit changes from Vdata to the potential Vref of the reference signal; since the control terminal N1 of the driving subcircuit is in a suspended state during the light-emitting period P3, the potential of N1 will also have a voltage change of Vref-Vdata, so that the potential of N1 becomes Vdd-|Vth_T3|+Vref-Vdata; the driving subcircuit conducts the electrical connection between the first level signal output terminal VDD and the light-emitting element EL, and transmits the generated driving signal to the light-emitting element EL.

[0114] The generated driving signal includes a current signal, which is:

[0115] Ioled=β*(Vgs-Vth_T3) 2 =β*(Vref-Vdata) 2

[0116] β represents a constant, and Vgs represents the gate-source voltage corresponding to the driving sub-circuit.

[0117] It can be seen that the driving voltage generated by the above pixel driving circuit has nothing to do with the threshold voltage corresponding to the driving sub-circuit.

[0118] According to the specific structure and working process of the above-mentioned pixel driving circuit, in the pixel driving circuit provided by the embodiment of the present disclosure, the pulse widths of the first control signal output by the first control terminal AZn and the third control signal output by the third control terminal AZn-1 are both adjustable. Therefore, the threshold voltage compensation time can be adjusted by adjusting the pulse widths of the first control signal and the third control signal, thereby reducing the problem of mura caused by the short compensation time under high-frequency conditions. Moreover, through the compensation sub-circuit, the first reset sub-circuit, and the second reset sub-circuit, the potentials of the control terminal N1 of the driving sub-circuit and the second terminal N2 of the first coupling sub-circuit can be controlled to be well maintained during the light-emitting period P3 under low-frequency conditions. Therefore, when the pixel driving circuit provided by the embodiment of the present disclosure is applied to a display device, the display device can effectively be compatible with high-frequency display and low-frequency display, meeting people's needs for high refresh rate and low power consumption.

[0119] It should be noted that when the pixel driving circuit provided by the embodiment of the present disclosure is applied to a display device, the pixel driving circuit provided by the embodiment of the present disclosure can support the display device to achieve a refresh rate display of 1 Hz to 120 Hz.

[0120] like Figure 1 As shown, in some embodiments, the pixel driving circuit further includes:

[0121] a second light-emitting control subcircuit, wherein the second terminal of the driver subcircuit is coupled to the light-emitting element EL via the second light-emitting control subcircuit; the second light-emitting control subcircuit is respectively coupled to the light-emitting control terminal EM, the second terminal of the driver subcircuit, and the light-emitting element EL; and is configured to control the electrical connection between the second terminal of the driver subcircuit and the light-emitting element EL to be turned on or off under the control of the light-emitting control terminal EM;

[0122] The third reset sub-circuit is coupled to the first control terminal AZn, the light-emitting element EL and the initialization signal output terminal Init respectively; and is used to control the conduction or disconnection of the electrical connection between the light-emitting element EL and the initialization signal output terminal Init under the control of the first control terminal AZn.

[0123] Illustratively, under the control of the light-emitting control signal output by the light-emitting control terminal EM, the second light-emitting control sub-circuit controls the conduction or disconnection of the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL to control whether the driving signal generated by the driving sub-circuit is transmitted to the light-emitting element EL.

[0124] Illustratively, under the control of the first control signal output from the first control terminal AZn, the third reset subcircuit controls the conduction or disconnection of the electrical connection between the light-emitting element EL and the initialization signal output terminal Init to control whether the initialization signal is transmitted to the anode of the light-emitting element EL.

[0125] The driving method further includes:

[0126] In the reset period P1, under the control of the light-emitting control signal, the second light-emitting control subcircuit controls the disconnection of the electrical connection between the second end of the driving subcircuit and the light-emitting element EL; under the control of the first control signal, the third reset subcircuit controls the disconnection of the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0127] During the compensation period P2, under the control of the light-emitting control signal, the second light-emitting control subcircuit controls the disconnection of the electrical connection between the second end of the driving subcircuit and the light-emitting element EL; under the control of the first control signal, the third reset subcircuit controls the connection of the electrical connection between the light-emitting element EL and the initialization signal output terminal Init, thereby resetting the potential of the anode N5 of the light-emitting element EL to Vinit.

[0128] During the light-emitting period P3, under the control of the light-emitting control signal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element EL; under the control of the first control signal, the third reset subcircuit controls the electrical connection between the light-emitting element EL and the initialization signal output terminal Init to be disconnected.

[0129] In the pixel driver circuit provided in the above embodiment, the provision of the second light-emission control subcircuit and the third reset subcircuit prevents abnormal light emission from the light-emitting element EL, thereby ensuring the display quality of the display device. Furthermore, coupling both the third reset subcircuit and the compensation subcircuit to the first control terminal AZn effectively simplifies the structure of the gate driver circuit GOA in the display device.

[0130] like Figure 11 As shown, in some embodiments, the pixel driving circuit further includes:

[0131] a second light-emitting control subcircuit, wherein the second terminal of the driver subcircuit is coupled to the light-emitting element EL via the second light-emitting control subcircuit; the second light-emitting control subcircuit is respectively coupled to the light-emitting control terminal EM, the second terminal of the driver subcircuit, and the light-emitting element EL; and is configured to control the electrical connection between the second terminal of the driver subcircuit and the light-emitting element EL to be turned on or off under the control of the light-emitting control terminal EM;

[0132] The fourth reset subcircuit is coupled to the write control terminal Sn, the light emitting element EL and the initialization signal output terminal Init respectively; and is used to control the conduction or disconnection of the electrical connection between the light emitting element EL and the initialization signal output terminal Init under the control of the write control terminal Sn.

[0133] Illustratively, under the control of the light-emitting control signal output by the light-emitting control terminal EM, the second light-emitting control sub-circuit controls the conduction or disconnection of the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL to control whether the driving signal generated by the driving sub-circuit is transmitted to the light-emitting element EL.

[0134] Illustratively, under the control of the write control signal output from the write control terminal Sn, the fourth reset subcircuit controls the conduction or disconnection of the electrical connection between the light-emitting element EL and the initialization signal output terminal Init to control whether the initialization signal is transmitted to the anode of the light-emitting element EL.

[0135] The driving method further includes:

[0136] During the reset period P1, under the control of the light-emitting control signal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element EL; and under the control of the write control signal, the fourth reset subcircuit controls to connect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init, thereby resetting the potential of the anode N5 of the light-emitting element EL to Vinit.

[0137] During the compensation period P2, under the control of the light-emission control signal, the second light-emission control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element EL; and under the control of the write control signal, the fourth reset subcircuit controls to disconnect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0138] During the light-emitting period P3, under the control of the light-emitting control signal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element EL; under the control of the write control signal, the fourth reset subcircuit controls the electrical connection between the light-emitting element EL and the initialization signal output terminal Init to be disconnected.

[0139] In the pixel driver circuit provided in the above embodiment, the provision of a second light-emission control subcircuit and a third reset subcircuit prevents abnormal light emission from the light-emitting element EL, thereby ensuring the display quality of the display device. Furthermore, the provision of a fourth reset subcircuit and a data write subcircuit, both coupled to the write control terminal Sn, effectively simplifies the structure of the gate driver circuit GOA in the display device and reduces the layout space occupied by the pixel driver circuit.

[0140] like Figure 2 and Figure 12 As shown, in some embodiments, the data writing subcircuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2, the driving subcircuit includes a third transistor T3, the first reset subcircuit includes a fourth transistor T4, the second reset subcircuit includes a fifth transistor T5, the first light emitting control subcircuit includes a sixth transistor T6, the first coupling subcircuit includes a first capacitor C1, and the second coupling subcircuit includes a second capacitor C2;

[0141] The gate of the first transistor T1 is coupled to the write control terminal Sn, the first electrode of the first transistor T1 is coupled to the data signal input terminal DA, and the second electrode of the first transistor T1 is coupled to the second end of the second capacitor C2;

[0142] The gate of the second transistor T2 is coupled to the first control terminal AZn, the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3;

[0143] The first electrode of the third transistor T3 is coupled to the first level signal output terminal VDD;

[0144] The gate of the fourth transistor T4 is coupled to the second control terminal SnB, the first electrode of the fourth transistor T4 is coupled to the initialization signal output terminal Init, and the second electrode of the fourth transistor T4 is coupled to the gate of the third transistor T3;

[0145] The gate of the fifth transistor T5 is coupled to the third control terminal AZn-1, the first electrode of the fifth transistor T5 is coupled to the first level signal output terminal VDD, and the second electrode of the fifth transistor T5 is coupled to the second end of the first capacitor C1;

[0146] The gate of the sixth transistor T6 is coupled to the light emitting control terminal EM, the first electrode of the sixth transistor T6 is coupled to the reference signal output terminal Ref, and the second electrode of the sixth transistor T6 is coupled to the second end of the second capacitor C2;

[0147] A first terminal of the first capacitor C1 is coupled to the gate of the third transistor T3;

[0148] A first end of the second capacitor C2 is coupled to a second end of the first capacitor C1 .

[0149] like Figure 2 and Figure 12 As shown, in some embodiments, the first transistor T1, the third transistor T3 and the sixth transistor T6 all include P-type low-temperature polysilicon transistors, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 all include N-type oxide transistors.

[0150] like Figure 3 As shown, when the pixel driving circuit adopts the above structure, the specific working process of the pixel driving circuit is as follows:

[0151] In the reset period P1, the light emitting control signal is high, the write control signal is low, the second control signal is high, the third control signal is high, and the first control signal is low; the first transistor T1 is turned on, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned on.

[0152] During the compensation period P2, the light emitting control signal is at a high level, the write control signal is at a high level, the second control signal is at a low level, the third control signal is at a high level, and the first control signal is at a high level; the second transistor T2 is turned on, the third transistor T3 is turned on, and the fifth transistor T5 is turned on.

[0153] In the light emitting period P3 , the light emitting control signal is at a low level, the write control signal is at a high level, the second control signal is at a low level, the third control signal is at a low level, and the first control signal is at a low level; the sixth transistor T6 is turned on.

[0154] like Figure 1 and Figure 2 As shown, in some embodiments, the second light emitting control sub-circuit includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the light emitting control terminal EM, a first electrode of the seventh transistor T7 is coupled to the second terminal of the driving sub-circuit, and a second electrode of the seventh transistor T7 is coupled to the light emitting element EL;

[0155] The third reset sub-circuit includes an eighth transistor T8, a gate of the eighth transistor T8 is coupled to the first control terminal AZn, a first electrode of the eighth transistor T8 is coupled to the initialization signal output terminal Init, and a second electrode of the eighth transistor T8 is coupled to the light emitting element EL.

[0156] Exemplarily, the seventh transistor T7 includes a P-type low-temperature polysilicon transistor, and the eighth transistor T8 includes an N-type oxide transistor.

[0157] During the reset period P1 , both the seventh transistor T7 and the eighth transistor T8 are turned off.

[0158] During the compensation period P2 , the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on.

[0159] During the light emitting period P3 , the seventh transistor T7 is turned on and the eighth transistor T8 is turned off.

[0160] The pixel driving circuit provided in the above embodiment adopts an 8T2C (i.e., eight transistors and two capacitors) structure. When the pixel driving circuit is applied to a display device, the display device is well compatible with high-frequency drive display and low-frequency drive display. Moreover, by setting the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 to use N-type oxide thin-film transistors with low leakage current, the leakage of key nodes (such as N1, N2, and N5) in the pixel circuit is effectively reduced, ensuring the maintenance of the potential of the key nodes during low-frequency display; at the same time, setting the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 to be P-type low-temperature polysilicon thin-film transistors, ensuring the driving current for pixel driving circuit compensation and data writing, and well realizing data writing and threshold voltage compensation at high refresh rates.

[0161] In addition, by setting the eighth transistor T8 to be an N-type oxide thin film transistor, the node N5 can be discharged quickly, thereby improving the contrast of the display device.

[0162] like Figure 11 and Figure 12 As shown, in some embodiments, the second light emitting control sub-circuit includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the light emitting control terminal EM, a first electrode of the seventh transistor T7 is coupled to the second terminal of the driving sub-circuit, and a second electrode of the seventh transistor T7 is coupled to the light emitting element EL;

[0163] The fourth reset sub-circuit includes a ninth transistor T9, a gate of the ninth transistor T9 is coupled to the write control terminal Sn, a first electrode of the ninth transistor T9 is coupled to the initialization signal output terminal Init, and a second electrode of the ninth transistor T9 is coupled to the light emitting element EL.

[0164] Exemplarily, the seventh transistor T7 and the ninth transistor T9 both include P-type low-temperature polysilicon transistors.

[0165] During the reset period P1 , the seventh transistor T7 is turned off, and the ninth transistor T9 is turned on.

[0166] During the compensation period P2 , the seventh transistor T7 and the ninth transistor T9 are turned off.

[0167] During the light emitting period P3 , the seventh transistor T7 is turned on and the ninth transistor T9 is turned off.

[0168] The pixel driving circuit provided in the above embodiment adopts an 8T2C structure. When the pixel driving circuit is applied to a display device, the display device is well compatible with high-frequency drive display and low-frequency drive display. Moreover, by setting the second transistor T2, the fourth transistor T4, and the fifth transistor T5 to use N-type oxide thin-film transistors with low leakage current, the leakage of key nodes (such as N1 and N2) in the pixel circuit is effectively reduced, ensuring that the potential of the key nodes is maintained during low-frequency display; at the same time, setting the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 to be P-type low-temperature polysilicon thin-film transistors, ensures the driving current for pixel driving circuit compensation and data writing, and well realizes data writing and threshold voltage compensation at high refresh rates.

[0169] like Figure 1 、 Figure 3 and Figure 11 As shown, the embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is used to drive the pixel driving circuit provided by the above embodiment. The driving method includes: in each display cycle,

[0170] During the reset period P1, under the control of the second control terminal SnB, the first reset sub-circuit controls the electrical connection between the control terminal of the drive sub-circuit and the initialization signal output terminal Init. Under the control of the third control terminal AZn-1, the second reset sub-circuit controls the electrical connection between the second terminal of the first coupling sub-circuit and the first level signal output terminal VDD. Under the control of the write control terminal Sn, the data write sub-circuit controls the electrical connection between the second terminal of the second coupling sub-circuit and the data signal input terminal DA.

[0171] During compensation period P2, under the control of the second control terminal SnB, the first reset sub-circuit controls the disconnection of the electrical connection between the control terminal of the driver sub-circuit and the initialization signal output terminal Init. Under the control of the third control terminal AZn-1, the second reset sub-circuit continues to control the disconnection of the electrical connection between the second terminal of the first coupling sub-circuit and the first level signal output terminal VDD. Under the control of the write control terminal Sn, the data write sub-circuit controls the disconnection of the electrical connection between the second terminal of the second coupling sub-circuit and the data signal input terminal DA. Under the control of the first control terminal AZn, the compensation sub-circuit controls the disconnection of the electrical connection between the control terminal of the driver sub-circuit and the second terminal of the driver sub-circuit. The driver sub-circuit connects the electrical connection between the first level signal output terminal VDD and the compensation sub-circuit until the threshold voltage of the driver sub-circuit is written to the control terminal of the driver sub-circuit.

[0172] During the light-emitting period P3, under the control of the second control terminal SnB, the first reset sub-circuit controls the disconnection of the electrical connection between the control terminal of the driving sub-circuit and the initialization signal output terminal Init; under the control of the third control terminal AZn-1, the second reset sub-circuit controls the disconnection of the electrical connection between the second terminal of the first coupling sub-circuit and the first level signal output terminal VDD; under the control of the write control terminal Sn, the data write sub-circuit controls the disconnection of the electrical connection between the second terminal of the second coupling sub-circuit and the data signal input terminal DA; under the control of the first control terminal AZn, the compensation sub-circuit controls the disconnection of the electrical connection between the control terminal of the driving sub-circuit and the second terminal of the driving sub-circuit; under the control of the light-emitting control terminal EM, the first light-emitting control sub-circuit controls the connection of the electrical connection between the second terminal of the second coupling sub-circuit and the reference signal output terminal Ref; the driving sub-circuit connects the electrical connection between the first level signal output terminal VDD and the light-emitting element EL, and transmits the generated drive signal to the light-emitting element EL.

[0173] When the pixel driving circuit is driven using the driving method provided by the embodiment of the present disclosure, the pulse widths of the first control signal output by the first control terminal AZn and the third control signal output by the third control terminal AZn-1 are both adjustable. Therefore, by adjusting the pulse widths of the first control signal and the third control signal, the threshold voltage compensation time can be adjusted, thereby reducing the problem of mura caused by the short compensation time under high-frequency conditions. Moreover, through the compensation sub-circuit, the first reset sub-circuit, and the second reset sub-circuit, the potentials of the control terminal N1 of the driving sub-circuit and the second terminal N2 of the first coupling sub-circuit can be well maintained during the light-emitting period P3 under low-frequency conditions. Therefore, when the pixel driving circuit is applied to a display device, the display device can effectively be compatible with high-frequency display and low-frequency display, meeting people's needs for high refresh rate and low power consumption.

[0174] like Figure 1 and Figure 3 As shown, in some embodiments, when the pixel driving circuit further includes a second light emitting control subcircuit and a third reset subcircuit, the driving method further includes:

[0175] During the reset period P1, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls to disconnect the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL; and under the control of the first control terminal AZn, the third reset sub-circuit controls to disconnect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0176] During the compensation period P2, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls to disconnect the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL; and under the control of the first control terminal AZn, the third reset sub-circuit controls to connect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0177] During the light-emitting period P3, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls the electrical connection between the second end of the driving sub-circuit and the light-emitting element EL; under the control of the first control terminal AZn, the third reset sub-circuit controls the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0178] like Figure 3 and Figure 11 As shown, in some embodiments, when the pixel driving circuit further includes a second light emitting control subcircuit and a fourth reset subcircuit, the driving method further includes:

[0179] During the reset period P1, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls to disconnect the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL; and under the control of the write control terminal Sn, the fourth reset sub-circuit controls to connect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0180] During the compensation period P2, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls to disconnect the electrical connection between the second terminal of the driving sub-circuit and the light-emitting element EL; and under the control of the write control terminal Sn, the fourth reset sub-circuit controls to disconnect the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0181] During the light-emitting period P3, under the control of the light-emitting control terminal EM, the second light-emitting control sub-circuit controls the electrical connection between the second end of the driving sub-circuit and the light-emitting element EL; under the control of the write control terminal Sn, the fourth reset sub-circuit controls the electrical connection between the light-emitting element EL and the initialization signal output terminal Init.

[0182] like Figure 4 and Figure 13 As shown, an embodiment of the present disclosure further provides a display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels include the pixel driving circuit provided in the above embodiment, and the sub-pixels further include:

[0183] a power line pattern, at least a portion of which extends along a first direction, and the power line pattern is multiplexed as a first level signal output terminal VDD;

[0184] a data line pattern, at least a portion of which extends along the first direction, and the data line pattern is multiplexed as a data signal input terminal DA;

[0185] a reference signal line pattern, at least a portion of which extends along the first direction, and the reference signal line pattern is multiplexed as a reference signal output terminal Ref; the data line pattern is located between the power line pattern and the reference signal line pattern;

[0186] a first control signal line pattern, at least a portion of which extends along a second direction intersecting the first direction, and the first control signal line pattern being multiplexed as a first control terminal AZn coupled to a compensation subcircuit in a pixel driving circuit;

[0187] a second control signal line pattern, at least a portion of the second control signal line pattern extending along the second direction, the second control signal line pattern being multiplexed as a second control terminal SnB;

[0188] a third control signal line pattern, at least a portion of which extends along the second direction, and the third control signal line pattern is multiplexed as a third control terminal AZn-1;

[0189] an initialization signal line pattern, at least a portion of which extends along the second direction, and the initialization signal line pattern is multiplexed as an initialization signal output terminal Init;

[0190] a light-emitting control signal line pattern, at least a portion of which extends along the second direction, and the light-emitting control signal line pattern is multiplexed into a light-emitting control terminal EM;

[0191] A data writing control line pattern, at least a portion of which extends along the second direction, and the data writing control line pattern is multiplexed as a writing control terminal Sn.

[0192] Exemplarily, the multiple sub-pixels are distributed in an array on the substrate, and the multiple sub-pixels can be divided into multiple rows of sub-pixels arranged along a first direction, and each row of sub-pixels includes multiple sub-pixels arranged along a second direction; the multiple sub-pixels can be divided into multiple columns of sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction.

[0193] Exemplarily, in the same column of sub-pixels, the power line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same column of sub-pixels, the data line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same column of sub-pixels, the reference signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure.

[0194] Exemplarily, in the same row of sub-pixels, the first control signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same row of sub-pixels, the second control signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same row of sub-pixels, the third control signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same row of sub-pixels, the initialization signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same row of sub-pixels, the light-emitting control signal line graphics included in each sub-pixel are coupled in sequence to form an integrated structure; in the same row of sub-pixels, the data writing control line graphics included in each sub-pixel are coupled in sequence to form an integrated structure.

[0195] Exemplarily, the power line pattern is multiplexed as a first level signal output terminal VDD, and the driving sub-circuit and the second reset sub-circuit are both coupled to the power line pattern.

[0196] Exemplarily, the data line pattern is multiplexed as a data signal input terminal DA, and the data writing sub-circuit is coupled to the data line pattern.

[0197] Exemplarily, the reference signal line pattern is multiplexed as a reference signal output terminal Ref, and the first light emitting control sub-circuit is coupled to the reference signal line pattern.

[0198] Exemplarily, the first control signal line pattern is multiplexed as a first control terminal AZn coupled to a compensation subcircuit in a pixel driving circuit. In the same sub-pixel, the compensation subcircuit is coupled to the first control signal line pattern.

[0199] Exemplarily, the second control signal line pattern is multiplexed as the second control terminal SnB, and the first reset sub-circuit is coupled to the second control signal line pattern.

[0200] Exemplarily, the third control signal line pattern is multiplexed as a third control terminal AZn-1, and the second reset sub-circuit is coupled to the third control signal line pattern.

[0201] Exemplarily, the initialization signal line pattern is multiplexed as the initialization signal output terminal Init, and the first reset sub-circuit and the third reset sub-circuit are coupled to the initialization signal line pattern.

[0202] Exemplarily, the light-emitting control signal line pattern is multiplexed into a light-emitting control terminal EM, and both the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are coupled to the light-emitting control signal line pattern.

[0203] Exemplarily, the data write control line pattern is multiplexed as a write control terminal Sn, and the data write sub-circuit is coupled to the data write control line pattern.

[0204] like Figure 20 As shown, exemplarily, the display substrate includes a polyimide layer (PI layer), a barrier layer Ba, a first buffer layer Bu1, a first active layer 10, a first gate insulating layer GI1, a first gate metal layer 20, a second gate insulating layer GI2, a second gate metal layer 30, a first interlayer insulating layer ILD1, a second buffer layer Bu2, a second active layer 50, a third gate insulating layer GI3, a third gate metal layer 40, a second interlayer insulating layer ILD2, a first source and drain metal layer SD, a planarization layer, an anode layer, an organic light-emitting functional layer and a cathode layer.

[0205] like Figure 5 , Figure 14 and Figure 20 As shown, illustratively, the first active layer 10 is made of P-Si material, and the first active layer 10 includes active patterns in the first transistor T1, the third transistor T3, and the sixth transistor T6.

[0206] like Figure 6 , Figure 15 and Figure 20 As shown, illustratively, the first gate metal layer 20 includes a light emitting control signal line pattern, a data writing control line pattern, a gate of the third transistor T3, a first plate C11 of the first capacitor C1, and a second plate C22 of the second capacitor C2 (i.e., the second end of the second capacitor C2).

[0207] like Figure 7 , Figure 16 and Figure 20 As shown, illustratively, the second gate metal layer 30 includes an initialization signal line pattern, a second plate C12 of the first capacitor C1, a first plate C21 of the second capacitor C2, a first compensation line 31, and a second compensation line 32. Exemplarily, the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are formed into an integrated structure.

[0208] It should be noted that the second compensation line 32 is used to couple the power line patterns in different sub-pixels together, which is beneficial to improving the uniformity of the power signal.

[0209] like Figure 8 、 Figure 17 and Figure 20 As shown, illustratively, the second active layer 50 is made of IGZO material, and the second active layer 50 includes active patterns in the second transistor T2, the fourth transistor T4 and the fifth transistor T5.

[0210] like Figure 9 、 Figure 18 and Figure 20 As shown, illustratively, the third gate metal layer 40 includes a first control signal line pattern, a second control signal line pattern, a third control signal line pattern, a gate of the second transistor T2 and a gate of the fifth transistor T5.

[0211] like Figure 10 、 Figure 19 and Figure 20 As shown, illustratively, the first source-drain metal layer includes a power line pattern, a data line pattern, a reference signal line pattern, and some conductive connection parts with conductive functions.

[0212] In the display substrate provided by the embodiment of the present disclosure, by arranging the data line pattern between the power line pattern and the reference signal line pattern, the problem of interference with the working stability of the surrounding transistors due to changes in the data signal transmitted on the data line pattern is better avoided.

[0213] In addition, since the pulse widths of the first control signal output by the first control terminal AZn and the third control signal output by the third control terminal AZn-1 in the pixel driving circuit provided in the above embodiment are both adjustable, the threshold voltage compensation time can be adjusted by adjusting the pulse widths of the first control signal and the third control signal, thereby reducing the problem of mura caused by the short compensation time under high-frequency conditions. Moreover, through the compensation sub-circuit, the first reset sub-circuit, and the second reset sub-circuit, the potentials of the control terminal N1 of the driving sub-circuit and the second terminal N2 of the first coupling sub-circuit can be well maintained during the light-emitting period P3 under low-frequency conditions. Therefore, when the display substrate provided in the embodiment of the present disclosure includes the above-mentioned pixel driving circuit, the display substrate can effectively be compatible with high-frequency display and low-frequency display, meeting people's needs for high refresh rate and low power consumption.

[0214] like Figure 4 and Figure 13 As shown, in some embodiments, the data writing subcircuit in the pixel driving circuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2, the driving subcircuit includes a third transistor T3, the first reset subcircuit includes a fourth transistor T4, the second reset subcircuit includes a fifth transistor T5, the first light emitting control subcircuit includes a sixth transistor T6, the first coupling subcircuit includes a first capacitor C1, and the second coupling subcircuit includes a second capacitor C2;

[0215] The first capacitor C1 includes a first plate C11 and a second plate C12 that are oppositely disposed, and the first plate C11 is located between the second plate C12 and the substrate;

[0216] like Figure 8 and Figure 17 As shown, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 all include N-type oxide transistors, the second transistor T2 includes a second active pattern 502, the fourth transistor T4 includes a fourth active pattern 504, and the fifth transistor T5 includes a fifth active pattern 505;

[0217] The second active pattern 502, the fourth active pattern 504 and the fifth active pattern 505 are provided in the same layer and the same material. The fourth active pattern 504 is located between the second control signal line and the substrate. The fourth active pattern 504 is located on the side of the second electrode away from the substrate.

[0218] Exemplarily, the first plate C11 of the first capacitor C1 is reused as the gate of the third transistor T3, and the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate.

[0219] Exemplarily, the second active pattern 502 , the fourth active pattern 504 , and the fifth active pattern 505 are all made of IGZO material.

[0220] Exemplarily, the first active pattern 101 included in the first transistor T1 and the sixth active pattern 106 included in the sixth transistor T6 are formed into an integrated structure.

[0221] Exemplarily, the third transistor T3 further includes a third active pattern 103 .

[0222] Exemplarily, the first active pattern 101 includes a portion extending along the first direction and a portion extending along the second direction; the sixth active pattern 106 includes a portion extending along the first direction and a portion extending along the second direction.

[0223] like Figure 8 and Figure 17 As shown, in some embodiments, the second active pattern 502 extends along the second direction, the fourth active pattern 504 extends along the first direction, the second active pattern 502 and the fourth active pattern 504 form an integral structure, and the orthographic projection of the second active pattern 502 on the substrate is located between the orthographic projection of the first control signal line pattern on the substrate and the orthographic projection of the second control signal line pattern on the substrate.

[0224] Illustratively, the second active pattern 502 and the fourth active pattern 504 are formed into a structure similar to a “┘”.

[0225] Exemplarily, the gate of the second transistor T2 and the second control signal line pattern form an integrated structure.

[0226] The second active pattern 502 and the fourth active pattern 504 are formed into an integrated structure, so that the second active pattern 502 and the fourth active pattern 504 can be formed in the same patterning process, which is beneficial to simplifying the manufacturing process of the display substrate.

[0227] The display substrate with the above layout is beneficial to reducing the layout space occupied by a single pixel driving circuit and is beneficial to improving the resolution of the display substrate.

[0228] like Figure 4 、 Figure 8 、 Figure 13 and Figure 17As shown, in some embodiments, the fifth active pattern 505 extends along the second direction, and the orthographic projection of the fifth active pattern 505 on the substrate is located between the orthographic projection of the third control signal line pattern on the substrate and the orthographic projection of the second electrode plate on the substrate.

[0229] The display substrate using the above layout method is more conducive to reducing the layout space occupied by a single pixel driving circuit while ensuring the stability and reliability of the pixel driving circuit, which is conducive to improving the resolution of the display substrate.

[0230] like Figure 4 and Figure 8 As shown, in some embodiments, when the pixel driving circuit further includes a second light emitting control subcircuit and a third reset subcircuit, the third reset subcircuit includes an eighth transistor T8, the eighth transistor T8 includes an eighth active pattern 508, the eighth active pattern 508 extends along the second direction, and the eighth active pattern 508 is provided in the same layer and material as the second active pattern 502.

[0231] Exemplarily, the second active layer 50 further includes the eighth active pattern 508 .

[0232] The eighth active pattern 508 and the second active pattern 502 are provided in the same layer and with the same material, so that the eighth active pattern 508 and the second active pattern 502 can be formed in the same patterning process, which is conducive to simplifying the manufacturing process of the display substrate.

[0233] Furthermore, the eighth active pattern 508 is made of IGZO material, so that the eighth transistor T8 is formed as an N-type oxide transistor, which is more conducive to the potential stability of the N5 node.

[0234] like Figure 4 As shown, in some embodiments, the third control signal line pattern is also multiplexed as a first control terminal AZn coupled to a third reset sub-circuit included in a pixel driving circuit in an adjacent sub-pixel along the first direction; the gate of the eighth transistor T8 is coupled to the third control signal line pattern in the adjacent sub-pixel along the first direction; and the orthographic projection of the eighth active pattern 508 on the substrate is located between the orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the third control signal line pattern in the adjacent sub-pixel along the first direction on the substrate.

[0235] For example, the gate of the eighth transistor T8 is connected to the third control signal line pattern (eg, Figure 4 AZn-1') in the molecule forms an integrated structure.

[0236] Exemplarily, the first control signal line pattern transmits the same signal as the third control signal line pattern in the adjacent sub-pixels along the first direction.

[0237] The display substrate using the above layout method is more conducive to reducing the layout space occupied by a single pixel driving circuit while ensuring the stability and reliability of the pixel driving circuit, which is conducive to improving the resolution of the display substrate.

[0238] In some embodiments, the orthographic projection of the initialization signal line pattern on the substrate, the orthographic projection of the light-emitting control signal line pattern on the substrate, the orthographic projection of the data writing control line pattern on the substrate, the orthographic projection of the second control signal line pattern on the substrate, the orthographic projection of the first control signal line pattern on the substrate, and the orthographic projection of the third control signal line pattern on the substrate are arranged sequentially along the first direction. This arrangement reduces the layout difficulty of the pixel driving circuit, effectively reduces the layout space occupied, and is conducive to improving the resolution of the display substrate.

[0239] like Figure 13 and Figure 14 As shown, in some embodiments, when the pixel driving circuit further includes a second light-emitting control subcircuit and a fourth reset subcircuit, the second light-emitting control subcircuit includes a seventh transistor T7, the seventh transistor T7 includes a seventh active pattern 107, the fourth reset subcircuit includes a ninth transistor T9, the ninth transistor T9 includes a ninth active pattern 109, the seventh active pattern 107 and the ninth active pattern 109 both extend along the first direction, and the seventh active pattern 107 and the ninth active pattern 109 form an integral structure.

[0240] Exemplarily, the first active layer 10 includes the seventh active pattern 107 and the ninth active pattern 109 .

[0241] The seventh active pattern 107 and the ninth active pattern 109 are formed into an integrated structure, so that the seventh active pattern 107 and the ninth active pattern 109 can be formed in the same patterning process, which is beneficial to simplifying the manufacturing process of the display substrate.

[0242] like Figure 13 and Figure 14 As shown, in some embodiments, the orthographic projection of the ninth active pattern 109 on the substrate is located between the orthographic projection of the light emitting control signal line pattern on the substrate and the orthographic projection of the initialization signal line pattern on the substrate.

[0243] The display substrate using the above layout method is more conducive to reducing the layout space occupied by a single pixel driving circuit while ensuring the stability and reliability of the pixel driving circuit, which is conducive to improving the resolution of the display substrate.

[0244] In some embodiments, the orthographic projection of the initialization signal line pattern on the substrate, the orthographic projection of the data write control line pattern on the substrate, the orthographic projection of the light emission control signal line pattern on the substrate, the orthographic projection of the second control signal line pattern on the substrate, the orthographic projection of the first control signal line pattern on the substrate, and the orthographic projection of the third control signal line pattern on the substrate are arranged sequentially along the first direction. This arrangement reduces the layout difficulty of the pixel drive circuit, effectively reduces the layout space occupied, and is conducive to improving the resolution of the display substrate.

[0245] like Figure 4 and Figure 13 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of sub-pixel rows arranged along a first direction, and each sub-pixel row includes a plurality of sub-pixels arranged along a second direction;

[0246] The display substrate further includes a plurality of first compensation lines 31 , which correspond one-to-one to at least some sub-pixel rows. The first compensation lines 31 are respectively coupled to reference signal line patterns included in each sub-pixel in the corresponding sub-pixel row.

[0247] Exemplarily, at least a portion of the first compensation line 31 extends along the second direction.

[0248] Exemplarily, at least a portion of the second compensation line 32 extends along the second direction, and the orthographic projection of the second compensation line 32 on the substrate is located between the orthographic projection of the first compensation line 31 on the substrate and the orthographic projection of the third control signal line pattern on the substrate.

[0249] The above arrangement of coupling the first compensation line 31 to the reference signal line pattern included in each sub-pixel in the corresponding sub-pixel row is more conducive to the uniformity and stability of the reference signal provided by the reference signal line pattern.

[0250] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0251] The display substrate provided by the above embodiment can better prevent the problem of interference with the operating stability of the surrounding transistors due to changes in the data signals transmitted on the data line pattern. It also reduces the layout difficulty of the pixel driving circuit and effectively reduces the layout space occupied, which is conducive to improving the resolution of the display substrate. At the same time, the display substrate is effectively compatible with high-frequency and low-frequency displays, meeting people's needs for high refresh rate and low power consumption.

[0252] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0253] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer.

[0254] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0255] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0256] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0257] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0258] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit for driving a light-emitting element, the pixel driving circuit comprising: a driving sub-circuit, wherein a first terminal of the driving sub-circuit is coupled to the first level signal output terminal, and a second terminal of the driving sub-circuit is coupled to the light-emitting element; The driving sub-circuit includes a third active pattern; a compensation subcircuit, coupled to the first control terminal, the control terminal of the driving subcircuit, and the second terminal of the driving subcircuit, respectively; the compensation subcircuit includes a second active pattern; a first coupling subcircuit, wherein a first terminal of the first coupling subcircuit is coupled to a control terminal of the driving subcircuit; a second coupling subcircuit, wherein a first end of the second coupling subcircuit is coupled to a second end of the first coupling subcircuit; a first reset subcircuit, coupled to the second control terminal, the control terminal of the driving subcircuit, and the initialization signal output terminal; the first reset subcircuit includes a fourth active pattern; a second reset subcircuit coupled to the third control terminal, the second terminal of the first coupling subcircuit, and the first level signal output terminal; the second reset subcircuit includes a fifth active pattern; a first light-emitting control subcircuit coupled to the light-emitting control terminal, the second terminal of the second coupling subcircuit, and the reference signal output terminal; a data writing subcircuit coupled to the writing control terminal, the second terminal of the second coupling subcircuit, and the data signal input terminal, respectively; while the writing control terminal controls the data writing subcircuit to conduct an electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal, the third control terminal controls the second reset subcircuit to conduct an electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; The second active pattern, the fourth active pattern and the fifth active pattern are all arranged in different layers from the third active pattern.

2. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a second light-emitting control subcircuit, the second light-emitting control subcircuit being coupled to the light-emitting control terminal, the second terminal of the driving subcircuit, and the light-emitting element, respectively; and configured to control, under the control of the light-emitting control terminal, to switch on or off the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; The third reset subcircuit is coupled to the first control terminal, the light-emitting element and the initialization signal output terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal under the control of the first control terminal.

3. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a second light-emitting control subcircuit, wherein the second end of the driver subcircuit is coupled to the light-emitting element via the second light-emitting control subcircuit; the second light-emitting control subcircuit is coupled to the light-emitting control end, the second end of the driver subcircuit, and the light-emitting element, respectively; and is configured to control the electrical connection between the second end of the driver subcircuit and the light-emitting element to be turned on or off under the control of the light-emitting control end; The fourth reset subcircuit is coupled to the write control terminal, the light emitting element and the initialization signal output terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the light emitting element and the initialization signal output terminal under the control of the write control terminal.

4. The pixel driving circuit according to claim 1, wherein: The data writing subcircuit includes a first transistor, the compensation subcircuit includes a second transistor, the driving subcircuit includes a third transistor, the first reset subcircuit includes a fourth transistor, the second reset subcircuit includes a fifth transistor, the first light emission control subcircuit includes a sixth transistor, the first coupling subcircuit includes a first capacitor, and the second coupling subcircuit includes a second capacitor; The gate of the first transistor is coupled to the write control terminal, the first electrode of the first transistor is coupled to the data signal input terminal, and the second electrode of the first transistor is coupled to the second terminal of the second capacitor; The gate of the second transistor is coupled to the first control terminal, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the gate of the third transistor; The first electrode of the third transistor is coupled to the first level signal output terminal; The gate of the fourth transistor is coupled to the second control terminal, the first electrode of the fourth transistor is coupled to the initialization signal output terminal, and the second electrode of the fourth transistor is coupled to the gate of the third transistor; The gate of the fifth transistor is coupled to the third control terminal, the first electrode of the fifth transistor is coupled to the first level signal output terminal, and the second electrode of the fifth transistor is coupled to the second terminal of the first capacitor; The gate of the sixth transistor is coupled to the light emitting control terminal, the first electrode of the sixth transistor is coupled to the reference signal output terminal, and the second electrode of the sixth transistor is coupled to the second terminal of the second capacitor; A first terminal of the first capacitor is coupled to the gate of the third transistor; The first end of the second capacitor is coupled to the second end of the first capacitor.

5. The pixel driving circuit according to claim 4, wherein: The first transistor, the third transistor, and the sixth transistor each include a P-type low-temperature polysilicon transistor, and the second transistor, the fourth transistor, and the fifth transistor each include an N-type oxide transistor.

6. The pixel driving circuit according to claim 2, wherein: The second light emitting control sub-circuit includes a seventh transistor, a gate of the seventh transistor is coupled to the light emitting control terminal, a first electrode of the seventh transistor is coupled to the second terminal of the driving sub-circuit, and a second electrode of the seventh transistor is coupled to the light emitting element; The third reset sub-circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the first control terminal, a first electrode of the eighth transistor is coupled to the initialization signal output terminal, and a second electrode of the eighth transistor is coupled to the light-emitting element.

7. The pixel driving circuit according to claim 3, wherein: The second light emitting control sub-circuit includes a seventh transistor, a gate of the seventh transistor is coupled to the light emitting control terminal, a first electrode of the seventh transistor is coupled to the second terminal of the driving sub-circuit, and a second electrode of the seventh transistor is coupled to the light emitting element; The fourth reset sub-circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the write control terminal, a first electrode of the ninth transistor is coupled to the initialization signal output terminal, and a second electrode of the ninth transistor is coupled to the light-emitting element.

8. A driving method for a pixel driving circuit, for driving the pixel driving circuit according to any one of claims 1 to 7, the driving method comprising: In each display cycle, During the reset period, under the control of the second control terminal, the first reset subcircuit controls the electrical connection between the control terminal of the drive subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit controls the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; and under the control of the write control terminal, the data write subcircuit controls the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal. During the compensation period, under the control of the second control terminal, the first reset subcircuit controls the disconnection of the electrical connection between the control terminal of the driver subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit continues to control the disconnection of the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; under the control of the write control terminal, the data write subcircuit controls the disconnection of the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal; under the control of the first control terminal, the compensation subcircuit controls the disconnection of the electrical connection between the control terminal of the driver subcircuit and the second terminal of the driver subcircuit; the driver subcircuit connects the electrical connection between the first level signal output terminal and the compensation subcircuit until the threshold voltage of the driver subcircuit is written to the control terminal of the driver subcircuit; During the light-emitting period, under the control of the second control terminal, the first reset subcircuit controls the disconnection of the electrical connection between the control terminal of the driving subcircuit and the initialization signal output terminal; under the control of the third control terminal, the second reset subcircuit controls the disconnection of the electrical connection between the second terminal of the first coupling subcircuit and the first level signal output terminal; under the control of the write control terminal, the data write subcircuit controls the disconnection of the electrical connection between the second terminal of the second coupling subcircuit and the data signal input terminal; under the control of the first control terminal, the compensation subcircuit controls the disconnection of the electrical connection between the control terminal of the driving subcircuit and the second terminal of the driving subcircuit; under the control of the light-emitting control terminal, the first light-emitting control subcircuit controls the connection of the electrical connection between the second terminal of the second coupling subcircuit and the reference signal output terminal; the driving subcircuit connects the electrical connection between the first level signal output terminal and the light-emitting element, and transmits the generated driving signal to the light-emitting element.

9. The driving method of the pixel driving circuit according to claim 8, wherein: In a case where the pixel driving circuit further includes a second light emitting control subcircuit and a third reset subcircuit, the driving method further includes: During the reset period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the first control terminal, the third reset subcircuit controls to disconnect the electrical connection between the light-emitting element and the initialization signal output terminal. During the compensation period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the first control terminal, the third reset subcircuit controls to connect the electrical connection between the light-emitting element and the initialization signal output terminal. During the light-emitting period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element; under the control of the first control terminal, the third reset subcircuit controls the disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal.

10. The driving method of the pixel driving circuit according to claim 8, wherein: In a case where the pixel driving circuit further includes a second light emitting control subcircuit and a fourth reset subcircuit, the driving method further includes: During the reset period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the write control terminal, the fourth reset subcircuit controls to connect the electrical connection between the light-emitting element and the initialization signal output terminal. During the compensation period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls to disconnect the electrical connection between the second terminal of the driving subcircuit and the light-emitting element; and under the control of the write control terminal, the fourth reset subcircuit controls to disconnect the electrical connection between the light-emitting element and the initialization signal output terminal. During the light-emitting period, under the control of the light-emitting control terminal, the second light-emitting control subcircuit controls the electrical connection between the second end of the driving subcircuit and the light-emitting element; under the control of the write control terminal, the fourth reset subcircuit controls the disconnection of the electrical connection between the light-emitting element and the initialization signal output terminal.

11. A display substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; The sub-pixel includes the pixel driving circuit according to any one of claims 1 to 7, and the sub-pixel further includes: a power line pattern, at least a portion of which extends along a first direction, and the power line pattern is multiplexed as a first level signal output terminal; a data line pattern, at least a portion of which extends along the first direction, and the data line pattern is multiplexed as a data signal input terminal; a reference signal line pattern, at least a portion of which extends along the first direction, and the reference signal line pattern is multiplexed as a reference signal output terminal; the data line pattern is located between the power line pattern and the reference signal line pattern; a first control signal line pattern, at least a portion of the first control signal line pattern extending along a second direction, the second direction intersecting the first direction, the first control signal line pattern being multiplexed as a first control terminal coupled to a compensation subcircuit in a pixel driving circuit; a second control signal line pattern, at least a portion of the second control signal line pattern extending along the second direction, the second control signal line pattern being multiplexed as a second control end; a third control signal line pattern, at least a portion of the third control signal line pattern extending along the second direction, the third control signal line pattern being multiplexed as a third control end; an initialization signal line pattern, at least a portion of which extends along the second direction, and the initialization signal line pattern is multiplexed as an initialization signal output terminal; a light-emitting control signal line pattern, at least a portion of which extends along the second direction, and the light-emitting control signal line pattern is multiplexed as a light-emitting control terminal; A data writing control line pattern, at least a portion of which extends along the second direction, and the data writing control line pattern is multiplexed as a writing control terminal.

12. The display substrate according to claim 11, wherein: The data writing subcircuit in the pixel driving circuit includes a first transistor, the compensation subcircuit includes a second transistor, the driving subcircuit includes a third transistor, the first reset subcircuit includes a fourth transistor, the second reset subcircuit includes a fifth transistor, the first light emission control subcircuit includes a sixth transistor, the first coupling subcircuit includes a first capacitor, and the second coupling subcircuit includes a second capacitor; The first capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, and the first electrode plate is located between the second electrode plate and the substrate; The second transistor, the fourth transistor, and the fifth transistor each include an N-type oxide transistor, the second transistor includes a second active pattern, the fourth transistor includes a fourth active pattern, and the fifth transistor includes a fifth active pattern; The second active pattern, the fourth active pattern and the fifth active pattern are provided in the same layer and the same material. The fourth active pattern is located between the second control signal line and the substrate. The fourth active pattern is located on a side of the second electrode away from the substrate.

13. The display substrate according to claim 12, wherein: The second active pattern extends along the second direction, and the fourth active pattern extends along the first direction. The second active pattern and the fourth active pattern form an integral structure. The orthographic projection of the second active pattern on the substrate is located between the orthographic projection of the first control signal line pattern on the substrate and the orthographic projection of the second control signal line pattern on the substrate.

14. The display substrate according to claim 12, wherein: The fifth active pattern extends along the second direction, and an orthographic projection of the fifth active pattern on the substrate is located between an orthographic projection of the third control signal line pattern on the substrate and an orthographic projection of the second electrode plate on the substrate.

15. The display substrate according to claim 12, wherein: When the pixel driving circuit further includes a second light emitting control subcircuit and a third reset subcircuit, the third reset subcircuit includes an eighth transistor, the eighth transistor includes an eighth active pattern, the eighth active pattern extends along the second direction, and the eighth active pattern is provided in the same layer and material as the second active pattern.

16. The display substrate according to claim 15, wherein: The third control signal line pattern is also multiplexed as a first control terminal coupled to a third reset sub-circuit included in a pixel driving circuit in an adjacent sub-pixel along the first direction; the gate of the eighth transistor is coupled to the third control signal line pattern in the adjacent sub-pixel along the first direction; and the orthographic projection of the eighth active pattern on the substrate is located between the orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the third control signal line pattern in the adjacent sub-pixel along the first direction on the substrate.

17. The display substrate according to claim 12, wherein: In a case where the pixel driving circuit further includes a second light-emitting control subcircuit and a fourth reset subcircuit, the second light-emitting control subcircuit includes a seventh transistor, the seventh transistor includes a seventh active pattern, the fourth reset subcircuit includes a ninth transistor, the ninth transistor includes a ninth active pattern, the seventh active pattern and the ninth active pattern both extend along the first direction, and the seventh active pattern and the ninth active pattern form an integral structure.

18. The display substrate according to claim 17, wherein: The orthographic projection of the ninth active pattern on the substrate is located between the orthographic projection of the light emitting control signal line pattern on the substrate and the orthographic projection of the initialization signal line pattern on the substrate.

19. The display substrate according to claim 11, wherein: The plurality of sub-pixels are divided into a plurality of sub-pixel rows arranged along a first direction, and each sub-pixel row includes a plurality of sub-pixels arranged along a second direction; The display substrate further includes a plurality of first compensation lines corresponding to at least some sub-pixel rows one by one, and the first compensation lines are respectively coupled to reference signal line patterns included in each sub-pixel in the corresponding sub-pixel row.

20. A display device comprising the display substrate according to any one of claims 11 to 19.

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