Semiconductor device

Abstract

A semiconductor device of one embodiment includes a semiconductor chip including a transistor and a drain pad provided over a substrate, a capacitor including an upper electrode and a lower electrode that sandwich a dielectric, a pad, and a dummy pad provided over the substrate of the semiconductor chip. The semiconductor device includes a first wiring that connects the pad and the drain pad of the semiconductor chip to each other, a second wiring that connects the dummy pad and the upper electrode of the capacitor to each other, and a third wiring that connects the pad and the dummy pad to each other.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2020-149904, dated September 7, 2020, and incorporates all the contents set forth in said Japanese application. Background Technology

[0003] Patent Document 1 describes an internally matched high-output field-effect transistor (internal matched FET). The internally matched FET includes two GaAs FET chips disposed within a package and an alumina substrate for input / output matching circuitry. The internally matched FET includes an input-side alumina substrate and an output-side alumina substrate. Each of the input-side and output-side alumina substrates is provided with a matching circuit for achieving impedance matching.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 63-86904 Summary of the Invention

[0007] One embodiment of a semiconductor device includes: a semiconductor chip having transistors and electrode pads disposed on a substrate; a capacitor having an upper electrode and a lower electrode sandwiching a dielectric; a first relay pad; and a second relay pad disposed on the substrate of the semiconductor chip. The semiconductor device further includes: a first lead connecting the first relay pad to the electrode pads of the semiconductor chip; a second lead connecting the second relay pad to the upper electrode of the capacitor; and a third lead connecting the first relay pad to the second relay pad. Attached Figure Description

[0008] Figure 1 This is a top view showing the internal structure of a semiconductor device according to one embodiment.

[0009] Figure 2 It means Figure 1 A top view of a semiconductor device, including semiconductor chips, capacitors, and leads.

[0010] Figure 3 This is a diagram illustrating an example of the relationship between lead length and current.

[0011] Figure 4 It means Figure 1 A diagram of a semiconductor device, including semiconductor chips, capacitors, and leads.

[0012] Figure 5 It means Figure 1 A top view of a semiconductor device, including semiconductor chips, capacitors, and leads.

[0013] Figure 6 This is a top view showing the semiconductor chip, capacitor, and leads of the semiconductor device in the first modified example.

[0014] Figure 7 It means Figure 6 Diagram of semiconductor chips, capacitors, and leads.

[0015] Figure 8 It is a magnified 3D view of the lead wire.

[0016] Figure 9 This is a top view showing the semiconductor chip, capacitor, and leads of the semiconductor device in the second variation.

[0017] Figure 10 It means Figure 9 The back side view of the semiconductor chip and the back side view of the capacitor.

[0018] Figure 11 This is a top view showing the semiconductor chip, first relay pad, capacitor, and leads of the semiconductor device in the third variation. Detailed Implementation

[0019] In conventional internally matched FETs, the GaAsFET chip and the matching circuit are interconnected via bonding wires. Furthermore, in high-frequency amplifiers processing low-frequency signals, it is sometimes necessary to reduce the number of leads connected to the electrode pads of the semiconductor chip, such as the drain pad, and to extend the length of each lead. With high current per lead and long lead lengths, there are concerns that the leads may melt.

[0020] The purpose of this disclosure is to provide a semiconductor device that can shorten the leads connected to the electrode pads of a semiconductor chip.

[0021] [Description of embodiments of this disclosure]

[0022] First, embodiments of the present disclosure will be described. One embodiment of a semiconductor device includes: a semiconductor chip having transistors and electrode pads disposed on a substrate; a capacitor having an upper electrode and a lower electrode sandwiching a dielectric; a first relay pad; and a second relay pad disposed on the substrate of the semiconductor chip. The semiconductor device further includes: a first lead connecting the first relay pad to the electrode pads of the semiconductor chip; a second lead connecting the second relay pad to the upper electrode of the capacitor; and a third lead connecting the first relay pad to the second relay pad.

[0023] In this semiconductor device, a semiconductor chip has transistors and electrode pads on a substrate, and a capacitor has upper and lower electrodes sandwiching a dielectric. A first lead connects the electrode pads of the semiconductor chip to a first relay pad. A third lead connects the first relay pad to a second relay pad. A second lead connects the second relay pad to the upper electrode of the capacitor. Thus, the semiconductor chip and the capacitor are interconnected via a first lead extending from the semiconductor chip, a first relay pad, a third lead, a second relay pad on the semiconductor chip, and a second lead extending toward the capacitor. Therefore, by having a first lead, a first relay pad, a third lead, a second relay pad, and a second lead, the lead connected to the electrode pads of the semiconductor chip can be used only as a first lead. The number of leads can be shortened by connecting each lead to the first relay pad and the second relay pad.

[0024] The first relay pad can also be positioned on the dielectric of the capacitor, separated from the upper electrode. The second relay pad can also be positioned along one side of the semiconductor chip. In this case, the first relay pad can be positioned on the dielectric of the capacitor, and the second relay pad can be positioned along one side of the semiconductor chip opposite the capacitor.

[0025] The electrode pads can also be configured along one side of the semiconductor chip. The second relay pad can also be configured adjacent to the electrode pads. In this case, the electrode pads and the second relay pad on the semiconductor chip can be configured in a manner that arranges them along one side of the semiconductor chip opposite the capacitor.

[0026] The aforementioned semiconductor device may also include: a plurality of first relay pads arranged along one side of a capacitor; and a plurality of second relay pads and a plurality of electrode pads arranged along one side of a semiconductor chip. Alternatively, each of the plurality of second relay pads may be configured adjacent to an electrode pad. In this case, the plurality of first relay pads can be arranged along one side of the capacitor opposite the semiconductor chip, and the electrode pads and second relay pads can be arranged along one side of the semiconductor chip opposite the capacitor.

[0027] The aforementioned semiconductor device may also include multiple first leads and multiple second leads, or each of the multiple adjacent first leads may be connected to a common first relay pad. Similarly, each of the multiple adjacent second leads may be connected to a common second relay pad. In this case, multiple leads are connected to each of the first and second relay pads, thus allowing for more efficient use of the first and second relay pads as lead connection points.

[0028] The aforementioned semiconductor device may also have a back electrode on the back side of the capacitor dielectric, located in a region other than the area opposite the first relay pad. In this case, parasitic capacitance generated on the first relay pad can be suppressed by not providing a back electrode on the back side of the first relay pad.

[0029] The aforementioned semiconductor device may also have a back electrode on the back side of the semiconductor chip or the back side of the substrate, located in a region other than the area opposite the second relay pad. In this case, parasitic capacitance generated on the second relay pad can be suppressed by not providing a back electrode on the back side of the second relay pad.

[0030] The first relay pad can also be located between the capacitor and the semiconductor chip. In this case, the first relay pad can be positioned in a location separate from both the capacitor and the semiconductor chip.

[0031] The substrate can also be made of silicon carbide (SiC), diamond, or metal. In this case, the substrate can be made of a material with high heat dissipation.

[0032] [Details of the embodiments disclosed herein]

[0033] Hereinafter, specific examples of the semiconductor device of this disclosure will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to the examples described below, and is intended to include all modifications shown in the technical solution and those equivalent to the technical solution. In the description of the drawings, the same or equivalent elements are given the same reference numerals, and repeated descriptions are omitted where appropriate. For the purposes of the drawings, some parts are simplified or exaggerated for ease of understanding, and the size ratios, etc., are not limited to those shown in the drawings.

[0034] Figure 1 This is a diagram showing the internal configuration of a semiconductor device 1 according to one embodiment. (See diagram below.) Figure 1 As shown, the semiconductor device 1 includes an input terminal 2, an output terminal 3, a semiconductor chip 10, a branch circuit board 20, a synthesis circuit board 30, a filter circuit 40, a capacitor 50, and a capacitor 60. For example, the semiconductor device 1 includes two filter circuits 40 and two capacitors 50 and 60.

[0035] For example, the semiconductor chip 10 is an amplification element section including two amplification elements 11. As an example, the output of each amplification element 11 is 30W, and the overall output of the semiconductor chip 10 is 60W. The semiconductor device 1 is, for example, a high-frequency amplifier equipped with a package 4. The package 4 houses the semiconductor chip 10, the branch circuit board 20, the synthesis circuit board 30, the filter circuit 40, and capacitors 50 and 60.

[0036] Package 4 is made of metal and is connected to a reference potential. For example, package 4 has a rectangular planar shape. Package 4 has end walls 4a and 4b facing each other in a first direction A1 and side walls 4c and 4d facing each other in a second direction A2. The first direction A1 and the second direction A2 intersect each other, and as an example, they are orthogonal to each other. Package 4 has a rectangular flat base plate 4e.

[0037] The base plate 4e, for example, has a plane extending in both a first direction A1 and a second direction A2. End walls 4a and 4b are erected along one pair of sides of the base plate 4e (sides extending along the second direction A2). Side walls 4c and 4d are erected along the other pair of sides of the base plate 4e (sides extending along the first direction A1). The package 4 also has a cover (not shown). This cover seals the opening formed by the end walls 4a and 4b and the side walls 4c and 4d.

[0038] Input terminal 2 is a metallic wiring pattern that receives a high-frequency signal from outside the semiconductor device 1. The high-frequency signal is, for example, a multi-carrier transmission signal, which is formed by superimposing multiple carrier signals with different frequencies. The frequency band of the carrier signal is, for example, 500MHz or less. Input terminal 2 is located at the center of the end wall 4a in the second direction A2. Input terminal 2 extends from the outside of the package 4 inwards.

[0039] For example, the semiconductor chip 10 is disposed on the substrate 4e of the package 4 and includes a central region of the package 4 in the first direction A1. Each amplification element 11 of the semiconductor chip 10 incorporates a transistor. The transistor is a field-effect transistor (FET), and as an example, a high electron mobility transistor (HEMT). Each amplification element 11 has a gate pad, a source pad, and a drain pad.

[0040] For example, gate pads (signal input terminals) and source pads are alternately arranged on one side (end edge) of the input terminal 2 side of each amplifying element 11. Drain pads (signal output terminals) are arranged on the end edge of the output terminal 3 side of each amplifying element 11. Each source pad is electrically connected to the base plate 4e of the package 4 via a via and is set as a reference potential. This via is in the thickness direction (e.g., with...) Figure 1 The amplifying element 11 extends through the paper in a direction orthogonal to the plane of the paper. Each amplifying element 11 amplifies the high-frequency signal input to each gate pad and outputs the amplified high-frequency signal from each drain pad. It should be noted that the configuration of the periphery of the drain pad of the amplifying element 11 will be described in detail later.

[0041] Branch circuit substrate 20 is disposed on the base plate 4e of package 4. Branch circuit substrate 20 is arranged side by side with input terminal 2 and semiconductor chip 10 along the first direction A1. Branch circuit substrate 20 is located between input terminal 2 and semiconductor chip 10. Branch circuit substrate 20 has a ceramic substrate 21 and branch circuits 22 disposed on the main surface of substrate 21. For example, the planar shape of substrate 21 is rectangular.

[0042] For example, one long side 21a of the branch circuit substrate 20 is opposite to the input terminal 2, and the other long side 21b of the branch circuit substrate 20 is opposite to the semiconductor chip 10 across the capacitor 50. The back side of the substrate 21 is opposite to the bottom plate 4e of the package 4. One short side 21c of the substrate 21 is opposite to the sidewall 4c of the package 4, and the other short side 21d of the substrate 21 is opposite to the sidewall 4d of the package 4.

[0043] Branch circuit 22 includes wiring pattern 23 disposed on the main surface of substrate 21. Wiring pattern 23 is electrically connected to input terminal 2 via bonding line 9a. High-frequency signal is input from the center of input terminal 2 in the second direction A2 to wiring pattern 23 via bonding line 9a. Wiring pattern 23 has, for example, a shape that is linearly symmetrical with respect to the center line of substrate 21 along the first direction A1.

[0044] The wiring pattern 23 branches repeatedly from the connection point with the bonding line 9a, eventually reaching eight metal pads 23a. The eight metal pads 23a are arranged along the long side 21b. Adjacent metal pads 23a are interconnected via film resistors, forming Wilkinson couplers. This ensures isolation between the multiple gate pads of the semiconductor chip 10 and achieves matching of the input impedance of the semiconductor chip 10 as observed from the input terminal 2. As an example, in Figure 1 Only one film resistor 23b is shown. Eight metal pads 23a are electrically connected to capacitor 50 via bonding lines 9b.

[0045] Capacitor 50 is disposed on the base plate 4e of package 4. Capacitor 50 is positioned between branch circuit substrate 20 and semiconductor chip 10. Capacitor 50 is, for example, a parallel-plate capacitor (die capacitor) with multiple metal pads (not shown) on the main surface of the dielectric substrate. The number of metal pads of capacitor 50 is, for example, the same as the number of metal pads 23a. The multiple metal pads of capacitor 50 are arranged in a row along the second direction A2. Each metal pad is electrically connected to a corresponding metal pad 23a via bonding wire 9b. Each metal pad is electrically connected to a corresponding gate pad of semiconductor chip 10 via bonding wire 9c.

[0046] In capacitor 50, the inductive component generated by bonding lines 9b and 9c and the capacitance of the metal pads connecting the nodes between these inductive components to the reference potential (base plate 4e) constitute a T-type filter circuit. Capacitor 50 performs impedance transformation through this T-type filter circuit. Typically, in semiconductor chip 10, the impedance viewed from the gate pad towards the inside of the transistor differs from the characteristic impedance of the transmission line (e.g., 50Ω). Capacitor 50 uses a T-type filter circuit to transform this impedance into a 50Ω matching circuit obtained from the view from input terminal 2 towards the inside of the transistor.

[0047] Capacitor 60 is disposed on the base plate 4e of package 4. Capacitor 60 is disposed between semiconductor chip 10 and composite circuit substrate 30. Like capacitor 50, capacitor 60 is, for example, a parallel plate capacitor (chip capacitor). Capacitor 60 has upper and lower electrodes sandwiching a dielectric. That is, like capacitor 50, capacitor 60 also has multiple metal pads (not shown) on the main surface of the dielectric substrate.

[0048] The number of metal pads on capacitor 60 is, for example, the same as the number of metal pads 23a. The plurality of metal pads on capacitor 60 are arranged in a row along the second direction A2. These metal pads are electrically connected to the corresponding drain pads of semiconductor chip 10 via lead group 70 (described later). These metal pads are also electrically connected to the corresponding metal pads 33a of composite circuit board 30 via bonding wire 9e. It should be noted that in... Figure 1 The diagram of lead group 70 has been simplified.

[0049] In capacitor 60, the inductive components generated by lead group 70 and bonding line 9e, and the capacitance of the metal pads connecting the nodes between these inductive components to the reference potential (base plate 4e) constitute a T-type filter circuit. Capacitor 60 performs impedance transformation through this T-type filter circuit. Typically, the impedance viewed from the drain pad into the transistor in semiconductor chip 10 differs from the characteristic impedance of the transmission line (e.g., 50Ω), and is usually less than 50Ω. Capacitor 60 uses the T-type filter circuit to transform this impedance into a 50Ω matching circuit, obtained by viewing the transistor from the output terminal 3.

[0050] The composite circuit board 30 is disposed on the base plate 4e of the package 4. The composite circuit board 30 is arranged side by side with the semiconductor chip 10 and the output terminal 3 along the first direction A1. The composite circuit board 30 is located between the semiconductor chip 10 and the output terminal 3. The composite circuit board 30 has a ceramic substrate 31 and a composite substrate 32 disposed on the main surface of the substrate 31. The planar shape of the substrate 31 is, for example, rectangular.

[0051] One long side 31a of substrate 31 faces semiconductor chip 10 across capacitor 60, and the other long side 31b of substrate 31 faces output terminal 3. The back side of substrate 31 faces base plate 4e of package 4. One short side 31c of substrate 31 faces sidewall 4c of package 4, and the other short side 31d of substrate 31 faces sidewall 4d of package 4.

[0052] The composite substrate 32 combines signals output from multiple drain pads of the semiconductor chip 10 into a single output signal. The composite substrate 32 includes a wiring pattern 33 disposed on the main surface of the substrate 31. The wiring pattern 33 has, for example, a line-symmetrical shape with respect to the center line of the substrate 31 along the first direction A1. The wiring pattern 33 includes four metal pads 33a. The four metal pads 33a are arranged side-by-side along the long side 31a of the substrate 31.

[0053] Adjacent metal pads 33a are interconnected via film resistors, forming a Wilkinson coupler. This ensures isolation between the multiple drain pads of the semiconductor chip 10 and achieves matching of the output impedance of the semiconductor chip 10 as observed from the output terminal 3. It should be noted that, as an example, in... Figure 1 Only one film resistor 33b is shown in the figure.

[0054] Each metal pad 33a is electrically connected to the corresponding two metal pads of the capacitor 60 via bonding line 9e. The wiring pattern 33 repeatedly couples from the four metal pads 33a and eventually reaches the connection point with bonding line 9f. The wiring pattern 33 is electrically connected to the output terminal 3 via bonding line 9f. The amplified high-frequency signal is output from the center of the substrate 31 on the second direction A2 to the output terminal 3.

[0055] Output terminal 3 has a metallic wiring pattern. Output terminal 3 outputs an amplified high-frequency signal to the outside of semiconductor device 1. Output terminal 3 is located at the center of end wall 4b in the second direction A2. Output terminal 3 extends from the inside of package 4 to the outside.

[0056] For example, the semiconductor device 1 includes a pair of filter circuits 40. The filter circuits 40 are provided, for example, to reduce third-order intermodulation distortion contained in the output signal. One filter circuit 40 is disposed between the central portion of the substrate 31 in the second direction A2 and a corner portion 31e located on the opposite side of the semiconductor chip 10 in the substrate 31.

[0057] Another filter circuit 40 is disposed between the central portion of the substrate 31 in the second direction A2 and another corner 31f located on the opposite side of the semiconductor chip 10 in the substrate 31. That is, one filter circuit 40 is disposed near the corner 31e with respect to the center of the main surface of the substrate 31, and the other filter circuit 40 is disposed near the corner 31f with respect to the center of the main surface of the substrate 31.

[0058] Next, refer to Figure 2 The details of the semiconductor chip 10 and the capacitor 60 are explained. Figure 2 This is a top view showing the semiconductor chip 10 and the capacitor 60. The semiconductor chip 10 is an elongated rectangle. The semiconductor chip 10 has a long side 12 (one side) opposite the capacitor 60.

[0059] For example, the long side 12 extends along the second direction A2. The semiconductor chip 10 includes a substrate 15, a gate pad, an active region, a drain pad 18 (electrode pad), and an empty pad 19 (second relay pad). The substrate 15 is rectangular with the aforementioned long side 12.

[0060] The semiconductor chip 10, for example, has a plurality of drain pads 18 and a plurality of empty pads 19. Each of the drain pads 18 and empty pads 19 is configured to be arranged along the long side 12 opposite to the capacitor 60. The presence of empty pads 19 in the semiconductor chip 10 can shorten the lead length of each lead in the lead group 70.

[0061] As described above, the capacitor 60 includes a dielectric 61, an upper electrode 62, a lower electrode (not shown), and a pad 63 (first relay pad). The capacitor 60 (dielectric 61) has a long side 64 (one side) opposite to the semiconductor chip 10. For example, the long side 64 extends along the second direction A2.

[0062] An upper electrode 62 and pads 63 are disposed on a dielectric 61. The pads 63 are located closer to the semiconductor chip 10 than the upper electrode 62. The dielectric 61 is rectangular with the aforementioned long side 64. The capacitor 60 includes a plurality of pads 63. The plurality of pads 63 are located closer to the semiconductor chip 10 than the upper electrode 62. For example, a plurality of pads 63 are arranged along the long side 64. Each pad 63 is rectangular with a long side extending along the second direction A2.

[0063] As described above, the semiconductor chip 10 and the capacitor 60 are electrically connected to each other via a lead assembly 70. The lead assembly 70 includes a first lead 71, a second lead 72, and a third lead 73. The first lead 71 connects the pad 63 to the drain pad 18 of the semiconductor chip 10. The second lead 72 connects the upper electrode 62 of the capacitor 60 to the empty pad 19. The third lead 73 connects the empty pad 19 to the pad 63.

[0064] For example, the first lead 71 connecting the drain pad 18 to the pad 63, the third lead 73 connecting the empty pad 19 to the pad 63, and the second lead 72 connecting the empty pad 19 to the upper electrode 62 are arranged sequentially along the second direction A2. As an example, at least one of the first lead 71, the second lead 72, and the third lead 73 has a lead length of 0.6 mm. It should be noted that the second lead 72 may also be longer than the first lead 71 and the third lead 73.

[0065] Thus, in this embodiment, the lead group 70 connecting the semiconductor chip 10 and the capacitor 60 includes a first lead 71, a second lead 72, and a third lead 73. This shortens the lead length of each lead constituting the lead group 70. Figure 3 As illustrated, the lead length (L) is short, which results in a higher fusing current (I) for each lead.

[0066] Figure 4 This diagram represents the semiconductor chip 10, the capacitor 60, and the third lead 73. (See diagram below.) Figure 4 As shown, the semiconductor chip 10 includes, for example, an Ag-P layer 10b, an Au layer 10c, a SiC layer 10d, and a GaN layer 10f. The semiconductor chip 10 has a structure in which an Au layer 10c is disposed on the Ag-P layer 10b, a SiC layer 10d is disposed on the Au layer 10c, and a GaN layer 10f is disposed on the SiC layer 10d.

[0067] Empty pads 19 are disposed on the GaN layer 10f. Empty pads 19 may contain, for example, gold (Au). In the semiconductor chip 10, heat flows from the empty pads 19 through the GaN layer 10f to the SiC layer 10d. Heat from the lead group 70 (e.g., the third lead 73) is dissipated, thereby suppressing the melting of the lead group 70 due to heat generation. As an example, the thickness T1 of the substrate 4e is 1000 μm, the thickness T2 of the Ag-P layer 10b is 30 μm, and the thickness T3 of the Au layer 10c and the SiC layer 10d is 100 μm. The thickness T4 of the GaN layer 10f is 0.6 μm, the thickness T5 of the empty pads 19 is 10 μm, and the height H of the third lead 73 rising from the empty pads 19 is 100 μm.

[0068] For example, the substrate 15 of the semiconductor chip 10 includes an Ag-P layer 10b, an Au layer 10c, a SiC layer 10d, and a GaN layer 10f. As described above, the substrate 15 functions as a heat sink to dissipate heat generated by the device. The substrate 15 is, for example, made of a material with high heat dissipation properties. For example, the substrate 15 may have a diamond layer or a metal layer together with the SiC layer 10d, or a diamond layer or a metal layer may be used instead of the SiC layer 10d. The material of the metal layer of the substrate 15 is, for example, a red metal material containing copper or gold, or a silvery-white metal material containing silver, nickel, or aluminum.

[0069] The capacitor 60 includes, for example, an Ag-P layer 60b, an Au layer 60c, and a ceramic layer 60d. The capacitor 60 has a structure in which the Au layer 60c is disposed on the Ag-P layer 60b, and the ceramic layer 60d is disposed on the Au layer 60c. A pad 63 is disposed on the ceramic layer 60d. The pad 63 contains, for example, gold (Au). In the capacitor 60, heat from the lead group 70 (e.g., the third lead 73) is dissipated from the pad 63 to the ceramic layer 60d. As a result, melting of the lead group 70 due to heat can be suppressed.

[0070] Figure 5 It means Figure 1 A top view of the semiconductor chip 10, capacitor 60, and lead assembly 70 shown. Figure 5 As shown, the lead group 70 includes a plurality of first leads 71, a plurality of second leads 72, and a plurality of third leads 73. The lead group 70 may also have a plurality of groups 75 consisting of the first leads 71, the second leads 72, and the third leads 73. For example, the plurality of groups 75 are arranged along the second direction A2.

[0071] For example, in each group 75, the first lead 71, the third lead 73, and the second lead 72 are arranged sequentially along the second direction A2. As an example, the number of groups 75 is 9. For example, the length L1 of the second direction A2 of the empty pad 19 is longer than the length L2 of the second direction A2 of the drain pad 18. As an example, the length L1 of the empty pad 19 is 250 μm, and the length L2 of the drain pad 18 is 150 μm. The length X from the drain pad 18 located at one end of the second direction A2 to the drain pad 18 located at the other end of the second direction A2 is 5.34 mm.

[0072] Next, the effects obtained from the semiconductor device 1 of the embodiment will be explained. In the semiconductor device 1, the semiconductor chip 10 has a transistor and a drain pad 18 on a substrate 15. The capacitor 60 has an upper electrode 62 and a lower electrode sandwiching a dielectric 61. A first lead 71 connects the drain pad 18 of the semiconductor chip 10 to the pad 63. A third lead 73 connects the pad 63 to the empty pad 19. A second lead 72 connects the empty pad 19 to the upper electrode 62 of the capacitor 60. Thus, the semiconductor chip 10 and the capacitor 60 are interconnected via the first lead 71 extending from the semiconductor chip 10, the pad 63, the third lead 73, the empty pad 19 on the semiconductor chip 10, and the second lead 72 extending toward the capacitor 60.

[0073] By including a first lead 71, a pad 63, a third lead 73, an empty pad 19, and a second lead 72, the lead connected to the drain pad 18 of the semiconductor chip 10 can be used only as the first lead 71. The lead length can be shortened by interconnecting the leads via the pad 63 and the empty pad 19.

[0074] The pad 63 can also be positioned on the dielectric 61 of the capacitor 60, separate from the upper electrode 62. The empty pad 19 can also be positioned along the long side 12 of the semiconductor chip 10. In this case, the pad 63 can be positioned on the dielectric 61 of the capacitor 60. The empty pad 19 can be positioned along the long side 12 of the semiconductor chip 10 opposite the capacitor 60.

[0075] Alternatively, the drain pad 18 can be arranged along the long side 12 of the semiconductor chip 10, and the empty pad 19 can be arranged adjacent to the drain pad 18. In this case, the drain pad 18 and the empty pad 19 on the semiconductor chip 10 can be arranged in a manner that runs along the long side 12 of the semiconductor chip 10 opposite to the capacitor 60.

[0076] The semiconductor device 1 may also include: a plurality of pads 63 arranged along the long side 64 of the capacitor 60; and a plurality of empty pads 19 and a plurality of drain pads 18 arranged along the long side 12 of the semiconductor chip 10. Alternatively, each of the plurality of empty pads 19 may be configured adjacent to a drain pad 18. In this case, the plurality of pads 63 can be arranged along the long side 64 of the capacitor 60 opposite the semiconductor chip 10, and the drain pads 18 and empty pads 19 can be arranged along the long side 12 of the semiconductor chip 10 opposite the capacitor 60.

[0077] The substrate 15 can also be made of silicon carbide (SiC), diamond, or metal. In this case, the substrate 15 can be made of a material with high heat dissipation.

[0078] Next, refer to Figure 6 The semiconductor device of the first modified example will be described. For example... Figure 6 As shown, the semiconductor device of the first modified example includes a drain pad 18A, an empty pad 19B, a pad 63A, and a lead group 70A. The drain pad 18A is different from the drain pad 18, and the empty pad 19B is different from the empty pad 19. The pad 63A is different from the pad 63, and the lead group 70A is different from the lead group 70. Hereinafter, descriptions that are repeated in the description of the semiconductor device 1 described above will be omitted as appropriate.

[0079] Figure 7 It means Figure 6 The diagram shows a top view of the semiconductor chip 10A and capacitor 60A of the semiconductor device in the second direction A2 of the first modified example. Figure 7 As shown, the semiconductor chip 10A of the first modified example includes empty pads 19A and empty pads 19B. Empty pads 19A are provided at each end of the semiconductor chip 10A in the second direction A2. The shape, size, and function of empty pads 19A are, for example, the same as those of the empty pads 19 described above. Empty pads 19B, viewed from the empty pads 19A, are positioned at the center of the semiconductor chip 10A in the second direction A2. A plurality of empty pads 19B are sandwiched between a pair of empty pads 19A.

[0080] In the semiconductor device of the first modified example, one or two first leads 71 ​​are connected to the drain pad 18A. Two second leads 72 and two third leads 73 are connected to the empty pad 19B, and one or two first leads 71 ​​and one or two third leads 73 are connected to the pad 63A. In the semiconductor device of the first modified example, the empty pad 19B and the pad 63A are generally used as pads for connecting multiple leads.

[0081] Lead group 70A comprises multiple first groups 75A and multiple second groups 75B, with different lead arrangements in the first groups 75A and the second groups 75B. The first groups 75A and the second groups 75B are arranged alternately, for example, along a second direction A2. In the first group 75A, the second lead 72, the third lead 73, and the first lead 71 are arranged sequentially along the second direction A2. In the second group 75B, the first lead 71, the third lead 73, and the second lead 72 are arranged sequentially along the second direction A2. As an example, the number of first groups 75A and the number of second groups 75B are 6. For example, the length L3 of the second direction A2 of empty pad 19B and the length of the second direction A2 of pad 63A are 500 μm.

[0082] The semiconductor device of the first modified example described above includes a plurality of first leads 71 ​​and a plurality of second leads 72. Each of the plurality of adjacent first leads 71 ​​is connected to a common pad 63A. Each of the plurality of adjacent second leads 72 is connected to a common empty pad 19B. Therefore, the pads 63A and 19B can be used more efficiently as connection portions for the leads. Furthermore, the lead length of each lead in the lead group 70A can be further shortened. The shorter spacing between the leads in the lead group 70A increases the mutual inductance, thus reducing the increase in mutual inductance by shortening the lead length of each lead. Therefore, the possibility of melting of each lead in the lead group 70A can be further reduced.

[0083] More specifically, such as Figure 8 As illustrated, the lead W1 at the end of the second direction A2 is mainly affected by the closest lead W2 on one side and the next adjacent lead W3. On the other hand, lead W4 is affected by leads W2, W3, W5 and W6 on both sides. Therefore, the effective lead length based on mutual inductance varies significantly compared to lead W1. If the length of each lead is set as l, the radius of each lead is set as r, the distance of each lead from the ground height is set as h, the spacing of the leads is set as d, and the permeability of vacuum is set as μ0, then the mutual inductance M is expressed as follows (1).

[0084] [Formula 1]

[0085]

[0086] According to the above formula (1), the mutual inductance M is proportional to the length l of the lead wire, and the narrower the gap d between the leads, the greater the mutual inductance M. Therefore, the narrower the gap between the leads, the greater the mutual inductance M, and thus the length l of the leads can be shortened.

[0087] Next, refer to Figure 9 and Figure 10 The semiconductor device of the second variation will be described. Figure 9 The surfaces of the semiconductor chip 10C and capacitor 60C of the second modified example are shown. Figure 10 The back side of the semiconductor chip 10C and capacitor 60C is shown. The semiconductor chip 10C has drain pad 18A, drain pad 18B, and empty pads 19A and 19B.

[0088] In this modified example, drain pads 18A are located at each end of the semiconductor chip 10C in the second direction A2. For example, a first lead 71 is connected to drain pad 18A. Two first leads 71 ​​are connected to drain pad 18B. Two second leads 72 and two third leads 73 are connected to empty pad 19B.

[0089] Capacitor 60C includes a dielectric 61, an upper electrode 62, pads 63A and 63B. Pads 63B are provided at each end of capacitor 60C in a second direction A2. Two first leads 71 ​​and two third leads 73 are connected to pads 63A. One first lead 71 and one third lead 73 are connected to pads 63B. In a second variation, lead group 70C includes a plurality of first groups 75A and a plurality of second groups 75B arranged along the second direction A2. The second groups 75B and the first groups 75A are arranged alternately along the second direction A2.

[0090] The semiconductor chip 10C also includes a back electrode 10g, and the capacitor 60C also includes a back electrode 67. The back electrode 10g is, for example, rectangular along the long side 12, long side 13, and short side 14 of the semiconductor chip 10. The back electrode 10g is disposed on the back side of the semiconductor chip 10C, which includes the gate pads and the active region. The back electrode 10g is not disposed on the back side of the semiconductor chip 10C, which includes the drain pads 18A, 18B, and the empty pad 19B. That is, the back electrode 10g is removed from the back side of the drain pads 18A, 18B, and the empty pad 19B of the semiconductor chip 10C.

[0091] The back electrode 67 of capacitor 60C is located on the back side of the upper electrode 62. The back electrode 67 is not located on the back side of the capacitor 60C with pads 63A and 63B. That is, the back electrode 67 is removed from the back side of the pads 63A and 63B of capacitor 60C.

[0092] The semiconductor device of the second modification described above has a back electrode 67 on the back side of the capacitor 60C, located in a region other than the region opposite to the pads 63A and 63B. Thus, parasitic capacitance generated on the pads 63A and 63B can be suppressed by not providing the back electrode 67 on the back side of the pads 63A and 63B.

[0093] The second modified semiconductor device has a back electrode 10g on the back side of the semiconductor chip 10C or the back side of the substrate 15, located in a region other than the area opposite the empty pad 19B. In this way, parasitic capacitance generated on the empty pad 19B can be suppressed by not providing the back electrode 10g on the back side of the empty pad 19B.

[0094] Next, refer to Figure 11 The semiconductor device of the third variation will be described. For example... Figure 11 As shown, the semiconductor device of the third modification includes a semiconductor chip 10, a capacitor 60D, and a relay substrate 80. The capacitor 60D differs from the capacitor 60 described above in that it does not have a pad 63. The semiconductor device of the third modification has a relay pad 81 (first relay pad) provided on the relay substrate 80, which is separate from the semiconductor chip 10 and the capacitor 60D, instead of the pad 63.

[0095] The relay substrate 80 is configured as a rectangle having a long side extending in the second direction A2 and a short side extending in the first direction A1. The relay pad 81 is configured as a rectangle having a long side extending along the long side of the relay substrate 80 and a short side extending along the short side of the relay substrate 80. A plurality of first leads 71 ​​extending from each of a plurality of drain pads 18 and a plurality of third leads 73 extending from a plurality of empty pads 19 are connected to the relay pad 81.

[0096] In the semiconductor device of the third modification described above, the relay pad 81 is provided between the capacitor 60D and the semiconductor chip 10. Therefore, the relay pad 81 can be positioned in a location separate from both the capacitor 60D and the semiconductor chip 10.

[0097] The embodiments of the semiconductor device disclosed herein have been described above. However, the present invention is not limited to the embodiments or modifications described above. That is, those skilled in the art will readily recognize that the present invention can be modified and altered in various ways without changing the spirit of the technical solution. For example, the shape, size, quantity, material, and configuration of the components of the semiconductor device are not limited to the above-described contents and can be appropriately modified.

[0098] For example, in the above embodiment, an example of a semiconductor chip 10 having two amplification elements 11 has been described. However, the number of amplification elements 11 may be one, or it may be three or more, and can be changed appropriately.

[0099] In the above description, an example was given in which relay pads 81, located on a relay substrate 80 separate from the semiconductor chip 10 and the capacitor 60D, replace the pads 63 of the capacitor 60. However, it is also possible to replace the empty pads 19 of the semiconductor chip 10 with relay pads located on a relay substrate separate from the semiconductor chip 10 and the capacitor 60. In this way, the relay pads can be provided integrally with the semiconductor chip 10 or the capacitor 60, or they can be provided separately. The arrangement of the relay pads can be appropriately modified. The number and arrangement of the first lead 71, the second lead 72, and the third lead 73 can also be appropriately modified.

[0100] Explanation of reference numerals in the attached figures:

[0101] 1... Semiconductor devices

[0102] 2……Input Terminals

[0103] 3……Output terminals

[0104] 4...Packaging components

[0105] 4a, 4b...end wall

[0106] 4c, 4d... sidewalls

[0107] 4e...base plate

[0108] 9a, 9b, 9c, 9e, 9f... junction lines

[0109] 10, 10A, 10C... Semiconductor chips

[0110] 10b……Ag-P layer

[0111] 10c……Au layer

[0112] 10d...SiC layer

[0113] 10f……GaN layer

[0114] 10g...back electrode

[0115] 11……Amplifying elements

[0116] 12……Long side (one side)

[0117] 13……long side

[0118] 14……Short side

[0119] 15...Substrate

[0120] 18, 18A, 18B... Drain pads (electrode pads)

[0121] 19, 19A, 19B... Empty pads (second relay pads)

[0122] 20……Branch Circuit Board

[0123] 21...Substrate

[0124] 21a, 21b...long side

[0125] 21c, 21d... shorter side

[0126] 22……Branch Circuit

[0127] 23……Wiring pattern

[0128] 23a……Metal pad

[0129] 23b……Membrane resistance

[0130] 30……Synthetic Circuit Board

[0131] 31...Substrate

[0132] 31a, 31b... Long side

[0133] 31c, 31d... shorter sides

[0134] 31e, 31f... corners

[0135] 32...Synthetic substrate

[0136] 33……Wiring pattern

[0137] 33a……Metal pad

[0138] 33b...film resistance

[0139] 40... Filtering circuit

[0140] 50... capacitor

[0141] 60, 60A, 60C, 60D... capacitors

[0142] 60b……Ag-P layer

[0143] 60c……Au layer

[0144] 60d... Ceramic layer

[0145] 61……Dielectric

[0146] 62……Upper Electrode

[0147] Pads 63, 63A, 63B... (First relay pad)

[0148] 64……long side (one side)

[0149] 67……Back electrode

[0150] 70, 70A, 70C... lead sets

[0151] 71……First Lead

[0152] 72……Second lead

[0153] 73……Third lead

[0154] 75... groups

[0155] 75A...First Group

[0156] 75B...Second Group

[0157] 80……Relay substrate

[0158] 81……Relay pad (first relay pad)

[0159] A1……First Direction

[0160] A2……Second Direction

[0161] d……interval

[0162] M……mutual induction

[0163] W1, W2, W3, W4, W5, W6... Lead wires.

Claims

1. A semiconductor device comprising: a semiconductor chip having a transistor and an electrode pad provided on a substrate; a capacitor having an upper electrode and a lower electrode sandwiching a dielectric; a first relay pad; a second relay pad provided on the substrate of the semiconductor chip; a first lead connecting the first relay pad and the electrode pad of the semiconductor chip to each other; a second lead connecting the second relay pad and the upper electrode of the capacitor to each other; and a third lead connecting the first relay pad and the second relay pad to each other, the first relay pad being disposed at a position on the dielectric of the capacitor separate from the upper electrode, the second relay pad being disposed along one side of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the electrode pad is disposed along one side of the semiconductor chip, and the second relay pad is disposed adjacent to the electrode pad.

3. The semiconductor device according to claim 1 or 2, comprising: a plurality of the first relay pads arranged along one side of the capacitor; and a plurality of the second relay pads and a plurality of the electrode pads arranged along one side of the semiconductor chip, each of the plurality of the second relay pads being disposed adjacent to the electrode pad.

4. The semiconductor device according to claim 1 or 2, comprising a plurality of the first leads and a plurality of the second leads, each of the plurality of the first leads adjacent to each other being connected to a common first relay pad, and each of the plurality of the second leads adjacent to each other being connected to a common second relay pad.

5. The semiconductor device according to claim 1 or 2, wherein a back surface electrode is provided on a back surface of the dielectric of the capacitor in a region other than a region opposite to the first relay pad.

6. The semiconductor device according to claim 1 or 2, wherein a back surface electrode is provided on a back surface of the semiconductor chip or a back surface of the substrate in a region other than a region opposite to the second relay pad.

7. The semiconductor device according to claim 1 or 2, wherein the substrate is composed of silicon carbide, diamond, or a metal. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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