A decoding resource allocation method, device and system

Abstract

This application discloses a decoding resource allocation method, device, and system for facilitating load balancing of multiple distributed decoders in various service scenarios, facilitating decoder resource sharing and energy conservation and emission reduction for base stations. The decoding resource allocation method provided in this application includes: obtaining user data to be decoded for at least one cell from a processor via a direct memory access (DMA) controller and transmitting the data to be decoded to a scheduler within a field programmable gate array (FPGA); and allocating a decoding resource pool for the user data to be decoded for the at least one cell via the scheduler.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a decoding resource allocation method, device, and system. Background Art

[0002] In current NR (New Radio) systems, uplink Low Density Parity Check Code (LDPC) decoding is divided into X groups, each containing Y LDPC decoders. Each decoder group shares the same double-rate synchronous dynamic random access memory (DDR) for Hybrid Automatic Repeat Request (HARQ) data caching. Resource scheduling for different decoder groups is handled solely by the processor. Limited by the HARQ retransmitting user grouping strategy and the overhead of the processor allocation mechanism, decoder load distribution is uneven in most scenarios.

[0003] However, the current solution has the following problems:

[0004] In peak-speed business scenarios, each cell monopolizes all decoder resources during the decoding cycle. In some time slices, all decoders cannot be fully utilized, resulting in unbalanced load with some decoders idle, low decoder utilization, and long processing cycles that affect scheduling performance.

[0005] In low-speed service scenarios, all decoder resources are used in each cell decoding cycle, causing the decoder resources to be idle for most of the time, resulting in high energy consumption and the inability to dynamically reduce power consumption.

[0006] In summary, in the prior art, HARQ is distributed in different DDR memories and processed separately, which is not conducive to decoder resource sharing and base station energy conservation and emission reduction. Summary of the Invention

[0007] The embodiments of the present application provide a decoding resource allocation method, device, and system to facilitate load balancing of multiple distributed decoders in various business scenarios, which is beneficial to resource sharing of decoders and energy conservation and emission reduction of base stations.

[0008] An embodiment of the present application provides a decoding resource allocation method, including:

[0009] Obtaining user data to be decoded of at least one cell from the processor through the DMA controller and transmitting it to the scheduler in the field programmable gate array FPGA;

[0010] A decoding resource pool is allocated by the scheduler for the user data to be decoded in the at least one cell.

[0011] The method uses a direct memory access (DMA) controller to obtain user data to be decoded in at least one cell from a processor and transmits the data to a scheduler within a field programmable gate array (FPGA). The scheduler allocates a decoding resource pool to the user data to be decoded in the at least one cell, thereby facilitating load balancing of multiple distributed decoders in various service scenarios, facilitating decoder resource sharing and energy conservation and emission reduction for base stations, and further accelerating the scheduling of the decoding resource pool through the FPGA.

[0012] Optionally, allocating, by the scheduler, a decoding resource pool for the user data to be decoded of the at least one cell specifically includes:

[0013] The scheduler allocates a decoding resource pool to the to-be-decoded user data of the at least one cell according to an idle state of the at least one decoding resource pool.

[0014] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j, where j is a natural number;

[0015] sending the user data to be decoded of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity through the scheduling queue;

[0016] Sending the to-be-decoded data of the scheduled user to the ping-pong buffers 0-j through the first multiplexer according to the empty or full status of the ping-pong buffers;

[0017] Ping-pong buffers 0-j correspond one-to-one with decoding resource pools 0-j, and ping-pong buffer i corresponds to decoding resource pool i, where 0≤i≤j. Decoding resource pool i decodes the data in ping-pong buffer i. Decoding resource pool 0 decodes the data in ping-pong buffer 0, decoding resource pool 1 decodes the data in ping-pong buffer 1, and so on. Decoding resource pool j decodes the data in ping-pong buffer j.

[0018] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j;

[0019] The method further includes:

[0020] The hybrid automatic repeat request HARQ data of the decoding resource pools 0-j are simultaneously written into the double rate synchronous dynamic random access DDR memories 0-j through the shared cache controller.

[0021] In the embodiment of the present application, all decoding resource pools share DDR memories 0-j, and the HARQ memory capacity requirement can be reduced to 1 / j of the DDR memory capacity of the existing solution.

[0022] Optionally, the shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller;

[0023] For each of the slice controllers, the slice controller slices the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0-N, calculates each HARQ data block slice number 0-N modulo j+1 to obtain HARQ data block slices 0-j, and stores the obtained HARQ data block slices 0-j in HARQ slice buffers 0-j corresponding to the slice controller, respectively.

[0024] The data in each HARQ slice buffer i is stored in DDR memory i through the second multiplexer, where i belongs to (0, j), that is, 0≤i≤j. That is, the data in each HARQ slice buffer 0 is stored in DDR memory 0 through the multiplexer, and the data in each HARQ slice buffer 1 is stored in DDR memory 1. And so on, the data in each HARQ slice buffer j is stored in DDR memory j.

[0025] An embodiment of the present application provides a decoding resource allocation device, comprising a DMA controller, a scheduler, and at least one decoding resource pool; wherein,

[0026] The DMA controller is configured to obtain user data to be decoded of at least one cell from the processor and transmit the data to the scheduler;

[0027] The scheduler is configured to allocate a decoding resource pool for the user data to be decoded in the at least one cell.

[0028] Optionally, the scheduler allocates a decoding resource pool to the user data to be decoded of the at least one cell according to an idle state of at least one decoding resource pool.

[0029] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j;

[0030] The scheduling queue is used to send the to-be-decoded user data of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity;

[0031] The first multiplexer is configured to send the to-be-decoded data of the scheduled user to the ping-pong buffer according to the empty or full status of the ping-pong buffers 0 to j;

[0032] Ping-pong buffers 0-j correspond one-to-one with decoding resource pools 0-j, and ping-pong buffer i corresponds to decoding resource pool i, with 0≤i≤j. That is, resource pool i decodes the data in ping-pong buffer i. For example, decoding resource pool 0 decodes the data in ping-pong buffer 0, decoding resource pool 1 decodes the data in ping-pong buffer 1, and so on. Decoding resource pool j decodes the data in ping-pong buffer j.

[0033] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j;

[0034] The device further comprises:

[0035] The shared cache controller is used to write the hybrid automatic repeat request HARQ data of the decoding resource pool 0-j into the double rate synchronous dynamic random access DDR memory 0-j at the same time.

[0036] Optionally, the shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller;

[0037] Each of the slice controllers is configured to: slice the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0 to N, calculate the modulo j+1 of each HARQ data block slice number 0 to N to obtain HARQ data block slices 0 to j, and store the obtained HARQ data block slices 0 to j in HARQ slice buffers 0 to j corresponding to the slice controller, respectively;

[0038] The data in each HARQ slice buffer i is stored in DDR memory i through the second multiplexer, where i belongs to (0, j), that is, 0≤i≤j, that is, the multiplexer is used to store the data in each HARQ slice buffer 0 in DDR memory 0, store the data in each HARQ slice buffer 1 in DDR memory 1, and so on, and store the data in each HARQ slice buffer j in DDR memory j.

[0039] Optionally, the device is a field programmable gate array (FPGA).

[0040] An embodiment of the present application provides a decoding processing system, comprising a processor and any one of the above-described decoding resource allocation devices, wherein the processor transfers user data to be decoded of at least one cell to the decoding resource allocation device via direct memory access (DMA), and the decoding resource allocation device allocates decoding resources for the user data to be decoded of the at least one cell.

[0041] An embodiment of the present application provides a computing device, including:

[0042] a memory for storing program instructions;

[0043] The processor is configured to call the program instructions stored in the memory and execute any one of the methods described in accordance with the obtained program. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A schematic diagram of uplink HARQ memory allocation provided in an embodiment of the present application;

[0046] Figure 2 Schematic diagram of the user weight grouping scheme (4 users per cell) within a cell provided in an embodiment of the present application;

[0047] Figure 3 Schematic diagram of a pooling implementation framework based on HARQ shared cache (i.e., the system structure provided by an embodiment of the present application) provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of an implementation method of a scheduler in an FPGA provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the processing flow of the scheduler provided in an embodiment of the present application;

[0050] Figure 6 A block diagram of a shared cache controller provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram comparing the performance utilization of the decoding resource pool of the present solution and the existing solution provided in the embodiment of the present application;

[0052] Figure 8 A flowchart of a decoding resource allocation method provided in an embodiment of the present application;

[0053] Figure 9 A schematic diagram of the computing device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] The NR uplink HARQ buffer is bound to the decoder group and cached separately in different DDR memories. Due to the aforementioned independent HARQ packet cache limitation, the decoding resource grouping of cell users is limited by the fixed grouping limit required by retransmission HARQ. This incurs a lot of processor overhead to maintain all user HARQ packets and independently maintain X sets of HARQ buffer address lists for X groups of decoders.

[0056] On the other hand, since the HARQ memory management of multiple decoder groups is implemented in the processor, it is necessary to pre-divide all users in all cells into the decoder groups corresponding to the HARQ memory in the processor. Figure 1 As shown, multiple cell processes are processed in parallel on different processor cores, and there are a total of j+1 groups of decoders corresponding to j+1 groups of HARQ memory management tables.

[0057] If complex weighted scheduling management is added to ensure load balancing among multiple decoder groups, a maximum of one processor core will be used to uniformly maintain decoders and HARQ resource allocation for all cell users, which will result in excessive overhead.

[0058] To reduce process conflicts, currently each process is managed independently in each cell, and decoding group numbers are assigned to different users. The disadvantage of this solution is that it can lead to uneven load on decoding groups across different cells.

[0059] Taking the LDPC decoder as an example, each decoder has a throughput of 1.7 Gbps at a bit rate of 0.815. The processing capacity of X groups of decoders is X * Y * 1.7 Gbps. The decoding performance requirement for a single uplink stream (assuming 100 MHz bandwidth and 256QAM (quadrature amplitude modulation) modulation, ignoring retransmission) is 100 (Mbps) * 8 (256QAM) = 0.8 Gbps. This means that each decoder processes two streams, and the utilization efficiency needs to reach above 94%.

[0060] The user weights in a cell are allocated to X groups of decoders. If the number of users in the cell is not divisible by X, refer to Figure 2 ,Take a total of i cells with three groups of decoders as an example, and each cell has 4 and 1 users respectively, and there are 1 / 3 and 2 / 3 decoding performance losses respectively.

[0061] Table 1 Utilization efficiency of user weight grouping scheme within a cell

[0062] Decoding resources Utilization efficiency (4 users / cell) Utilization efficiency (1 user / cell) Decoder Group 0 100％ 100％ Decoder Group 1 50％ 0％ Decoder Group 2 50％ 0％

[0063] In summary, the uplink decoding scheme, which allocates decoders based on user weight within a cell, results in many idle time slices for decoders, significantly wasting utilization. Using a complex processor scheduling mechanism would increase processor utilization and impact overall processing performance. Therefore, a new uplink decoding solution is needed to facilitate load balancing across multiple distributed decoders in various service scenarios.

[0064] Therefore, the embodiments of the present application provide a decoding resource allocation method, device, and system to facilitate load balancing of multiple distributed decoders in various business scenarios, which is beneficial to resource sharing of decoders and energy conservation and emission reduction of base stations.

[0065] Among them, the method and the device are based on the same application concept. Since the principles of solving problems by the method and the device are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0066] The technical solutions provided in the embodiments of the present application can be applicable to a variety of systems, especially 5G systems. For example, applicable systems may be global system of mobile communication (GSM) systems, code division multiple access (CDMA) systems, wideband code division multiple access (WCDMA) general packet radio service (GPRS) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, universal mobile telecommunication systems (UMTS), worldwide interoperability for microwave access (WiMAX) systems, 5G systems, and 5G NR systems. These various systems include terminal devices and network devices.

[0067] The following describes in detail the various embodiments of the present application in conjunction with the accompanying drawings. It should be noted that the order in which the embodiments of the present application are presented only represents the order of the embodiments, and does not represent the advantages or disadvantages of the technical solutions provided by the embodiments.

[0068] The technical solution provided in the embodiment of the present application provides a solution for sharing the HARQ resource pool to meet the maximum utilization requirement of the decoder.

[0069] According to the previous analysis, multi-core processors handle multiple cell processes in parallel, and decoding resource pool allocation can only be performed sequentially, which affects the parallel computing performance of the multi-core processor. On the other hand, because multiple decoder groups independently cache and process, resource allocation is limited by retransmitting users. Since each resource pool has independent HARQ cache, it can only be allocated to a specific resource pool, which will also cause load imbalance between multiple resource pools.

[0070] Among them, the decoding resource pool described in the embodiment of the present application includes at least one low-density parity check code LDPC decoder.

[0071] The technical solution provided by the embodiment of the present application will release the resource allocation process of the processor, on the one hand, solve the performance loss caused by the conflict of the sorting process, and on the other hand, optimize the HARQ cache of each decoding resource pool into a shared cache, which is not restricted by the retransmission user. The user can be arbitrarily allocated to all resource pools, and the FPGA's direct memory access (DMA) transmission and active user scheduling are used to release the processor occupancy and improve the load balancing scheduling of the decoder. Among them, the specific process of the DMA transmission is that the central processing unit CPU configures the DMA descriptor to the FPGA, and the FPGA actively reads the CPU memory to complete the data transmission. The active user scheduling refers to the allocation of resource pool processing, which changes from CPU active allocation to CPU not performing allocation processing, and the resource pool is allocated by the FPGA.

[0072] The block diagram of the pooling solution based on HARQ shared cache is as follows Figure 3 As shown, the processing of multiple cells is implemented on a multi-core processor. In the technical solution provided in the embodiment of the present application, after the processor completes the processing of each cell, it prepares the data to be sent to the FPGA for decoding processing. It only needs to transfer it to the DMA controller to release the CPU resources immediately, eliminating the user weight calculation processing and other cell coordinated decoding resource scheduling processes, avoiding process blocking waiting time caused by multi-core conflicts.

[0073] Scheduling between multiple decoding resource pools is moved down to the Field-Programmable Gate Array (FPGA) for accelerated processing. The FPGA mainly includes a DMA controller, a scheduler, decoding resource pools 0 to j, a shared cache controller, and DDR memory 0 to j modules.

[0074] The function of the DMA controller is to realize DMA transmission of cell 0 to N data, that is, the transmission process is actively controlled by the FPGA, which can reduce the load of the x86 multi-core processor.

[0075] The function of the scheduler is to schedule each user to enter decoding resource pools 0 to j for LDPC decoding processing according to the idle status of decoding resource pools 0 to j.

[0076] The function of decoding resource pools 0 to j is to contain a total of j+1 groups of independent LDPC decoder resources for LDPC decoding processing of different users.

[0077] The function of the shared cache controller is to write the HARQ data of decoding resource pools 0 to j into DDR memories 0 to j simultaneously in a j+1 channel DDR memory interleaving manner.

[0078] The function of DDR memories 0 to j is to meet the storage requirements of HARQ data of j+1 decoding resource pools, with a total of j+1 groups of DDR memories.

[0079] The following provides detailed examples of the technical solutions provided in the above embodiments of the present application from two aspects.

[0080] 1. The technical solution provided by the embodiment of the present application moves the scheduling work of the multi-core processor for the decoder to the resource pool for processing, and accelerates the resource pool scheduling processing through FPGA. The scheduler is designed as follows Figure 4 shown.

[0081] The scheduler mainly includes a scheduling queue, a first multiplexer, and ping-pong buffers 0-j.

[0082] The function of the scheduling queue is to schedule the cell data transmitted by DMA according to the user-level granularity for subsequent processing. For example, user 0, user 1, ..., user X are scheduled in turn by the subsequent multiplexer.

[0083] The function of the first multiplexer is to send the scheduled users to the ping-pong buffers according to the empty or full status of the ping-pong buffers 0-j.

[0084] Ping-Pong Buffers 0-j function as follows: Each decoding resource pool corresponds to a ping-pong buffer, which can store two pieces of user data to be decoded. For example, decoding resource pool 0 corresponds to ping-pong buffer 0, decoding resource pool 1 corresponds to ping-pong buffer 1, and so on. Decoding resource pool j corresponds to ping-pong buffer j.

[0085] For example, the scheduling queue first sends the data to be decoded of user 0 to the first multiplexer. For the data to be decoded of user 0, the first multiplexer finds that ping-pong buffer 0 is idle based on the empty and full status of each ping-pong buffer 0~j, and can store the data to be decoded of user 0 in a cache in ping-pong buffer 0. Then, correspondingly, decoding resource pool 0 reads the data to be decoded of user 0 in ping-pong buffer 0 and performs decoding processing.

[0086] The specific processing flow of the scheduler, for example, Figure 5 Shown, including:

[0087] After the DMA transmission is completed, the data to be decoded by each user in the cell enters the scheduling queue in order;

[0088] The scheduling queue contains data to be decoded for users to be scheduled. The first multiplexer determines whether the subsequent ping-pong buffers 0 to j are occupied. Each ping-pong buffer can store two users. If both storage units of the two users in ping-pong buffer 0 are occupied, the two storage units of the next ping-pong buffer 1 are polled until an unoccupied ping-pong buffer is found. The data to be decoded for the user to be scheduled is then stored in the unoccupied ping-pong buffer, and the scheduling of the user to be scheduled is completed. If no unoccupied ping-pong buffer is found after traversing all ping-pong buffers 0 to j, the polling continues, starting from ping-pong buffer 0.

[0089] If the currently scheduled user enters an unoccupied ping-pong buffer, the current user scheduling is completed. If each ping-pong buffer is full of two users, no new user can be scheduled in.

[0090] The data to be decoded of all users in the scheduling queue are distributed sequentially. Once all users have completed the processing, the scheduling process is completed.

[0091] Second, HARQ buffers for decoders in multiple resource pools are usually cached independently in different resource pools. However, the disadvantage is that retransmission user scheduling is limited to the initial transmission processing resource pool. Load calculation needs to be performed after considering user priority. The load distribution algorithm is difficult and can only be managed on the processor, requiring additional processor resources and affecting processor performance. In the embodiment of the present application, the HARQ buffers of different decoding resource pools are centralized for processing as follows:

[0092] The HARQ cache for j+1 decoding resource pools uses a parallel expansion mechanism with j+1 groups of DDR controllers. This not only eliminates resource pool scheduling restrictions, but also reduces the number of user HARQ address tables maintained on the processor side from one set per resource pool to one shared by all resource pools. This eliminates the need to distinguish the cache location of the last scheduling, simplifies fair scheduling by using the same strategy for all users, and facilitates hardware-implemented scheduling.

[0093] The user HARQ address table is in the following format. The unified cache is to change the j+1 resource pools corresponding to j+1 HARQ address tables to have only one HARQ address table for the j+1 resource pools.

[0094] Table 2: HARQ address table

[0095] User index 0HARQ0 Corresponding to the address stored in DDR User index 0HARQ1 Corresponding to the address stored in DDR …… …… User index 0HARQN Corresponding to the address stored in DDR User index 1HARQ0 Corresponding to the address stored in DDR …… …… …… ……

[0096] Table 3: Comparison of HARQ cache memory usage between this solution and existing solutions

[0097]

[0098] In the embodiment of the present application, all resource pools share memory, so the HARQ memory capacity requirement can be reduced to 1 / (j+1) of the existing DDR memory capacity. Figure 3 As shown, a shared cache controller needs to be added to manage access to DDR memories 0-j.

[0099] like Figure 6 As shown, the shared cache controller includes: slice controllers 0~j, a second multiplexer, and HARQ slice caches 0~j corresponding to each slice controller, that is, slice controller 0 is correspondingly provided with HARQ slice caches 0~j, slice controller 1 is correspondingly provided with HARQ slice caches 0~j, and so on, slice controller j is correspondingly provided with HARQ slice caches 0~j.

[0100] For each of the slice controllers: the slice controller slices the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0 to N, and modulo j+1 each HARQ data block slice number 0 to N to obtain HARQ data block slices 0 to j, and stores the obtained HARQ data block slices 0 to j in the HARQ slice cache 0 to j corresponding to the slice controller; for example: slice controller 0 slices the HARQ data blocks of decoding resource pools 0 to j in units of 64 bytes to obtain HARQ data blocks Slices 0 to N, after each HARQ data block slice number 0 to N is modulo j+1, HARQ data block slices 0 to j are obtained, and the HARQ data block slices 0 to j obtained by the modulo are respectively stored in the HARQ slice buffers 0 to j corresponding to the slice controller 0, that is, HARQ data block slice 0 is stored in the HARQ slice buffer 0 corresponding to the slice controller 0, and HARQ data block slice 1 is stored in the HARQ slice buffer 1 corresponding to the slice controller 0. And so on, HARQ data block slice j is stored in the HARQ slice buffer j corresponding to the slice controller 0;

[0101] The data in each HARQ slice cache 0 (that is, the HARQ slice cache 0 corresponding to each slice controller) is stored in DDR memory 0 through the second multiplexer, and the data in each HARQ slice cache 1 (that is, the HARQ slice cache 1 corresponding to each slice controller) is stored in DDR memory 1, and so on, the data in each HARQ slice cache j (that is, the HARQ slice cache j corresponding to each slice controller) is stored in DDR memory j.

[0102] The shared cache controller slices the HARQ data of each user, encodes it modulo, and stores it in DDR memory 0 to j respectively. That is, each group of DDR memory stores 1 / (j+1) of all user HARQ data, thereby achieving the purpose of shared cache.

[0103] In summary, based on the above-mentioned optimization processing of the decoding resource pool, all users in all cells share the HARQ cache, and hardware acceleration scheduling is adopted in the resource pool, and dynamic allocation is made according to the load conditions of different decoding resource pools, thereby achieving the purpose of load balancing of all decoding resource pools. Figure 7 shown.

[0104] The technical solution provided in the embodiments of the present application implements an uplink HARQ cache pooling solution, proposes a HARQ shared cache mechanism for parallel processing scenarios of multiple resource pools, and proposes a resource pool hardware acceleration scheduling algorithm to address the limitations of the software scheduling algorithm, thereby significantly improving decoder load balancing.

[0105] See also Figure 8 On the FPGA side, a decoding resource allocation method provided in an embodiment of the present application includes:

[0106] S101. Obtain user data to be decoded of at least one cell from a processor (which may be an X86 multi-core processor) through a DMA controller and transmit the data to a scheduler in a field programmable gate array (FPGA).

[0107] S102: Allocate a decoding resource pool for the user data to be decoded in the at least one cell through the scheduler.

[0108] The decoding resource pool includes at least one low-density parity check code LDPC decoder.

[0109] The method uses a direct memory access (DMA) controller to obtain user data to be decoded in at least one cell from a processor and transmits the data to a scheduler within a field programmable gate array (FPGA). The scheduler allocates a decoding resource pool to the user data to be decoded in the at least one cell, thereby facilitating load balancing of multiple distributed decoders in various service scenarios, facilitating decoder resource sharing and energy conservation and emission reduction for base stations, and further accelerating the scheduling of the decoding resource pool through the FPGA.

[0110] Optionally, allocating, by the scheduler, a decoding resource pool for the user data to be decoded of the at least one cell specifically includes:

[0111] The scheduler allocates a decoding resource pool to the to-be-decoded user data of the at least one cell according to an idle state of the at least one decoding resource pool.

[0112] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j, where j is a natural number;

[0113] sending the user data to be decoded of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity through the scheduling queue;

[0114] Sending the to-be-decoded data of the scheduled user to the ping-pong buffers 0-j through the first multiplexer according to the empty or full status of the ping-pong buffers;

[0115] Among them, ping-pong buffers 0-j correspond one-to-one with the decoding resource pools 0-j, and ping-pong buffer i corresponds to decoding resource pool i, 0≤i≤j. Decoding resource pool i is used to decode the data in ping-pong buffer i. Decoding resource pool 0 is used to decode the data in ping-pong buffer 0, decoding resource pool 1 is used to decode the data in ping-pong buffer 1, and so on. Decoding resource pool j is used to decode the data in ping-pong buffer j.

[0116] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j;

[0117] The method further includes:

[0118] The hybrid automatic repeat request HARQ data of the decoding resource pools 0-j are simultaneously written into the double rate synchronous dynamic random access DDR memories 0-j through the shared cache controller.

[0119] In the embodiment of the present application, all decoding resource pools share DDR memories 0-j, and the HARQ memory capacity requirement can be reduced to 1 / (j+1) of the DDR memory capacity of the existing solution.

[0120] Optionally, the shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller;

[0121] For each of the slice controllers, the slice controller slices the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0-N, calculates each HARQ data block slice number 0-N modulo j+1 to obtain HARQ data block slices 0-j, and stores the obtained HARQ data block slices 0-j in HARQ slice buffers 0-j corresponding to the slice controller, respectively.

[0122] The data in each HARQ slice buffer i is stored in DDR memory i through the second multiplexer, where i belongs to (0, j), that is, 0≤i≤j. That is, the data in each HARQ slice buffer 0 is stored in DDR memory 0 through the multiplexer, and the data in each HARQ slice buffer 1 is stored in DDR memory 1. And so on, the data in each HARQ slice buffer j is stored in DDR memory j.

[0123] The embodiment of the present application provides a decoding resource allocation device (see Figure 3 ), including a DMA controller, a scheduler and at least one decoding resource pool; wherein,

[0124] The DMA controller is configured to obtain user data to be decoded of at least one cell from the processor and transmit the data to the scheduler;

[0125] The scheduler is configured to allocate a decoding resource pool for the user data to be decoded in the at least one cell.

[0126] Optionally, the scheduler allocates a decoding resource pool to the user data to be decoded of the at least one cell according to an idle state of at least one decoding resource pool.

[0127] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler (see Figure 4 ) includes a scheduling queue, a first multiplexer, and ping-pong buffers 0-j;

[0128] The scheduling queue is used to send the to-be-decoded user data of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity;

[0129] The first multiplexer is configured to send the to-be-decoded data of the scheduled user to the ping-pong buffer according to the empty or full status of the ping-pong buffers 0-j;

[0130] Among them, ping-pong buffers 0-j correspond one-to-one with the decoding resource pools 0-j, and ping-pong buffer i corresponds to decoding resource pool i, with 0≤i≤j. Decoding resource pool i is used to decode the data in ping-pong buffer i. That is, decoding resource pool 0 is used to decode the data in ping-pong buffer 0, decoding resource pool 1 is used to decode the data in ping-pong buffer 1, and so on. Decoding resource pool j is used to decode the data in ping-pong buffer j.

[0131] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j;

[0132] The device also includes (see Figure 3 ):

[0133] The shared cache controller is used to write the hybrid automatic repeat request HARQ data of the decoding resource pool 0-j into the double rate synchronous dynamic random access DDR memory 0-j at the same time.

[0134] Optionally, the shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller;

[0135] Each of the slice controllers is configured to: slice the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0 to N, calculate the modulo j+1 of each HARQ data block slice number 0 to N to obtain HARQ data block slices 0 to j, and store the HARQ data block slices 0 to j in HARQ slice buffers 0 to j corresponding to the slice controller, respectively;

[0136] The data in each HARQ slice buffer i is stored in DDR memory i through the second multiplexer, where i belongs to (0, j), that is, 0≤i≤j, that is, the second multiplexer is used to store the data in each HARQ slice buffer 0 in DDR memory 0, store the data in each HARQ slice buffer 1 in DDR memory 1, and so on, and store the data in each HARQ slice buffer j in DDR memory j.

[0137] Optionally, the device is a field programmable gate array (FPGA).

[0138] The present application provides a decoding processing system, for example, see Figure 3 , including a processor (e.g. Figure 3 The multi-core processor shown) and any of the decoding resource allocation devices (such as Figure 3 The processor transfers the to-be-decoded user data of at least one cell to the decoding resource allocation device through direct memory access (DMA), and the decoding resource allocation device allocates decoding resources for the to-be-decoded user data of the at least one cell.

[0139] refer to Figure 9 As shown, an embodiment of the present application provides a computing device, which may specifically be a desktop computer, a portable computer, a smart phone, a tablet computer, a personal digital assistant (PDA), etc. The computing device may include a central processing unit (CPU), a memory 100, input / output devices, etc. The input device may include a keyboard, a mouse, a touch screen, etc., and the output device may include a display device such as a liquid crystal display (LCD) or a cathode ray tube (CRT).

[0140] The memory 100 may include a read-only memory (ROM) and a random access memory (RAM), and provides program instructions and data stored in the memory to the processor 200. In the embodiment of the present application, the memory may be used to store the program of any of the methods provided in the embodiment of the present application.

[0141] The processor 200 calls the program instructions stored in the memory to execute any of the methods provided in the embodiments of the present application according to the obtained program instructions.

[0142] For example, the processor 200 is used to obtain user data to be decoded of at least one cell from the processor through a DMA controller and transmit it to a scheduler in a field programmable gate array FPGA; and the scheduler allocates a decoding resource pool for the user data to be decoded of the at least one cell.

[0143] The decoding resource pool includes at least one low-density parity check code LDPC decoder.

[0144] The DMA controller obtains user data to be decoded of at least one cell from the processor and transmits it to a scheduler within a field programmable gate array (FPGA). The scheduler allocates a decoding resource pool for the user data to be decoded of the at least one cell, thereby facilitating load balancing of multiple distributed decoders in various service scenarios, facilitating resource sharing among decoders and energy conservation and emission reduction at the base station. Furthermore, the FPGA can further accelerate the scheduling of the decoding resource pool.

[0145] Optionally, allocating, by the scheduler, a decoding resource pool for the user data to be decoded of the at least one cell specifically includes:

[0146] The scheduler allocates a decoding resource pool to the to-be-decoded user data of the at least one cell according to an idle state of the at least one decoding resource pool.

[0147] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j, where j is a natural number;

[0148] sending the user data to be decoded of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity through the scheduling queue;

[0149] Sending the to-be-decoded data of the scheduled user to the ping-pong buffers 0-j through the first multiplexer according to the empty or full status of the ping-pong buffers;

[0150] Among them, ping-pong buffers 0-j correspond one-to-one with the decoding resource pools 0-j, and ping-pong buffer i corresponds to decoding resource pool i, 0≤i≤j. Decoding resource pool i is used to decode the data in ping-pong buffer i. Decoding resource pool 0 is used to decode the data in ping-pong buffer 0, decoding resource pool 1 is used to decode the data in ping-pong buffer 1, and so on. Decoding resource pool j is used to decode the data in ping-pong buffer j.

[0151] Optionally, the at least one decoding resource pool includes decoding resource pools 0 to j;

[0152] The processor 200 is further configured to simultaneously write the hybrid automatic repeat request HARQ data of the decoding resource pools 0-j into the double rate synchronous dynamic random access memory DDR memories 0-j through the shared cache controller.

[0153] In the embodiment of the present application, all decoding resource pools share DDR memories 0-j, and the HARQ memory capacity requirement can be reduced to 1 / (j+1) of the DDR memory capacity of the existing solution.

[0154] Optionally, the shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller;

[0155] For each of the slice controllers, the slice controller slices the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0-N, calculates each HARQ data block slice number 0-N modulo j+1 to obtain HARQ data block slices 0-j, and stores the obtained HARQ data block slices 0-j in HARQ slice buffers 0-j corresponding to the slice controller, respectively.

[0156] The data in each HARQ slice buffer i is stored in DDR memory i through the second multiplexer, where i belongs to (0, j), that is, 0≤i≤j. That is, the data in each HARQ slice buffer 0 is stored in DDR memory 0 through the second multiplexer, and the data in each HARQ slice buffer 1 is stored in DDR memory 1. And so on, the data in each HARQ slice buffer j is stored in DDR memory j.

[0157] An embodiment of the present application provides a computer storage medium for storing computer program instructions used by the apparatus provided in the above-mentioned embodiment of the present application, which includes a program for executing any of the methods provided in the above-mentioned embodiment of the present application.

[0158] The computer storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO)), optical storage (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid-state drives (SSDs), etc.).

[0159] The above method processing flow can be implemented by a software program, and the software program can be stored in a storage medium. When the stored software program is called, the above method steps are executed.

[0160] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0161] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0162] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0163] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0164] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A decoding resource allocation method, characterized in that: The method comprises: Obtaining user data to be decoded of at least one cell from the processor through the DMA controller and transmitting it to the scheduler in the field programmable gate array FPGA; Allocating, by the scheduler, a decoding resource pool for user data to be decoded of the at least one cell according to an idle state of the at least one decoding resource pool; The at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j, where j is a natural number; sending the user data to be decoded of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity through the scheduling queue; Sending the to-be-decoded data of the scheduled user to the ping-pong buffers 0-j through the first multiplexer according to the empty or full status of the ping-pong buffers; Among them, ping-pong buffers 0-j correspond one-to-one to the decoding resource pools 0-j, ping-pong buffer i corresponds to decoding resource pool i, and 0≤i≤j.

2. The method according to claim 1, characterized in that The at least one decoding resource pool includes decoding resource pools 0 to j; The method further comprises: The hybrid automatic repeat request HARQ data of the decoding resource pools 0-j are simultaneously written into the double rate synchronous dynamic random access DDR memories 0-j through the shared cache controller.

3. The method according to claim 2, characterized in that The shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller; For each of the slice controllers, the slice controller slices the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0-N, calculates each HARQ data block slice number 0-N modulo j+1 to obtain HARQ data block slices 0-j, and stores the obtained HARQ data block slices 0-j in HARQ slice buffers 0-j corresponding to the slice controller, respectively. The data in each HARQ slice buffer i is stored in the DDR memory i through the second multiplexer, where 0≤i≤j.

4. A decoding resource allocation device, characterized in that: The device includes: a DMA controller, a scheduler and at least one decoding resource pool; wherein, The DMA controller is configured to obtain user data to be decoded of at least one cell from the processor and transmit the data to the scheduler; The scheduler is configured to allocate a decoding resource pool to user data to be decoded of the at least one cell according to an idle state of the at least one decoding resource pool; The at least one decoding resource pool includes decoding resource pools 0 to j; the scheduler includes a scheduling queue, a first multiplexer, and ping-pong buffers 0 to j; The scheduling queue is used to send the to-be-decoded user data of the cell transmitted by the DMA controller to the first multiplexer according to the user-level granularity; The first multiplexer is configured to send the to-be-decoded data of the scheduled user to the ping-pong buffer according to the empty or full status of the ping-pong buffers 0-j; Among them, ping-pong buffers 0-j correspond one-to-one to the decoding resource pools 0-j, ping-pong buffer i corresponds to decoding resource pool i, and 0≤i≤j.

5. The device according to claim 4, characterized in that The at least one decoding resource pool includes decoding resource pools 0 to j; The device further comprises: The shared cache controller is used to write the hybrid automatic repeat request HARQ data of the decoding resource pool 0-j into the double rate synchronous dynamic random access DDR memory 0-j at the same time.

6. The device according to claim 5, characterized in that The shared cache controller includes: slice controllers 0-j, a second multiplexer, and HARQ slice caches 0-j corresponding to each slice controller; Each of the slice controllers is configured to: slice the HARQ data blocks of each decoding resource pool in units of 64 bytes to obtain HARQ data block slices 0 to N, calculate the modulo j+1 of each HARQ data block slice number 0 to N to obtain HARQ data block slices 0 to j, and store the obtained HARQ data block slices 0 to j in HARQ slice buffers 0 to j corresponding to the slice controller, respectively; The data in each HARQ slice buffer i is stored in the DDR memory i through the second multiplexer, where 0≤i≤j.

7. The device according to any one of claims 4 to 6, characterized in that: The device is a field programmable gate array FPGA.

8. A decoding processing system, characterized in that: The method comprises a processor and a decoding resource allocation device according to any one of claims 4 to 7, wherein the processor transfers user data to be decoded of at least one cell to the decoding resource allocation device through direct memory access (DMA), and the decoding resource allocation device allocates decoding resources for the user data to be decoded of the at least one cell.

9. A computing device, characterized in that include: a memory for storing program instructions; A processor, configured to call the program instructions stored in the memory and execute the method according to any one of claims 1 to 3 according to the obtained program.

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