A heterogeneous SoC chip multi-core processor soft error detection system and method

Abstract

The application discloses a kind of heterogeneous SoC chip multicore processor soft error detection system and method, the system includes APU application unit and RPU error detection unit, wherein, APU application unit includes core application module and data sampling module, core application module will three copies of core application be respectively deployed in different kernel;Data sampling module is used to collect the field information of core application in different kernel in core application module at preset time;RPU error detection unit includes data receiving module and soft error detection module, data receiving module is used to receive sampling data and carries out preliminary timeout judgment according to the arrival time of sampling data of different kernel, when there is certain kernel timeout, then determine fault kernel, if all are not timeout, then soft error detection module is used to carry out soft error detection to sampling information.The timer of the present application is independent of user code, no longer needs to analyze user code, improves the efficiency of engineering designer.

Description

Technical Field

[0001] This invention belongs to the field of soft error detection technology, specifically relating to a soft error detection system and method for heterogeneous SoC chip multi-core processors. Background Technology

[0002] Trapped by the Earth's magnetic field, the near-Earth space environment contains a large number of space radiation particles capable of producing radiation effects. Currently known space radiation particles mainly consist of protons, electrons, alpha particles, heavy ions, and gamma rays, forming the Earth's radiation belts in near-Earth space. When sufficiently high-energy space radiation particles collide with the PN junction of an integrated circuit, the PN junction will experience logic state flipping or circuit failure; this system failure phenomenon is called a single-event event. In 2010, Xilinx, an American manufacturer, launched a "FPGA + processor" SoC chip, naming its first product the Zynq-7000. The Zynq-7000 tightly integrates an ARM Cortex-A9 MPCore processor system with programmable logic FPGA on a single chip, giving the Zynq series devices many characteristics such as flexibility, configurability, and high performance. Therefore, Zynq devices attracted the interest of many aerospace units, including NASA, upon their release. Subsequently, Xilinx further launched an MPSoC chip combining an "FPGA + ARM Cortex-A53 quad-core processor + ARM Cortex-R5 dual-core processor," significantly improving processing performance.

[0003] Currently, there are two main types of soft error detection methods for Zynq multi-core processors. In the first method, the dual-core processor is the primary application target for Zynq-7000 devices, running in a dual-core comparison mode, with the checking circuitry set up separately within the FPGA. The second method treats the Zynq MPSoC device as the protection target, with the FPGA as the main application function provider, and the multi-core processor handling the scheduling of the entire task. The multi-core processor runs in a three-core comparison mode, with the information comparison unit handled by a real-time processing unit with a lockstep mechanism. The three-core comparison mode not only detects soft errors but also identifies the faulty core. Both methods implement soft error detection at the assembly language level. Specifically, the task's assembly code is divided into basic blocks according to certain rules, and a checkpoint is set at the end of each basic block. The basic blocks function to locate the processor's soft error location. When the task reaches a checkpoint, it sends specified variable information to the checking circuitry or information comparison unit, which then determines whether a single-event soft error has occurred in the processor.

[0004] The disadvantages of existing technologies are: 1) The technical implementation level is assembly language, while current tasks often involve large amounts of C language code, which is very difficult to implement; 2) The basic block division rules in existing technologies are cumbersome. For large-scale tasks, basic block division requires a lot of effort and is inefficient; 3) The dual-core comparison method cannot locate the faulty core, which is detrimental to the subsequent recovery of the faulty core; 4) In large-scale aerospace missions, FPGAs are often used as the functional core, so FPGA logic resources are scarce. Designing a check circuit specifically for the processor requires squeezing out the logic resources of the FPGA design. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a software error detection system and method for heterogeneous SoC chip multi-core processors.

[0006] One aspect of the present invention provides a soft error detection system for a heterogeneous SoC chip multi-core processor, including an APU application unit and an RPU error detection unit, wherein,

[0007] The APU application unit includes a core application module and a data sampling module. The core application module deploys three identical core applications in different processor cores and sets a predetermined running time for each core application. The data sampling module is used to collect on-site information of the core applications in different cores of the core application module at a preset time.

[0008] The RPU error detection unit includes a data receiving module and a soft error detection module. The data receiving module receives sampled data obtained from the data sampling module and performs a preliminary timeout judgment based on the arrival time of the sampled data of different kernels. If a kernel times out, the current kernel is directly determined to be a faulty kernel. If the sampling time of multiple kernels has not timed out, the collected data is transmitted to the soft error detection module. The soft error detection module performs soft error detection on the sampled information to obtain the fault location and fault type.

[0009] In one embodiment of the present invention, the core application module further includes a sampling timer. When the timer interrupt of the sampling timer is triggered, each kernel switches to the data sampling module to perform data sampling of the core applications in different kernels of the core application module.

[0010] In one embodiment of the present invention, the runtime of different kernels in the core application module satisfies:

[0011]

[0012] Where t1 represents the start time of the first kernel, t2 represents the start time of the second kernel, t3 represents the start time of the third kernel, Δt1 represents the time difference between the first and second kernels, Δt2 represents the time difference between the second and third kernels, Δt represents the time difference between the first and third kernels, and T represents the time difference between the first and third kernels. m This indicates the runtime of each core application module.

[0013] In one embodiment of the present invention, the data sampling module includes a data sampling component and a data transmission component, wherein,

[0014] The data sampling component is used to obtain key information for detecting single-event soft errors in the core application module, including the kernel ID and data in general-purpose registers, floating-point registers, program counters, stack pointer registers, and program status registers;

[0015] The data transmission component is used to send an interrupt mask to the data receiving module to inform the RPU error detection unit to complete the data sampling task.

[0016] In one embodiment of the present invention, the data receiving module includes an information recording component, a timing component, and a preliminary fault analysis component, wherein,

[0017] The information recording component receives and saves sampled data from different kernels of the data sampling module;

[0018] The timing component is used to record the arrival time of each interrupt and the order in which the interrupt kernels arrive when a start interrupt request is received from the APU application unit, forming a kernel vector O = <F,S,T,Δt FS ,Δt ST >, where F represents the first received kernel number, S represents the second received kernel number, T represents the third received kernel number, and Δt FS Δt represents the time difference between the arrival of the sampled signals from the first and second kernels. ST This indicates the time difference between the arrival of the sampling signals from the second and third kernels;

[0019] The preliminary fault analysis component, based on the kernel vector O provided by the timing component, determines whether each kernel has prematurely issued an interrupt or failed to issue an interrupt within a timeout period, performs a preliminary analysis of abnormal kernels, and updates the kernel abnormal state E. i .

[0020] In one embodiment of the present invention, the soft error detection module includes a similarity analysis component, a fault cause analysis component, and a fault model matching component, wherein,

[0021] The similarity analysis component is used to receive data and abnormal states of each kernel from the data receiving module and calculate the overall similarity of the kernel data;

[0022] The fault cause analysis component is used to analyze and locate fault causes based on pre-set rules for calculating the number of abnormal bits and a fault kernel location algorithm.

[0023] The fault model matching component is used to obtain a fault model based on the fault cause analysis and location results.

[0024] Another aspect of the present invention provides a method for detecting soft errors in a heterogeneous SoC chip multi-core processor, comprising:

[0025] S1: Deploy three identical core applications on different processor cores and set a predetermined time difference for the three core applications;

[0026] S2: Collect on-site information of core applications in different kernels at preset times;

[0027] S3: Make a preliminary timeout judgment based on the arrival time of the collected data from different kernels. If a kernel times out, the current kernel is directly determined to be a faulty kernel. If the arrival time of multiple kernels has not timed out, proceed to step S4.

[0028] S4: Perform soft error detection on the sampled information of the multiple kernels to obtain the fault location and fault type.

[0029] In one embodiment of the present invention, S1 further includes:

[0030] A sampling timer is set so that when the timer interrupt is triggered, each kernel switches to the data sampling module to perform data sampling of the core applications in different kernels.

[0031] In one embodiment of the present invention, S3 includes...

[0032] Upon receiving a timer interrupt request from the sampling timer, the arrival time of each interrupt and the order in which the interrupt kernels arrive are recorded, forming a kernel vector O = <F,S,T,Δt FS ,Δt ST >, where F represents the first received kernel number, S represents the second received kernel number, T represents the third received kernel number, and Δt FS Δt represents the time difference between the arrival of the sampled signals from the first and second kernels. ST This indicates the time difference between the arrival of the sampling signals from the second and third kernels;

[0033] Based on the kernel vector O provided by the timing component, it is determined whether each kernel issued an interrupt prematurely or failed to issue an interrupt within a timeout period. An abnormal kernel is preliminarily analyzed, and the kernel abnormal state E is updated. i .

[0034] In one embodiment of the present invention, S4 includes:

[0035] The overall similarity of kernel data is calculated based on the sampled data and abnormal states of each kernel.

[0036] Based on the pre-set rules for calculating the number of abnormal bits and the fault kernel location algorithm, the cause of the fault is analyzed and the fault is located, and the fault type is obtained.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] 1. The technical implementation level of the heterogeneous SoC chip multi-core processor soft error detection system of the present invention is C language, which greatly reduces the engineering difficulty compared with the assembly language level soft error detection method. The present invention adopts a timer-based soft error detection method. The timer and user code are independent of each other. Therefore, the engineers only need to set the timer in the user code, and no longer need to analyze the user code, which improves the efficiency of the engineers.

[0039] 2. The most significant feature of the method of this invention is that it supports the location of faulty kernels and the accurate matching of fault models, providing support for the targeted recovery of faulty kernels in the future; the three-core comparison function is transferred to the processor core, preserving sufficient FPGA resources.

[0040] 3. In addition to supporting the location of faulty kernels, the data sampling and detection method mentioned in this invention can more precisely locate the cause of faults and analyze the possible impact of faults on tasks, thereby further improving detection accuracy.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0042] Figure 1 This is a structural block diagram of a heterogeneous SoC chip multi-core processor soft error detection system provided in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram illustrating the working process of a heterogeneous SoC chip multi-core processor soft error detection system provided in an embodiment of the present invention;

[0044] Figure 3 This is a flowchart of a single-core data sampling process for an APU application unit provided in an embodiment of the present invention;

[0045] Figure 4This is a timing diagram for multi-core synchronous sampling of an APU application unit provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the structure of a data receiving module of an RPU error detection unit provided in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of the structure of a soft error detection module of an RPU error detection unit provided in an embodiment of the present invention;

[0048] Figure 7 This is a flowchart of an abnormal fault detection method provided in an embodiment of the present invention;

[0049] Figure 8 This is a flowchart of a method for detecting soft errors in a heterogeneous SoC chip multi-core processor, provided in an embodiment of the present invention. Detailed Implementation

[0050] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a software error detection system and method for heterogeneous SoC chip multi-core processors proposed according to the present invention.

[0051] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0053] Example 1

[0054] SoC, short for System On Chip, integrates multiple systems onto a single chip, consisting of an FPGA and a multi-core processor, with the multi-core processor handling management and scheduling. This embodiment addresses single-event effects on SoC chips in a space radiation environment, focusing on designing methods for detecting and identifying soft errors in multi-core processors, thereby ensuring timely detection and location of processor soft errors. The embodiment uses an MPSoC chip, containing an FPGA, a quad-core Cortex-A53 processor, and a dual-core Cortex-R5 processor. The quad-core Cortex-A53 processor is referred to as the Application Processing Unit (APU), and the dual-core Cortex-R5 processor as the Real-time Processing Unit (RPU). Currently, single-event upsets are known to occur in 65nm memory chips. With significant advancements in chip manufacturing processes, such as the 28nm process used in this embodiment, and the reduction in operating voltage of electronic devices, the probability of single-event effects in memory or triggers is increasing.

[0055] This embodiment proposes a single-event soft error detection system for multi-core processors based on heterogeneous SoC chips. The system in this embodiment requires the RPU to be configured in lockstep mode, serving as a high-reliability unit within the heterogeneous SoC chip. This embodiment proposes an APU data synchronization sampling mechanism to ensure synchronous data sampling across the APU's multi-core processors. The APU soft error detection technology proposed in this embodiment can promptly detect soft errors occurring within the APU, locate abnormal kernels, and further identify the type of soft error.

[0056] In this invention, the RPU and APU communicate with each other via inter-processor communication. The specific implementation methods for shared memory and inter-processor interrupts are known to those skilled in the art and are not limited herein.

[0057] Please see Figure 1 and Figure 2 , Figure 1 This is a structural block diagram of a heterogeneous SoC chip multi-core processor soft error detection system provided in an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the working process of a heterogeneous SoC chip multi-core processor soft error detection system provided in an embodiment of the present invention. The soft error detection system includes an APU application unit 1 and an RPU error detection unit 2. The APU application unit 1 includes a core application module 11 and a data sampling module 12. The core application module 11 deploys three identical core applications in different processor cores and sets a predetermined runtime difference for the three core applications. The data sampling module 12 is used to collect the on-site information of the core applications in different cores of the core application module at a preset time.

[0058] RPU error detection unit 2 includes a data receiving module 21 and a soft error detection module 22. The data receiving module 21 is used to receive the sampled data obtained from the data sampling module 12 and perform preliminary timeout judgment based on the arrival time of the sampled data of different kernels. If a kernel times out, the current kernel is directly determined to be a faulty kernel. If the sampling time of multiple kernels has not timed out, the collected data is transmitted to the soft error detection module 22. The soft error detection module 22 is used to perform soft error detection on the sampled information, obtain the fault location and fault type, and enable the APU application unit to enter the fault recovery mechanism when a soft error occurs.

[0059] Specifically, in this embodiment, the APU is referred to as APU Application Unit 1, which specifically includes a core application module 11 and a data sampling module 12; the RPU is referred to as RPU Error Detection Unit 2, which specifically includes a data receiving module 21 and a soft error detection module 22. APU Application Unit 1 is the decision-maker for the management and scheduling of heterogeneous SoC chips. The core application module 11 is the carrier of specific tasks, and the data sampling module 12 collects the on-site information of the core application module 11, providing basic data support for soft error detection. RPU Error Detection Unit 2 executes a lockstep mechanism, specifically including the data receiving module 21 and the soft error detection module 22, and is responsible for detecting and analyzing soft errors in the APU Application Unit.

[0060] Furthermore, the core application module 11 replicates the core application three times, deploying each copy on a different processor core. Since the core application is identical, there may be contention for peripheral or internal resources. To mitigate the potential adverse effects of resource contention, a time difference is set for the three copies of the core application. Afterward, the core application module 11 officially runs. The core application is the object of soft error detection and constitutes the core application module. All other modules serve the soft error detection within the core application. It should be noted that the heterogeneous SoC chip we are using, the Arm Cortex-A53 processor in the APU, is a quad-core processor; however, in this task scenario, we did not fully utilize this resource, using only three cores. The remaining core may be used in future tasks.

[0061] Furthermore, the core application module 1 also includes a sampling timer. When the sampling timer's timer interrupt is triggered, each kernel switches to the data sampling module to perform data sampling of the core applications in different kernels within the core application module. The sampling timer ensures that the data sampling of the three kernels is synchronized. When the core application runs, the timer interrupt is triggered, the core application module is blocked, and it enters the data sampling module. The data sampling module 12 collects the context information of the core application module 11 before the interrupt and sends the sampled data in the form of an inter-processor interrupt (IPI).

[0062] The data receiving module 21 receives the sampling information from the three cores sequentially and performs a preliminary timeout judgment based on the arrival time of the sampling signals from the three cores. If any core times out, it can be directly determined as a faulty core, and the faulty core should enter the fault recovery mechanism. If the sampling information from the three cores has not timed out, the data receiving module 21 further transmits the sampling signals to the soft error detection module 22.

[0063] The soft error detection module 22 performs single-event soft error diagnosis and localization, as well as analyzes the type of soft error. If the soft error detection module 22 detects a soft error, the APU application unit 1 enters the fault recovery mechanism. If the soft error detection module 22 does not detect a soft error, it continues to determine whether the core application has completed. If it has, it proceeds to the next task cycle; otherwise, it resumes the operation of the core application.

[0064] Figure 3 This is a flowchart of a single-core data sampling process for an APU application unit provided in this embodiment of the invention. The data sampling module 12 in this embodiment includes a data sampling component and a data transmission component. The data sampling operation is jointly performed by the data sampling component and the data transmission component. The data sampling component is used to detect key information about single-event soft errors in the core application module in a timely and accurate manner, and consists of data from the kernel ID, general-purpose registers, floating-point registers, program counter, stack pointer register, and program status register. In this embodiment, the sampling signal in the data sampling module 12 is specified as type HeartInfo and satisfies rules 1 and 2, as shown in Table 1 for specific definitions and usage.

[0065] Rule 1: Kernel numbers 1, 2, and 3 correspond to the sampled signal HB respectively. A HB B HB C The correspondence remains unchanged;

[0066] Rule 2: Once the kernel number is determined, it remains fixed.

[0067] Table 1. Definition method of sampling signal

[0068]

[0069] In this embodiment, the triggering mechanism of the data sampling module 12 is a timer interrupt. When the sampling timer's timer interrupt is triggered, the core application module 11 suspends its operation and automatically switches to the data sampling module 12. The processor responds to the interrupt and saves the interrupt context, pushing the pre-interrupt context data of the core application module onto the stack so that the core application module 11 can be restored after the data sampling module 12 finishes sampling. In the data sampling module 12, the stack register value is read to obtain the storage address of the interrupt stack. By traversing the interrupt stack, the register data of all core application modules is obtained, and the register data is organized and packaged into a HeartInfo type.

[0070] Subsequently, the data transmission component calls Write_Mem(u64 Addr, u64 HB) to set the address to be written to the shared memory area and the sampling signal, thereby writing sampled data to the shared memory area. Afterward, the data transmission component 122 sets the IPI interrupt mask IPI_MASK to inform the RPU error detection unit that the data sampling task has been completed.

[0071] Please see Figure 4 , Figure 4 This is a timing diagram of multi-core synchronous sampling in the APU application unit according to an embodiment of the present invention. The multi-core synchronous sampling mechanism is fundamental to the correct analysis of abnormal kernels in the APU application unit. For example... Figure 4 As shown, firstly, three identical project files are generated for APU application unit 1, differing only in the lscript.ld script file. The lscript.ld script assigns different OCM address spaces to the three project files: 0x0001-0x1000 for the first kernel, 0x1001-0x2000 for the second kernel, and 0x2001-0x3000 for the third kernel. Secondly, each kernel has a start interrupt and a timer interrupt. The start interrupt is triggered at the beginning of core application module 11, informing RPU error detection unit 2 of the kernel execution order and start time. The start interrupt sequentially sends IPI interrupts to RPU error detection unit 2, reporting the start times t1, t2, and t3 of the three kernels in APU application unit 1, then initializes the kernel's private timer and begins running the core application module. The timer interrupt completes its initial settings after the start interrupt is triggered. The start interrupt and timer interrupt settings are as follows:

[0072] XIpiPsu_TriggerIpi(); / / Trigger the start interrupt

[0073] TimerInterruptInit(); / / Initial settings for timer interrupt

[0074] See also Figure 4 The runtime of the data sampling module must be less than the runtime of the core application module. In APU application unit 1, the runtime T of the core application module 11 is... m The running time T of the data sampling module s T m It is a constant value, and also the trigger time of the timer interrupt, T. s This may vary depending on the RPU error detection unit. s and T m Rule 3 must be satisfied.

[0075] Rule 3: The cycle is defined as one completion by the core application module and the data sampling module. The cycle is variable, and within any task cycle, T s Always less than T m ,Right now

[0076] It should be noted that the different kernel execution times are one of the prerequisites for multi-core data synchronous sampling, and also the basis for the single-event soft error detection module. The time difference between kernel execution times should be much smaller than the execution time T of the core application module. m The kernel runtime satisfies Formula 1.

[0077]

[0078] Where t1 is the start time of the first kernel, t2 is the start time of the second kernel, t3 is the start time of the third kernel, Δt1 is the time difference between the first and second kernels, Δt2 is the time difference between the second and third kernels, and Δt is the time difference between the first and third kernels.

[0079] When the sampling timer's timer interrupt is triggered, each kernel switches to the data sampling module to complete the data sampling work for the core application module. Waiting for the soft error detection module to send back a continue command, the data sampling module resets the sampling timer, thus ensuring that the running time of the soft error detection modules in the three kernels remains consistent.

[0080] Furthermore, the memory of the RPU error detection unit 2 includes two task modules: a data receiving module 21 and a soft error detection module 22. The data receiving module 21 is responsible for receiving data from the APU application unit, and the soft error detection module 22 is responsible for detecting whether a single-event soft error has occurred in the APU application unit.

[0081] Specifically, please see Figure 5 , Figure 5This is a schematic diagram of the structure of a data receiving module for an RPU error detection unit provided in an embodiment of the present invention. The data receiving module 21 of this embodiment includes three receiving ports HB. A HB B HB C and three output ports HB A ′、HB B ′、HB C The receiving port is responsible for receiving sampled data from the data sampling module. The output port HB... i ′,i=A,B,C, In addition to the sampled data, add the kernel's abnormal state E. i i = A, B, C. The output port will sample the data HB. i and abnormal state E i Send to soft error detection module 22.

[0082] See also Figure 5 The data receiving module 21 includes a timing component, an information recording component, and a preliminary fault analysis component. The information recording component receives and stores sampled data from different kernels of the data sampling module. The timing component is used to record the arrival time of each interrupt and the order in which the interrupt kernels arrive when it receives a start interrupt request initiated by the APU application unit 1, forming a kernel vector O = <F,S,T,Δt FS ,Δt ST >, where F represents the first received kernel number, S represents the second received kernel number, T represents the third received kernel number, and Δt FS Δt represents the time difference between the arrival of the sampled signals from the first and second kernels. ST This represents the time difference between the arrival of the sampling signals of the second and third kernels; the preliminary fault analysis component, based on the kernel vector O provided by the timing component, determines whether each kernel has issued an interrupt prematurely or failed to issue an interrupt within a timeout period, performs a preliminary analysis of the abnormal kernels, and updates the kernel abnormal state E. i .

[0083] Subsequently, after the soft error detection module determines that the kernel is error-free, it updates the kernel's time difference and sequence, thereby providing a reliable reference for subsequent sampling signal reception tasks.

[0084] See also Figure 5 The preliminary fault analysis component, based on the kernel vector O provided by the timing component, determines whether a kernel issued an interrupt prematurely or whether a kernel timed out without issuing an interrupt, performs a preliminary analysis of the abnormal kernel, and updates the kernel abnormal state E. iIn this embodiment, the preliminary fault analysis component sets three judgments for the arrival of the APU sampling signal: "RYG". R indicates that the kernel sampling signal is severely premature or severely delayed, Y indicates that the kernel is in a sub-healthy state, and G indicates that the kernel is in a healthy state. The kernel state determination is based on the following rules.

[0085] Rule 4: If the current kernel order is equal to the known kernel order, and the kernel time difference is less than or equal to the known time difference, then all three kernels are considered healthy. That is: if (<F′,S′,T′> =<F,S,T> )∧(Δt F′S′ ≤Δt FS )∧(Δt S′T′ ≤Δt ST ), then E i =G,i=A,B,C.

[0086] Rule 5: If the current kernel order is equal to the known kernel order, one kernel's time difference is less than or equal to the known time difference, and the other kernel's time difference is greater than the known time difference but less than or equal to twice the known time difference, then an abnormal kernel ID can be identified, and the abnormal kernel is determined to be in a sub-healthy state. That is: if<F′,S′,T′> =<F,S,T> When Δt m ′≤Δt m , Δt n <Δt n ′≤2Δt n If m, n∈{FS,ST}, m≠n, then E i =Y, i∈(m∪nm∩n),E j =G, j∈m∩n.

[0087] It should be noted that the kernel time difference refers to the time difference between two kernel sampling signals received sequentially by the data receiving module. Since there are three sampling signals, there are two kernel time differences. The known time difference is the time difference between the previous receipt of the sampling signal by the data receiving module, which is the Δt described earlier. FS and Δt ST .

[0088] Rule 6: If the current kernel order is equal to the known kernel order, one kernel's time difference is less than or equal to the known time difference, and the other kernel's time difference is greater than twice the known time difference, then the abnormal kernel ID can be identified, and the abnormal kernel can be determined to be severely ahead or severely behind. That is: if<F′,S′,T′> =<F,S,T> When Δt m ′≤Δt m , Δt n ′>2Δt n If m, n∈{FS,sT}, m≠n, then E i =R, i∈(m∪nm∩n),E j=G, j∈m∩n.

[0089] Rule 7: If the current kernel order is not equal to the known kernel order, the time difference between the two kernels is less than 1.5 times, or the time difference between the two kernels is less than the known maximum time difference, then all kernels are considered healthy. That is: if<F′,s′,T′> ≠<F,S,T> When 1.5min{Δt m ′,Δt n ′}≥max{Δt m ′,Δt n ′} or max{Δt m ′,Δt n ′}<max{Δt m , Δt n When m, n∈{FS,ST}, and m≠n, E i =G, i =A, B, C.

[0090] Rule 8: If the current kernel order is not equal to the known kernel order, and one of the time differences between the two kernels is greater than the known maximum time difference, but the time difference between the two kernels is less than twice the known maximum time difference, then an abnormal kernel ID can be identified, and the abnormal kernel can be determined to be in a sub-healthy state. That is: if<F′,S′,T′> ≠<F,S,T> ,max{Δt m ′,Δt n ′}>max{Δt m , Δt n}, when 1.5min{Δt m ′,Δt n ′}<max{Δt m ′,Δt n ′}≤2min{Δt m When ',Δtn'},m,n∈{FS,ST},m≠n,E i =Y, i∈(m∪nm∩n),E j =G, j∈m∩n.

[0091] Rule 9: If the current kernel order is not equal to the known kernel order, and one of the time differences between the two kernels is greater than the known maximum time difference, and the time difference between the two kernels is greater than twice the known maximum time difference, then an abnormal kernel ID can be identified, and the abnormal kernel can be determined to be severely ahead or severely behind. That is: if<F′,S′,T′> ≠<F,S,T> ,max{Δt m ′,Δt n ′}>max{Δt m , Δt n}, when max{Δt m ′,Δt n ′}>2min{Δt m ′,Δt nWhen m, n∈{FS, ST}, and m≠n, E i =R, i∈(m∪nm∩n),E j =G, j∈m∩n.

[0092] Furthermore, the information recording component is responsible for recording the sampling signals generated by the APU application unit 1. Each sampling signal is sent in the form of an interrupt and needs to be protected to prevent loss of the sampling signal when exiting the data receiving module. In the data receiving module, the sampling signals are allocated a fixed address space, and a pointer is used to point to the address space of the sampling signals to save the sampling signals in the interrupt in a timely manner. Thus, the soft error detection module can use the pointer to access the sampling signals.

[0093] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a soft error detection module of an RPU error detection unit provided in an embodiment of the present invention. The soft error detection module 22 includes a similarity analysis component, a fault cause analysis component, and a fault model matching component. The similarity analysis component is used to receive data and abnormal states of each kernel from the data receiving module and calculate the overall similarity of the kernel data. The fault cause analysis component is used to perform fault cause analysis and location according to a pre-set abnormal bit count calculation rule and a fault kernel location algorithm. The fault model matching component is used to obtain a fault model based on the fault cause analysis and location results.

[0094] Specifically, the soft error detection module 22 is a crucial step in assessing APU anomalies and is also the most important component of single-event error detection. In this embodiment, the soft error detection module 22 includes a similarity analysis component, a fault cause analysis component, and a fault model matching component, and has three input ports and three output ports. The similarity analysis component calculates the overall similarity of the kernel data, the fault cause analysis component analyzes the reasons for similarity mismatches, and the fault model matching component categorizes different fault causes into fault models. The input port data of the soft error detection module 22 is the output HB of the data receiving module. A ′、HB B ′、HB C The data includes data and abnormal states from each kernel of the data receiving module 21; the output of the soft error detection module is the fault mode F for each kernel. A F B F C .

[0095] The similarity analysis component uses Formula 2 to calculate the overall similarity of the sampled data from the APU error detection unit.

[0096]

[0097] Among them, HB i Let i = A, B, C, be the sampled data sent by the data sampling module, and J be the overall similarity of the three sampled data. The overall similarity is used to determine whether a single-event upset (SWE) has occurred in APU application unit 1. If the overall similarity is not equal to 100%, it is considered that at least one kernel has experienced a SWE, but at this time it is not possible to specifically determine which kernel it is, let alone which position of the abnormal kernel the SWE has occurred in.

[0098] Furthermore, not every single-event flip (SIF) causes processor task errors or failures; there is a possibility that erroneous register data can be rapidly overwritten by subsequent data. However, due to the stealthy propagation characteristics of instruction addresses or data registers in module operation, there are also cases where abnormal bits caused by SIFs can lead to data errors or abnormal instruction jumps in subsequent task execution. Therefore, when the overall similarity is 100%, it is assumed that the APU error detection unit does not have SIFs; however, if it is not equal to 100%, further fault cause analysis is required.

[0099] Please see Figure 7 , Figure 7 This is a flowchart of an abnormal fault detection process according to an embodiment of the present invention. After determining that the overall similarity J≠100%, it is necessary to further analyze the sampled signals to determine the abnormal fault type, the number of abnormal bits, and the fault kernel. Before specifically performing the analysis of the sampled signals, rules for calculating the number of abnormal bits and fault kernel location algorithms are formulated.

[0100] Rule 10: Calculation rule for the number of abnormal bits. Given that the registers (including general-purpose registers, floating-point registers, program counter, stack pointer register, and program status register) are 64 bits, the register similarity J... reg The similarity calculation process here refers to formula (2), the difference being that when calculating the similarity of different registers, data from the current registers of different kernels are used. Let n be the number of abnormal bits in the register. reg ,but This allows us to obtain the similarity and number of abnormal bits for each register.

[0101] Furthermore, the fault kernel localization algorithm executes the following steps:

[0102] Step (1): Divide the three kernels A, B, and C into three groups: AB, AC, and BC;

[0103] Step (2): Perform similarity analysis on the three sets of kernels;

[0104] Specifically, referring to formula (2), the overall similarity of the sampled signals between each pair of the three kernels is calculated. The three kernels are grouped into pairs and the calculation is performed three times to obtain the similarity between each pair of kernels.

[0105] Step (3): If one of the three sets of kernels has a similarity of 100%, and the other two sets have a similarity of less than 100%, then it is determined that a faulty kernel has occurred.

[0106] Step (4): Locate the faulty kernel. The faulty kernel location conforms to K. fault ∈(G error1 ∪G error2 )and K fault Refers to a faulty kernel, G error1 and G error2 G refers to abnormal groupings with a similarity of less than 100%. normal This refers to normal groupings with 100% similarity.

[0107] Step (5): If the similarity of the three sets of kernels is less than 100%, it means that there are at least two faulty kernels, and the system should immediately perform soft error recovery.

[0108] See also Figure 7 The similarity analysis is performed sequentially on the general-purpose registers, floating-point registers, program status word register, PC counter, stack pointer register, and sampled data from the memory area using rule 10 to determine whether a single-event soft error (SEE) has occurred in these registers or data. Then, the fault type is determined, and the name of the faulty register and the number of faulty bits are output. The number of faulty bits quantifies the degree of SEE in the faulty register, specifying how many bits differ between the data in the faulty register and the data in the normal register. The fault type categorizes the specific location of the SEE in the sampled signal, specifically into general-purpose register faults and floating-point register faults. gf Program status register fault F spsr PC register fault F pc Stack pointer register fault F sp and storage area failure F mem Finally, the faulty kernel K was determined using a faulty kernel localization algorithm. fault .

[0109] In summary, the soft error detection module 22 can perform soft error diagnosis, location, and analysis of soft error types. If the soft error detection module 22 detects a soft error, the APU application unit 1 enters the fault recovery mechanism. If the soft error detection module 22 does not detect a soft error, it determines whether the core application has completed. If it has, it proceeds to the next task cycle; otherwise, it resumes operation of the core application.

[0110] This invention addresses the problem of soft error detection and identification in multi-core processors of heterogeneous SoC chips. It constructs a timer-based multi-core processor data sampling method to provide a data foundation for processor soft error detection. Compared to control flow-based soft error detection methods implemented at the assembly language level, the timer-based method elevates the implementation level to a high-level programming language, significantly reducing design complexity. This invention designs a soft error detection algorithm adapted to the sampled data, enabling timely detection of soft errors in multi-core processors. To better assess the impact of soft errors on programs, this invention designs a fault model matching scheme for soft errors, further classifying soft errors, predicting the potential harm they may cause to the system, and providing guidance for processor fault tolerance mechanisms.

[0111] Example 2

[0112] Based on the above embodiments, this embodiment provides a method for detecting soft errors in multi-core processors of heterogeneous SoC chips. Please refer to [link to relevant documentation]. Figure 8 The detection method includes:

[0113] S1: Deploy three identical core applications on different processor cores and set a predetermined time difference for the three core applications.

[0114] Specifically, in this embodiment, the core application is replicated three times and deployed on different processor cores. Since the core application is identical, there may be competition for peripheral or internal resources. To mitigate the adverse effects of resource contention by the core application, a certain time difference is set for the three copies of the core application.

[0115] Different kernel runtimes are a prerequisite for multi-core data synchronization sampling and also form the basis of soft error detection modules. The time difference between kernel runtimes should be much smaller than the runtime T of the core application modules. m The kernel runtime satisfies formula (1) in Example 1.

[0116] Furthermore, step S1 also includes:

[0117] A sampling timer is set so that when the timer interrupt is triggered, each kernel switches to the data sampling module to perform data sampling of the core applications in different kernels.

[0118] S2: Collects on-site information of core applications in different kernels at preset times.

[0119] Specifically, in this embodiment, the APU is referred to as APU Application Unit 1, which specifically includes a core application module 11 and a data sampling module 12. The data sampling module 12 collects the field information of the core application module 11, providing basic data support for soft error detection. In this embodiment, the data sampling module 12 includes a data sampling component and a data transmission component, and the data sampling operation is jointly composed of the data sampling component and the data transmission component. The data sampling component is used to detect key information of single-event soft errors in the core application module in a timely and accurate manner, and consists of data from the kernel ID, general-purpose registers, floating-point registers, program counter, stack pointer register, and program status register. In this embodiment, the sampling signal in the data sampling module 12 is specified as HeartInfo type.

[0120] S3: Make a preliminary timeout judgment based on the arrival time of the collected data from different kernels. If a kernel times out, the current kernel is directly determined to be a faulty kernel. If the arrival time of multiple kernels does not time out, then proceed to step S4.

[0121] Specifically, step S3 in this embodiment includes:

[0122] Upon receiving a timer interrupt request from the sampling timer, the arrival time of each interrupt and the order in which the interrupt kernels arrive are recorded, forming a kernel vector O = <F,S,T,Δt FS ,Δt ST >, where F represents the first received kernel number, S represents the second received kernel number, T represents the third received kernel number, and Δt FS Δt represents the time difference between the arrival of the sampled signals from the first and second kernels. ST This indicates the time difference between the arrival of the sampling signals from the second and third kernels;

[0123] Based on the kernel vector O provided by the timing component, it is determined whether each kernel issued an interrupt prematurely or failed to issue an interrupt within a timeout period. An abnormal kernel is preliminarily analyzed, and the kernel abnormal state E is updated. i .

[0124] S4: Perform soft error detection on the sampled information of the multiple kernels to obtain the fault location and fault type.

[0125] Step S4 of this embodiment includes: calculating the overall similarity of kernel data based on the sampled data and abnormal states of each kernel; performing fault cause analysis and fault location based on the pre-set abnormal bit quantity calculation rules and fault kernel location algorithm, and obtaining the fault type. For the specific processing procedure, please refer to Embodiment 1, which will not be repeated here.

[0126] The data sampling and detection method mentioned in this embodiment, in addition to supporting the location of faulty kernels, can more precisely pinpoint the cause of the fault and analyze the potential impact of the fault on the task, further improving detection accuracy. The most significant feature of the method of this invention is its support for the location of faulty kernels, providing support for subsequent targeted recovery of faulty kernels; the three-core comparison function is transferred to the processor core, preserving sufficient FPGA resources.

[0127] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0128] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0129] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A heterogeneous SoC chip multi-core processor soft error detection system, characterized in that, The APU application unit and the RPU error detection unit are included, wherein, The APU application unit includes a core application module and a data sampling module, the core application module deploys three identical core applications in different processor cores respectively and sets a predetermined running time for the three core applications; the data sampling module is used for collecting field information of the core applications in different cores in the core application module at a predetermined time; The RPU error detection unit includes a data receiving module and a soft error detection module, the data receiving module is used for receiving sampling data obtained from the data sampling module and making a preliminary timeout judgment according to the arrival time of the sampling data of different cores, when there is a timeout of a certain core, the current core is directly determined as a fault core, if the sampling time of multiple cores is not timed out, the sampling data is transmitted to the soft error detection module, the soft error detection module is used for soft error detection of the sampling information to obtain a fault location and a fault type; The data receiving module includes an information recording component, a timing component and a preliminary fault analysis component, wherein, The information recording component receives and saves the sampling data of different cores from the data sampling module; The timing component is used to record the time of arrival of each interrupt and the order of arrival of interrupt kernels when receiving the start interrupt request initiated by the APU application unit, forming a kernel vector wherein, F represents the first received kernel number, S represents the second received kernel number, T represents the third received kernel number, represents the time difference between the arrival of the first kernel and the second kernel sampling signal, represents the time difference between the arrival of the second kernel and the third kernel sampling signal; The preliminary fault analysis component is based on the kernel vector provided by the timing component. O Determine whether each kernel issued an interrupt prematurely or failed to issue an interrupt within a timeout period, perform a preliminary analysis of abnormal kernels, and update the kernel abnormal state. E i .

2. The heterogeneous SoC chip multi-core processor soft error detection system of claim 1, wherein, The core application module further includes a sampling timer, when the timing interrupt of the sampling timer is triggered, each core switches to the data sampling module to perform data sampling work on the core applications in different cores in the core application module.

3. The heterogeneous SoC chip multi-core processor soft error detection system of claim 1, wherein, The running time of different cores in the core application module satisfies: wherein, represents the start time of the first kernel starting running, represents the start time of the second kernel starting running, represents the start time of the third kernel starting running, represents the time difference between the first kernel and the second kernel, represents the time difference between the second kernel and the third kernel, represents the time difference between the first kernel and the third kernel, represents the running time of the kernel application module each time.

4. The heterogeneous SoC chip multi-core processor soft error detection system of claim 1, wherein, The data sampling module includes a data sampling component and a data sending component, wherein, The data sampling component is used for obtaining key information of the detection core application module single event soft error, including core ID and data in general register, floating point register, program counter, stack pointer register, program status register; The data sending component is used for sending an interrupt mask to the data receiving module to inform the RPU error detection unit that the data sampling task is completed.

5. The heterogeneous SoC chip multi-core processor soft error detection system of any of claims 1 to 4, wherein, The soft error detection module includes a similarity analysis component, a fault cause analysis component and a fault model matching component, wherein, The similarity analysis component is used for receiving data and abnormal state of each core from the data receiving module and calculating the overall similarity of the core data; The fault cause analysis component is used for fault cause analysis and positioning according to the pre-set abnormal bit quantity calculation rule and fault core positioning algorithm; The fault model matching component is used for obtaining a fault model according to the fault cause analysis and positioning result.

6. A method for soft error detection in a heterogeneous SoC chip multi-core processor, the method comprising: It includes: S1: deploying three identical core applications in different processor cores respectively and setting a predetermined time difference for the three core applications; S2: collecting field information of the core applications in different cores at a predetermined time; S3: making a preliminary timeout judgment according to the arrival time of the collected data from different cores, when there is a timeout of a certain core, the current core is directly determined as a fault core, if the arrival time of multiple cores is not timed out, step S4 is executed; S4: performing soft error detection on the sampling information of the plurality of cores to obtain a fault position and a fault type; The S3 comprises: Upon receiving the timing interrupt request of the sampling timer, record the time of arrival of each interrupt and the order of arrival of the interrupt kernel to form a kernel vector wherein, F denotes the first kernel number received, S denotes the second kernel number received, T denotes the third kernel number received, denotes the time difference of arrival of the first kernel and the second kernel sampling signals, denotes the time difference of arrival of the second kernel and the third kernel sampling signals; According to the kernel vector provided by the timing component O , determine whether each kernel issues an interrupt in advance or whether it times out without issuing an interrupt, preliminarily analyze the abnormal kernel, and update the kernel exception state E i .

7. The heterogeneous SoC chip multi-core processor soft error detection method of claim 6, wherein, The S1 further comprises: A sampling timer is set, so that when a timing interrupt of the sampling timer is triggered, each core switches to a data sampling module to perform data sampling work on the core application in different cores.

8. The heterogeneous SoC chip multi-core processor soft error detection method of claim 6 or 7, wherein, The S4 comprises: According to the sampling data and the abnormal state of each core, an overall similarity of core data is calculated. According to a pre-set abnormal bit quantity calculation rule and a fault core positioning algorithm, fault cause analysis and fault positioning are performed, and a fault type is obtained.

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