A multi-core SoC shared external memory interface design method

Abstract

The application discloses a design method of a multi-core SoC shared external memory interface, wherein a global control register, a clock configuration register and a space control register are internally designed and configured in an external memory interface controller, clock configuration of the external memory interface controller, frequency division coefficient when a system clock is selected, and external memory timing control are performed, the global control register is used for configuring internal working clock of the external memory interface controller and reading external memory state, the clock configuration register is used for configuring output clock of the external memory interface controller and connecting working clock of the external memory, and the space control register is used for external memory read-write timing control of four memory spaces supported by the external memory interface controller; the application optimizes external memory interfaces of multiple processor cores by adopting simplified design, shares one external memory interface, and achieves the effect of reducing system size and improving work efficiency.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of IP design in semiconductor integrated circuits, and particularly relates to a design method of a multi-core SoC shared external memory interface. BACKGROUND

[0002] SoC (System on Chip) is also called system on chip, which is an electronic system integrated on a chip. Generally, SoC is defined as an integrated circuit containing a processor, on-chip logic, high-speed interface, and general-purpose peripherals. With the passage of time and technological development, the definition of SoC is constantly developing and improving. Now, SoC is to integrate complex systems or subsystems into a silicon chip using various intellectual property rights, thereby improving system performance and reducing the cost of each function of the system. In addition to the processor, on-chip logic, high-speed interface, and general-purpose peripherals, SoC can also integrate DSP, analog circuit modules, digital-analog hybrid signal modules, RF circuit modules, and many other functional modules. The communication between SoC and external memory is realized through the EMIF module.

[0003] EMIF (External Memory Interface) is a storage interface between SoC processor and various external storage devices, which is a configurable bus interface. The signal lines on the interface cover the read-write interface signals of various memories (SRAM, FLASH, DDR-RAM). By configuring the corresponding registers through software, the EMIF external memory interface can work in a fixed interface form that matches the external memory used in the design.

[0004] Due to the large number of EMIF external memory interfaces, if each processor is designed with a corresponding EMIF interface, a large number of external port signals will be generated, which is relatively large in size. SUMMARY

[0005] The purpose of the present application is to provide a design method of a multi-core SoC shared external memory interface. In the design, a MUX selector is used to enable multiple processors to share an EMIF external memory interface, thereby reducing the system external port and reducing the system area.

[0006] The technical solution of the present application is:

[0007] A design method of a multi-core SoC shared external memory interface, comprising the steps of:

[0008] S1, first design an external memory interface controller EMIF, which supports 8-bit, 16-bit, and 32-bit memory width for data bus width, and has a maximum address of 1G space;

[0009] The external memory interface controller EMIF communicates data with the AXI bus through SLAVE3, configures internal registers, and configures chip selection, byte enable, and data width information required for external memory read and write operation.

[0010] The external memory interface controller EMIF communicates data with the AXI bus through SLAVE3, configures internal registers, and configures chip selection, byte enable, and data width information required for external memory read and write operation.

[0011] S2, design a multi-core SoC shared external memory interface: the internal design of the external memory interface controller configures a global control register GBLCTL, four clock configuration registers CLKxCTL and four space control registers CExCTL, performs external memory interface controller clock configuration, selects the frequency division coefficient when the system clock is used, and controls the external memory timing;

[0012] The global control register GBLCTL is used to configure the internal working clock of the external memory interface controller and read the external memory state.

[0013] The clock configuration register CLKxCTL is used to configure the output clock of the external memory interface controller, and the working clock of the connected external memory, x=0~3.

[0014] The space control register CExCTL is used to control the read and write timing of the external memory in the four memory spaces supported by the external memory interface controller, CE0~CE3, x=0~3.

[0015] Preferably, the external memory interface controller EMIF realizes the read and write timing control of the external memory, and is designed to include a register configuration module, a clock module, a timing conversion module, and an external memory timing control module.

[0016] Preferably, the design of the register configuration module includes: before the external memory interface controller works, the global control register GBLCTL, the clock configuration register CLKxCTL, and the CEx space control register CExCTL are configured.

[0017] The design of the clock module preferably comprises: an external storage interface controller design capable of simultaneously connecting four different types of external storage, and for each type of external storage, the interface controller needs to output a matching clock eclkout; therefore, four frequency division registers clk0_div, clk1_div, clk2_div and clk3_div are designed to be matched with four spaces CEs0-3, and one frequency division coefficient clkdiv is selected by the high four bits addr[31:28] of the address to divide the system clock; finally, the output is controlled by the global control register clksel to select the output eclkout.

[0018] The design of the timing conversion module preferably comprises: converting the clock configuration register configured by the system clock sclk and the CEx space control register into a timing signal that meets the output clock eclkout, and cooperating with the address to perform four-to-one output of the clock division coefficient and the CEx space timing control.

[0019] The design of the external storage timing control module preferably comprises: four address mapping spaces are designed in the external storage interface controller, when the address addr sent by the SoC processor is C0000000-CFFFFFFF, the external storage interface controller selects the storage space of CE0, the output port CEn[0] is low, the storage space of CE0 is enabled, and the output clock is the working clock corresponding to the storage space; when the input address addr is D0000000-DFFFFFFF (256M), the storage space of CE1 is selected, the output port CEn[1] is designed to be low, the storage space of CE1 is enabled, and the corresponding clock is output; when the input address addr is E0000000-EFFFFFFF (256M), the storage space of CE2 is selected, the output port CEn[2] is designed to be low, the storage space of CE2 is enabled, and the corresponding clock is output; when the input address addr is F0000000-FFFFFFFF (256M), the storage space of CE3 is selected, the output port CEn[3] is designed to be low, the storage space of CE3 is enabled, and the corresponding clock is output.

[0020] The advantages of the present application are:

[0021] The present application provides a shared external storage interface technology, solves the contradiction between the expansibility of the system structure and the area power consumption, optimizes the external storage interfaces of multiple processor cores by using a simplified design, shares one external storage interface, and achieves the effect of reducing the system size and improving the work efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0022] The application will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 Connection diagram of external memory interface and bus;

[0024] Figure 2 Structure block diagram of external memory interface controller;

[0025] Figure 3 Structure diagram of register configuration module;

[0026] Figure 4 Design block diagram of external memory interface controller clock;

[0027] Figure 5 Design block diagram of timing conversion module. DETAILED DESCRIPTION

[0028] SoC on-chip system needs to process a large amount of signal data in the running process, and the internal storage space of the processor is far from enough. In addition to designing SRAM in the chip, external memory needs to be connected for BOOT, data communication and other work. Therefore, the application designs an external memory interface controller, and SoC accesses external memory through the external memory interface controller, which can be seamlessly connected with FLASH, SRAM, ferroelectric, magnetoresistance and other types of memory.

[0029] The application first designs an EMIF external memory interface controller, which supports 8-bit, 16-bit and 32-bit memory width of data bus width, and has a maximum address of 1G space and fast data throughput. The connection diagram of the bus is shown in Figure 1 .

[0030] Figure 1 The external memory interface controller EMIF communicates data with the AXI bus through SLAVE3, configures internal registers, and configures information such as chip selection, byte enable and data width required for external memory read-write operation.

[0031] The external memory interface controller EMIF communicates data with the processor core through the slave3 connection AXI bus, and the off-chip signal directly connects the external memory for read-write control. The interface is shown in Table 1.

[0032] Table 1: Interface list of external memory interface controller

[0033]

[0034] It can be seen that EMIF has more external interfaces and bus connection ports. If there are multiple processor cores in a SoC system, and each processor core is connected to an external memory controller EMIF, it will cause the complexity of the internal bus connection of the SoC, the increase of the number of external ports, the increase of the volume, and the increase of the cost. If multiple processors share an external memory interface, and the EMIF clock, chip selection, space and other signals are controlled in a polling manner, the number of external memory control ports will be greatly reduced, and the system volume will be reduced. A method for sharing an external memory interface by multiple core SoCs is designed. Taking an SoC with four processors as an example, the connection relationship is as shown in the following figure. Figure 2

[0035] Figure 2 The internal design configuration registers GBLCTL, CLKxCTL (x = 0 ~ 3) and CExCTL (x = 0 ~ 3) of the external memory interface controller are used for clock configuration of the external memory interface controller, selection of frequency division coefficient when the system clock is used, and external memory timing control.

[0036] Figure 2 The global control register GBLCTL is used for configuring the internal working clock of the external memory interface controller and reading the state of the external memory.

[0037] Figure 2 The clock configuration register CLKxCTL (x = 0 ~ 3) is used for configuring the output clock of the external memory interface controller and connecting the working clock of the external memory.

[0038] Figure 2 The space control register CExCTL (x = 0 ~ 3) is used for the read-write timing control of the four memory spaces CE0 ~ CE3 supported by the external memory interface controller.

[0039] The external memory interface controller EMIF mainly realizes the read-write timing control of the external memory, and the design includes a register configuration module, a clock module, a timing conversion module, and an external memory timing control module.

[0040] (1) Register configuration module

[0041] Before the external memory interface controller works, the global control register (GBLCTL), the clock configuration register (CLKxCTL) and the CEx space control register (CExCTL) need to be configured. As shown in the following figure. Figure 3

[0042] ​​When the address addr from slave3 and write enable we are valid, according to the corresponding address, the write enable wgblctl_en, wclk0ctl_en, wclk1ctl_en, wclk2ctl_en, wclk3ctl_en, wce0ctl_en, wce1ctl_en, wce2ctl_en and wce3ctl_en of the register are generated, which respectively start the write operation of different configuration registers:

[0043] When wgblctl_en is high, the lowest bit of the write data wdata is assigned to the register clksel, and the internal working clock is configured. The default value of clksel is 1, and the external input clock eclkin is used.

[0044] When wclk0ctl_en is high, the lower 10 bits of the write data wdata are assigned to the register clk0_div, and the clock division coefficient of the corresponding ce0 space is set. The default value of clk0_div is 0, and the clock is not divided.

[0045] When wclk1ctl_en is high, the lower 10 bits of the write data wdata are assigned to the register clk1_div, and the clock division coefficient of the corresponding ce1 space is set. The default value of clk1_div is 0, and the clock is not divided.

[0046] When wclk2ctl_en is high, the lower 10 bits of the write data wdata are assigned to the register clk2_div, and the clock division coefficient of the corresponding ce2 space is set. The default value of clk2_div is 0, and the clock is not divided.

[0047] When wclk3ctl_en is high, the lower 10 bits of the write data wdata are assigned to the register clk3_div, and the clock division coefficient of the corresponding ce3 space is set. The default value of clk3_div is 0, and the clock is not divided.

[0048] When wce0ctl_en is high, the 32-bit write data wdata is assigned to the register ce0ctl, and the external memory read-write timing of the corresponding ce0 space is set. The default value of ce0ctl is 32’ffffff66, that is, the write setup time width is 15 clock cycles, the write enable time width is 63 clock cycles, the write hold time width is 3 clock cycles, the read setup time width is 15 clock cycles, the turnaround time is 3 clock cycles, the read enable time width is 63 clock cycles, the read hold time width is 3 clock cycles, and the memory type is 32-bit wide asynchronous SRAM.

[0049] When wce1ctl_en is high, 32-bit write data wdata is assigned to register ce1ctl to set the read / write timing of the external memory corresponding to the ce1 space. The default value of ce1ctl is {27'h7fffffb, 2'b00, ce1boot}, except that the memory type is different, the other bits are set the same as ce0ctl. The memory type (the lower 5 bits of the ce1ctl register) is configured through the external input port bootmode (HD_sel). When bootmode is connected as 01, ce1boot is 3'b000, and the external memory is 8-bit wide flash. When bootmode is connected as 10, ce1boot is 3'b001, and the external memory is 16-bit wide flash. When bootmode is connected as 11, ce1boot is 3'b010, and the external memory is 32-bit wide flash. When bootmode is connected as 00, ce1boot is 3'b110, and the external memory is 32-bit wide asynchronous SRAM.

[0050] When wce2ctl_en is high, 32-bit write data wdata is assigned to register ce2ctl to set the read / write timing of the external memory corresponding to the ce2 space. The default value of ce2ctl is 32'ffffff66, which is set the same as ce0ctl.

[0051] When wce3ctl_en is high, 32-bit write data wdata is assigned to register ce3ctl to set the read / write timing of the external memory corresponding to the ce3 space. The default value of ce3ctl is 32'ffffff66, which is set the same as ce0ctl.

[0052] (2) Clock module

[0053] The external storage interface controller can be connected to four different types of external memories at the same time. For each type of external memory, the interface controller needs to output its matching clock eclkout. Therefore, four frequency division registers clk0_div, clk1_div, clk2_div and clk3_div are designed to map and match the four spaces CE0-3. One frequency division coefficient clkdiv is selected by the high four bits of the address addr[31:28] to divide the system clock. Finally, the global control register clksel controls the output to select eclkout. This clock can be arbitrarily configured according to the timing requirements of the external memory. The structure is shown in Figure 4

[0054] (3) Timing conversion module

[0055] ​The clock configuration register and CEx space control register configured by system clock sclk are converted into timing signals satisfying output clock eclkout, and clock division coefficient and CEx space timing control are outputted in four-to-one mode with address. The structure is shown in Figure 5

[0056] The four-to-one output clkdiv of clock configuration register is inputted as the division coefficient of clock module, and the four-to-one output of CEx space control register including wrsetup, wrstrb, wrhld, rdsetup, ta, rdstrb, rdhld and mtype is inputted as the input of external memory timing control module. The address addr, write enable we and read enable re in one clock cycle are converted into latch signals in the module, and read and write control is performed with low frequency output clock eclkout.

[0057] (4) External memory timing control module

[0058] Four address mapping spaces are designed in the external memory interface controller. When the address addr sent by SoC processor is C0000000-CFFFFFFF (256M), the external memory interface controller selects the storage space of CE0, the output port CEn[0] is low, the memory connected with CE0 works, and the output clock is the working clock corresponding to the memory; when the input address addr is D0000000-DFFFFFFF (256M), the storage space of CE1 is selected, the output port CEn[1] is designed to be low, the memory connected with CE1 works, and the corresponding clock is outputted; when the input address addr is E0000000-EFFFFFFF (256M), the storage space of CE2 is selected, the output port CEn[2] is designed to be low, the memory connected with CE2 works, and the corresponding clock is outputted; when the input address addr is F0000000-FFFFFFFF (256M), the storage space of CE3 is selected, the output port CEn[3] is designed to be low, the memory connected with CE3 works, and the corresponding clock is outputted.

[0059] The four bits of CEn[3:0] can simultaneously connect the chip select enable of four external memories, and start the corresponding memory to work. If the four bits of CEn[3:0] are connected with the same type of memory, the maximum addressable space can be expanded to 1G. The addressable space range of external memory interface controller is shown in Table 2.

[0060] Table 2 Addressable memory space range of external memory interface controller

[0061]

[0062] ​The above examples are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any modification made according to the spirit and essence of the main technical solution of the present application should be covered within the protection scope of the present application.

Claims

1. A design method for a shared external memory interface in a multi-core SoC, characterized in that, Including the following steps: S1. First, design an external storage interface controller (EMIF) with a data bus width that supports 8-bit, 16-bit, and 32-bit memory widths and a maximum addressable space of 1G. The External Storage Interface Controller (EMIF) communicates with the AXI bus via SLAVE3, configures internal registers, and performs chip select, byte enable, and data width configurations required for external memory read and write operations. The external storage interface controller EMIF communicates with the processor core via the SLAVE3 AXI bus, and external signals are directly connected to the external memory for read and write control. S2. Design a multi-core SoC shared external memory interface: The external memory interface controller internally configures a global control register GBLCTL, four clock configuration registers CLKxCTL and four space control registers CExCTL to configure the external memory interface controller clock, select the frequency division factor when selecting the system clock, and control the external memory timing. The Global Control Register GBLCTL is used to configure the internal operating clock of the external storage interface controller and to read the status of the external memory. The clock configuration register CLKxCTL is used to configure the output clock of the external storage interface controller, which is the working clock of the external memory. x = 0 to 3. The space control register CExCTL is used for the timing control of external memory read and write operations in the four memory spaces CE0 to CE3 supported by the external memory interface controller, with x = 0 to 3.

2. The design method for a multi-core SoC shared external memory interface according to claim 1, characterized in that, The External Memory Interface Controller (EMIF) implements read / write timing control for external memory. The design includes a register configuration module, a clock module, a timing conversion module, and an external memory timing control module.

3. The design method for a multi-core SoC shared external memory interface according to claim 2, characterized in that, The design of the register configuration module includes: before the external storage interface controller starts working, configuring the global control register GBLCTL, the clock configuration register CLKxCTL, and the CEx space control register CExCTL.

4. The multi-core SoC shared external memory interface design method according to claim 3, characterized in that, The design of the clock module includes: the external storage interface controller is designed to connect to four different types of external memory simultaneously. For each type of external memory, the interface controller needs to output its matching clock eclkout. Therefore, four frequency divider registers, clk0_div, clk1_div, clk2_div and clk3_div, are designed to be mapped and matched with four spaces, CE0 to 3. The high four bits of the address addr[31:28] are used to select one of the frequency divider coefficients clkdiv for output, and the system clock is divided according to this coefficient. Finally, the output is controlled by the global control register clksel, and the output eclkout is selected.

5. The multi-core SoC shared external memory interface design method according to claim 3, characterized in that, The timing conversion module is designed to convert the clock configuration register and CEx space control register configured by the system clock sclk into a timing signal that satisfies the output clock eclkout, and then use the address to perform a four-in-one output by clock division coefficient and CEx space timing control.

6. The multi-core SoC shared external memory interface design method according to claim 3, characterized in that, The design of the external memory timing control module includes: the external memory interface controller is designed with 4 address mapping spaces. When the address addr sent by the SoC processor is C0000000~CFFFFFFF, the external memory interface controller selects the memory space of CE0, and the output port CEn[0] is low, so that the external memory connected to CE0 works, and the output clock is the working clock of the corresponding memory; when the input address addr is D0000000~DFFFFFFF, the memory space of CE1 is selected, and the output port CEn[1] is low, so that the external memory connected to CE1 works, and the corresponding clock is output; when the input address addr is E0000000~EFFFFFFF, the memory space of CE2 is selected, and the output port CEn[2] is low, so that the external memory connected to CE2 works, and the corresponding clock is output; when the input address addr is F0000000~FFFFFFFF, the memory space of CE3 is selected, and the output port CEn[3] is low, so that the external memory connected to CE3 works, and the corresponding clock is output.

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